1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 struct drr_params; 50 struct dc_underflow_debug_data; 51 52 struct subvp_pipe_control_lock_fast_params { 53 struct dc *dc; 54 bool lock; 55 bool subvp_immediate_flip; 56 }; 57 58 struct pipe_control_lock_params { 59 struct dc *dc; 60 struct pipe_ctx *pipe_ctx; 61 bool lock; 62 }; 63 64 struct set_flip_control_gsl_params { 65 struct pipe_ctx *pipe_ctx; 66 bool flip_immediate; 67 }; 68 69 struct program_triplebuffer_params { 70 const struct dc *dc; 71 struct pipe_ctx *pipe_ctx; 72 bool enableTripleBuffer; 73 }; 74 75 struct update_plane_addr_params { 76 struct dc *dc; 77 struct pipe_ctx *pipe_ctx; 78 }; 79 80 struct set_input_transfer_func_params { 81 struct dc *dc; 82 struct pipe_ctx *pipe_ctx; 83 struct dc_plane_state *plane_state; 84 }; 85 86 struct program_gamut_remap_params { 87 struct pipe_ctx *pipe_ctx; 88 }; 89 90 struct program_manual_trigger_params { 91 struct pipe_ctx *pipe_ctx; 92 }; 93 94 struct send_dmcub_cmd_params { 95 struct dc_context *ctx; 96 union dmub_rb_cmd *cmd; 97 enum dm_dmub_wait_type wait_type; 98 }; 99 100 struct setup_dpp_params { 101 struct pipe_ctx *pipe_ctx; 102 }; 103 104 struct program_bias_and_scale_params { 105 struct pipe_ctx *pipe_ctx; 106 }; 107 108 struct set_output_transfer_func_params { 109 struct dc *dc; 110 struct pipe_ctx *pipe_ctx; 111 const struct dc_stream_state *stream; 112 }; 113 114 struct update_visual_confirm_params { 115 struct dc *dc; 116 struct pipe_ctx *pipe_ctx; 117 int mpcc_id; 118 }; 119 120 struct power_on_mpc_mem_pwr_params { 121 struct mpc *mpc; 122 int mpcc_id; 123 bool power_on; 124 }; 125 126 struct set_output_csc_params { 127 struct mpc *mpc; 128 int opp_id; 129 const uint16_t *regval; 130 enum mpc_output_csc_mode ocsc_mode; 131 }; 132 133 struct set_ocsc_default_params { 134 struct mpc *mpc; 135 int opp_id; 136 enum dc_color_space color_space; 137 enum mpc_output_csc_mode ocsc_mode; 138 }; 139 140 struct subvp_save_surf_addr { 141 struct dc_dmub_srv *dc_dmub_srv; 142 const struct dc_plane_address *addr; 143 uint8_t subvp_index; 144 }; 145 146 struct wait_for_dcc_meta_propagation_params { 147 const struct dc *dc; 148 const struct pipe_ctx *top_pipe_to_program; 149 }; 150 151 struct dmub_hw_control_lock_fast_params { 152 struct dc *dc; 153 bool is_required; 154 bool lock; 155 }; 156 157 struct program_cursor_update_now_params { 158 struct dc *dc; 159 struct pipe_ctx *pipe_ctx; 160 }; 161 162 union block_sequence_params { 163 struct update_plane_addr_params update_plane_addr_params; 164 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 165 struct pipe_control_lock_params pipe_control_lock_params; 166 struct set_flip_control_gsl_params set_flip_control_gsl_params; 167 struct program_triplebuffer_params program_triplebuffer_params; 168 struct set_input_transfer_func_params set_input_transfer_func_params; 169 struct program_gamut_remap_params program_gamut_remap_params; 170 struct program_manual_trigger_params program_manual_trigger_params; 171 struct send_dmcub_cmd_params send_dmcub_cmd_params; 172 struct setup_dpp_params setup_dpp_params; 173 struct program_bias_and_scale_params program_bias_and_scale_params; 174 struct set_output_transfer_func_params set_output_transfer_func_params; 175 struct update_visual_confirm_params update_visual_confirm_params; 176 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 177 struct set_output_csc_params set_output_csc_params; 178 struct set_ocsc_default_params set_ocsc_default_params; 179 struct subvp_save_surf_addr subvp_save_surf_addr; 180 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 181 struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; 182 struct program_cursor_update_now_params program_cursor_update_now_params; 183 }; 184 185 enum block_sequence_func { 186 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 187 OPTC_PIPE_CONTROL_LOCK, 188 HUBP_SET_FLIP_CONTROL_GSL, 189 HUBP_PROGRAM_TRIPLEBUFFER, 190 HUBP_UPDATE_PLANE_ADDR, 191 DPP_SET_INPUT_TRANSFER_FUNC, 192 DPP_PROGRAM_GAMUT_REMAP, 193 OPTC_PROGRAM_MANUAL_TRIGGER, 194 DMUB_SEND_DMCUB_CMD, 195 DPP_SETUP_DPP, 196 DPP_PROGRAM_BIAS_AND_SCALE, 197 DPP_SET_OUTPUT_TRANSFER_FUNC, 198 MPC_UPDATE_VISUAL_CONFIRM, 199 MPC_POWER_ON_MPC_MEM_PWR, 200 MPC_SET_OUTPUT_CSC, 201 MPC_SET_OCSC_DEFAULT, 202 DMUB_SUBVP_SAVE_SURF_ADDR, 203 HUBP_WAIT_FOR_DCC_META_PROP, 204 DMUB_HW_CONTROL_LOCK_FAST, 205 PROGRAM_CURSOR_UPDATE_NOW, 206 /* This must be the last value in this enum, add new ones above */ 207 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 208 }; 209 210 struct block_sequence { 211 union block_sequence_params params; 212 enum block_sequence_func func; 213 }; 214 215 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 216 217 struct hw_sequencer_funcs { 218 void (*hardware_release)(struct dc *dc); 219 /* Embedded Display Related */ 220 void (*edp_power_control)(struct dc_link *link, bool enable); 221 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 222 void (*edp_wait_for_T12)(struct dc_link *link); 223 224 /* Pipe Programming Related */ 225 void (*init_hw)(struct dc *dc); 226 void (*power_down_on_boot)(struct dc *dc); 227 void (*enable_accelerated_mode)(struct dc *dc, 228 struct dc_state *context); 229 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 230 struct dc_state *context); 231 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 232 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 233 void (*apply_ctx_for_surface)(struct dc *dc, 234 const struct dc_stream_state *stream, 235 int num_planes, struct dc_state *context); 236 void (*program_front_end_for_ctx)(struct dc *dc, 237 struct dc_state *context); 238 void (*wait_for_pending_cleared)(struct dc *dc, 239 struct dc_state *context); 240 void (*post_unlock_program_front_end)(struct dc *dc, 241 struct dc_state *context); 242 void (*update_plane_addr)(const struct dc *dc, 243 struct pipe_ctx *pipe_ctx); 244 void (*update_dchub)(struct dce_hwseq *hws, 245 struct dchub_init_data *dh_data); 246 void (*wait_for_mpcc_disconnect)(struct dc *dc, 247 struct resource_pool *res_pool, 248 struct pipe_ctx *pipe_ctx); 249 void (*edp_backlight_control)( 250 struct dc_link *link, 251 bool enable); 252 void (*program_triplebuffer)(const struct dc *dc, 253 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 254 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 255 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 256 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 257 258 /* Pipe Lock Related */ 259 void (*pipe_control_lock)(struct dc *dc, 260 struct pipe_ctx *pipe, bool lock); 261 void (*interdependent_update_lock)(struct dc *dc, 262 struct dc_state *context, bool lock); 263 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 264 bool flip_immediate); 265 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 266 267 /* Timing Related */ 268 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 269 struct crtc_position *position); 270 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 271 void (*calc_vupdate_position)( 272 struct dc *dc, 273 struct pipe_ctx *pipe_ctx, 274 uint32_t *start_line, 275 uint32_t *end_line); 276 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 277 int group_size, struct pipe_ctx *grouped_pipes[]); 278 void (*enable_timing_synchronization)(struct dc *dc, 279 struct dc_state *state, 280 int group_index, int group_size, 281 struct pipe_ctx *grouped_pipes[]); 282 void (*enable_vblanks_synchronization)(struct dc *dc, 283 int group_index, int group_size, 284 struct pipe_ctx *grouped_pipes[]); 285 void (*setup_periodic_interrupt)(struct dc *dc, 286 struct pipe_ctx *pipe_ctx); 287 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 288 struct dc_crtc_timing_adjust adjust); 289 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 290 int num_pipes, 291 const struct dc_static_screen_params *events); 292 293 /* Stream Related */ 294 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 295 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 296 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 297 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 298 struct dc_link_settings *link_settings); 299 300 /* Bandwidth Related */ 301 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 302 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 303 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 304 305 /* Infopacket Related */ 306 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 307 void (*send_immediate_sdp_message)( 308 struct pipe_ctx *pipe_ctx, 309 const uint8_t *custom_sdp_message, 310 unsigned int sdp_message_size); 311 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 312 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 313 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 314 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 315 316 /* Cursor Related */ 317 void (*set_cursor_position)(struct pipe_ctx *pipe); 318 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 319 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 320 void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 321 void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 322 void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 323 void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe); 324 void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context, 325 const struct dc_stream_state *stream); 326 void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); 327 328 /* Colour Related */ 329 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 330 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 331 enum dc_color_space colorspace, 332 uint16_t *matrix, int opp_id); 333 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 334 335 /* VM Related */ 336 int (*init_sys_ctx)(struct dce_hwseq *hws, 337 struct dc *dc, 338 struct dc_phy_addr_space_config *pa_config); 339 void (*init_vm_ctx)(struct dce_hwseq *hws, 340 struct dc *dc, 341 struct dc_virtual_addr_space_config *va_config, 342 int vmid); 343 344 /* Writeback Related */ 345 void (*update_writeback)(struct dc *dc, 346 struct dc_writeback_info *wb_info, 347 struct dc_state *context); 348 void (*enable_writeback)(struct dc *dc, 349 struct dc_writeback_info *wb_info, 350 struct dc_state *context); 351 void (*disable_writeback)(struct dc *dc, 352 unsigned int dwb_pipe_inst); 353 354 /* Clock Related */ 355 enum dc_status (*set_clock)(struct dc *dc, 356 enum dc_clock_type clock_type, 357 uint32_t clk_khz, uint32_t stepping); 358 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 359 struct dc_clock_config *clock_cfg); 360 void (*optimize_pwr_state)(const struct dc *dc, 361 struct dc_state *context); 362 void (*exit_optimized_pwr_state)(const struct dc *dc, 363 struct dc_state *context); 364 void (*calculate_pix_rate_divider)(struct dc *dc, 365 struct dc_state *context, 366 const struct dc_stream_state *stream); 367 368 /* Audio Related */ 369 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 370 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 371 372 /* Stereo 3D Related */ 373 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 374 375 /* HW State Logging Related */ 376 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 377 void (*log_color_state)(struct dc *dc, 378 struct dc_log_buffer_ctx *log_ctx); 379 void (*get_hw_state)(struct dc *dc, char *pBuf, 380 unsigned int bufSize, unsigned int mask); 381 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 382 383 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 384 struct set_backlight_level_params *params); 385 386 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 387 388 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 389 390 void (*enable_dp_link_output)(struct dc_link *link, 391 const struct link_resource *link_res, 392 enum signal_type signal, 393 enum clock_source_id clock_source, 394 const struct dc_link_settings *link_settings); 395 void (*enable_tmds_link_output)(struct dc_link *link, 396 const struct link_resource *link_res, 397 enum signal_type signal, 398 enum clock_source_id clock_source, 399 enum dc_color_depth color_depth, 400 uint32_t pixel_clock); 401 void (*enable_lvds_link_output)(struct dc_link *link, 402 const struct link_resource *link_res, 403 enum clock_source_id clock_source, 404 uint32_t pixel_clock); 405 void (*disable_link_output)(struct dc_link *link, 406 const struct link_resource *link_res, 407 enum signal_type signal); 408 409 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 410 411 /* Idle Optimization Related */ 412 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 413 414 bool (*does_plane_fit_in_mall)(struct dc *dc, 415 unsigned int pitch, 416 unsigned int height, 417 enum surface_pixel_format format, 418 struct dc_cursor_attributes *cursor_attr); 419 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 420 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 421 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 422 void (*subvp_pipe_control_lock)(struct dc *dc, 423 struct dc_state *context, 424 bool lock, 425 bool should_lock_all_pipes, 426 struct pipe_ctx *top_pipe_to_program, 427 bool subvp_prev_use); 428 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 429 430 void (*z10_restore)(const struct dc *dc); 431 void (*z10_save_init)(struct dc *dc); 432 bool (*is_abm_supported)(struct dc *dc, 433 struct dc_state *context, struct dc_stream_state *stream); 434 435 void (*set_disp_pattern_generator)(const struct dc *dc, 436 struct pipe_ctx *pipe_ctx, 437 enum controller_dp_test_pattern test_pattern, 438 enum controller_dp_color_space color_space, 439 enum dc_color_depth color_depth, 440 const struct tg_color *solid_color, 441 int width, int height, int offset); 442 void (*blank_phantom)(struct dc *dc, 443 struct timing_generator *tg, 444 int width, 445 int height); 446 void (*update_visual_confirm_color)(struct dc *dc, 447 struct pipe_ctx *pipe_ctx, 448 int mpcc_id); 449 void (*update_phantom_vp_position)(struct dc *dc, 450 struct dc_state *context, 451 struct pipe_ctx *phantom_pipe); 452 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 453 454 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 455 struct pg_block_update *update_state); 456 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 457 struct pg_block_update *update_state); 458 void (*hw_block_power_up)(struct dc *dc, 459 struct pg_block_update *update_state); 460 void (*hw_block_power_down)(struct dc *dc, 461 struct pg_block_update *update_state); 462 void (*root_clock_control)(struct dc *dc, 463 struct pg_block_update *update_state, bool power_on); 464 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 465 const struct dc_state *cur_ctx, 466 const struct dc_state *new_ctx); 467 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 468 const struct pipe_ctx *top_pipe_to_program); 469 void (*dmub_hw_control_lock)(struct dc *dc, 470 struct dc_state *context, 471 bool lock); 472 void (*fams2_update_config)(struct dc *dc, 473 struct dc_state *context, 474 bool enable); 475 void (*dmub_hw_control_lock_fast)(union block_sequence_params *params); 476 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 477 void (*program_outstanding_updates)(struct dc *dc, 478 struct dc_state *context); 479 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 480 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 481 void (*detect_pipe_changes)(struct dc_state *old_state, 482 struct dc_state *new_state, 483 struct pipe_ctx *old_pipe, 484 struct pipe_ctx *new_pipe); 485 void (*enable_plane)(struct dc *dc, 486 struct pipe_ctx *pipe_ctx, 487 struct dc_state *context); 488 void (*update_dchubp_dpp)(struct dc *dc, 489 struct pipe_ctx *pipe_ctx, 490 struct dc_state *context); 491 void (*post_unlock_reset_opp)(struct dc *dc, 492 struct pipe_ctx *opp_head); 493 void (*get_underflow_debug_data)(const struct dc *dc, 494 struct timing_generator *tg, 495 struct dc_underflow_debug_data *out_data); 496 }; 497 498 void color_space_to_black_color( 499 const struct dc *dc, 500 enum dc_color_space colorspace, 501 struct tg_color *black_color); 502 503 bool hwss_wait_for_blank_complete( 504 struct timing_generator *tg); 505 506 const uint16_t *find_color_matrix( 507 enum dc_color_space color_space, 508 uint32_t *array_size); 509 510 void get_surface_tile_visual_confirm_color( 511 struct pipe_ctx *pipe_ctx, 512 struct tg_color *color); 513 void get_surface_visual_confirm_color( 514 const struct pipe_ctx *pipe_ctx, 515 struct tg_color *color); 516 517 void get_hdr_visual_confirm_color( 518 struct pipe_ctx *pipe_ctx, 519 struct tg_color *color); 520 void get_mpctree_visual_confirm_color( 521 struct pipe_ctx *pipe_ctx, 522 struct tg_color *color); 523 void get_smartmux_visual_confirm_color( 524 struct dc *dc, 525 struct tg_color *color); 526 void get_vabc_visual_confirm_color( 527 struct pipe_ctx *pipe_ctx, 528 struct tg_color *color); 529 void get_subvp_visual_confirm_color( 530 struct pipe_ctx *pipe_ctx, 531 struct tg_color *color); 532 void get_fams2_visual_confirm_color( 533 struct dc *dc, 534 struct dc_state *context, 535 struct pipe_ctx *pipe_ctx, 536 struct tg_color *color); 537 538 void get_mclk_switch_visual_confirm_color( 539 struct pipe_ctx *pipe_ctx, 540 struct tg_color *color); 541 542 void get_cursor_visual_confirm_color( 543 struct pipe_ctx *pipe_ctx, 544 struct tg_color *color); 545 546 void get_dcc_visual_confirm_color( 547 struct dc *dc, 548 struct pipe_ctx *pipe_ctx, 549 struct tg_color *color); 550 551 void set_p_state_switch_method( 552 struct dc *dc, 553 struct dc_state *context, 554 struct pipe_ctx *pipe_ctx); 555 556 void set_drr_and_clear_adjust_pending( 557 struct pipe_ctx *pipe_ctx, 558 struct dc_stream_state *stream, 559 struct drr_params *params); 560 561 void hwss_execute_sequence(struct dc *dc, 562 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 563 int num_steps); 564 565 void hwss_build_fast_sequence(struct dc *dc, 566 struct dc_dmub_cmd *dc_dmub_cmd, 567 unsigned int dmub_cmd_count, 568 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 569 unsigned int *num_steps, 570 struct pipe_ctx *pipe_ctx, 571 struct dc_stream_status *stream_status, 572 struct dc_state *context); 573 574 void hwss_wait_for_all_blank_complete(struct dc *dc, 575 struct dc_state *context); 576 577 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 578 struct dc_state *context); 579 580 void hwss_wait_for_no_pipes_pending(struct dc *dc, 581 struct dc_state *context); 582 583 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 584 struct dc_state *dc_context); 585 586 void hwss_process_outstanding_hw_updates(struct dc *dc, 587 struct dc_state *dc_context); 588 589 void hwss_send_dmcub_cmd(union block_sequence_params *params); 590 591 void hwss_program_manual_trigger(union block_sequence_params *params); 592 593 void hwss_setup_dpp(union block_sequence_params *params); 594 595 void hwss_program_bias_and_scale(union block_sequence_params *params); 596 597 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 598 599 void hwss_set_output_csc(union block_sequence_params *params); 600 601 void hwss_set_ocsc_default(union block_sequence_params *params); 602 603 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 604 605 #endif /* __DC_HW_SEQUENCER_H__ */ 606