1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 50 struct subvp_pipe_control_lock_fast_params { 51 struct dc *dc; 52 bool lock; 53 bool subvp_immediate_flip; 54 }; 55 56 struct pipe_control_lock_params { 57 struct dc *dc; 58 struct pipe_ctx *pipe_ctx; 59 bool lock; 60 }; 61 62 struct set_flip_control_gsl_params { 63 struct pipe_ctx *pipe_ctx; 64 bool flip_immediate; 65 }; 66 67 struct program_triplebuffer_params { 68 const struct dc *dc; 69 struct pipe_ctx *pipe_ctx; 70 bool enableTripleBuffer; 71 }; 72 73 struct update_plane_addr_params { 74 struct dc *dc; 75 struct pipe_ctx *pipe_ctx; 76 }; 77 78 struct set_input_transfer_func_params { 79 struct dc *dc; 80 struct pipe_ctx *pipe_ctx; 81 struct dc_plane_state *plane_state; 82 }; 83 84 struct program_gamut_remap_params { 85 struct pipe_ctx *pipe_ctx; 86 }; 87 88 struct program_manual_trigger_params { 89 struct pipe_ctx *pipe_ctx; 90 }; 91 92 struct send_dmcub_cmd_params { 93 struct dc_context *ctx; 94 union dmub_rb_cmd *cmd; 95 enum dm_dmub_wait_type wait_type; 96 }; 97 98 struct setup_dpp_params { 99 struct pipe_ctx *pipe_ctx; 100 }; 101 102 struct program_bias_and_scale_params { 103 struct pipe_ctx *pipe_ctx; 104 }; 105 106 struct set_output_transfer_func_params { 107 struct dc *dc; 108 struct pipe_ctx *pipe_ctx; 109 const struct dc_stream_state *stream; 110 }; 111 112 struct update_visual_confirm_params { 113 struct dc *dc; 114 struct pipe_ctx *pipe_ctx; 115 int mpcc_id; 116 }; 117 118 struct power_on_mpc_mem_pwr_params { 119 struct mpc *mpc; 120 int mpcc_id; 121 bool power_on; 122 }; 123 124 struct set_output_csc_params { 125 struct mpc *mpc; 126 int opp_id; 127 const uint16_t *regval; 128 enum mpc_output_csc_mode ocsc_mode; 129 }; 130 131 struct set_ocsc_default_params { 132 struct mpc *mpc; 133 int opp_id; 134 enum dc_color_space color_space; 135 enum mpc_output_csc_mode ocsc_mode; 136 }; 137 138 struct subvp_save_surf_addr { 139 struct dc_dmub_srv *dc_dmub_srv; 140 const struct dc_plane_address *addr; 141 uint8_t subvp_index; 142 }; 143 144 union block_sequence_params { 145 struct update_plane_addr_params update_plane_addr_params; 146 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 147 struct pipe_control_lock_params pipe_control_lock_params; 148 struct set_flip_control_gsl_params set_flip_control_gsl_params; 149 struct program_triplebuffer_params program_triplebuffer_params; 150 struct set_input_transfer_func_params set_input_transfer_func_params; 151 struct program_gamut_remap_params program_gamut_remap_params; 152 struct program_manual_trigger_params program_manual_trigger_params; 153 struct send_dmcub_cmd_params send_dmcub_cmd_params; 154 struct setup_dpp_params setup_dpp_params; 155 struct program_bias_and_scale_params program_bias_and_scale_params; 156 struct set_output_transfer_func_params set_output_transfer_func_params; 157 struct update_visual_confirm_params update_visual_confirm_params; 158 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 159 struct set_output_csc_params set_output_csc_params; 160 struct set_ocsc_default_params set_ocsc_default_params; 161 struct subvp_save_surf_addr subvp_save_surf_addr; 162 }; 163 164 enum block_sequence_func { 165 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 166 OPTC_PIPE_CONTROL_LOCK, 167 HUBP_SET_FLIP_CONTROL_GSL, 168 HUBP_PROGRAM_TRIPLEBUFFER, 169 HUBP_UPDATE_PLANE_ADDR, 170 DPP_SET_INPUT_TRANSFER_FUNC, 171 DPP_PROGRAM_GAMUT_REMAP, 172 OPTC_PROGRAM_MANUAL_TRIGGER, 173 DMUB_SEND_DMCUB_CMD, 174 DPP_SETUP_DPP, 175 DPP_PROGRAM_BIAS_AND_SCALE, 176 DPP_SET_OUTPUT_TRANSFER_FUNC, 177 MPC_UPDATE_VISUAL_CONFIRM, 178 MPC_POWER_ON_MPC_MEM_PWR, 179 MPC_SET_OUTPUT_CSC, 180 MPC_SET_OCSC_DEFAULT, 181 DMUB_SUBVP_SAVE_SURF_ADDR, 182 }; 183 184 struct block_sequence { 185 union block_sequence_params params; 186 enum block_sequence_func func; 187 }; 188 189 struct hw_sequencer_funcs { 190 void (*hardware_release)(struct dc *dc); 191 /* Embedded Display Related */ 192 void (*edp_power_control)(struct dc_link *link, bool enable); 193 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 194 void (*edp_wait_for_T12)(struct dc_link *link); 195 196 /* Pipe Programming Related */ 197 void (*init_hw)(struct dc *dc); 198 void (*power_down_on_boot)(struct dc *dc); 199 void (*enable_accelerated_mode)(struct dc *dc, 200 struct dc_state *context); 201 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 202 struct dc_state *context); 203 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 204 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 205 void (*apply_ctx_for_surface)(struct dc *dc, 206 const struct dc_stream_state *stream, 207 int num_planes, struct dc_state *context); 208 void (*program_front_end_for_ctx)(struct dc *dc, 209 struct dc_state *context); 210 void (*wait_for_pending_cleared)(struct dc *dc, 211 struct dc_state *context); 212 void (*post_unlock_program_front_end)(struct dc *dc, 213 struct dc_state *context); 214 void (*update_plane_addr)(const struct dc *dc, 215 struct pipe_ctx *pipe_ctx); 216 void (*update_dchub)(struct dce_hwseq *hws, 217 struct dchub_init_data *dh_data); 218 void (*wait_for_mpcc_disconnect)(struct dc *dc, 219 struct resource_pool *res_pool, 220 struct pipe_ctx *pipe_ctx); 221 void (*edp_backlight_control)( 222 struct dc_link *link, 223 bool enable); 224 void (*program_triplebuffer)(const struct dc *dc, 225 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 226 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 227 void (*power_down)(struct dc *dc); 228 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 229 230 /* Pipe Lock Related */ 231 void (*pipe_control_lock)(struct dc *dc, 232 struct pipe_ctx *pipe, bool lock); 233 void (*interdependent_update_lock)(struct dc *dc, 234 struct dc_state *context, bool lock); 235 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 236 bool flip_immediate); 237 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 238 239 /* Timing Related */ 240 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 241 struct crtc_position *position); 242 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 243 void (*calc_vupdate_position)( 244 struct dc *dc, 245 struct pipe_ctx *pipe_ctx, 246 uint32_t *start_line, 247 uint32_t *end_line); 248 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 249 int group_size, struct pipe_ctx *grouped_pipes[]); 250 void (*enable_timing_synchronization)(struct dc *dc, 251 struct dc_state *state, 252 int group_index, int group_size, 253 struct pipe_ctx *grouped_pipes[]); 254 void (*enable_vblanks_synchronization)(struct dc *dc, 255 int group_index, int group_size, 256 struct pipe_ctx *grouped_pipes[]); 257 void (*setup_periodic_interrupt)(struct dc *dc, 258 struct pipe_ctx *pipe_ctx); 259 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 260 struct dc_crtc_timing_adjust adjust); 261 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 262 int num_pipes, 263 const struct dc_static_screen_params *events); 264 265 /* Stream Related */ 266 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 267 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 268 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 269 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 270 struct dc_link_settings *link_settings); 271 272 /* Bandwidth Related */ 273 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 274 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 275 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 276 277 /* Infopacket Related */ 278 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 279 void (*send_immediate_sdp_message)( 280 struct pipe_ctx *pipe_ctx, 281 const uint8_t *custom_sdp_message, 282 unsigned int sdp_message_size); 283 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 284 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 285 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 286 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 287 288 /* Cursor Related */ 289 void (*set_cursor_position)(struct pipe_ctx *pipe); 290 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 291 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 292 293 /* Colour Related */ 294 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 295 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 296 enum dc_color_space colorspace, 297 uint16_t *matrix, int opp_id); 298 299 /* VM Related */ 300 int (*init_sys_ctx)(struct dce_hwseq *hws, 301 struct dc *dc, 302 struct dc_phy_addr_space_config *pa_config); 303 void (*init_vm_ctx)(struct dce_hwseq *hws, 304 struct dc *dc, 305 struct dc_virtual_addr_space_config *va_config, 306 int vmid); 307 308 /* Writeback Related */ 309 void (*update_writeback)(struct dc *dc, 310 struct dc_writeback_info *wb_info, 311 struct dc_state *context); 312 void (*enable_writeback)(struct dc *dc, 313 struct dc_writeback_info *wb_info, 314 struct dc_state *context); 315 void (*disable_writeback)(struct dc *dc, 316 unsigned int dwb_pipe_inst); 317 318 bool (*mmhubbub_warmup)(struct dc *dc, 319 unsigned int num_dwb, 320 struct dc_writeback_info *wb_info); 321 322 /* Clock Related */ 323 enum dc_status (*set_clock)(struct dc *dc, 324 enum dc_clock_type clock_type, 325 uint32_t clk_khz, uint32_t stepping); 326 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 327 struct dc_clock_config *clock_cfg); 328 void (*optimize_pwr_state)(const struct dc *dc, 329 struct dc_state *context); 330 void (*exit_optimized_pwr_state)(const struct dc *dc, 331 struct dc_state *context); 332 333 /* Audio Related */ 334 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 335 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 336 337 /* Stereo 3D Related */ 338 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 339 340 /* HW State Logging Related */ 341 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 342 void (*log_color_state)(struct dc *dc, 343 struct dc_log_buffer_ctx *log_ctx); 344 void (*get_hw_state)(struct dc *dc, char *pBuf, 345 unsigned int bufSize, unsigned int mask); 346 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 347 348 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 349 uint32_t backlight_pwm_u16_16, 350 uint32_t frame_ramp); 351 352 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 353 354 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 355 356 void (*enable_dp_link_output)(struct dc_link *link, 357 const struct link_resource *link_res, 358 enum signal_type signal, 359 enum clock_source_id clock_source, 360 const struct dc_link_settings *link_settings); 361 void (*enable_tmds_link_output)(struct dc_link *link, 362 const struct link_resource *link_res, 363 enum signal_type signal, 364 enum clock_source_id clock_source, 365 enum dc_color_depth color_depth, 366 uint32_t pixel_clock); 367 void (*enable_lvds_link_output)(struct dc_link *link, 368 const struct link_resource *link_res, 369 enum clock_source_id clock_source, 370 uint32_t pixel_clock); 371 void (*disable_link_output)(struct dc_link *link, 372 const struct link_resource *link_res, 373 enum signal_type signal); 374 375 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 376 377 /* Idle Optimization Related */ 378 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 379 380 bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane, 381 struct dc_cursor_attributes *cursor_attr); 382 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 383 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 384 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 385 void (*subvp_pipe_control_lock)(struct dc *dc, 386 struct dc_state *context, 387 bool lock, 388 bool should_lock_all_pipes, 389 struct pipe_ctx *top_pipe_to_program, 390 bool subvp_prev_use); 391 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 392 393 void (*z10_restore)(const struct dc *dc); 394 void (*z10_save_init)(struct dc *dc); 395 bool (*is_abm_supported)(struct dc *dc, 396 struct dc_state *context, struct dc_stream_state *stream); 397 398 void (*set_disp_pattern_generator)(const struct dc *dc, 399 struct pipe_ctx *pipe_ctx, 400 enum controller_dp_test_pattern test_pattern, 401 enum controller_dp_color_space color_space, 402 enum dc_color_depth color_depth, 403 const struct tg_color *solid_color, 404 int width, int height, int offset); 405 void (*blank_phantom)(struct dc *dc, 406 struct timing_generator *tg, 407 int width, 408 int height); 409 void (*update_visual_confirm_color)(struct dc *dc, 410 struct pipe_ctx *pipe_ctx, 411 int mpcc_id); 412 void (*update_phantom_vp_position)(struct dc *dc, 413 struct dc_state *context, 414 struct pipe_ctx *phantom_pipe); 415 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 416 417 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 418 struct pg_block_update *update_state); 419 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 420 struct pg_block_update *update_state); 421 void (*hw_block_power_up)(struct dc *dc, 422 struct pg_block_update *update_state); 423 void (*hw_block_power_down)(struct dc *dc, 424 struct pg_block_update *update_state); 425 void (*root_clock_control)(struct dc *dc, 426 struct pg_block_update *update_state, bool power_on); 427 void (*set_idle_state)(const struct dc *dc, bool allow_idle); 428 uint32_t (*get_idle_state)(const struct dc *dc); 429 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 430 const struct dc_state *cur_ctx, 431 const struct dc_state *new_ctx); 432 }; 433 434 void color_space_to_black_color( 435 const struct dc *dc, 436 enum dc_color_space colorspace, 437 struct tg_color *black_color); 438 439 bool hwss_wait_for_blank_complete( 440 struct timing_generator *tg); 441 442 const uint16_t *find_color_matrix( 443 enum dc_color_space color_space, 444 uint32_t *array_size); 445 446 void get_surface_tile_visual_confirm_color( 447 struct pipe_ctx *pipe_ctx, 448 struct tg_color *color); 449 void get_surface_visual_confirm_color( 450 const struct pipe_ctx *pipe_ctx, 451 struct tg_color *color); 452 453 void get_hdr_visual_confirm_color( 454 struct pipe_ctx *pipe_ctx, 455 struct tg_color *color); 456 void get_mpctree_visual_confirm_color( 457 struct pipe_ctx *pipe_ctx, 458 struct tg_color *color); 459 460 void get_subvp_visual_confirm_color( 461 struct pipe_ctx *pipe_ctx, 462 struct tg_color *color); 463 464 void get_mclk_switch_visual_confirm_color( 465 struct pipe_ctx *pipe_ctx, 466 struct tg_color *color); 467 468 void set_p_state_switch_method( 469 struct dc *dc, 470 struct dc_state *context, 471 struct pipe_ctx *pipe_ctx); 472 473 void hwss_execute_sequence(struct dc *dc, 474 struct block_sequence block_sequence[], 475 int num_steps); 476 477 void hwss_build_fast_sequence(struct dc *dc, 478 struct dc_dmub_cmd *dc_dmub_cmd, 479 unsigned int dmub_cmd_count, 480 struct block_sequence block_sequence[], 481 int *num_steps, 482 struct pipe_ctx *pipe_ctx, 483 struct dc_stream_status *stream_status); 484 485 void hwss_send_dmcub_cmd(union block_sequence_params *params); 486 487 void hwss_program_manual_trigger(union block_sequence_params *params); 488 489 void hwss_setup_dpp(union block_sequence_params *params); 490 491 void hwss_program_bias_and_scale(union block_sequence_params *params); 492 493 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 494 495 void hwss_set_output_csc(union block_sequence_params *params); 496 497 void hwss_set_ocsc_default(union block_sequence_params *params); 498 499 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 500 501 #endif /* __DC_HW_SEQUENCER_H__ */ 502