1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 50 struct subvp_pipe_control_lock_fast_params { 51 struct dc *dc; 52 bool lock; 53 bool subvp_immediate_flip; 54 }; 55 56 struct pipe_control_lock_params { 57 struct dc *dc; 58 struct pipe_ctx *pipe_ctx; 59 bool lock; 60 }; 61 62 struct set_flip_control_gsl_params { 63 struct pipe_ctx *pipe_ctx; 64 bool flip_immediate; 65 }; 66 67 struct program_triplebuffer_params { 68 const struct dc *dc; 69 struct pipe_ctx *pipe_ctx; 70 bool enableTripleBuffer; 71 }; 72 73 struct update_plane_addr_params { 74 struct dc *dc; 75 struct pipe_ctx *pipe_ctx; 76 }; 77 78 struct set_input_transfer_func_params { 79 struct dc *dc; 80 struct pipe_ctx *pipe_ctx; 81 struct dc_plane_state *plane_state; 82 }; 83 84 struct program_gamut_remap_params { 85 struct pipe_ctx *pipe_ctx; 86 }; 87 88 struct program_manual_trigger_params { 89 struct pipe_ctx *pipe_ctx; 90 }; 91 92 struct send_dmcub_cmd_params { 93 struct dc_context *ctx; 94 union dmub_rb_cmd *cmd; 95 enum dm_dmub_wait_type wait_type; 96 }; 97 98 struct setup_dpp_params { 99 struct pipe_ctx *pipe_ctx; 100 }; 101 102 struct program_bias_and_scale_params { 103 struct pipe_ctx *pipe_ctx; 104 }; 105 106 struct set_output_transfer_func_params { 107 struct dc *dc; 108 struct pipe_ctx *pipe_ctx; 109 const struct dc_stream_state *stream; 110 }; 111 112 struct update_visual_confirm_params { 113 struct dc *dc; 114 struct pipe_ctx *pipe_ctx; 115 int mpcc_id; 116 }; 117 118 struct power_on_mpc_mem_pwr_params { 119 struct mpc *mpc; 120 int mpcc_id; 121 bool power_on; 122 }; 123 124 struct set_output_csc_params { 125 struct mpc *mpc; 126 int opp_id; 127 const uint16_t *regval; 128 enum mpc_output_csc_mode ocsc_mode; 129 }; 130 131 struct set_ocsc_default_params { 132 struct mpc *mpc; 133 int opp_id; 134 enum dc_color_space color_space; 135 enum mpc_output_csc_mode ocsc_mode; 136 }; 137 138 struct subvp_save_surf_addr { 139 struct dc_dmub_srv *dc_dmub_srv; 140 const struct dc_plane_address *addr; 141 uint8_t subvp_index; 142 }; 143 144 struct fams2_global_control_lock_fast_params { 145 struct dc *dc; 146 bool is_required; 147 bool lock; 148 }; 149 150 union block_sequence_params { 151 struct update_plane_addr_params update_plane_addr_params; 152 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 153 struct pipe_control_lock_params pipe_control_lock_params; 154 struct set_flip_control_gsl_params set_flip_control_gsl_params; 155 struct program_triplebuffer_params program_triplebuffer_params; 156 struct set_input_transfer_func_params set_input_transfer_func_params; 157 struct program_gamut_remap_params program_gamut_remap_params; 158 struct program_manual_trigger_params program_manual_trigger_params; 159 struct send_dmcub_cmd_params send_dmcub_cmd_params; 160 struct setup_dpp_params setup_dpp_params; 161 struct program_bias_and_scale_params program_bias_and_scale_params; 162 struct set_output_transfer_func_params set_output_transfer_func_params; 163 struct update_visual_confirm_params update_visual_confirm_params; 164 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 165 struct set_output_csc_params set_output_csc_params; 166 struct set_ocsc_default_params set_ocsc_default_params; 167 struct subvp_save_surf_addr subvp_save_surf_addr; 168 struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; 169 }; 170 171 enum block_sequence_func { 172 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 173 OPTC_PIPE_CONTROL_LOCK, 174 HUBP_SET_FLIP_CONTROL_GSL, 175 HUBP_PROGRAM_TRIPLEBUFFER, 176 HUBP_UPDATE_PLANE_ADDR, 177 DPP_SET_INPUT_TRANSFER_FUNC, 178 DPP_PROGRAM_GAMUT_REMAP, 179 OPTC_PROGRAM_MANUAL_TRIGGER, 180 DMUB_SEND_DMCUB_CMD, 181 DPP_SETUP_DPP, 182 DPP_PROGRAM_BIAS_AND_SCALE, 183 DPP_SET_OUTPUT_TRANSFER_FUNC, 184 MPC_UPDATE_VISUAL_CONFIRM, 185 MPC_POWER_ON_MPC_MEM_PWR, 186 MPC_SET_OUTPUT_CSC, 187 MPC_SET_OCSC_DEFAULT, 188 DMUB_SUBVP_SAVE_SURF_ADDR, 189 DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST, 190 191 }; 192 193 struct block_sequence { 194 union block_sequence_params params; 195 enum block_sequence_func func; 196 }; 197 198 struct hw_sequencer_funcs { 199 void (*hardware_release)(struct dc *dc); 200 /* Embedded Display Related */ 201 void (*edp_power_control)(struct dc_link *link, bool enable); 202 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 203 void (*edp_wait_for_T12)(struct dc_link *link); 204 205 /* Pipe Programming Related */ 206 void (*init_hw)(struct dc *dc); 207 void (*power_down_on_boot)(struct dc *dc); 208 void (*enable_accelerated_mode)(struct dc *dc, 209 struct dc_state *context); 210 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 211 struct dc_state *context); 212 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 213 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 214 void (*apply_ctx_for_surface)(struct dc *dc, 215 const struct dc_stream_state *stream, 216 int num_planes, struct dc_state *context); 217 void (*program_front_end_for_ctx)(struct dc *dc, 218 struct dc_state *context); 219 void (*wait_for_pending_cleared)(struct dc *dc, 220 struct dc_state *context); 221 void (*post_unlock_program_front_end)(struct dc *dc, 222 struct dc_state *context); 223 void (*update_plane_addr)(const struct dc *dc, 224 struct pipe_ctx *pipe_ctx); 225 void (*update_dchub)(struct dce_hwseq *hws, 226 struct dchub_init_data *dh_data); 227 void (*wait_for_mpcc_disconnect)(struct dc *dc, 228 struct resource_pool *res_pool, 229 struct pipe_ctx *pipe_ctx); 230 void (*edp_backlight_control)( 231 struct dc_link *link, 232 bool enable); 233 void (*program_triplebuffer)(const struct dc *dc, 234 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 235 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 236 void (*power_down)(struct dc *dc); 237 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 238 239 /* Pipe Lock Related */ 240 void (*pipe_control_lock)(struct dc *dc, 241 struct pipe_ctx *pipe, bool lock); 242 void (*interdependent_update_lock)(struct dc *dc, 243 struct dc_state *context, bool lock); 244 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 245 bool flip_immediate); 246 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 247 248 /* Timing Related */ 249 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 250 struct crtc_position *position); 251 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 252 void (*calc_vupdate_position)( 253 struct dc *dc, 254 struct pipe_ctx *pipe_ctx, 255 uint32_t *start_line, 256 uint32_t *end_line); 257 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 258 int group_size, struct pipe_ctx *grouped_pipes[]); 259 void (*enable_timing_synchronization)(struct dc *dc, 260 struct dc_state *state, 261 int group_index, int group_size, 262 struct pipe_ctx *grouped_pipes[]); 263 void (*enable_vblanks_synchronization)(struct dc *dc, 264 int group_index, int group_size, 265 struct pipe_ctx *grouped_pipes[]); 266 void (*setup_periodic_interrupt)(struct dc *dc, 267 struct pipe_ctx *pipe_ctx); 268 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 269 struct dc_crtc_timing_adjust adjust); 270 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 271 int num_pipes, 272 const struct dc_static_screen_params *events); 273 274 /* Stream Related */ 275 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 276 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 277 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 278 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 279 struct dc_link_settings *link_settings); 280 281 /* Bandwidth Related */ 282 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 283 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 284 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 285 286 /* Infopacket Related */ 287 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 288 void (*send_immediate_sdp_message)( 289 struct pipe_ctx *pipe_ctx, 290 const uint8_t *custom_sdp_message, 291 unsigned int sdp_message_size); 292 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 293 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 294 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 295 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 296 297 /* Cursor Related */ 298 void (*set_cursor_position)(struct pipe_ctx *pipe); 299 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 300 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 301 302 /* Colour Related */ 303 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 304 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 305 enum dc_color_space colorspace, 306 uint16_t *matrix, int opp_id); 307 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 308 309 /* VM Related */ 310 int (*init_sys_ctx)(struct dce_hwseq *hws, 311 struct dc *dc, 312 struct dc_phy_addr_space_config *pa_config); 313 void (*init_vm_ctx)(struct dce_hwseq *hws, 314 struct dc *dc, 315 struct dc_virtual_addr_space_config *va_config, 316 int vmid); 317 318 /* Writeback Related */ 319 void (*update_writeback)(struct dc *dc, 320 struct dc_writeback_info *wb_info, 321 struct dc_state *context); 322 void (*enable_writeback)(struct dc *dc, 323 struct dc_writeback_info *wb_info, 324 struct dc_state *context); 325 void (*disable_writeback)(struct dc *dc, 326 unsigned int dwb_pipe_inst); 327 328 bool (*mmhubbub_warmup)(struct dc *dc, 329 unsigned int num_dwb, 330 struct dc_writeback_info *wb_info); 331 332 /* Clock Related */ 333 enum dc_status (*set_clock)(struct dc *dc, 334 enum dc_clock_type clock_type, 335 uint32_t clk_khz, uint32_t stepping); 336 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 337 struct dc_clock_config *clock_cfg); 338 void (*optimize_pwr_state)(const struct dc *dc, 339 struct dc_state *context); 340 void (*exit_optimized_pwr_state)(const struct dc *dc, 341 struct dc_state *context); 342 void (*calculate_pix_rate_divider)(struct dc *dc, 343 struct dc_state *context, 344 const struct dc_stream_state *stream); 345 346 /* Audio Related */ 347 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 348 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 349 350 /* Stereo 3D Related */ 351 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 352 353 /* HW State Logging Related */ 354 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 355 void (*log_color_state)(struct dc *dc, 356 struct dc_log_buffer_ctx *log_ctx); 357 void (*get_hw_state)(struct dc *dc, char *pBuf, 358 unsigned int bufSize, unsigned int mask); 359 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 360 361 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 362 uint32_t backlight_pwm_u16_16, 363 uint32_t frame_ramp); 364 365 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 366 367 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 368 369 void (*enable_dp_link_output)(struct dc_link *link, 370 const struct link_resource *link_res, 371 enum signal_type signal, 372 enum clock_source_id clock_source, 373 const struct dc_link_settings *link_settings); 374 void (*enable_tmds_link_output)(struct dc_link *link, 375 const struct link_resource *link_res, 376 enum signal_type signal, 377 enum clock_source_id clock_source, 378 enum dc_color_depth color_depth, 379 uint32_t pixel_clock); 380 void (*enable_lvds_link_output)(struct dc_link *link, 381 const struct link_resource *link_res, 382 enum clock_source_id clock_source, 383 uint32_t pixel_clock); 384 void (*disable_link_output)(struct dc_link *link, 385 const struct link_resource *link_res, 386 enum signal_type signal); 387 388 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 389 390 /* Idle Optimization Related */ 391 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 392 393 bool (*does_plane_fit_in_mall)(struct dc *dc, 394 unsigned int pitch, 395 unsigned int height, 396 enum surface_pixel_format format, 397 struct dc_cursor_attributes *cursor_attr); 398 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 399 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 400 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 401 void (*subvp_pipe_control_lock)(struct dc *dc, 402 struct dc_state *context, 403 bool lock, 404 bool should_lock_all_pipes, 405 struct pipe_ctx *top_pipe_to_program, 406 bool subvp_prev_use); 407 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 408 409 void (*z10_restore)(const struct dc *dc); 410 void (*z10_save_init)(struct dc *dc); 411 bool (*is_abm_supported)(struct dc *dc, 412 struct dc_state *context, struct dc_stream_state *stream); 413 414 void (*set_disp_pattern_generator)(const struct dc *dc, 415 struct pipe_ctx *pipe_ctx, 416 enum controller_dp_test_pattern test_pattern, 417 enum controller_dp_color_space color_space, 418 enum dc_color_depth color_depth, 419 const struct tg_color *solid_color, 420 int width, int height, int offset); 421 void (*blank_phantom)(struct dc *dc, 422 struct timing_generator *tg, 423 int width, 424 int height); 425 void (*update_visual_confirm_color)(struct dc *dc, 426 struct pipe_ctx *pipe_ctx, 427 int mpcc_id); 428 void (*update_phantom_vp_position)(struct dc *dc, 429 struct dc_state *context, 430 struct pipe_ctx *phantom_pipe); 431 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 432 433 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 434 struct pg_block_update *update_state); 435 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 436 struct pg_block_update *update_state); 437 void (*hw_block_power_up)(struct dc *dc, 438 struct pg_block_update *update_state); 439 void (*hw_block_power_down)(struct dc *dc, 440 struct pg_block_update *update_state); 441 void (*root_clock_control)(struct dc *dc, 442 struct pg_block_update *update_state, bool power_on); 443 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 444 const struct dc_state *cur_ctx, 445 const struct dc_state *new_ctx); 446 void (*fams2_global_control_lock)(struct dc *dc, 447 struct dc_state *context, 448 bool lock); 449 void (*fams2_update_config)(struct dc *dc, 450 struct dc_state *context, 451 bool enable); 452 void (*fams2_global_control_lock_fast)(union block_sequence_params *params); 453 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 454 }; 455 456 void color_space_to_black_color( 457 const struct dc *dc, 458 enum dc_color_space colorspace, 459 struct tg_color *black_color); 460 461 bool hwss_wait_for_blank_complete( 462 struct timing_generator *tg); 463 464 const uint16_t *find_color_matrix( 465 enum dc_color_space color_space, 466 uint32_t *array_size); 467 468 void get_surface_tile_visual_confirm_color( 469 struct pipe_ctx *pipe_ctx, 470 struct tg_color *color); 471 void get_surface_visual_confirm_color( 472 const struct pipe_ctx *pipe_ctx, 473 struct tg_color *color); 474 475 void get_hdr_visual_confirm_color( 476 struct pipe_ctx *pipe_ctx, 477 struct tg_color *color); 478 void get_mpctree_visual_confirm_color( 479 struct pipe_ctx *pipe_ctx, 480 struct tg_color *color); 481 482 void get_subvp_visual_confirm_color( 483 struct pipe_ctx *pipe_ctx, 484 struct tg_color *color); 485 486 void get_fams2_visual_confirm_color( 487 struct dc *dc, 488 struct dc_state *context, 489 struct pipe_ctx *pipe_ctx, 490 struct tg_color *color); 491 492 void get_mclk_switch_visual_confirm_color( 493 struct pipe_ctx *pipe_ctx, 494 struct tg_color *color); 495 496 void set_p_state_switch_method( 497 struct dc *dc, 498 struct dc_state *context, 499 struct pipe_ctx *pipe_ctx); 500 501 void hwss_execute_sequence(struct dc *dc, 502 struct block_sequence block_sequence[], 503 int num_steps); 504 505 void hwss_build_fast_sequence(struct dc *dc, 506 struct dc_dmub_cmd *dc_dmub_cmd, 507 unsigned int dmub_cmd_count, 508 struct block_sequence block_sequence[], 509 unsigned int *num_steps, 510 struct pipe_ctx *pipe_ctx, 511 struct dc_stream_status *stream_status, 512 struct dc_state *context); 513 514 void hwss_send_dmcub_cmd(union block_sequence_params *params); 515 516 void hwss_program_manual_trigger(union block_sequence_params *params); 517 518 void hwss_setup_dpp(union block_sequence_params *params); 519 520 void hwss_program_bias_and_scale(union block_sequence_params *params); 521 522 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 523 524 void hwss_set_output_csc(union block_sequence_params *params); 525 526 void hwss_set_ocsc_default(union block_sequence_params *params); 527 528 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 529 530 #endif /* __DC_HW_SEQUENCER_H__ */ 531