1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 /* 29 * Pre-requisites: headers required by header of this unit 30 */ 31 #include "include/gpio_types.h" 32 33 /* 34 * Header of this unit 35 */ 36 37 #include "hw_translate.h" 38 39 /* 40 * Post-requisites: headers required by this unit 41 */ 42 43 #if defined(CONFIG_DRM_AMD_DC_SI) 44 #include "dce60/hw_translate_dce60.h" 45 #endif 46 #include "dce80/hw_translate_dce80.h" 47 #include "dce110/hw_translate_dce110.h" 48 #include "dce120/hw_translate_dce120.h" 49 #include "dcn10/hw_translate_dcn10.h" 50 #include "dcn20/hw_translate_dcn20.h" 51 #include "dcn21/hw_translate_dcn21.h" 52 #include "dcn30/hw_translate_dcn30.h" 53 #include "dcn315/hw_translate_dcn315.h" 54 #include "dcn32/hw_translate_dcn32.h" 55 #include "dcn401/hw_translate_dcn401.h" 56 #include "dcn42/hw_translate_dcn42.h" 57 #include "dcn42b/hw_translate_dcn42b.h" 58 #include "dcn60/hw_translate_dcn60.h" 59 60 /* 61 * This unit 62 */ 63 64 bool dal_hw_translate_init( 65 struct hw_translate *translate, 66 enum dce_version dce_version, 67 enum dce_environment dce_environment) 68 { 69 (void)dce_environment; 70 switch (dce_version) { 71 #if defined(CONFIG_DRM_AMD_DC_SI) 72 case DCE_VERSION_6_0: 73 case DCE_VERSION_6_1: 74 case DCE_VERSION_6_4: 75 dal_hw_translate_dce60_init(translate); 76 return true; 77 #endif 78 case DCE_VERSION_8_0: 79 case DCE_VERSION_8_1: 80 case DCE_VERSION_8_3: 81 dal_hw_translate_dce80_init(translate); 82 return true; 83 case DCE_VERSION_10_0: 84 case DCE_VERSION_11_0: 85 case DCE_VERSION_11_2: 86 case DCE_VERSION_11_22: 87 dal_hw_translate_dce110_init(translate); 88 return true; 89 case DCE_VERSION_12_0: 90 case DCE_VERSION_12_1: 91 dal_hw_translate_dce120_init(translate); 92 return true; 93 case DCN_VERSION_1_0: 94 case DCN_VERSION_1_01: 95 dal_hw_translate_dcn10_init(translate); 96 return true; 97 case DCN_VERSION_2_0: 98 dal_hw_translate_dcn20_init(translate); 99 return true; 100 case DCN_VERSION_2_01: 101 case DCN_VERSION_2_1: 102 dal_hw_translate_dcn21_init(translate); 103 return true; 104 case DCN_VERSION_3_0: 105 case DCN_VERSION_3_01: 106 case DCN_VERSION_3_02: 107 case DCN_VERSION_3_03: 108 case DCN_VERSION_3_1: 109 case DCN_VERSION_3_14: 110 case DCN_VERSION_3_16: 111 dal_hw_translate_dcn30_init(translate); 112 return true; 113 case DCN_VERSION_3_15: 114 dal_hw_translate_dcn315_init(translate); 115 return true; 116 case DCN_VERSION_3_2: 117 case DCN_VERSION_3_21: 118 case DCN_VERSION_3_5: 119 case DCN_VERSION_3_51: 120 case DCN_VERSION_3_6: 121 dal_hw_translate_dcn32_init(translate); 122 return true; 123 case DCN_VERSION_4_01: 124 dal_hw_translate_dcn401_init(translate); 125 return true; 126 case DCN_VERSION_4_2: 127 dal_hw_translate_dcn42_init(translate); 128 return true; 129 case DCN_VERSION_4_2B: 130 dal_hw_translate_dcn42b_init(translate); 131 return true; 132 case DCN_VERSION_6_0: 133 dal_hw_translate_dcn60_init(translate); 134 return true; 135 default: 136 BREAK_TO_DEBUGGER(); 137 return false; 138 } 139 } 140 141 bool dal_hw_translate_gpio_offset_to_id( 142 const struct gpio_id_offset_entry *table, 143 uint32_t table_size, 144 uint32_t offset, 145 uint32_t mask, 146 enum gpio_id *id, 147 uint32_t *en) 148 { 149 uint32_t i; 150 151 for (i = 0; i < table_size; i++) { 152 const struct gpio_id_offset_entry *entry = &table[i]; 153 154 if (entry->offset != offset) 155 continue; 156 157 if (entry->check_mask && entry->mask != mask) 158 continue; 159 160 *id = entry->id; 161 *en = entry->en; 162 163 return true; 164 } 165 166 return false; 167 } 168 169 /* we don't care about the GPIO_ID for DDC 170 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK 171 * directly in the create method 172 */ 173 bool dal_hw_translate_gpio_ddc_offset_to_id( 174 const struct gpio_ddc_offset_entry *table, 175 uint32_t table_size, 176 uint32_t offset, 177 uint32_t *en) 178 { 179 uint32_t i; 180 181 for (i = 0; i < table_size; i++) { 182 const struct gpio_ddc_offset_entry *entry = &table[i]; 183 184 if (entry->offset != offset) 185 continue; 186 187 *en = entry->en; 188 189 return true; 190 } 191 192 return false; 193 } 194 195 bool dal_hw_translate_id_to_offset( 196 const struct gpio_pin_entry *table, 197 uint32_t table_size, 198 enum gpio_id id, 199 uint32_t en, 200 struct gpio_pin_info *info) 201 { 202 uint32_t i; 203 204 for (i = 0; i < table_size; i++) { 205 const struct gpio_pin_entry *entry = &table[i]; 206 207 if (entry->id != id || entry->en != en) 208 continue; 209 210 info->offset = entry->offset; 211 info->mask = entry->mask; 212 213 info->offset_y = info->offset + 2; 214 info->offset_en = info->offset + 1; 215 info->offset_mask = info->offset - 1; 216 217 info->mask_y = info->mask; 218 info->mask_en = info->mask; 219 info->mask_mask = info->mask; 220 221 return true; 222 } 223 224 return false; 225 } 226