1*4562236bSHarry Wentland /* 2*4562236bSHarry Wentland * Copyright 2012-16 Advanced Micro Devices, Inc. 3*4562236bSHarry Wentland * 4*4562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 5*4562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 6*4562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 7*4562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 9*4562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 10*4562236bSHarry Wentland * 11*4562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 12*4562236bSHarry Wentland * all copies or substantial portions of the Software. 13*4562236bSHarry Wentland * 14*4562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 21*4562236bSHarry Wentland * 22*4562236bSHarry Wentland * Authors: AMD 23*4562236bSHarry Wentland * 24*4562236bSHarry Wentland */ 25*4562236bSHarry Wentland 26*4562236bSHarry Wentland #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ 27*4562236bSHarry Wentland #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ 28*4562236bSHarry Wentland 29*4562236bSHarry Wentland #include "gpio_regs.h" 30*4562236bSHarry Wentland 31*4562236bSHarry Wentland #define ONE_MORE_0 1 32*4562236bSHarry Wentland #define ONE_MORE_1 2 33*4562236bSHarry Wentland #define ONE_MORE_2 3 34*4562236bSHarry Wentland #define ONE_MORE_3 4 35*4562236bSHarry Wentland #define ONE_MORE_4 5 36*4562236bSHarry Wentland #define ONE_MORE_5 6 37*4562236bSHarry Wentland 38*4562236bSHarry Wentland 39*4562236bSHarry Wentland #define HPD_GPIO_REG_LIST_ENTRY(type, cd, id) \ 40*4562236bSHarry Wentland .type ## _reg = REG(DC_GPIO_HPD_## type),\ 41*4562236bSHarry Wentland .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\ 42*4562236bSHarry Wentland .type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT 43*4562236bSHarry Wentland 44*4562236bSHarry Wentland #define HPD_GPIO_REG_LIST(id) \ 45*4562236bSHarry Wentland {\ 46*4562236bSHarry Wentland HPD_GPIO_REG_LIST_ENTRY(MASK, cd, id),\ 47*4562236bSHarry Wentland HPD_GPIO_REG_LIST_ENTRY(A, cd, id),\ 48*4562236bSHarry Wentland HPD_GPIO_REG_LIST_ENTRY(EN, cd, id),\ 49*4562236bSHarry Wentland HPD_GPIO_REG_LIST_ENTRY(Y, cd, id)\ 50*4562236bSHarry Wentland } 51*4562236bSHarry Wentland 52*4562236bSHarry Wentland #define HPD_REG_LIST(id) \ 53*4562236bSHarry Wentland HPD_GPIO_REG_LIST(ONE_MORE_ ## id), \ 54*4562236bSHarry Wentland .int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\ 55*4562236bSHarry Wentland .toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id) 56*4562236bSHarry Wentland 57*4562236bSHarry Wentland #define HPD_MASK_SH_LIST(mask_sh) \ 58*4562236bSHarry Wentland SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\ 59*4562236bSHarry Wentland SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\ 60*4562236bSHarry Wentland SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\ 61*4562236bSHarry Wentland SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh) 62*4562236bSHarry Wentland 63*4562236bSHarry Wentland struct hpd_registers { 64*4562236bSHarry Wentland struct gpio_registers gpio; 65*4562236bSHarry Wentland uint32_t int_status; 66*4562236bSHarry Wentland uint32_t toggle_filt_cntl; 67*4562236bSHarry Wentland }; 68*4562236bSHarry Wentland 69*4562236bSHarry Wentland struct hpd_sh_mask { 70*4562236bSHarry Wentland /* int_status */ 71*4562236bSHarry Wentland uint32_t DC_HPD_SENSE_DELAYED; 72*4562236bSHarry Wentland uint32_t DC_HPD_SENSE; 73*4562236bSHarry Wentland /* toggle_filt_cntl */ 74*4562236bSHarry Wentland uint32_t DC_HPD_CONNECT_INT_DELAY; 75*4562236bSHarry Wentland uint32_t DC_HPD_DISCONNECT_INT_DELAY; 76*4562236bSHarry Wentland }; 77*4562236bSHarry Wentland 78*4562236bSHarry Wentland 79*4562236bSHarry Wentland #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ */ 80