1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef _DML2_WRAPPER_H_ 28 #define _DML2_WRAPPER_H_ 29 30 #include "os_types.h" 31 32 #define DML2_MAX_NUM_DPM_LVL 30 33 34 struct dml2_context; 35 struct display_mode_lib_st; 36 struct dc; 37 struct pipe_ctx; 38 struct dc_plane_state; 39 struct dc_sink; 40 struct dc_stream_state; 41 struct resource_context; 42 struct display_stream_compressor; 43 44 // Configuration of the MALL on the SoC 45 struct dml2_soc_mall_info { 46 // Cache line size of 0 means MALL is not enabled/present 47 unsigned int cache_line_size_bytes; 48 unsigned int cache_num_ways; 49 unsigned int max_cab_allocation_bytes; 50 51 unsigned int mblk_width_pixels; 52 unsigned int mblk_size_bytes; 53 unsigned int mblk_height_4bpe_pixels; 54 unsigned int mblk_height_8bpe_pixels; 55 }; 56 57 // Output of DML2 for clock requirements 58 struct dml2_dcn_clocks { 59 unsigned int dispclk_khz; 60 unsigned int dcfclk_khz; 61 unsigned int fclk_khz; 62 unsigned int uclk_mts; 63 unsigned int phyclk_khz; 64 unsigned int socclk_khz; 65 unsigned int ref_dtbclk_khz; 66 bool p_state_supported; 67 unsigned int cab_num_ways_required; 68 unsigned int dcfclk_khz_ds; 69 }; 70 71 struct dml2_dc_callbacks { 72 struct dc *dc; 73 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 74 bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context); 75 bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm); 76 bool (*update_pipes_for_stream_with_slice_count)( 77 struct dc_state *new_ctx, 78 const struct dc_state *cur_ctx, 79 const struct resource_pool *pool, 80 const struct dc_stream_state *stream, 81 int new_slice_count); 82 bool (*update_pipes_for_plane_with_slice_count)( 83 struct dc_state *new_ctx, 84 const struct dc_state *cur_ctx, 85 const struct resource_pool *pool, 86 const struct dc_plane_state *plane, 87 int slice_count); 88 int (*get_odm_slice_index)(const struct pipe_ctx *opp_head); 89 int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe); 90 struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx); 91 }; 92 93 struct dml2_dc_svp_callbacks { 94 struct dc *dc; 95 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 96 struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc, 97 struct dc_state *state, 98 struct dc_stream_state *main_stream); 99 struct dc_plane_state* (*create_phantom_plane)(struct dc *dc, 100 struct dc_state *state, 101 struct dc_plane_state *main_plane); 102 enum dc_status (*add_phantom_stream)(struct dc *dc, 103 struct dc_state *state, 104 struct dc_stream_state *phantom_stream, 105 struct dc_stream_state *main_stream); 106 bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context); 107 bool (*remove_phantom_plane)(const struct dc *dc, 108 struct dc_stream_state *stream, 109 struct dc_plane_state *plane_state, 110 struct dc_state *context); 111 enum dc_status (*remove_phantom_stream)(struct dc *dc, 112 struct dc_state *state, 113 struct dc_stream_state *stream); 114 void (*release_phantom_plane)(const struct dc *dc, 115 struct dc_state *state, 116 struct dc_plane_state *plane); 117 void (*release_phantom_stream)(const struct dc *dc, 118 struct dc_state *state, 119 struct dc_stream_state *stream); 120 void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); 121 enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx); 122 enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream); 123 struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream); 124 }; 125 126 struct dml2_clks_table_entry { 127 unsigned int dcfclk_mhz; 128 unsigned int fclk_mhz; 129 unsigned int memclk_mhz; 130 unsigned int socclk_mhz; 131 unsigned int dtbclk_mhz; 132 unsigned int dispclk_mhz; 133 unsigned int dppclk_mhz; 134 }; 135 136 struct dml2_clks_num_entries { 137 unsigned int num_dcfclk_levels; 138 unsigned int num_fclk_levels; 139 unsigned int num_memclk_levels; 140 unsigned int num_socclk_levels; 141 unsigned int num_dtbclk_levels; 142 unsigned int num_dispclk_levels; 143 unsigned int num_dppclk_levels; 144 }; 145 146 struct dml2_clks_limit_table { 147 struct dml2_clks_table_entry clk_entries[DML2_MAX_NUM_DPM_LVL]; 148 struct dml2_clks_num_entries num_entries_per_clk; 149 unsigned int num_states; 150 }; 151 152 // Various overrides, per ASIC or per SKU specific, or for debugging purpose when/if available 153 struct dml2_soc_bbox_overrides { 154 double xtalclk_mhz; 155 double dchub_refclk_mhz; 156 double dprefclk_mhz; 157 double disp_pll_vco_speed_mhz; 158 double urgent_latency_us; 159 double sr_exit_latency_us; 160 double sr_enter_plus_exit_latency_us; 161 double sr_exit_z8_time_us; 162 double sr_enter_plus_exit_z8_time_us; 163 double dram_clock_change_latency_us; 164 double fclk_change_latency_us; 165 unsigned int dram_num_chan; 166 unsigned int dram_chanel_width_bytes; 167 struct dml2_clks_limit_table clks_table; 168 }; 169 170 struct dml2_configuration_options { 171 int dcn_pipe_count; 172 bool use_native_pstate_optimization; 173 bool enable_windowed_mpo_odm; 174 bool use_native_soc_bb_construction; 175 bool skip_hw_state_mapping; 176 bool optimize_odm_4to1; 177 bool minimize_dispclk_using_odm; 178 bool override_det_buffer_size_kbytes; 179 struct dml2_dc_callbacks callbacks; 180 struct { 181 bool force_disable_subvp; 182 bool force_enable_subvp; 183 unsigned int subvp_fw_processing_delay_us; 184 unsigned int subvp_pstate_allow_width_us; 185 unsigned int subvp_prefetch_end_to_mall_start_us; 186 unsigned int subvp_swath_height_margin_lines; 187 struct dml2_dc_svp_callbacks callbacks; 188 } svp_pstate; 189 struct dml2_soc_mall_info mall_cfg; 190 struct dml2_soc_bbox_overrides bbox_overrides; 191 unsigned int max_segments_per_hubp; 192 unsigned int det_segment_size; 193 bool map_dc_pipes_with_callbacks; 194 }; 195 196 /* 197 * dml2_create - Creates dml2_context. 198 * @in_dc: dc. 199 * @config: dml2 configuration options. 200 * @dml2: Created dml2 context. 201 * 202 * Create and destroy of DML2 is done as part of dc_state creation 203 * and dc_state_free. DML2 IP, SOC and STATES are initialized at 204 * creation time. 205 * 206 * Return: True if dml2 is successfully created, false otherwise. 207 */ 208 bool dml2_create(const struct dc *in_dc, 209 const struct dml2_configuration_options *config, 210 struct dml2_context **dml2); 211 212 void dml2_destroy(struct dml2_context *dml2); 213 void dml2_copy(struct dml2_context *dst_dml2, 214 struct dml2_context *src_dml2); 215 bool dml2_create_copy(struct dml2_context **dst_dml2, 216 struct dml2_context *src_dml2); 217 218 /* 219 * dml2_validate - Determines if a display configuration is supported or not. 220 * @in_dc: dc. 221 * @context: dc_state to be validated. 222 * @fast_validate: Fast validate will not populate context.res_ctx. 223 * 224 * DML1.0 compatible interface for validation. 225 * 226 * Based on fast_validate option internally would call: 227 * 228 * -dml2_validate_and_build_resource - for non fast_validate option 229 * Calculates if dc_state can be supported on the SOC, and attempts to 230 * optimize the power management feature supports versus minimum clocks. 231 * If supported, also builds out_new_hw_state to represent the hw programming 232 * for the new dc state. 233 * 234 * -dml2_validate_only - for fast_validate option 235 * Calculates if dc_state can be supported on the SOC (i.e. at maximum 236 * clocks) with all mandatory power features enabled. 237 238 * Context: Two threads may not invoke this function concurrently unless they reference 239 * separate dc_states for validation. 240 * Return: True if mode is supported, false otherwise. 241 */ 242 bool dml2_validate(const struct dc *in_dc, 243 struct dc_state *context, 244 bool fast_validate); 245 246 /* 247 * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info. 248 * @dml2: input dml2 context pointer. 249 * @fclk_change_support: output pointer holding the fclk change support info (vactive, vblank, unsupported). 250 * @dram_clk_change_support: output pointer holding the uclk change support info (vactive, vblank, unsupported). 251 */ 252 void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, 253 unsigned int *fclk_change_support, unsigned int *dram_clk_change_support); 254 255 #endif //_DML2_WRAPPER_H_ 256