1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "display_mode_core.h" 28 #include "dml2_internal_types.h" 29 #include "dml2_utils.h" 30 #include "dml2_policy.h" 31 #include "dml2_translation_helper.h" 32 #include "dml2_mall_phantom.h" 33 #include "dml2_dc_resource_mgmt.h" 34 #include "dml21_wrapper.h" 35 36 37 static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) 38 { 39 if (dml2->config.use_native_soc_bb_construction) 40 dml2_init_ip_params(dml2, in_dc, out); 41 else 42 dml2_translate_ip_params(in_dc, out); 43 } 44 45 static void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out) 46 { 47 if (dml2->config.use_native_soc_bb_construction) 48 dml2_init_socbb_params(dml2, in_dc, out); 49 else 50 dml2_translate_socbb_params(in_dc, out); 51 } 52 53 static void initialize_dml2_soc_states(struct dml2_context *dml2, 54 const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out) 55 { 56 if (dml2->config.use_native_soc_bb_construction) 57 dml2_init_soc_states(dml2, in_dc, in_bbox, out); 58 else 59 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); 60 } 61 62 static void map_hw_resources(struct dml2_context *dml2, 63 struct dml_display_cfg_st *in_out_display_cfg, struct dml_mode_support_info_st *mode_support_info) 64 { 65 unsigned int num_pipes = 0; 66 int i, j; 67 68 for (i = 0; i < __DML_NUM_PLANES__; i++) { 69 in_out_display_cfg->hw.ODMMode[i] = mode_support_info->ODMMode[i]; 70 in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; 71 in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; 72 in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i]; 73 in_out_display_cfg->hw.DLGRefClkFreqMHz = 24; 74 if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && 75 dml2->v20.dml_core_ctx.project != dml_project_dcn36 && 76 dml2->v20.dml_core_ctx.project != dml_project_dcn351) { 77 /*dGPU default as 50Mhz*/ 78 in_out_display_cfg->hw.DLGRefClkFreqMHz = 50; 79 } 80 for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) { 81 if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) { 82 dml_print("DML::%s: Index out of bounds: i=%d, __DML2_WRAPPER_MAX_STREAMS_PLANES__=%d\n", 83 __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__); 84 break; 85 } 86 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i]; 87 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; 88 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i]; 89 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true; 90 num_pipes++; 91 } 92 } 93 } 94 95 static unsigned int pack_and_call_dml_mode_support_ex(struct dml2_context *dml2, 96 const struct dml_display_cfg_st *display_cfg, 97 struct dml_mode_support_info_st *evaluation_info) 98 { 99 struct dml2_wrapper_scratch *s = &dml2->v20.scratch; 100 101 s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx; 102 s->mode_support_params.in_display_cfg = display_cfg; 103 s->mode_support_params.out_evaluation_info = evaluation_info; 104 105 memset(evaluation_info, 0, sizeof(struct dml_mode_support_info_st)); 106 s->mode_support_params.out_lowest_state_idx = 0; 107 108 return dml_mode_support_ex(&s->mode_support_params); 109 } 110 111 static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrapper_optimize_configuration_params *p) 112 { 113 int unused_dpps = p->ip_params->max_num_dpp; 114 int i, j; 115 int odms_needed, refresh_rate_hz, dpps_needed, subvp_height, pstate_width_fw_delay_lines, surface_count; 116 int subvp_timing_to_add, new_timing_index, subvp_surface_to_add, new_surface_index; 117 float frame_time_sec, max_frame_time_sec; 118 int largest_blend_and_timing = 0; 119 bool optimization_done = false; 120 121 for (i = 0; i < (int) p->cur_display_config->num_timings; i++) { 122 if (p->cur_display_config->plane.BlendingAndTiming[i] > largest_blend_and_timing) 123 largest_blend_and_timing = p->cur_display_config->plane.BlendingAndTiming[i]; 124 } 125 126 if (p->new_policy != p->cur_policy) 127 *p->new_policy = *p->cur_policy; 128 129 if (p->new_display_config != p->cur_display_config) 130 *p->new_display_config = *p->cur_display_config; 131 132 // Optimize P-State Support 133 if (dml2->config.use_native_pstate_optimization) { 134 if (p->cur_mode_support_info->DRAMClockChangeSupport[0] == dml_dram_clock_change_unsupported) { 135 // Find a display with < 120Hz refresh rate with maximal refresh rate that's not already subvp 136 subvp_timing_to_add = -1; 137 subvp_surface_to_add = -1; 138 max_frame_time_sec = 0; 139 surface_count = 0; 140 for (i = 0; i < (int) p->cur_display_config->num_timings; i++) { 141 refresh_rate_hz = (int)div_u64((unsigned long long) p->cur_display_config->timing.PixelClock[i] * 1000 * 1000, 142 (p->cur_display_config->timing.HTotal[i] * p->cur_display_config->timing.VTotal[i])); 143 if (refresh_rate_hz < 120) { 144 // Check its upstream surfaces to see if this one could be converted to subvp. 145 dpps_needed = 0; 146 for (j = 0; j < (int) p->cur_display_config->num_surfaces; j++) { 147 if (p->cur_display_config->plane.BlendingAndTiming[j] == i && 148 p->cur_display_config->plane.UseMALLForPStateChange[j] == dml_use_mall_pstate_change_disable) { 149 dpps_needed += p->cur_mode_support_info->DPPPerSurface[j]; 150 subvp_surface_to_add = j; 151 surface_count++; 152 } 153 } 154 155 if (surface_count == 1 && dpps_needed > 0 && dpps_needed <= unused_dpps) { 156 frame_time_sec = (float)1 / refresh_rate_hz; 157 if (frame_time_sec > max_frame_time_sec) { 158 max_frame_time_sec = frame_time_sec; 159 subvp_timing_to_add = i; 160 } 161 } 162 } 163 } 164 if (subvp_timing_to_add >= 0) { 165 new_timing_index = p->new_display_config->num_timings++; 166 new_surface_index = p->new_display_config->num_surfaces++; 167 // Add a phantom pipe reflecting the main pipe's timing 168 dml2_util_copy_dml_timing(&p->new_display_config->timing, new_timing_index, subvp_timing_to_add); 169 170 pstate_width_fw_delay_lines = (int)(((double)(p->config->svp_pstate.subvp_fw_processing_delay_us + 171 p->config->svp_pstate.subvp_pstate_allow_width_us) / 1000000) * 172 (p->new_display_config->timing.PixelClock[subvp_timing_to_add] * 1000 * 1000) / 173 (double)p->new_display_config->timing.HTotal[subvp_timing_to_add]); 174 175 subvp_height = p->cur_mode_support_info->SubViewportLinesNeededInMALL[subvp_timing_to_add] + pstate_width_fw_delay_lines; 176 177 p->new_display_config->timing.VActive[new_timing_index] = subvp_height; 178 p->new_display_config->timing.VTotal[new_timing_index] = subvp_height + 179 p->new_display_config->timing.VTotal[subvp_timing_to_add] - p->new_display_config->timing.VActive[subvp_timing_to_add]; 180 181 p->new_display_config->output.OutputDisabled[new_timing_index] = true; 182 183 p->new_display_config->plane.UseMALLForPStateChange[subvp_surface_to_add] = dml_use_mall_pstate_change_sub_viewport; 184 185 dml2_util_copy_dml_plane(&p->new_display_config->plane, new_surface_index, subvp_surface_to_add); 186 dml2_util_copy_dml_surface(&p->new_display_config->surface, new_surface_index, subvp_surface_to_add); 187 188 p->new_display_config->plane.ViewportHeight[new_surface_index] = subvp_height; 189 p->new_display_config->plane.ViewportHeightChroma[new_surface_index] = subvp_height; 190 p->new_display_config->plane.ViewportStationary[new_surface_index] = false; 191 192 p->new_display_config->plane.UseMALLForStaticScreen[new_surface_index] = dml_use_mall_static_screen_disable; 193 p->new_display_config->plane.UseMALLForPStateChange[new_surface_index] = dml_use_mall_pstate_change_phantom_pipe; 194 195 p->new_display_config->plane.NumberOfCursors[new_surface_index] = 0; 196 197 p->new_policy->ImmediateFlipRequirement[new_surface_index] = dml_immediate_flip_not_required; 198 199 p->new_display_config->plane.BlendingAndTiming[new_surface_index] = new_timing_index; 200 201 optimization_done = true; 202 } 203 } 204 } 205 206 // Optimize Clocks 207 if (!optimization_done) { 208 if (largest_blend_and_timing == 0 && p->cur_policy->ODMUse[0] == dml_odm_use_policy_combine_as_needed && dml2->config.minimize_dispclk_using_odm) { 209 odms_needed = dml2_util_get_maximum_odm_combine_for_output(dml2->config.optimize_odm_4to1, 210 p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; 211 212 if (odms_needed <= unused_dpps) { 213 if (odms_needed == 1) { 214 p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_2to1; 215 optimization_done = true; 216 } else if (odms_needed == 3) { 217 p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_4to1; 218 optimization_done = true; 219 } else 220 optimization_done = false; 221 } 222 } 223 } 224 225 return optimization_done; 226 } 227 228 static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state) 229 { 230 struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch; 231 struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch; 232 233 unsigned int dml_result = 0; 234 int result = -1, i, j; 235 236 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); 237 238 /* Zero out before each call before proceeding */ 239 memset(s, 0, sizeof(struct dml2_calculate_lowest_supported_state_for_temp_read_scratch)); 240 memset(&s_global->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); 241 memset(&s_global->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 242 243 for (i = 0; i < dml2->config.dcn_pipe_count; i++) { 244 /* Calling resource_build_scaling_params will populate the pipe params 245 * with the necessary information needed for correct DML calculations 246 * This is also done in DML1 driver code path and hence display_state 247 * cannot be const. 248 */ 249 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; 250 251 if (pipe->plane_state) { 252 if (!dml2->config.callbacks.build_scaling_params(pipe)) { 253 ASSERT(false); 254 return false; 255 } 256 } 257 } 258 259 map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); 260 261 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { 262 s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us; 263 } 264 265 for (i = 0; i < 4; i++) { 266 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { 267 dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us; 268 } 269 270 dml_result = pack_and_call_dml_mode_support_ex(dml2, &s->cur_display_config, &s->evaluation_info); 271 272 if (dml_result && s->evaluation_info.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive) { 273 map_hw_resources(dml2, &s->cur_display_config, &s->evaluation_info); 274 dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); 275 276 ASSERT(dml_result); 277 278 dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx); 279 dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_watermark_set.cstate_pstate.pstate_change_ns; 280 281 result = s_global->mode_support_params.out_lowest_state_idx; 282 283 while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_speed_mts) 284 result++; 285 286 break; 287 } 288 } 289 290 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { 291 dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latencies[i]; 292 } 293 294 return result; 295 } 296 297 static void copy_dummy_pstate_table(struct dummy_pstate_entry *dest, struct dummy_pstate_entry *src, unsigned int num_entries) 298 { 299 for (int i = 0; i < num_entries; i++) { 300 dest[i] = src[i]; 301 } 302 } 303 304 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, 305 const struct dml_mode_support_info_st *evaluation_info) 306 { 307 unsigned int planes_per_timing[__DML_NUM_PLANES__] = {0}; 308 int i; 309 310 for (i = 0; i < display_cfg->num_surfaces; i++) 311 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; 312 313 for (i = 0; i < __DML_NUM_PLANES__; i++) { 314 if (planes_per_timing[i] > 1 && evaluation_info->ODMMode[i] != dml_odm_mode_bypass) 315 return true; 316 } 317 318 return false; 319 } 320 321 static bool does_configuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, 322 const struct dml_mode_support_info_st *evaluation_info) 323 { 324 bool pass = true; 325 326 if (!ctx->config.enable_windowed_mpo_odm) { 327 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) 328 pass = false; 329 } 330 331 return pass; 332 } 333 334 static bool dml_mode_support_wrapper(struct dml2_context *dml2, 335 struct dc_state *display_state) 336 { 337 struct dml2_wrapper_scratch *s = &dml2->v20.scratch; 338 unsigned int result = 0, i; 339 unsigned int optimized_result = true; 340 341 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); 342 343 /* Zero out before each call before proceeding */ 344 memset(&s->cur_display_config, 0, sizeof(struct dml_display_cfg_st)); 345 memset(&s->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); 346 memset(&s->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 347 memset(&s->optimize_configuration_params, 0, sizeof(struct dml2_wrapper_optimize_configuration_params)); 348 349 for (i = 0; i < dml2->config.dcn_pipe_count; i++) { 350 /* Calling resource_build_scaling_params will populate the pipe params 351 * with the necessary information needed for correct DML calculations 352 * This is also done in DML1 driver code path and hence display_state 353 * cannot be const. 354 */ 355 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; 356 357 if (pipe->plane_state) { 358 if (!dml2->config.callbacks.build_scaling_params(pipe)) { 359 ASSERT(false); 360 return false; 361 } 362 } 363 } 364 365 map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); 366 if (!dml2->config.skip_hw_state_mapping) 367 dml2_apply_det_buffer_allocation_policy(dml2, &s->cur_display_config); 368 369 result = pack_and_call_dml_mode_support_ex(dml2, 370 &s->cur_display_config, 371 &s->mode_support_info); 372 373 if (result) 374 result = does_configuration_meet_sw_policies(dml2, &s->cur_display_config, &s->mode_support_info); 375 376 // Try to optimize 377 if (result) { 378 s->cur_policy = dml2->v20.dml_core_ctx.policy; 379 s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx; 380 s->optimize_configuration_params.config = &dml2->config; 381 s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip; 382 s->optimize_configuration_params.cur_display_config = &s->cur_display_config; 383 s->optimize_configuration_params.cur_mode_support_info = &s->mode_support_info; 384 s->optimize_configuration_params.cur_policy = &s->cur_policy; 385 s->optimize_configuration_params.new_display_config = &s->new_display_config; 386 s->optimize_configuration_params.new_policy = &s->new_policy; 387 388 while (optimized_result && optimize_configuration(dml2, &s->optimize_configuration_params)) { 389 dml2->v20.dml_core_ctx.policy = s->new_policy; 390 optimized_result = pack_and_call_dml_mode_support_ex(dml2, 391 &s->new_display_config, 392 &s->mode_support_info); 393 394 if (optimized_result) 395 optimized_result = does_configuration_meet_sw_policies(dml2, &s->new_display_config, &s->mode_support_info); 396 397 // If the new optimized state is supposed, then set current = new 398 if (optimized_result) { 399 s->cur_display_config = s->new_display_config; 400 s->cur_policy = s->new_policy; 401 } else { 402 // Else, restore policy to current 403 dml2->v20.dml_core_ctx.policy = s->cur_policy; 404 } 405 } 406 407 // Optimize ended with a failed config, so we need to restore DML state to last passing 408 if (!optimized_result) { 409 result = pack_and_call_dml_mode_support_ex(dml2, 410 &s->cur_display_config, 411 &s->mode_support_info); 412 } 413 } 414 415 if (result) 416 map_hw_resources(dml2, &s->cur_display_config, &s->mode_support_info); 417 418 return result; 419 } 420 421 static int find_drr_eligible_stream(struct dc_state *display_state) 422 { 423 int i; 424 425 for (i = 0; i < display_state->stream_count; i++) { 426 if (dc_state_get_stream_subvp_type(display_state, display_state->streams[i]) == SUBVP_NONE 427 && display_state->streams[i]->ignore_msa_timing_param) { 428 // Use ignore_msa_timing_param flag to identify as DRR 429 return i; 430 } 431 } 432 433 return -1; 434 } 435 436 static bool optimize_pstate_with_svp_and_drr(struct dml2_context *dml2, struct dc_state *display_state) 437 { 438 struct dml2_wrapper_scratch *s = &dml2->v20.scratch; 439 bool pstate_optimization_done = false; 440 bool pstate_optimization_success = false; 441 bool result = false; 442 int drr_display_index = 0, non_svp_streams = 0; 443 bool force_svp = dml2->config.svp_pstate.force_enable_subvp; 444 445 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 446 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; 447 448 result = dml_mode_support_wrapper(dml2, display_state); 449 450 if (!result) { 451 pstate_optimization_done = true; 452 } else if (s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported && !force_svp) { 453 pstate_optimization_success = true; 454 pstate_optimization_done = true; 455 } 456 457 if (display_state->stream_count == 1 && dml2->config.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch(dml2->config.callbacks.dc, display_state)) { 458 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; 459 460 result = dml_mode_support_wrapper(dml2, display_state); 461 } else { 462 non_svp_streams = display_state->stream_count; 463 464 while (!pstate_optimization_done) { 465 result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); 466 467 // Always try adding SVP first 468 if (result) 469 result = dml2_svp_add_phantom_pipe_to_dc_state(dml2, display_state, &s->mode_support_info); 470 else 471 pstate_optimization_done = true; 472 473 474 if (result) { 475 result = dml_mode_support_wrapper(dml2, display_state); 476 } else { 477 pstate_optimization_done = true; 478 } 479 480 if (result) { 481 non_svp_streams--; 482 483 if (s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported) { 484 if (dml2_svp_validate_static_schedulability(dml2, display_state, s->mode_support_info.DRAMClockChangeSupport[0])) { 485 pstate_optimization_success = true; 486 pstate_optimization_done = true; 487 } else { 488 pstate_optimization_success = false; 489 pstate_optimization_done = false; 490 } 491 } else { 492 drr_display_index = find_drr_eligible_stream(display_state); 493 494 // If there is only 1 remaining non SubVP pipe that is DRR, check static 495 // schedulability for SubVP + DRR. 496 if (non_svp_streams == 1 && drr_display_index >= 0) { 497 if (dml2_svp_drr_schedulable(dml2, display_state, &display_state->streams[drr_display_index]->timing)) { 498 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = true; 499 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index = drr_display_index; 500 result = dml_mode_support_wrapper(dml2, display_state); 501 } 502 503 if (result && s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported) { 504 pstate_optimization_success = true; 505 pstate_optimization_done = true; 506 } else { 507 pstate_optimization_success = false; 508 pstate_optimization_done = false; 509 } 510 } 511 512 if (pstate_optimization_success) { 513 pstate_optimization_done = true; 514 } else { 515 pstate_optimization_done = false; 516 } 517 } 518 } 519 } 520 } 521 522 if (!pstate_optimization_success) { 523 dml2_svp_remove_all_phantom_pipes(dml2, display_state); 524 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; 525 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; 526 result = dml_mode_support_wrapper(dml2, display_state); 527 } 528 529 return result; 530 } 531 532 static bool call_dml_mode_support_and_programming(struct dc_state *context) 533 { 534 unsigned int result = 0; 535 unsigned int min_state = 0; 536 int min_state_for_g6_temp_read = 0; 537 538 539 if (!context) 540 return false; 541 542 struct dml2_context *dml2 = context->bw_ctx.dml2; 543 struct dml2_wrapper_scratch *s = &dml2->v20.scratch; 544 545 if (!context->streams[0]->sink->link->dc->caps.is_apu) { 546 min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context); 547 548 ASSERT(min_state_for_g6_temp_read >= 0); 549 } 550 551 if (!dml2->config.use_native_pstate_optimization) { 552 result = optimize_pstate_with_svp_and_drr(dml2, context); 553 } else { 554 result = dml_mode_support_wrapper(dml2, context); 555 } 556 557 /* Upon trying to sett certain frequencies in FRL, min_state_for_g6_temp_read is reported as -1. This leads to an invalid value of min_state causing crashes later on. 558 * Use the default logic for min_state only when min_state_for_g6_temp_read is a valid value. In other cases, use the value calculated by the DML directly. 559 */ 560 if (!context->streams[0]->sink->link->dc->caps.is_apu) { 561 if (min_state_for_g6_temp_read >= 0) 562 min_state = min_state_for_g6_temp_read > s->mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s->mode_support_params.out_lowest_state_idx; 563 else 564 min_state = s->mode_support_params.out_lowest_state_idx; 565 } 566 567 if (result) { 568 if (!context->streams[0]->sink->link->dc->caps.is_apu) { 569 result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true); 570 } else { 571 result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); 572 } 573 } 574 return result; 575 } 576 577 static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context) 578 { 579 struct dml2_context *dml2 = context->bw_ctx.dml2; 580 struct dml2_wrapper_scratch *s = &dml2->v20.scratch; 581 struct dml2_dcn_clocks out_clks; 582 unsigned int result = 0; 583 bool need_recalculation = false; 584 uint32_t cstate_enter_plus_exit_z8_ns; 585 586 if (context->stream_count == 0) { 587 unsigned int lowest_state_idx = 0; 588 589 out_clks.p_state_supported = true; 590 out_clks.dispclk_khz = 0; /* No requirement, and lowest index will generally be maximum dispclk. */ 591 out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; 592 out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; 593 out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; 594 out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; 595 out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; 596 out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; 597 context->bw_ctx.bw.dcn.clk.dtbclk_en = false; 598 dml2_copy_clocks_to_dc_state(&out_clks, context); 599 return true; 600 } 601 602 /* Zero out before each call before proceeding */ 603 memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); 604 memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); 605 memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); 606 memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); 607 608 /* Initialize DET scratch */ 609 dml2_initialize_det_scratch(dml2); 610 611 copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); 612 613 result = call_dml_mode_support_and_programming(context); 614 /* Call map dc pipes to map the pipes based on the DML output. For correctly determining if recalculation 615 * is required or not, the resource context needs to correctly reflect the number of active pipes. We would 616 * only know the correct number if active pipes after dml2_map_dc_pipes is called. 617 */ 618 if (result && !dml2->config.skip_hw_state_mapping) 619 dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); 620 621 /* Verify and update DET Buffer configuration if needed. dml2_verify_det_buffer_configuration will check if DET Buffer 622 * size needs to be updated. If yes it will update the DETOverride variable and set need_recalculation flag to true. 623 * Based on that flag, run mode support again. Verification needs to be run after dml_mode_programming because the getters 624 * return correct det buffer values only after dml_mode_programming is called. 625 */ 626 if (result && !dml2->config.skip_hw_state_mapping) { 627 need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); 628 if (need_recalculation) { 629 /* Engage the DML again if recalculation is required. */ 630 call_dml_mode_support_and_programming(context); 631 if (!dml2->config.skip_hw_state_mapping) { 632 dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); 633 } 634 need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); 635 ASSERT(need_recalculation == false); 636 } 637 } 638 639 if (result) { 640 unsigned int lowest_state_idx = s->mode_support_params.out_lowest_state_idx; 641 out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000; 642 out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported; 643 if (in_dc->config.use_default_clock_table && 644 (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { 645 lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; 646 out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000; 647 } 648 649 out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; 650 out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; 651 out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; 652 out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; 653 out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; 654 out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; 655 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); 656 657 if (!dml2->config.skip_hw_state_mapping) { 658 /* Call dml2_calculate_rq_and_dlg_params */ 659 dml2_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_count); 660 } 661 662 dml2_copy_clocks_to_dc_state(&out_clks, context); 663 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); 664 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); 665 memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c)); 666 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); 667 dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx); 668 //copy for deciding zstate use 669 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; 670 671 cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns; 672 673 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && 674 cstate_enter_plus_exit_z8_ns < in_dc->debug.minimum_z8_residency_time * 1000) 675 cstate_enter_plus_exit_z8_ns = in_dc->debug.minimum_z8_residency_time * 1000; 676 677 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; 678 } 679 680 return result; 681 } 682 683 static bool dml2_validate_only(struct dc_state *context) 684 { 685 struct dml2_context *dml2; 686 unsigned int result = 0; 687 688 if (!context || context->stream_count == 0) 689 return true; 690 691 dml2 = context->bw_ctx.dml2; 692 693 /* Zero out before each call before proceeding */ 694 memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); 695 memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); 696 memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); 697 memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); 698 699 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); 700 701 map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config); 702 if (!dml2->config.skip_hw_state_mapping) 703 dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config); 704 705 result = pack_and_call_dml_mode_support_ex(dml2, 706 &dml2->v20.scratch.cur_display_config, 707 &dml2->v20.scratch.mode_support_info); 708 709 if (result) 710 result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info); 711 712 return (result == 1) ? true : false; 713 } 714 715 static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) 716 { 717 if (dc->debug.override_odm_optimization) { 718 dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm; 719 } 720 } 721 722 bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, bool fast_validate) 723 { 724 bool out = false; 725 726 if (!dml2) 727 return false; 728 dml2_apply_debug_options(in_dc, dml2); 729 730 /* DML2.1 validation path */ 731 if (dml2->architecture == dml2_architecture_21) { 732 out = dml21_validate(in_dc, context, dml2, fast_validate); 733 return out; 734 } 735 736 /* Use dml_validate_only for fast_validate path */ 737 if (fast_validate) 738 out = dml2_validate_only(context); 739 else 740 out = dml2_validate_and_build_resource(in_dc, context); 741 return out; 742 } 743 744 static inline struct dml2_context *dml2_allocate_memory(void) 745 { 746 return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL); 747 } 748 749 static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) 750 { 751 if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) { 752 dml21_reinit(in_dc, dml2, config); 753 return; 754 } 755 756 // Store config options 757 (*dml2)->config = *config; 758 759 switch (in_dc->ctx->dce_version) { 760 case DCN_VERSION_3_5: 761 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn35; 762 break; 763 case DCN_VERSION_3_51: 764 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn351; 765 break; 766 case DCN_VERSION_3_6: 767 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn36; 768 break; 769 case DCN_VERSION_3_2: 770 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn32; 771 break; 772 case DCN_VERSION_3_21: 773 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn321; 774 break; 775 case DCN_VERSION_4_01: 776 (*dml2)->v20.dml_core_ctx.project = dml_project_dcn401; 777 break; 778 default: 779 (*dml2)->v20.dml_core_ctx.project = dml_project_default; 780 break; 781 } 782 783 initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip); 784 785 initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); 786 787 initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states); 788 } 789 790 bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) 791 { 792 // TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete. 793 if ((in_dc->debug.using_dml21) 794 && (in_dc->ctx->dce_version == DCN_VERSION_4_01 795 )) 796 return dml21_create(in_dc, dml2, config); 797 798 // Allocate Mode Lib Ctx 799 *dml2 = dml2_allocate_memory(); 800 801 if (!(*dml2)) 802 return false; 803 804 dml2_init(in_dc, config, dml2); 805 806 return true; 807 } 808 809 void dml2_destroy(struct dml2_context *dml2) 810 { 811 if (!dml2) 812 return; 813 814 if (dml2->architecture == dml2_architecture_21) 815 dml21_destroy(dml2); 816 kfree(dml2); 817 } 818 819 void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, 820 unsigned int *fclk_change_support, unsigned int *dram_clk_change_support) 821 { 822 *fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0]; 823 *dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0]; 824 } 825 826 void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2) 827 { 828 if (dml2->architecture == dml2_architecture_21) 829 dml21_prepare_mcache_programming(in_dc, context, dml2); 830 } 831 832 void dml2_copy(struct dml2_context *dst_dml2, 833 struct dml2_context *src_dml2) 834 { 835 if (src_dml2->architecture == dml2_architecture_21) { 836 dml21_copy(dst_dml2, src_dml2); 837 return; 838 } 839 /* copy Mode Lib Ctx */ 840 memcpy(dst_dml2, src_dml2, sizeof(struct dml2_context)); 841 } 842 843 bool dml2_create_copy(struct dml2_context **dst_dml2, 844 struct dml2_context *src_dml2) 845 { 846 if (src_dml2->architecture == dml2_architecture_21) 847 return dml21_create_copy(dst_dml2, src_dml2); 848 /* Allocate Mode Lib Ctx */ 849 *dst_dml2 = dml2_allocate_memory(); 850 851 if (!(*dst_dml2)) 852 return false; 853 854 /* copy Mode Lib Ctx */ 855 dml2_copy(*dst_dml2, src_dml2); 856 857 return true; 858 } 859 860 void dml2_reinit(const struct dc *in_dc, 861 const struct dml2_configuration_options *config, 862 struct dml2_context **dml2) 863 { 864 if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) { 865 dml21_reinit(in_dc, dml2, config); 866 return; 867 } 868 869 dml2_init(in_dc, config, dml2); 870 } 871