1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc.h" 27 #include "dc_dmub_srv.h" 28 #include "dmub/dmub_srv.h" 29 #include "core_types.h" 30 #include "dmub_replay.h" 31 32 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 33 34 #define MAX_PIPES 6 35 36 /* 37 * Get Replay state from firmware. 38 */ 39 static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst) 40 { 41 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 42 /* uint32_t raw_state = 0; */ 43 uint32_t retry_count = 0; 44 enum dmub_status status; 45 46 do { 47 // Send gpint command and wait for ack 48 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 30); 49 50 if (status == DMUB_STATUS_OK) { 51 // GPINT was executed, get response 52 dmub_srv_get_gpint_response(srv, (uint32_t *)state); 53 } else 54 // Return invalid state when GPINT times out 55 *state = REPLAY_STATE_INVALID; 56 } while (++retry_count <= 1000 && *state == REPLAY_STATE_INVALID); 57 58 // Assert if max retry hit 59 if (retry_count >= 1000 && *state == REPLAY_STATE_INVALID) { 60 ASSERT(0); 61 /* To-do: Add retry fail log */ 62 } 63 } 64 65 /* 66 * Enable/Disable Replay. 67 */ 68 static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst) 69 { 70 union dmub_rb_cmd cmd; 71 struct dc_context *dc = dmub->ctx; 72 uint32_t retry_count; 73 enum replay_state state = REPLAY_STATE_0; 74 75 memset(&cmd, 0, sizeof(cmd)); 76 cmd.replay_enable.header.type = DMUB_CMD__REPLAY; 77 cmd.replay_enable.data.panel_inst = panel_inst; 78 79 cmd.replay_enable.header.sub_type = DMUB_CMD__REPLAY_ENABLE; 80 if (enable) 81 cmd.replay_enable.data.enable = REPLAY_ENABLE; 82 else 83 cmd.replay_enable.data.enable = REPLAY_DISABLE; 84 85 cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data); 86 87 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 88 89 /* Below loops 1000 x 500us = 500 ms. 90 * Exit REPLAY may need to wait 1-2 frames to power up. Timeout after at 91 * least a few frames. Should never hit the max retry assert below. 92 */ 93 if (wait) { 94 for (retry_count = 0; retry_count <= 1000; retry_count++) { 95 dmub_replay_get_state(dmub, &state, panel_inst); 96 97 if (enable) { 98 if (state != REPLAY_STATE_0) 99 break; 100 } else { 101 if (state == REPLAY_STATE_0) 102 break; 103 } 104 105 fsleep(500); 106 } 107 108 /* assert if max retry hit */ 109 if (retry_count >= 1000) 110 ASSERT(0); 111 } 112 } 113 114 /* 115 * Set REPLAY power optimization flags. 116 */ 117 static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int power_opt, uint8_t panel_inst) 118 { 119 union dmub_rb_cmd cmd; 120 struct dc_context *dc = dmub->ctx; 121 122 memset(&cmd, 0, sizeof(cmd)); 123 cmd.replay_set_power_opt.header.type = DMUB_CMD__REPLAY; 124 cmd.replay_set_power_opt.header.sub_type = DMUB_CMD__SET_REPLAY_POWER_OPT; 125 cmd.replay_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_power_opt_data); 126 cmd.replay_set_power_opt.replay_set_power_opt_data.power_opt = power_opt; 127 cmd.replay_set_power_opt.replay_set_power_opt_data.panel_inst = panel_inst; 128 129 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 130 } 131 132 /* 133 * Setup Replay by programming phy registers and sending replay hw context values to firmware. 134 */ 135 static bool dmub_replay_copy_settings(struct dmub_replay *dmub, 136 struct dc_link *link, 137 struct replay_context *replay_context, 138 uint8_t panel_inst) 139 { 140 union dmub_rb_cmd cmd; 141 struct dc_context *dc = dmub->ctx; 142 struct dmub_cmd_replay_copy_settings_data *copy_settings_data 143 = &cmd.replay_copy_settings.replay_copy_settings_data; 144 struct pipe_ctx *pipe_ctx = NULL; 145 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 146 int i = 0; 147 148 for (i = 0; i < MAX_PIPES; i++) { 149 if (res_ctx && 150 res_ctx->pipe_ctx[i].stream && 151 res_ctx->pipe_ctx[i].stream->link && 152 res_ctx->pipe_ctx[i].stream->link == link && 153 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 154 pipe_ctx = &res_ctx->pipe_ctx[i]; 155 //TODO: refactor for multi edp support 156 break; 157 } 158 } 159 160 if (!pipe_ctx) 161 return false; 162 163 memset(&cmd, 0, sizeof(cmd)); 164 cmd.replay_copy_settings.header.type = DMUB_CMD__REPLAY; 165 cmd.replay_copy_settings.header.sub_type = DMUB_CMD__REPLAY_COPY_SETTINGS; 166 cmd.replay_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_replay_copy_settings_data); 167 168 // HW insts 169 copy_settings_data->aux_inst = replay_context->aux_inst; 170 copy_settings_data->digbe_inst = replay_context->digbe_inst; 171 copy_settings_data->digfe_inst = replay_context->digfe_inst; 172 173 if (pipe_ctx->plane_res.dpp) 174 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 175 else 176 copy_settings_data->dpp_inst = 0; 177 if (pipe_ctx->stream_res.tg) 178 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 179 else 180 copy_settings_data->otg_inst = 0; 181 182 copy_settings_data->dpphy_inst = link->link_enc->transmitter; 183 184 // Misc 185 copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns; 186 copy_settings_data->panel_inst = panel_inst; 187 copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags; 188 copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; 189 copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; 190 copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; 191 copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; 192 193 copy_settings_data->flags.u32All = 0; 194 copy_settings_data->flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled); 195 copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 196 // WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) 197 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && 198 !link->dc->debug.disable_fec) && 199 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 200 !link->panel_config.dsc.disable_dsc_edp && 201 link->dc->caps.edp_dsc_support)) && 202 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 /*&& 203 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 204 sizeof(DP_SINK_DEVICE_STR_ID_1)) || 205 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2, 206 sizeof(DP_SINK_DEVICE_STR_ID_2)))*/) 207 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 1; 208 else 209 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0; 210 211 212 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 213 214 return true; 215 } 216 217 /* 218 * Set coasting vtotal. 219 */ 220 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub, 221 uint16_t coasting_vtotal, 222 uint8_t panel_inst) 223 { 224 union dmub_rb_cmd cmd; 225 struct dc_context *dc = dmub->ctx; 226 227 memset(&cmd, 0, sizeof(cmd)); 228 cmd.replay_set_coasting_vtotal.header.type = DMUB_CMD__REPLAY; 229 cmd.replay_set_coasting_vtotal.header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL; 230 cmd.replay_set_coasting_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data); 231 cmd.replay_set_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal; 232 233 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 234 } 235 236 /* 237 * Get Replay residency from firmware. 238 */ 239 static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, 240 uint32_t *residency, const bool is_start, const bool is_alpm) 241 { 242 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 243 uint16_t param = (uint16_t)(panel_inst << 8); 244 245 if (is_alpm) 246 param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM; 247 248 if (is_start) 249 param |= REPLAY_RESIDENCY_ENABLE; 250 251 // Send gpint command and wait for ack 252 dmub_srv_send_gpint_command(srv, DMUB_GPINT__REPLAY_RESIDENCY, param, 30); 253 254 if (!is_start) 255 dmub_srv_get_gpint_response(srv, residency); 256 else 257 *residency = 0; 258 } 259 260 /* 261 * Set REPLAY power optimization flags and coasting vtotal. 262 */ 263 static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub, 264 unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal) 265 { 266 union dmub_rb_cmd cmd; 267 struct dc_context *dc = dmub->ctx; 268 269 memset(&cmd, 0, sizeof(cmd)); 270 cmd.replay_set_power_opt_and_coasting_vtotal.header.type = DMUB_CMD__REPLAY; 271 cmd.replay_set_power_opt_and_coasting_vtotal.header.sub_type = 272 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL; 273 cmd.replay_set_power_opt_and_coasting_vtotal.header.payload_bytes = 274 sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal); 275 cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.power_opt = power_opt; 276 cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.panel_inst = panel_inst; 277 cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal; 278 279 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 280 } 281 282 /* 283 * send Replay general cmd to DMUB. 284 */ 285 static void dmub_replay_send_cmd(struct dmub_replay *dmub, 286 enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element) 287 { 288 union dmub_rb_cmd cmd; 289 struct dc_context *ctx = NULL; 290 291 if (dmub == NULL || cmd_element == NULL) 292 return; 293 294 ctx = dmub->ctx; 295 if (ctx != NULL) { 296 297 if (msg != Replay_Msg_Not_Support) { 298 memset(&cmd, 0, sizeof(cmd)); 299 //Header 300 cmd.replay_set_timing_sync.header.type = DMUB_CMD__REPLAY; 301 } else 302 return; 303 } else 304 return; 305 306 switch (msg) { 307 case Replay_Set_Timing_Sync_Supported: 308 //Header 309 cmd.replay_set_timing_sync.header.sub_type = 310 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED; 311 cmd.replay_set_timing_sync.header.payload_bytes = 312 sizeof(struct dmub_rb_cmd_replay_set_timing_sync); 313 //Cmd Body 314 cmd.replay_set_timing_sync.replay_set_timing_sync_data.panel_inst = 315 cmd_element->sync_data.panel_inst; 316 cmd.replay_set_timing_sync.replay_set_timing_sync_data.timing_sync_supported = 317 cmd_element->sync_data.timing_sync_supported; 318 break; 319 case Replay_Set_Residency_Frameupdate_Timer: 320 //Header 321 cmd.replay_set_frameupdate_timer.header.sub_type = 322 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER; 323 cmd.replay_set_frameupdate_timer.header.payload_bytes = 324 sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer); 325 //Cmd Body 326 cmd.replay_set_frameupdate_timer.data.panel_inst = 327 cmd_element->panel_inst; 328 cmd.replay_set_frameupdate_timer.data.enable = 329 cmd_element->timer_data.enable; 330 cmd.replay_set_frameupdate_timer.data.frameupdate_count = 331 cmd_element->timer_data.frameupdate_count; 332 break; 333 case Replay_Msg_Not_Support: 334 default: 335 return; 336 break; 337 } 338 339 dc_wake_and_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 340 } 341 342 static const struct dmub_replay_funcs replay_funcs = { 343 .replay_copy_settings = dmub_replay_copy_settings, 344 .replay_enable = dmub_replay_enable, 345 .replay_get_state = dmub_replay_get_state, 346 .replay_set_power_opt = dmub_replay_set_power_opt, 347 .replay_set_coasting_vtotal = dmub_replay_set_coasting_vtotal, 348 .replay_residency = dmub_replay_residency, 349 .replay_set_power_opt_and_coasting_vtotal = dmub_replay_set_power_opt_and_coasting_vtotal, 350 .replay_send_cmd = dmub_replay_send_cmd, 351 }; 352 353 /* 354 * Construct Replay object. 355 */ 356 static void dmub_replay_construct(struct dmub_replay *replay, struct dc_context *ctx) 357 { 358 replay->ctx = ctx; 359 replay->funcs = &replay_funcs; 360 } 361 362 /* 363 * Allocate and initialize Replay object. 364 */ 365 struct dmub_replay *dmub_replay_create(struct dc_context *ctx) 366 { 367 struct dmub_replay *replay = kzalloc(sizeof(struct dmub_replay), GFP_KERNEL); 368 369 if (replay == NULL) { 370 BREAK_TO_DEBUGGER(); 371 return NULL; 372 } 373 374 dmub_replay_construct(replay, ctx); 375 376 return replay; 377 } 378 379 /* 380 * Deallocate Replay object. 381 */ 382 void dmub_replay_destroy(struct dmub_replay **dmub) 383 { 384 kfree(*dmub); 385 *dmub = NULL; 386 } 387