1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include "dc.h" 6 #include "dc_dmub_srv.h" 7 #include "dmub/dmub_srv.h" 8 #include "core_types.h" 9 #include "dmub_replay.h" 10 11 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 12 13 #define MAX_PIPES 6 14 15 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3}; 16 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5}; 17 18 /* 19 * Get Replay state from firmware. 20 */ 21 static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst) 22 { 23 uint32_t retry_count = 0; 24 25 do { 26 // Send gpint command and wait for ack 27 if (!dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 28 (uint32_t *)state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { 29 // Return invalid state when GPINT times out 30 *state = REPLAY_STATE_INVALID; 31 } 32 } while (++retry_count <= 1000 && *state == REPLAY_STATE_INVALID); 33 34 // Assert if max retry hit 35 if (retry_count >= 1000 && *state == REPLAY_STATE_INVALID) { 36 ASSERT(0); 37 /* To-do: Add retry fail log */ 38 } 39 } 40 41 /* 42 * Enable/Disable Replay. 43 */ 44 static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst) 45 { 46 union dmub_rb_cmd cmd; 47 struct dc_context *dc = dmub->ctx; 48 uint32_t retry_count; 49 enum replay_state state = REPLAY_STATE_0; 50 51 memset(&cmd, 0, sizeof(cmd)); 52 cmd.replay_enable.header.type = DMUB_CMD__REPLAY; 53 cmd.replay_enable.data.panel_inst = panel_inst; 54 55 cmd.replay_enable.header.sub_type = DMUB_CMD__REPLAY_ENABLE; 56 if (enable) 57 cmd.replay_enable.data.enable = REPLAY_ENABLE; 58 else 59 cmd.replay_enable.data.enable = REPLAY_DISABLE; 60 61 cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data); 62 63 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 64 65 /* Below loops 1000 x 500us = 500 ms. 66 * Exit REPLAY may need to wait 1-2 frames to power up. Timeout after at 67 * least a few frames. Should never hit the max retry assert below. 68 */ 69 if (wait) { 70 for (retry_count = 0; retry_count <= 1000; retry_count++) { 71 dmub_replay_get_state(dmub, &state, panel_inst); 72 73 if (enable) { 74 if (state != REPLAY_STATE_0) 75 break; 76 } else { 77 if (state == REPLAY_STATE_0) 78 break; 79 } 80 81 /* must *not* be fsleep - this can be called from high irq levels */ 82 udelay(500); 83 } 84 85 /* assert if max retry hit */ 86 if (retry_count >= 1000) 87 ASSERT(0); 88 } 89 } 90 91 /* 92 * Set REPLAY power optimization flags. 93 */ 94 static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int power_opt, uint8_t panel_inst) 95 { 96 union dmub_rb_cmd cmd; 97 struct dc_context *dc = dmub->ctx; 98 99 memset(&cmd, 0, sizeof(cmd)); 100 cmd.replay_set_power_opt.header.type = DMUB_CMD__REPLAY; 101 cmd.replay_set_power_opt.header.sub_type = DMUB_CMD__SET_REPLAY_POWER_OPT; 102 cmd.replay_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_power_opt_data); 103 cmd.replay_set_power_opt.replay_set_power_opt_data.power_opt = power_opt; 104 cmd.replay_set_power_opt.replay_set_power_opt_data.panel_inst = panel_inst; 105 106 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 107 } 108 109 /* 110 * Setup Replay by programming phy registers and sending replay hw context values to firmware. 111 */ 112 static bool dmub_replay_copy_settings(struct dmub_replay *dmub, 113 struct dc_link *link, 114 struct replay_context *replay_context, 115 uint8_t panel_inst) 116 { 117 union dmub_rb_cmd cmd; 118 struct dc_context *dc = dmub->ctx; 119 struct dmub_cmd_replay_copy_settings_data *copy_settings_data 120 = &cmd.replay_copy_settings.replay_copy_settings_data; 121 struct pipe_ctx *pipe_ctx = NULL; 122 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 123 int i = 0; 124 125 for (i = 0; i < MAX_PIPES; i++) { 126 if (res_ctx && 127 res_ctx->pipe_ctx[i].stream && 128 res_ctx->pipe_ctx[i].stream->link && 129 res_ctx->pipe_ctx[i].stream->link == link && 130 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 131 pipe_ctx = &res_ctx->pipe_ctx[i]; 132 //TODO: refactor for multi edp support 133 break; 134 } 135 } 136 137 if (!pipe_ctx) 138 return false; 139 140 memset(&cmd, 0, sizeof(cmd)); 141 cmd.replay_copy_settings.header.type = DMUB_CMD__REPLAY; 142 cmd.replay_copy_settings.header.sub_type = DMUB_CMD__REPLAY_COPY_SETTINGS; 143 cmd.replay_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_replay_copy_settings_data); 144 145 // HW insts 146 copy_settings_data->aux_inst = replay_context->aux_inst; 147 copy_settings_data->digbe_inst = replay_context->digbe_inst; 148 copy_settings_data->digfe_inst = replay_context->digfe_inst; 149 150 if (pipe_ctx->plane_res.dpp) 151 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 152 else 153 copy_settings_data->dpp_inst = 0; 154 if (pipe_ctx->stream_res.tg) 155 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 156 else 157 copy_settings_data->otg_inst = 0; 158 159 copy_settings_data->dpphy_inst = link->link_enc->transmitter; 160 161 // Misc 162 copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns; 163 copy_settings_data->panel_inst = panel_inst; 164 copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags; 165 copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; 166 copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; 167 copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; 168 copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; 169 170 copy_settings_data->flags.u32All = 0; 171 copy_settings_data->flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled); 172 copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 173 // WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) 174 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && 175 !link->dc->debug.disable_fec) && 176 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 177 !link->panel_config.dsc.disable_dsc_edp && 178 link->dc->caps.edp_dsc_support)) && 179 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && 180 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 181 sizeof(DP_SINK_DEVICE_STR_ID_1)) || 182 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2, 183 sizeof(DP_SINK_DEVICE_STR_ID_2)))) 184 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 1; 185 else 186 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0; 187 188 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 189 190 return true; 191 } 192 193 /* 194 * Set coasting vtotal. 195 */ 196 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub, 197 uint32_t coasting_vtotal, 198 uint8_t panel_inst) 199 { 200 union dmub_rb_cmd cmd; 201 struct dc_context *dc = dmub->ctx; 202 struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL; 203 204 pCmd = &(cmd.replay_set_coasting_vtotal); 205 206 memset(&cmd, 0, sizeof(cmd)); 207 pCmd->header.type = DMUB_CMD__REPLAY; 208 pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL; 209 pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data); 210 pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); 211 pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16; 212 213 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 214 } 215 216 /* 217 * Get Replay residency from firmware. 218 */ 219 static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, 220 uint32_t *residency, const bool is_start, enum pr_residency_mode mode) 221 { 222 uint16_t param = (uint16_t)(panel_inst << 8); 223 224 switch (mode) { 225 case PR_RESIDENCY_MODE_PHY: 226 param |= REPLAY_RESIDENCY_FIELD_MODE_PHY; 227 break; 228 case PR_RESIDENCY_MODE_ALPM: 229 param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM; 230 break; 231 case PR_RESIDENCY_MODE_IPS2: 232 param |= REPLAY_RESIDENCY_REVISION_1; 233 param |= REPLAY_RESIDENCY_FIELD_MODE2_IPS; 234 break; 235 case PR_RESIDENCY_MODE_FRAME_CNT: 236 param |= REPLAY_RESIDENCY_REVISION_1; 237 param |= REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT; 238 break; 239 case PR_RESIDENCY_MODE_ENABLEMENT_PERIOD: 240 param |= REPLAY_RESIDENCY_REVISION_1; 241 param |= REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD; 242 break; 243 default: 244 break; 245 } 246 247 if (is_start) 248 param |= REPLAY_RESIDENCY_ENABLE; 249 250 // Send gpint command and wait for ack 251 if (!dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__REPLAY_RESIDENCY, param, 252 residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 253 *residency = 0; 254 } 255 256 /* 257 * Set REPLAY power optimization flags and coasting vtotal. 258 */ 259 static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub, 260 unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal) 261 { 262 union dmub_rb_cmd cmd; 263 struct dc_context *dc = dmub->ctx; 264 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal *pCmd = NULL; 265 266 pCmd = &(cmd.replay_set_power_opt_and_coasting_vtotal); 267 268 memset(&cmd, 0, sizeof(cmd)); 269 pCmd->header.type = DMUB_CMD__REPLAY; 270 pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL; 271 pCmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal); 272 pCmd->replay_set_power_opt_data.power_opt = power_opt; 273 pCmd->replay_set_power_opt_data.panel_inst = panel_inst; 274 pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); 275 pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16; 276 277 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 278 } 279 280 /* 281 * send Replay general cmd to DMUB. 282 */ 283 static void dmub_replay_send_cmd(struct dmub_replay *dmub, 284 enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element) 285 { 286 union dmub_rb_cmd cmd; 287 struct dc_context *ctx = NULL; 288 289 if (dmub == NULL || cmd_element == NULL) 290 return; 291 292 ctx = dmub->ctx; 293 if (ctx != NULL) { 294 295 if (msg != Replay_Msg_Not_Support) { 296 memset(&cmd, 0, sizeof(cmd)); 297 //Header 298 cmd.replay_set_timing_sync.header.type = DMUB_CMD__REPLAY; 299 } else 300 return; 301 } else 302 return; 303 304 switch (msg) { 305 case Replay_Set_Timing_Sync_Supported: 306 //Header 307 cmd.replay_set_timing_sync.header.sub_type = 308 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED; 309 cmd.replay_set_timing_sync.header.payload_bytes = 310 sizeof(struct dmub_rb_cmd_replay_set_timing_sync); 311 //Cmd Body 312 cmd.replay_set_timing_sync.replay_set_timing_sync_data.panel_inst = 313 cmd_element->sync_data.panel_inst; 314 cmd.replay_set_timing_sync.replay_set_timing_sync_data.timing_sync_supported = 315 cmd_element->sync_data.timing_sync_supported; 316 break; 317 case Replay_Set_Residency_Frameupdate_Timer: 318 //Header 319 cmd.replay_set_frameupdate_timer.header.sub_type = 320 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER; 321 cmd.replay_set_frameupdate_timer.header.payload_bytes = 322 sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer); 323 //Cmd Body 324 cmd.replay_set_frameupdate_timer.data.panel_inst = 325 cmd_element->panel_inst; 326 cmd.replay_set_frameupdate_timer.data.enable = 327 cmd_element->timer_data.enable; 328 cmd.replay_set_frameupdate_timer.data.frameupdate_count = 329 cmd_element->timer_data.frameupdate_count; 330 break; 331 case Replay_Set_Pseudo_VTotal: 332 //Header 333 cmd.replay_set_pseudo_vtotal.header.sub_type = 334 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL; 335 cmd.replay_set_pseudo_vtotal.header.payload_bytes = 336 sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal); 337 //Cmd Body 338 cmd.replay_set_pseudo_vtotal.data.panel_inst = 339 cmd_element->pseudo_vtotal_data.panel_inst; 340 cmd.replay_set_pseudo_vtotal.data.vtotal = 341 cmd_element->pseudo_vtotal_data.vtotal; 342 break; 343 case Replay_Disabled_Adaptive_Sync_SDP: 344 //Header 345 cmd.replay_disabled_adaptive_sync_sdp.header.sub_type = 346 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP; 347 cmd.replay_disabled_adaptive_sync_sdp.header.payload_bytes = 348 sizeof(struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp); 349 //Cmd Body 350 cmd.replay_disabled_adaptive_sync_sdp.data.panel_inst = 351 cmd_element->disabled_adaptive_sync_sdp_data.panel_inst; 352 cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled = 353 cmd_element->disabled_adaptive_sync_sdp_data.force_disabled; 354 break; 355 case Replay_Set_General_Cmd: 356 //Header 357 cmd.replay_set_general_cmd.header.sub_type = 358 DMUB_CMD__REPLAY_SET_GENERAL_CMD; 359 cmd.replay_set_general_cmd.header.payload_bytes = 360 sizeof(struct dmub_rb_cmd_replay_set_general_cmd); 361 //Cmd Body 362 cmd.replay_set_general_cmd.data.panel_inst = 363 cmd_element->set_general_cmd_data.panel_inst; 364 cmd.replay_set_general_cmd.data.subtype = 365 cmd_element->set_general_cmd_data.subtype; 366 cmd.replay_set_general_cmd.data.param1 = 367 cmd_element->set_general_cmd_data.param1; 368 cmd.replay_set_general_cmd.data.param2 = 369 cmd_element->set_general_cmd_data.param2; 370 break; 371 case Replay_Msg_Not_Support: 372 default: 373 return; 374 break; 375 } 376 377 dc_wake_and_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 378 } 379 380 static const struct dmub_replay_funcs replay_funcs = { 381 .replay_copy_settings = dmub_replay_copy_settings, 382 .replay_enable = dmub_replay_enable, 383 .replay_get_state = dmub_replay_get_state, 384 .replay_set_power_opt = dmub_replay_set_power_opt, 385 .replay_set_coasting_vtotal = dmub_replay_set_coasting_vtotal, 386 .replay_residency = dmub_replay_residency, 387 .replay_set_power_opt_and_coasting_vtotal = dmub_replay_set_power_opt_and_coasting_vtotal, 388 .replay_send_cmd = dmub_replay_send_cmd, 389 }; 390 391 /* 392 * Construct Replay object. 393 */ 394 static void dmub_replay_construct(struct dmub_replay *replay, struct dc_context *ctx) 395 { 396 replay->ctx = ctx; 397 replay->funcs = &replay_funcs; 398 } 399 400 /* 401 * Allocate and initialize Replay object. 402 */ 403 struct dmub_replay *dmub_replay_create(struct dc_context *ctx) 404 { 405 struct dmub_replay *replay = kzalloc(sizeof(struct dmub_replay), GFP_KERNEL); 406 407 if (replay == NULL) { 408 BREAK_TO_DEBUGGER(); 409 return NULL; 410 } 411 412 dmub_replay_construct(replay, ctx); 413 414 return replay; 415 } 416 417 /* 418 * Deallocate Replay object. 419 */ 420 void dmub_replay_destroy(struct dmub_replay **dmub) 421 { 422 kfree(*dmub); 423 *dmub = NULL; 424 } 425