1ab3ee7a5SZeyu Fan /* Copyright 2012-15 Advanced Micro Devices, Inc. 2ab3ee7a5SZeyu Fan * 3ab3ee7a5SZeyu Fan * Permission is hereby granted, free of charge, to any person obtaining a 4ab3ee7a5SZeyu Fan * copy of this software and associated documentation files (the "Software"), 5ab3ee7a5SZeyu Fan * to deal in the Software without restriction, including without limitation 6ab3ee7a5SZeyu Fan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7ab3ee7a5SZeyu Fan * and/or sell copies of the Software, and to permit persons to whom the 8ab3ee7a5SZeyu Fan * Software is furnished to do so, subject to the following conditions: 9ab3ee7a5SZeyu Fan * 10ab3ee7a5SZeyu Fan * The above copyright notice and this permission notice shall be included in 11ab3ee7a5SZeyu Fan * all copies or substantial portions of the Software. 12ab3ee7a5SZeyu Fan * 13ab3ee7a5SZeyu Fan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14ab3ee7a5SZeyu Fan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15ab3ee7a5SZeyu Fan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16ab3ee7a5SZeyu Fan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17ab3ee7a5SZeyu Fan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18ab3ee7a5SZeyu Fan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19ab3ee7a5SZeyu Fan * OTHER DEALINGS IN THE SOFTWARE. 20ab3ee7a5SZeyu Fan * 21ab3ee7a5SZeyu Fan * Authors: AMD 22ab3ee7a5SZeyu Fan * 23ab3ee7a5SZeyu Fan */ 24ab3ee7a5SZeyu Fan 25ab3ee7a5SZeyu Fan #ifndef __DC_OPP_DCE_H__ 26ab3ee7a5SZeyu Fan #define __DC_OPP_DCE_H__ 27ab3ee7a5SZeyu Fan 28ab3ee7a5SZeyu Fan #include "dc_types.h" 29ab3ee7a5SZeyu Fan #include "opp.h" 30ab3ee7a5SZeyu Fan #include "core_types.h" 31ab3ee7a5SZeyu Fan 32ab3ee7a5SZeyu Fan #define FROM_DCE11_OPP(opp)\ 33ab3ee7a5SZeyu Fan container_of(opp, struct dce110_opp, base) 34ab3ee7a5SZeyu Fan 35ab3ee7a5SZeyu Fan enum dce110_opp_reg_type { 36ab3ee7a5SZeyu Fan DCE110_OPP_REG_DCP = 0, 37ab3ee7a5SZeyu Fan DCE110_OPP_REG_DCFE, 38ab3ee7a5SZeyu Fan DCE110_OPP_REG_FMT, 39ab3ee7a5SZeyu Fan 40ab3ee7a5SZeyu Fan DCE110_OPP_REG_MAX 41ab3ee7a5SZeyu Fan }; 42ab3ee7a5SZeyu Fan 43ab3ee7a5SZeyu Fan #define OPP_COMMON_REG_LIST_BASE(id) \ 44ab3ee7a5SZeyu Fan SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 45ab3ee7a5SZeyu Fan SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 46ab3ee7a5SZeyu Fan SRI(FMT_CONTROL, FMT, id), \ 47ab3ee7a5SZeyu Fan SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 48ab3ee7a5SZeyu Fan SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 49ab3ee7a5SZeyu Fan SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 50ab3ee7a5SZeyu Fan SRI(FMT_CLAMP_CNTL, FMT, id), \ 51ab3ee7a5SZeyu Fan SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 52ab3ee7a5SZeyu Fan SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 53ab3ee7a5SZeyu Fan SRI(FMT_CLAMP_COMPONENT_B, FMT, id) 54ab3ee7a5SZeyu Fan 55ab3ee7a5SZeyu Fan #define OPP_DCE_80_REG_LIST(id) \ 56ab3ee7a5SZeyu Fan OPP_COMMON_REG_LIST_BASE(id), \ 57ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 58ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 59ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 60ab3ee7a5SZeyu Fan 61ab3ee7a5SZeyu Fan #define OPP_DCE_100_REG_LIST(id) \ 62ab3ee7a5SZeyu Fan OPP_COMMON_REG_LIST_BASE(id), \ 63ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 64ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 65ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 66ab3ee7a5SZeyu Fan 67ab3ee7a5SZeyu Fan #define OPP_DCE_110_REG_LIST(id) \ 68ab3ee7a5SZeyu Fan OPP_COMMON_REG_LIST_BASE(id), \ 69ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 70ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 71ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 72ab3ee7a5SZeyu Fan 73ab3ee7a5SZeyu Fan #define OPP_DCE_112_REG_LIST(id) \ 74ab3ee7a5SZeyu Fan OPP_COMMON_REG_LIST_BASE(id), \ 75ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 76ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 77ab3ee7a5SZeyu Fan SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ 78ab3ee7a5SZeyu Fan SRI(CONTROL, FMT_MEMORY, id) 79ab3ee7a5SZeyu Fan 802c8ad2d5SAlex Deucher #define OPP_DCE_120_REG_LIST(id) \ 812c8ad2d5SAlex Deucher OPP_COMMON_REG_LIST_BASE(id), \ 822c8ad2d5SAlex Deucher SRI(CONTROL, FMT_MEMORY, id) 832c8ad2d5SAlex Deucher 84d85a1e53SMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 85d85a1e53SMauro Rossi #define OPP_DCE_60_REG_LIST(id) \ 86d85a1e53SMauro Rossi SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 87d85a1e53SMauro Rossi SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 88d85a1e53SMauro Rossi SRI(FMT_CONTROL, FMT, id), \ 89d85a1e53SMauro Rossi SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 90d85a1e53SMauro Rossi SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 91d85a1e53SMauro Rossi SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 92d85a1e53SMauro Rossi SRI(FMT_CLAMP_CNTL, FMT, id) 93d85a1e53SMauro Rossi #endif 94d85a1e53SMauro Rossi 95ab3ee7a5SZeyu Fan #define OPP_SF(reg_name, field_name, post_fix)\ 96ab3ee7a5SZeyu Fan .field_name = reg_name ## __ ## field_name ## post_fix 97ab3ee7a5SZeyu Fan 98ab3ee7a5SZeyu Fan #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 99ab3ee7a5SZeyu Fan OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 100ab3ee7a5SZeyu Fan OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 101ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 102ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 103ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 104ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 105ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 106ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 107ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 108ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 109ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 110ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 111ab3ee7a5SZeyu Fan OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 112ab3ee7a5SZeyu Fan OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 113ab3ee7a5SZeyu Fan OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 114*ab0d29d9SRodrigo Siqueira OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 115ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 116ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 117ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 118ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 119ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 120ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 121ab3ee7a5SZeyu Fan OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 122ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 123ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 124ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 125ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 126ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 127ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 128ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 129ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 130ab3ee7a5SZeyu Fan OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 131ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 132ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 133ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) 134ab3ee7a5SZeyu Fan 135ab3ee7a5SZeyu Fan #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ 136ab3ee7a5SZeyu Fan OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 137ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 138ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 139ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 140ab3ee7a5SZeyu Fan 141ab3ee7a5SZeyu Fan #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ 142ab3ee7a5SZeyu Fan OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 143ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 144ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 145ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 146ab3ee7a5SZeyu Fan 147ab3ee7a5SZeyu Fan #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 148ab3ee7a5SZeyu Fan OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 149ab3ee7a5SZeyu Fan OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 150ab3ee7a5SZeyu Fan OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 151ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 152ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 153ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ 154ab3ee7a5SZeyu Fan OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 155ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 156ab3c1798SVitaly Prosyak OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 157ab3ee7a5SZeyu Fan 158ab3ee7a5SZeyu Fan #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ 1597a09f5beSYue Hin Lau OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) 160ab3ee7a5SZeyu Fan 1612c8ad2d5SAlex Deucher #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ 1622c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 1632c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 1642c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 1652c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 1662c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 1672c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 1682c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 1692c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 1702c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 1712c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 1722c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 1732c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 1742c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 1752c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 1762c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 1772c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 1782c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 1792c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 1802c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 1812c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 1822c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 1832c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 184ab3c1798SVitaly Prosyak OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ 1852c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 1862c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 1872c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 1882c8ad2d5SAlex Deucher OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 1892c8ad2d5SAlex Deucher OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 1902c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 1912c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 1922c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 1932c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 1942c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 1952c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 1962c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 1972c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 1982c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 1992c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 2002c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 2012c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 2022c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 2032c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ 2042c8ad2d5SAlex Deucher OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) 2052c8ad2d5SAlex Deucher 206d85a1e53SMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 207d85a1e53SMauro Rossi #define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\ 208d85a1e53SMauro Rossi OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 209d85a1e53SMauro Rossi OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 210d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 211d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 212d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 213d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 214d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 215d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 216d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 217d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 218d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 219d85a1e53SMauro Rossi OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 220d85a1e53SMauro Rossi OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 221d85a1e53SMauro Rossi OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 222d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 223d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 224d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 225d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 226d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 227d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 228d85a1e53SMauro Rossi OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 229d85a1e53SMauro Rossi OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 230d85a1e53SMauro Rossi OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 231d85a1e53SMauro Rossi OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh) 232d85a1e53SMauro Rossi #endif 233d85a1e53SMauro Rossi 234ab3ee7a5SZeyu Fan #define OPP_REG_FIELD_LIST(type) \ 235ab3ee7a5SZeyu Fan type FMT_DYNAMIC_EXP_EN; \ 236ab3ee7a5SZeyu Fan type FMT_DYNAMIC_EXP_MODE; \ 237ab3ee7a5SZeyu Fan type FMT_TRUNCATE_EN; \ 238ab3ee7a5SZeyu Fan type FMT_TRUNCATE_DEPTH; \ 239ab3ee7a5SZeyu Fan type FMT_TRUNCATE_MODE; \ 240ab3ee7a5SZeyu Fan type FMT_SPATIAL_DITHER_EN; \ 241ab3ee7a5SZeyu Fan type FMT_SPATIAL_DITHER_DEPTH; \ 242ab3ee7a5SZeyu Fan type FMT_SPATIAL_DITHER_MODE; \ 243ab3ee7a5SZeyu Fan type FMT_TEMPORAL_DITHER_EN; \ 244ab3ee7a5SZeyu Fan type FMT_TEMPORAL_DITHER_RESET; \ 245ab3ee7a5SZeyu Fan type FMT_TEMPORAL_DITHER_OFFSET; \ 246ab3ee7a5SZeyu Fan type FMT_TEMPORAL_DITHER_DEPTH; \ 247ab3ee7a5SZeyu Fan type FMT_TEMPORAL_LEVEL; \ 248ab3ee7a5SZeyu Fan type FMT_25FRC_SEL; \ 249ab3ee7a5SZeyu Fan type FMT_50FRC_SEL; \ 250ab3ee7a5SZeyu Fan type FMT_75FRC_SEL; \ 251ab3ee7a5SZeyu Fan type FMT_HIGHPASS_RANDOM_ENABLE; \ 252ab3ee7a5SZeyu Fan type FMT_FRAME_RANDOM_ENABLE; \ 253ab3ee7a5SZeyu Fan type FMT_RGB_RANDOM_ENABLE; \ 254ab3ee7a5SZeyu Fan type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 255ab3ee7a5SZeyu Fan type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 256ab3c1798SVitaly Prosyak type FMT_STEREOSYNC_OVERRIDE; \ 257ab3ee7a5SZeyu Fan type FMT_RAND_R_SEED; \ 258ab3ee7a5SZeyu Fan type FMT_RAND_G_SEED; \ 259ab3ee7a5SZeyu Fan type FMT_RAND_B_SEED; \ 260ab3ee7a5SZeyu Fan type FMT420_MEM0_SOURCE_SEL; \ 261ab3ee7a5SZeyu Fan type FMT420_MEM0_PWR_FORCE; \ 262ab3ee7a5SZeyu Fan type FMT_SRC_SELECT; \ 263ab3ee7a5SZeyu Fan type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ 264ab3ee7a5SZeyu Fan type FMT_420_PIXEL_PHASE_LOCKED; \ 265ab3ee7a5SZeyu Fan type FMT_CLAMP_DATA_EN; \ 266ab3ee7a5SZeyu Fan type FMT_CLAMP_COLOR_FORMAT; \ 267ab3ee7a5SZeyu Fan type FMT_CLAMP_LOWER_R; \ 268ab3ee7a5SZeyu Fan type FMT_CLAMP_UPPER_R; \ 269ab3ee7a5SZeyu Fan type FMT_CLAMP_LOWER_G; \ 270ab3ee7a5SZeyu Fan type FMT_CLAMP_UPPER_G; \ 271ab3ee7a5SZeyu Fan type FMT_CLAMP_LOWER_B; \ 272ab3ee7a5SZeyu Fan type FMT_CLAMP_UPPER_B; \ 273ab3ee7a5SZeyu Fan type FMT_PIXEL_ENCODING; \ 274ab3ee7a5SZeyu Fan type FMT_SUBSAMPLING_ORDER; \ 275ab3ee7a5SZeyu Fan type FMT_SUBSAMPLING_MODE; \ 276ab3ee7a5SZeyu Fan type FMT_CBCR_BIT_REDUCTION_BYPASS;\ 277ab3ee7a5SZeyu Fan 278ab3ee7a5SZeyu Fan struct dce_opp_shift { 279ab3ee7a5SZeyu Fan OPP_REG_FIELD_LIST(uint8_t) 280ab3ee7a5SZeyu Fan }; 281ab3ee7a5SZeyu Fan 282ab3ee7a5SZeyu Fan struct dce_opp_mask { 283ab3ee7a5SZeyu Fan OPP_REG_FIELD_LIST(uint32_t) 284ab3ee7a5SZeyu Fan }; 285ab3ee7a5SZeyu Fan 286ab3ee7a5SZeyu Fan struct dce_opp_registers { 287ab3ee7a5SZeyu Fan uint32_t FMT_DYNAMIC_EXP_CNTL; 288ab3ee7a5SZeyu Fan uint32_t FMT_BIT_DEPTH_CONTROL; 289ab3ee7a5SZeyu Fan uint32_t FMT_CONTROL; 290ab3ee7a5SZeyu Fan uint32_t FMT_DITHER_RAND_R_SEED; 291ab3ee7a5SZeyu Fan uint32_t FMT_DITHER_RAND_G_SEED; 292ab3ee7a5SZeyu Fan uint32_t FMT_DITHER_RAND_B_SEED; 293ab3ee7a5SZeyu Fan uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; 294ab3ee7a5SZeyu Fan uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; 295ab3ee7a5SZeyu Fan uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; 296ab3ee7a5SZeyu Fan uint32_t CONTROL; 297ab3ee7a5SZeyu Fan uint32_t FMT_CLAMP_CNTL; 298ab3ee7a5SZeyu Fan uint32_t FMT_CLAMP_COMPONENT_R; 299ab3ee7a5SZeyu Fan uint32_t FMT_CLAMP_COMPONENT_G; 300ab3ee7a5SZeyu Fan uint32_t FMT_CLAMP_COMPONENT_B; 301ab3ee7a5SZeyu Fan }; 302ab3ee7a5SZeyu Fan 303ab3ee7a5SZeyu Fan /* OPP RELATED */ 304ab3ee7a5SZeyu Fan #define TO_DCE110_OPP(opp)\ 305ab3ee7a5SZeyu Fan container_of(opp, struct dce110_opp, base) 306ab3ee7a5SZeyu Fan 307ab3ee7a5SZeyu Fan struct dce110_opp { 308ab3ee7a5SZeyu Fan struct output_pixel_processor base; 309ab3ee7a5SZeyu Fan const struct dce_opp_registers *regs; 310ab3ee7a5SZeyu Fan const struct dce_opp_shift *opp_shift; 311ab3ee7a5SZeyu Fan const struct dce_opp_mask *opp_mask; 312ab3ee7a5SZeyu Fan }; 313ab3ee7a5SZeyu Fan 3149cf29399SDave Airlie void dce110_opp_construct(struct dce110_opp *opp110, 315ab3ee7a5SZeyu Fan struct dc_context *ctx, 316ab3ee7a5SZeyu Fan uint32_t inst, 317ab3ee7a5SZeyu Fan const struct dce_opp_registers *regs, 318ab3ee7a5SZeyu Fan const struct dce_opp_shift *opp_shift, 319ab3ee7a5SZeyu Fan const struct dce_opp_mask *opp_mask); 320ab3ee7a5SZeyu Fan 321d85a1e53SMauro Rossi #if defined(CONFIG_DRM_AMD_DC_SI) 322d85a1e53SMauro Rossi void dce60_opp_construct(struct dce110_opp *opp110, 323d85a1e53SMauro Rossi struct dc_context *ctx, 324d85a1e53SMauro Rossi uint32_t inst, 325d85a1e53SMauro Rossi const struct dce_opp_registers *regs, 326d85a1e53SMauro Rossi const struct dce_opp_shift *opp_shift, 327d85a1e53SMauro Rossi const struct dce_opp_mask *opp_mask); 328d85a1e53SMauro Rossi #endif 329d85a1e53SMauro Rossi 330ab3ee7a5SZeyu Fan void dce110_opp_destroy(struct output_pixel_processor **opp); 331ab3ee7a5SZeyu Fan 332ab3ee7a5SZeyu Fan 333ab3ee7a5SZeyu Fan 334ab3ee7a5SZeyu Fan /* FORMATTER RELATED */ 335ab3ee7a5SZeyu Fan void dce110_opp_program_bit_depth_reduction( 336ab3ee7a5SZeyu Fan struct output_pixel_processor *opp, 337ab3ee7a5SZeyu Fan const struct bit_depth_reduction_params *params); 338ab3ee7a5SZeyu Fan 339ab3ee7a5SZeyu Fan void dce110_opp_program_clamping_and_pixel_encoding( 340ab3ee7a5SZeyu Fan struct output_pixel_processor *opp, 341ab3ee7a5SZeyu Fan const struct clamping_and_pixel_encoding_params *params); 342ab3ee7a5SZeyu Fan 343ab3ee7a5SZeyu Fan void dce110_opp_set_dyn_expansion( 344ab3ee7a5SZeyu Fan struct output_pixel_processor *opp, 345ab3ee7a5SZeyu Fan enum dc_color_space color_sp, 346ab3ee7a5SZeyu Fan enum dc_color_depth color_dpth, 347ab3ee7a5SZeyu Fan enum signal_type signal); 348ab3ee7a5SZeyu Fan 349ab3ee7a5SZeyu Fan void dce110_opp_program_fmt( 350ab3ee7a5SZeyu Fan struct output_pixel_processor *opp, 351ab3ee7a5SZeyu Fan struct bit_depth_reduction_params *fmt_bit_depth, 352ab3ee7a5SZeyu Fan struct clamping_and_pixel_encoding_params *clamping); 353ab3ee7a5SZeyu Fan 354ab3ee7a5SZeyu Fan void dce110_opp_set_clamping( 355ab3ee7a5SZeyu Fan struct dce110_opp *opp110, 356ab3ee7a5SZeyu Fan const struct clamping_and_pixel_encoding_params *params); 357ab3ee7a5SZeyu Fan 358ab3ee7a5SZeyu Fan #endif 359