1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dce_dmcu.h" 32 #include "dm_services.h" 33 #include "reg_helper.h" 34 #include "fixed31_32.h" 35 #include "dc.h" 36 37 #define TO_DCE_DMCU(dmcu)\ 38 container_of(dmcu, struct dce_dmcu, base) 39 40 #define REG(reg) \ 41 (dmcu_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 46 47 #define CTX \ 48 dmcu_dce->base.ctx 49 50 /* PSR related commands */ 51 #define PSR_ENABLE 0x20 52 #define PSR_EXIT 0x21 53 #define PSR_SET 0x23 54 #define PSR_SET_WAITLOOP 0x31 55 #define MCP_INIT_DMCU 0x88 56 #define MCP_INIT_IRAM 0x89 57 #define MCP_SYNC_PHY_LOCK 0x90 58 #define MCP_SYNC_PHY_UNLOCK 0x91 59 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 60 #define CRC_WIN_NOTIFY 0x92 61 #define CRC_STOP_UPDATE 0x93 62 #define MCP_SEND_EDID_CEA 0xA0 63 #define EDID_CEA_CMD_ACK 1 64 #define EDID_CEA_CMD_NACK 2 65 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 66 67 // PSP FW version 68 #define mmMP0_SMN_C2PMSG_58 0x1607A 69 70 //Register access policy version 71 #define mmMP0_SMN_C2PMSG_91 0x1609B 72 73 #if defined(CONFIG_DRM_AMD_DC_DCN) 74 static const uint32_t abm_gain_stepsize = 0x0060; 75 #endif 76 77 static bool dce_dmcu_init(struct dmcu *dmcu) 78 { 79 // Do nothing 80 return true; 81 } 82 83 static bool dce_dmcu_load_iram(struct dmcu *dmcu, 84 unsigned int start_offset, 85 const char *src, 86 unsigned int bytes) 87 { 88 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 89 unsigned int count = 0; 90 91 /* Enable write access to IRAM */ 92 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 93 IRAM_HOST_ACCESS_EN, 1, 94 IRAM_WR_ADDR_AUTO_INC, 1); 95 96 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 97 98 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 99 100 for (count = 0; count < bytes; count++) 101 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 102 103 /* Disable write access to IRAM to allow dynamic sleep state */ 104 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 105 IRAM_HOST_ACCESS_EN, 0, 106 IRAM_WR_ADDR_AUTO_INC, 0); 107 108 return true; 109 } 110 111 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 112 { 113 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 114 115 uint32_t psr_state_offset = 0xf0; 116 117 /* Enable write access to IRAM */ 118 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 119 120 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 121 122 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 123 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 124 125 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 126 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 127 128 /* Disable write access to IRAM after finished using IRAM 129 * in order to allow dynamic sleep state 130 */ 131 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 132 } 133 134 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 135 { 136 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 137 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 138 unsigned int dmcu_wait_reg_ready_interval = 100; 139 140 unsigned int retryCount; 141 enum dc_psr_state state = PSR_STATE0; 142 143 /* waitDMCUReadyForCmd */ 144 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 145 dmcu_wait_reg_ready_interval, 146 dmcu_max_retry_on_wait_reg_ready); 147 148 /* setDMCUParam_Cmd */ 149 if (enable) 150 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 151 PSR_ENABLE); 152 else 153 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 154 PSR_EXIT); 155 156 /* notifyDMCUMsg */ 157 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 158 if (wait == true) { 159 for (retryCount = 0; retryCount <= 100; retryCount++) { 160 dce_get_dmcu_psr_state(dmcu, &state); 161 if (enable) { 162 if (state != PSR_STATE0) 163 break; 164 } else { 165 if (state == PSR_STATE0) 166 break; 167 } 168 udelay(10); 169 } 170 } 171 } 172 173 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 174 struct dc_link *link, 175 struct psr_context *psr_context) 176 { 177 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 178 179 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 180 unsigned int dmcu_wait_reg_ready_interval = 100; 181 182 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 183 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 184 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 185 186 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 187 psr_context->psrExitLinkTrainingRequired); 188 189 /* Enable static screen interrupts for PSR supported display */ 190 /* Disable the interrupt coming from other displays. */ 191 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 192 STATIC_SCREEN1_INT_TO_UC_EN, 0, 193 STATIC_SCREEN2_INT_TO_UC_EN, 0, 194 STATIC_SCREEN3_INT_TO_UC_EN, 0, 195 STATIC_SCREEN4_INT_TO_UC_EN, 0); 196 197 switch (psr_context->controllerId) { 198 /* Driver uses case 1 for unconfigured */ 199 case 1: 200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 201 STATIC_SCREEN1_INT_TO_UC_EN, 1); 202 break; 203 case 2: 204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 205 STATIC_SCREEN2_INT_TO_UC_EN, 1); 206 break; 207 case 3: 208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 209 STATIC_SCREEN3_INT_TO_UC_EN, 1); 210 break; 211 case 4: 212 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 213 STATIC_SCREEN4_INT_TO_UC_EN, 1); 214 break; 215 case 5: 216 /* CZ/NL only has 4 CRTC!! 217 * really valid. 218 * There is no interrupt enable mask for these instances. 219 */ 220 break; 221 case 6: 222 /* CZ/NL only has 4 CRTC!! 223 * These are here because they are defined in HW regspec, 224 * but not really valid. There is no interrupt enable mask 225 * for these instances. 226 */ 227 break; 228 default: 229 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 230 STATIC_SCREEN1_INT_TO_UC_EN, 1); 231 break; 232 } 233 234 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 235 psr_context->sdpTransmitLineNumDeadline); 236 237 /* waitDMCUReadyForCmd */ 238 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 239 dmcu_wait_reg_ready_interval, 240 dmcu_max_retry_on_wait_reg_ready); 241 242 /* setDMCUParam_PSRHostConfigData */ 243 masterCmdData1.u32All = 0; 244 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 245 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 246 masterCmdData1.bits.rfb_update_auto_en = 247 psr_context->rfb_update_auto_en; 248 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 249 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 250 masterCmdData1.bits.phy_type = psr_context->phyType; 251 masterCmdData1.bits.frame_cap_ind = 252 psr_context->psrFrameCaptureIndicationReq; 253 masterCmdData1.bits.aux_chan = psr_context->channel; 254 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 255 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 256 masterCmdData1.u32All); 257 258 masterCmdData2.u32All = 0; 259 masterCmdData2.bits.dig_fe = psr_context->engineId; 260 masterCmdData2.bits.dig_be = psr_context->transmitterId; 261 masterCmdData2.bits.skip_wait_for_pll_lock = 262 psr_context->skipPsrWaitForPllLock; 263 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 264 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 265 masterCmdData2.bits.num_of_controllers = 266 psr_context->numberOfControllers; 267 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 268 masterCmdData2.u32All); 269 270 masterCmdData3.u32All = 0; 271 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 272 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 273 masterCmdData3.u32All); 274 275 /* setDMCUParam_Cmd */ 276 REG_UPDATE(MASTER_COMM_CMD_REG, 277 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 278 279 /* notifyDMCUMsg */ 280 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 281 282 return true; 283 } 284 285 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 286 { 287 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 288 unsigned int dmcu_uc_reset; 289 290 /* microcontroller is not running */ 291 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 292 293 /* DMCU is not running */ 294 if (dmcu_uc_reset) 295 return false; 296 297 return true; 298 } 299 300 static void dce_psr_wait_loop( 301 struct dmcu *dmcu, 302 unsigned int wait_loop_number) 303 { 304 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 305 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 306 307 if (dmcu->cached_wait_loop_number == wait_loop_number) 308 return; 309 310 /* DMCU is not running */ 311 if (!dce_is_dmcu_initialized(dmcu)) 312 return; 313 314 /* waitDMCUReadyForCmd */ 315 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 316 317 masterCmdData1.u32 = 0; 318 masterCmdData1.bits.wait_loop = wait_loop_number; 319 dmcu->cached_wait_loop_number = wait_loop_number; 320 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 321 322 /* setDMCUParam_Cmd */ 323 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 324 325 /* notifyDMCUMsg */ 326 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 327 } 328 329 static void dce_get_psr_wait_loop( 330 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 331 { 332 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 333 return; 334 } 335 336 #if defined(CONFIG_DRM_AMD_DC_DCN) 337 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 338 { 339 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 340 uint32_t dmcu_version_offset = 0xf1; 341 342 /* Enable write access to IRAM */ 343 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 344 IRAM_HOST_ACCESS_EN, 1, 345 IRAM_RD_ADDR_AUTO_INC, 1); 346 347 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 348 349 /* Write address to IRAM_RD_ADDR and read from DATA register */ 350 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 351 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 352 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 353 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 354 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 355 REG_READ(DMCU_IRAM_RD_DATA)); 356 357 /* Disable write access to IRAM to allow dynamic sleep state */ 358 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 359 IRAM_HOST_ACCESS_EN, 0, 360 IRAM_RD_ADDR_AUTO_INC, 0); 361 } 362 363 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 364 uint32_t fractional_pwm) 365 { 366 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 367 368 /* Wait until microcontroller is ready to process interrupt */ 369 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 370 371 /* Set PWM fractional enable/disable */ 372 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 373 374 /* Set command to enable or disable fractional PWM microcontroller */ 375 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 376 MCP_BL_SET_PWM_FRAC); 377 378 /* Notify microcontroller of new command */ 379 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 380 381 /* Ensure command has been executed before continuing */ 382 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 383 } 384 385 static bool dcn10_dmcu_init(struct dmcu *dmcu) 386 { 387 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 388 const struct dc_config *config = &dmcu->ctx->dc->config; 389 bool status = false; 390 struct dc_context *ctx = dmcu->ctx; 391 unsigned int i; 392 // 5 4 3 2 1 0 393 // F E D C B A - bit 0 is A, bit 5 is F 394 unsigned int tx_interrupt_mask = 0; 395 396 PERF_TRACE(); 397 /* Definition of DC_DMCU_SCRATCH 398 * 0 : firmare not loaded 399 * 1 : PSP load DMCU FW but not initialized 400 * 2 : Firmware already initialized 401 */ 402 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 403 404 for (i = 0; i < ctx->dc->link_count; i++) { 405 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 406 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 407 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 408 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 409 } 410 } 411 } 412 413 switch (dmcu->dmcu_state) { 414 case DMCU_UNLOADED: 415 status = false; 416 break; 417 case DMCU_LOADED_UNINITIALIZED: 418 /* Wait until microcontroller is ready to process interrupt */ 419 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 420 421 /* Set initialized ramping boundary value */ 422 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 423 424 /* Set backlight ramping stepsize */ 425 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 426 427 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 428 429 /* Set command to initialize microcontroller */ 430 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 431 MCP_INIT_DMCU); 432 433 /* Notify microcontroller of new command */ 434 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 435 436 /* Ensure command has been executed before continuing */ 437 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 438 439 // Check state is initialized 440 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 441 442 // If microcontroller is not in running state, fail 443 if (dmcu->dmcu_state == DMCU_RUNNING) { 444 /* Retrieve and cache the DMCU firmware version. */ 445 dcn10_get_dmcu_version(dmcu); 446 447 /* Initialize DMCU to use fractional PWM or not */ 448 dcn10_dmcu_enable_fractional_pwm(dmcu, 449 (config->disable_fractional_pwm == false) ? 1 : 0); 450 status = true; 451 } else { 452 status = false; 453 } 454 455 break; 456 case DMCU_RUNNING: 457 status = true; 458 break; 459 default: 460 status = false; 461 break; 462 } 463 464 PERF_TRACE(); 465 return status; 466 } 467 468 static bool dcn21_dmcu_init(struct dmcu *dmcu) 469 { 470 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 471 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 472 473 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 474 return false; 475 } 476 477 return dcn10_dmcu_init(dmcu); 478 } 479 480 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 481 unsigned int start_offset, 482 const char *src, 483 unsigned int bytes) 484 { 485 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 486 unsigned int count = 0; 487 488 /* If microcontroller is not running, do nothing */ 489 if (dmcu->dmcu_state != DMCU_RUNNING) 490 return false; 491 492 /* Enable write access to IRAM */ 493 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 494 IRAM_HOST_ACCESS_EN, 1, 495 IRAM_WR_ADDR_AUTO_INC, 1); 496 497 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 498 499 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 500 501 for (count = 0; count < bytes; count++) 502 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 503 504 /* Disable write access to IRAM to allow dynamic sleep state */ 505 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 506 IRAM_HOST_ACCESS_EN, 0, 507 IRAM_WR_ADDR_AUTO_INC, 0); 508 509 /* Wait until microcontroller is ready to process interrupt */ 510 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 511 512 /* Set command to signal IRAM is loaded and to initialize IRAM */ 513 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 514 MCP_INIT_IRAM); 515 516 /* Notify microcontroller of new command */ 517 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 518 519 /* Ensure command has been executed before continuing */ 520 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 521 522 return true; 523 } 524 525 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 526 { 527 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 528 529 uint32_t psr_state_offset = 0xf0; 530 531 /* If microcontroller is not running, do nothing */ 532 if (dmcu->dmcu_state != DMCU_RUNNING) 533 return; 534 535 /* Enable write access to IRAM */ 536 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 537 538 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 539 540 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 541 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 542 543 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 544 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 545 546 /* Disable write access to IRAM after finished using IRAM 547 * in order to allow dynamic sleep state 548 */ 549 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 550 } 551 552 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 553 { 554 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 555 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 556 unsigned int dmcu_wait_reg_ready_interval = 100; 557 558 unsigned int retryCount; 559 enum dc_psr_state state = PSR_STATE0; 560 561 /* If microcontroller is not running, do nothing */ 562 if (dmcu->dmcu_state != DMCU_RUNNING) 563 return; 564 565 /* waitDMCUReadyForCmd */ 566 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 567 dmcu_wait_reg_ready_interval, 568 dmcu_max_retry_on_wait_reg_ready); 569 570 /* setDMCUParam_Cmd */ 571 if (enable) 572 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 573 PSR_ENABLE); 574 else 575 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 576 PSR_EXIT); 577 578 /* notifyDMCUMsg */ 579 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 580 581 /* Below loops 1000 x 500us = 500 ms. 582 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 583 * least a few frames. Should never hit the max retry assert below. 584 */ 585 if (wait == true) { 586 for (retryCount = 0; retryCount <= 1000; retryCount++) { 587 dcn10_get_dmcu_psr_state(dmcu, &state); 588 if (enable) { 589 if (state != PSR_STATE0) 590 break; 591 } else { 592 if (state == PSR_STATE0) 593 break; 594 } 595 udelay(500); 596 } 597 598 /* assert if max retry hit */ 599 if (retryCount >= 1000) 600 ASSERT(0); 601 } 602 } 603 604 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 605 struct dc_link *link, 606 struct psr_context *psr_context) 607 { 608 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 609 610 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 611 unsigned int dmcu_wait_reg_ready_interval = 100; 612 613 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 614 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 615 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 616 617 /* If microcontroller is not running, do nothing */ 618 if (dmcu->dmcu_state != DMCU_RUNNING) 619 return false; 620 621 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 622 psr_context->psrExitLinkTrainingRequired); 623 624 /* Enable static screen interrupts for PSR supported display */ 625 /* Disable the interrupt coming from other displays. */ 626 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 627 STATIC_SCREEN1_INT_TO_UC_EN, 0, 628 STATIC_SCREEN2_INT_TO_UC_EN, 0, 629 STATIC_SCREEN3_INT_TO_UC_EN, 0, 630 STATIC_SCREEN4_INT_TO_UC_EN, 0); 631 632 switch (psr_context->controllerId) { 633 /* Driver uses case 1 for unconfigured */ 634 case 1: 635 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 636 STATIC_SCREEN1_INT_TO_UC_EN, 1); 637 break; 638 case 2: 639 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 640 STATIC_SCREEN2_INT_TO_UC_EN, 1); 641 break; 642 case 3: 643 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 644 STATIC_SCREEN3_INT_TO_UC_EN, 1); 645 break; 646 case 4: 647 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 648 STATIC_SCREEN4_INT_TO_UC_EN, 1); 649 break; 650 case 5: 651 /* CZ/NL only has 4 CRTC!! 652 * really valid. 653 * There is no interrupt enable mask for these instances. 654 */ 655 break; 656 case 6: 657 /* CZ/NL only has 4 CRTC!! 658 * These are here because they are defined in HW regspec, 659 * but not really valid. There is no interrupt enable mask 660 * for these instances. 661 */ 662 break; 663 default: 664 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 665 STATIC_SCREEN1_INT_TO_UC_EN, 1); 666 break; 667 } 668 669 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 670 psr_context->sdpTransmitLineNumDeadline); 671 672 if (psr_context->allow_smu_optimizations) 673 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 674 675 /* waitDMCUReadyForCmd */ 676 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 677 dmcu_wait_reg_ready_interval, 678 dmcu_max_retry_on_wait_reg_ready); 679 680 /* setDMCUParam_PSRHostConfigData */ 681 masterCmdData1.u32All = 0; 682 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 683 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 684 masterCmdData1.bits.rfb_update_auto_en = 685 psr_context->rfb_update_auto_en; 686 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 687 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 688 masterCmdData1.bits.phy_type = psr_context->phyType; 689 masterCmdData1.bits.frame_cap_ind = 690 psr_context->psrFrameCaptureIndicationReq; 691 masterCmdData1.bits.aux_chan = psr_context->channel; 692 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 693 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 694 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 695 masterCmdData1.u32All); 696 697 masterCmdData2.u32All = 0; 698 masterCmdData2.bits.dig_fe = psr_context->engineId; 699 masterCmdData2.bits.dig_be = psr_context->transmitterId; 700 masterCmdData2.bits.skip_wait_for_pll_lock = 701 psr_context->skipPsrWaitForPllLock; 702 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 703 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 704 masterCmdData2.bits.num_of_controllers = 705 psr_context->numberOfControllers; 706 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 707 masterCmdData2.u32All); 708 709 masterCmdData3.u32All = 0; 710 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 711 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 712 masterCmdData3.u32All); 713 714 715 /* setDMCUParam_Cmd */ 716 REG_UPDATE(MASTER_COMM_CMD_REG, 717 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 718 719 /* notifyDMCUMsg */ 720 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 721 722 /* waitDMCUReadyForCmd */ 723 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 724 725 return true; 726 } 727 728 static void dcn10_psr_wait_loop( 729 struct dmcu *dmcu, 730 unsigned int wait_loop_number) 731 { 732 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 733 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 734 735 /* If microcontroller is not running, do nothing */ 736 if (dmcu->dmcu_state != DMCU_RUNNING) 737 return; 738 739 if (wait_loop_number != 0) { 740 /* waitDMCUReadyForCmd */ 741 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 742 743 masterCmdData1.u32 = 0; 744 masterCmdData1.bits.wait_loop = wait_loop_number; 745 dmcu->cached_wait_loop_number = wait_loop_number; 746 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 747 748 /* setDMCUParam_Cmd */ 749 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 750 751 /* notifyDMCUMsg */ 752 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 753 } 754 } 755 756 static void dcn10_get_psr_wait_loop( 757 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 758 { 759 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 760 return; 761 } 762 763 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 764 { 765 /* microcontroller is not running */ 766 if (dmcu->dmcu_state != DMCU_RUNNING) 767 return false; 768 return true; 769 } 770 771 772 773 static bool dcn20_lock_phy(struct dmcu *dmcu) 774 { 775 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 776 777 /* If microcontroller is not running, do nothing */ 778 if (dmcu->dmcu_state != DMCU_RUNNING) 779 return false; 780 781 /* waitDMCUReadyForCmd */ 782 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 783 784 /* setDMCUParam_Cmd */ 785 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 786 787 /* notifyDMCUMsg */ 788 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 789 790 /* waitDMCUReadyForCmd */ 791 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 792 793 return true; 794 } 795 796 static bool dcn20_unlock_phy(struct dmcu *dmcu) 797 { 798 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 799 800 /* If microcontroller is not running, do nothing */ 801 if (dmcu->dmcu_state != DMCU_RUNNING) 802 return false; 803 804 /* waitDMCUReadyForCmd */ 805 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 806 807 /* setDMCUParam_Cmd */ 808 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 809 810 /* notifyDMCUMsg */ 811 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 812 813 /* waitDMCUReadyForCmd */ 814 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 815 816 return true; 817 } 818 819 static bool dcn10_send_edid_cea(struct dmcu *dmcu, 820 int offset, 821 int total_length, 822 uint8_t *data, 823 int length) 824 { 825 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 826 uint32_t header, data1, data2; 827 828 /* If microcontroller is not running, do nothing */ 829 if (dmcu->dmcu_state != DMCU_RUNNING) 830 return false; 831 832 if (length > 8 || length <= 0) 833 return false; 834 835 header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF); 836 data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | 837 (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); 838 data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | 839 (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); 840 841 /* waitDMCUReadyForCmd */ 842 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 843 844 /* setDMCUParam_Cmd */ 845 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA); 846 847 REG_WRITE(MASTER_COMM_DATA_REG1, header); 848 REG_WRITE(MASTER_COMM_DATA_REG2, data1); 849 REG_WRITE(MASTER_COMM_DATA_REG3, data2); 850 851 /* notifyDMCUMsg */ 852 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 853 854 /* waitDMCUReadyForCmd */ 855 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 856 857 return true; 858 } 859 860 static bool dcn10_get_scp_results(struct dmcu *dmcu, 861 uint32_t *cmd, 862 uint32_t *data1, 863 uint32_t *data2, 864 uint32_t *data3) 865 { 866 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 867 868 /* If microcontroller is not running, do nothing */ 869 if (dmcu->dmcu_state != DMCU_RUNNING) 870 return false; 871 872 *cmd = REG_READ(SLAVE_COMM_CMD_REG); 873 *data1 = REG_READ(SLAVE_COMM_DATA_REG1); 874 *data2 = REG_READ(SLAVE_COMM_DATA_REG2); 875 *data3 = REG_READ(SLAVE_COMM_DATA_REG3); 876 877 /* clear SCP interrupt */ 878 REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0); 879 880 return true; 881 } 882 883 static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, 884 int *version, 885 int *min_frame_rate, 886 int *max_frame_rate) 887 { 888 uint32_t data[4]; 889 int cmd, ack, len; 890 891 if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) 892 return false; 893 894 cmd = data[0] & 0x3FF; 895 len = (data[0] >> 10) & 0x3F; 896 ack = data[1]; 897 898 if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12) 899 return false; 900 901 if ((data[2] & 0xFF)) { 902 *version = (data[2] >> 8) & 0xFF; 903 *min_frame_rate = (data[3] >> 16) & 0xFFFF; 904 *max_frame_rate = data[3] & 0xFFFF; 905 return true; 906 } 907 908 return false; 909 } 910 911 static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) 912 { 913 uint32_t data[4]; 914 int cmd, ack; 915 916 if (!dcn10_get_scp_results(dmcu, 917 &data[0], &data[1], &data[2], &data[3])) 918 return false; 919 920 cmd = data[0] & 0x3FF; 921 ack = data[1]; 922 923 if (cmd != MCP_SEND_EDID_CEA) 924 return false; 925 926 if (ack == EDID_CEA_CMD_ACK) 927 return true; 928 929 *offset = data[2]; /* nack */ 930 return false; 931 } 932 933 #endif //(CONFIG_DRM_AMD_DC_DCN) 934 935 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 936 static void dcn10_forward_crc_window(struct dmcu *dmcu, 937 struct crc_region *crc_win, 938 struct otg_phy_mux *mux_mapping) 939 { 940 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 941 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 942 unsigned int dmcu_wait_reg_ready_interval = 100; 943 unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0; 944 945 /* If microcontroller is not running, do nothing */ 946 if (dmcu->dmcu_state != DMCU_RUNNING) 947 return; 948 949 if (!crc_win) 950 return; 951 952 /* waitDMCUReadyForCmd */ 953 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 954 dmcu_wait_reg_ready_interval, 955 dmcu_max_retry_on_wait_reg_ready); 956 957 /* build up nitification data */ 958 crc_start = (((unsigned int) crc_win->x_start) << 16) | crc_win->y_start; 959 crc_end = (((unsigned int) crc_win->x_end) << 16) | crc_win->y_end; 960 otg_phy_mux = 961 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 962 963 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 964 crc_start); 965 966 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 967 crc_end); 968 969 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 970 otg_phy_mux); 971 972 /* setDMCUParam_Cmd */ 973 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 974 CRC_WIN_NOTIFY); 975 976 /* notifyDMCUMsg */ 977 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 978 } 979 980 static void dcn10_stop_crc_win_update(struct dmcu *dmcu, 981 struct otg_phy_mux *mux_mapping) 982 { 983 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 984 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 985 unsigned int dmcu_wait_reg_ready_interval = 100; 986 unsigned int otg_phy_mux = 0; 987 988 /* If microcontroller is not running, do nothing */ 989 if (dmcu->dmcu_state != DMCU_RUNNING) 990 return; 991 992 /* waitDMCUReadyForCmd */ 993 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 994 dmcu_wait_reg_ready_interval, 995 dmcu_max_retry_on_wait_reg_ready); 996 997 /* build up nitification data */ 998 otg_phy_mux = 999 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 1000 1001 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 1002 otg_phy_mux); 1003 1004 /* setDMCUParam_Cmd */ 1005 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 1006 CRC_STOP_UPDATE); 1007 1008 /* notifyDMCUMsg */ 1009 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 1010 } 1011 #endif 1012 1013 static const struct dmcu_funcs dce_funcs = { 1014 .dmcu_init = dce_dmcu_init, 1015 .load_iram = dce_dmcu_load_iram, 1016 .set_psr_enable = dce_dmcu_set_psr_enable, 1017 .setup_psr = dce_dmcu_setup_psr, 1018 .get_psr_state = dce_get_dmcu_psr_state, 1019 .set_psr_wait_loop = dce_psr_wait_loop, 1020 .get_psr_wait_loop = dce_get_psr_wait_loop, 1021 .is_dmcu_initialized = dce_is_dmcu_initialized 1022 }; 1023 1024 #if defined(CONFIG_DRM_AMD_DC_DCN) 1025 static const struct dmcu_funcs dcn10_funcs = { 1026 .dmcu_init = dcn10_dmcu_init, 1027 .load_iram = dcn10_dmcu_load_iram, 1028 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1029 .setup_psr = dcn10_dmcu_setup_psr, 1030 .get_psr_state = dcn10_get_dmcu_psr_state, 1031 .set_psr_wait_loop = dcn10_psr_wait_loop, 1032 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1033 .send_edid_cea = dcn10_send_edid_cea, 1034 .recv_amd_vsdb = dcn10_recv_amd_vsdb, 1035 .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, 1036 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1037 .forward_crc_window = dcn10_forward_crc_window, 1038 .stop_crc_win_update = dcn10_stop_crc_win_update, 1039 #endif 1040 .is_dmcu_initialized = dcn10_is_dmcu_initialized 1041 }; 1042 1043 static const struct dmcu_funcs dcn20_funcs = { 1044 .dmcu_init = dcn10_dmcu_init, 1045 .load_iram = dcn10_dmcu_load_iram, 1046 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1047 .setup_psr = dcn10_dmcu_setup_psr, 1048 .get_psr_state = dcn10_get_dmcu_psr_state, 1049 .set_psr_wait_loop = dcn10_psr_wait_loop, 1050 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1051 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1052 .lock_phy = dcn20_lock_phy, 1053 .unlock_phy = dcn20_unlock_phy 1054 }; 1055 1056 static const struct dmcu_funcs dcn21_funcs = { 1057 .dmcu_init = dcn21_dmcu_init, 1058 .load_iram = dcn10_dmcu_load_iram, 1059 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1060 .setup_psr = dcn10_dmcu_setup_psr, 1061 .get_psr_state = dcn10_get_dmcu_psr_state, 1062 .set_psr_wait_loop = dcn10_psr_wait_loop, 1063 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1064 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1065 .lock_phy = dcn20_lock_phy, 1066 .unlock_phy = dcn20_unlock_phy 1067 }; 1068 #endif 1069 1070 static void dce_dmcu_construct( 1071 struct dce_dmcu *dmcu_dce, 1072 struct dc_context *ctx, 1073 const struct dce_dmcu_registers *regs, 1074 const struct dce_dmcu_shift *dmcu_shift, 1075 const struct dce_dmcu_mask *dmcu_mask) 1076 { 1077 struct dmcu *base = &dmcu_dce->base; 1078 1079 base->ctx = ctx; 1080 base->funcs = &dce_funcs; 1081 base->cached_wait_loop_number = 0; 1082 1083 dmcu_dce->regs = regs; 1084 dmcu_dce->dmcu_shift = dmcu_shift; 1085 dmcu_dce->dmcu_mask = dmcu_mask; 1086 } 1087 1088 #if defined(CONFIG_DRM_AMD_DC_DCN) 1089 static void dcn21_dmcu_construct( 1090 struct dce_dmcu *dmcu_dce, 1091 struct dc_context *ctx, 1092 const struct dce_dmcu_registers *regs, 1093 const struct dce_dmcu_shift *dmcu_shift, 1094 const struct dce_dmcu_mask *dmcu_mask) 1095 { 1096 uint32_t psp_version = 0; 1097 1098 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1099 1100 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 1101 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 1102 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 1103 dmcu_dce->base.psp_version = psp_version; 1104 } 1105 } 1106 #endif 1107 1108 struct dmcu *dce_dmcu_create( 1109 struct dc_context *ctx, 1110 const struct dce_dmcu_registers *regs, 1111 const struct dce_dmcu_shift *dmcu_shift, 1112 const struct dce_dmcu_mask *dmcu_mask) 1113 { 1114 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 1115 1116 if (dmcu_dce == NULL) { 1117 BREAK_TO_DEBUGGER(); 1118 return NULL; 1119 } 1120 1121 dce_dmcu_construct( 1122 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1123 1124 dmcu_dce->base.funcs = &dce_funcs; 1125 1126 return &dmcu_dce->base; 1127 } 1128 1129 #if defined(CONFIG_DRM_AMD_DC_DCN) 1130 struct dmcu *dcn10_dmcu_create( 1131 struct dc_context *ctx, 1132 const struct dce_dmcu_registers *regs, 1133 const struct dce_dmcu_shift *dmcu_shift, 1134 const struct dce_dmcu_mask *dmcu_mask) 1135 { 1136 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1137 1138 if (dmcu_dce == NULL) { 1139 BREAK_TO_DEBUGGER(); 1140 return NULL; 1141 } 1142 1143 dce_dmcu_construct( 1144 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1145 1146 dmcu_dce->base.funcs = &dcn10_funcs; 1147 1148 return &dmcu_dce->base; 1149 } 1150 1151 struct dmcu *dcn20_dmcu_create( 1152 struct dc_context *ctx, 1153 const struct dce_dmcu_registers *regs, 1154 const struct dce_dmcu_shift *dmcu_shift, 1155 const struct dce_dmcu_mask *dmcu_mask) 1156 { 1157 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1158 1159 if (dmcu_dce == NULL) { 1160 BREAK_TO_DEBUGGER(); 1161 return NULL; 1162 } 1163 1164 dce_dmcu_construct( 1165 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1166 1167 dmcu_dce->base.funcs = &dcn20_funcs; 1168 1169 return &dmcu_dce->base; 1170 } 1171 1172 struct dmcu *dcn21_dmcu_create( 1173 struct dc_context *ctx, 1174 const struct dce_dmcu_registers *regs, 1175 const struct dce_dmcu_shift *dmcu_shift, 1176 const struct dce_dmcu_mask *dmcu_mask) 1177 { 1178 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); 1179 1180 if (dmcu_dce == NULL) { 1181 BREAK_TO_DEBUGGER(); 1182 return NULL; 1183 } 1184 1185 dcn21_dmcu_construct( 1186 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1187 1188 dmcu_dce->base.funcs = &dcn21_funcs; 1189 1190 return &dmcu_dce->base; 1191 } 1192 #endif 1193 1194 void dce_dmcu_destroy(struct dmcu **dmcu) 1195 { 1196 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 1197 1198 kfree(dmcu_dce); 1199 *dmcu = NULL; 1200 } 1201