1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MCP_SYNC_PHY_LOCK 0x90 55 #define MCP_SYNC_PHY_UNLOCK 0x91 56 #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */ 57 #define CRC_WIN_NOTIFY 0x92 58 #define CRC_STOP_UPDATE 0x93 59 #define MCP_SEND_EDID_CEA 0xA0 60 #define EDID_CEA_CMD_ACK 1 61 #define EDID_CEA_CMD_NACK 2 62 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 63 64 // PSP FW version 65 #define mmMP0_SMN_C2PMSG_58 0x1607A 66 67 //Register access policy version 68 #define mmMP0_SMN_C2PMSG_91 0x1609B 69 70 static const uint32_t abm_gain_stepsize = 0x0060; 71 72 static bool dce_dmcu_init(struct dmcu *dmcu) 73 { 74 (void)dmcu; 75 // Do nothing 76 return true; 77 } 78 79 static bool dce_dmcu_load_iram(struct dmcu *dmcu, 80 unsigned int start_offset, 81 const char *src, 82 unsigned int bytes) 83 { 84 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 85 unsigned int count = 0; 86 87 /* Enable write access to IRAM */ 88 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 89 IRAM_HOST_ACCESS_EN, 1, 90 IRAM_WR_ADDR_AUTO_INC, 1); 91 92 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 93 94 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 95 96 for (count = 0; count < bytes; count++) 97 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 98 99 /* Disable write access to IRAM to allow dynamic sleep state */ 100 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 101 IRAM_HOST_ACCESS_EN, 0, 102 IRAM_WR_ADDR_AUTO_INC, 0); 103 104 return true; 105 } 106 107 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 108 { 109 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 110 111 uint32_t psr_state_offset = 0xf0; 112 113 /* Enable write access to IRAM */ 114 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 115 116 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 117 118 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 119 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 120 121 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 122 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 123 124 /* Disable write access to IRAM after finished using IRAM 125 * in order to allow dynamic sleep state 126 */ 127 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 128 } 129 130 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 131 { 132 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 133 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 134 unsigned int dmcu_wait_reg_ready_interval = 100; 135 136 unsigned int retryCount; 137 enum dc_psr_state state = PSR_STATE0; 138 139 /* waitDMCUReadyForCmd */ 140 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 141 dmcu_wait_reg_ready_interval, 142 dmcu_max_retry_on_wait_reg_ready); 143 144 /* setDMCUParam_Cmd */ 145 if (enable) 146 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 147 PSR_ENABLE); 148 else 149 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 150 PSR_EXIT); 151 152 /* notifyDMCUMsg */ 153 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 154 if (wait == true) { 155 for (retryCount = 0; retryCount <= 100; retryCount++) { 156 dce_get_dmcu_psr_state(dmcu, &state); 157 if (enable) { 158 if (state != PSR_STATE0) 159 break; 160 } else { 161 if (state == PSR_STATE0) 162 break; 163 } 164 udelay(10); 165 } 166 } 167 } 168 169 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 170 struct dc_link *link, 171 struct psr_context *psr_context) 172 { 173 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 174 175 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 176 unsigned int dmcu_wait_reg_ready_interval = 100; 177 178 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 179 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 180 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 181 182 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 183 psr_context->psrExitLinkTrainingRequired); 184 185 /* Enable static screen interrupts for PSR supported display */ 186 /* Disable the interrupt coming from other displays. */ 187 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 188 STATIC_SCREEN1_INT_TO_UC_EN, 0, 189 STATIC_SCREEN2_INT_TO_UC_EN, 0, 190 STATIC_SCREEN3_INT_TO_UC_EN, 0, 191 STATIC_SCREEN4_INT_TO_UC_EN, 0); 192 193 switch (psr_context->controllerId) { 194 /* Driver uses case 1 for unconfigured */ 195 case 1: 196 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 197 STATIC_SCREEN1_INT_TO_UC_EN, 1); 198 break; 199 case 2: 200 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 201 STATIC_SCREEN2_INT_TO_UC_EN, 1); 202 break; 203 case 3: 204 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 205 STATIC_SCREEN3_INT_TO_UC_EN, 1); 206 break; 207 case 4: 208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 209 STATIC_SCREEN4_INT_TO_UC_EN, 1); 210 break; 211 case 5: 212 /* CZ/NL only has 4 CRTC!! 213 * really valid. 214 * There is no interrupt enable mask for these instances. 215 */ 216 break; 217 case 6: 218 /* CZ/NL only has 4 CRTC!! 219 * These are here because they are defined in HW regspec, 220 * but not really valid. There is no interrupt enable mask 221 * for these instances. 222 */ 223 break; 224 default: 225 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 226 STATIC_SCREEN1_INT_TO_UC_EN, 1); 227 break; 228 } 229 230 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 231 psr_context->sdpTransmitLineNumDeadline); 232 233 /* waitDMCUReadyForCmd */ 234 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 235 dmcu_wait_reg_ready_interval, 236 dmcu_max_retry_on_wait_reg_ready); 237 238 /* setDMCUParam_PSRHostConfigData */ 239 masterCmdData1.u32All = 0; 240 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 241 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 242 masterCmdData1.bits.rfb_update_auto_en = 243 psr_context->rfb_update_auto_en; 244 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 245 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 246 masterCmdData1.bits.phy_type = psr_context->phyType; 247 masterCmdData1.bits.frame_cap_ind = 248 psr_context->psrFrameCaptureIndicationReq; 249 masterCmdData1.bits.aux_chan = psr_context->channel; 250 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 251 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 252 masterCmdData1.u32All); 253 254 masterCmdData2.u32All = 0; 255 masterCmdData2.bits.dig_fe = psr_context->engineId; 256 masterCmdData2.bits.dig_be = psr_context->transmitterId; 257 masterCmdData2.bits.skip_wait_for_pll_lock = 258 psr_context->skipPsrWaitForPllLock; 259 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 260 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 261 masterCmdData2.bits.num_of_controllers = 262 psr_context->numberOfControllers; 263 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 264 masterCmdData2.u32All); 265 266 masterCmdData3.u32All = 0; 267 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 268 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 269 masterCmdData3.u32All); 270 271 /* setDMCUParam_Cmd */ 272 REG_UPDATE(MASTER_COMM_CMD_REG, 273 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 274 275 /* notifyDMCUMsg */ 276 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 277 278 return true; 279 } 280 281 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 282 { 283 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 284 unsigned int dmcu_uc_reset; 285 286 /* microcontroller is not running */ 287 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 288 289 /* DMCU is not running */ 290 if (dmcu_uc_reset) 291 return false; 292 293 return true; 294 } 295 296 static void dce_psr_wait_loop( 297 struct dmcu *dmcu, 298 unsigned int wait_loop_number) 299 { 300 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 301 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 302 303 if (dmcu->cached_wait_loop_number == wait_loop_number) 304 return; 305 306 /* DMCU is not running */ 307 if (!dce_is_dmcu_initialized(dmcu)) 308 return; 309 310 /* waitDMCUReadyForCmd */ 311 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 312 313 masterCmdData1.u32 = 0; 314 masterCmdData1.bits.wait_loop = wait_loop_number; 315 dmcu->cached_wait_loop_number = wait_loop_number; 316 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 317 318 /* setDMCUParam_Cmd */ 319 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 320 321 /* notifyDMCUMsg */ 322 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 323 } 324 325 static void dce_get_psr_wait_loop( 326 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 327 { 328 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 329 return; 330 } 331 332 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 333 { 334 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 335 uint32_t dmcu_version_offset = 0xf1; 336 337 /* Enable write access to IRAM */ 338 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 339 IRAM_HOST_ACCESS_EN, 1, 340 IRAM_RD_ADDR_AUTO_INC, 1); 341 342 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 343 344 /* Write address to IRAM_RD_ADDR and read from DATA register */ 345 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 346 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 347 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 348 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 349 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 350 REG_READ(DMCU_IRAM_RD_DATA)); 351 352 /* Disable write access to IRAM to allow dynamic sleep state */ 353 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 354 IRAM_HOST_ACCESS_EN, 0, 355 IRAM_RD_ADDR_AUTO_INC, 0); 356 } 357 358 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu, 359 uint32_t fractional_pwm) 360 { 361 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 362 363 /* Wait until microcontroller is ready to process interrupt */ 364 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 365 366 /* Set PWM fractional enable/disable */ 367 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); 368 369 /* Set command to enable or disable fractional PWM microcontroller */ 370 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 371 MCP_BL_SET_PWM_FRAC); 372 373 /* Notify microcontroller of new command */ 374 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 375 376 /* Ensure command has been executed before continuing */ 377 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 378 } 379 380 static bool dcn10_dmcu_init(struct dmcu *dmcu) 381 { 382 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 383 const struct dc_config *config = &dmcu->ctx->dc->config; 384 bool status = false; 385 struct dc_context *ctx = dmcu->ctx; 386 unsigned int i; 387 // 5 4 3 2 1 0 388 // F E D C B A - bit 0 is A, bit 5 is F 389 unsigned int tx_interrupt_mask = 0; 390 391 PERF_TRACE(); 392 /* Definition of DC_DMCU_SCRATCH 393 * 0 : firmare not loaded 394 * 1 : PSP load DMCU FW but not initialized 395 * 2 : Firmware already initialized 396 */ 397 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 398 399 for (i = 0; i < ctx->dc->link_count; i++) { 400 if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) { 401 if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A && 402 ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) { 403 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter; 404 } 405 } 406 } 407 408 switch (dmcu->dmcu_state) { 409 case DMCU_UNLOADED: 410 status = false; 411 break; 412 case DMCU_LOADED_UNINITIALIZED: 413 /* Wait until microcontroller is ready to process interrupt */ 414 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 415 416 /* Set initialized ramping boundary value */ 417 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 418 419 /* Set backlight ramping stepsize */ 420 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize); 421 422 REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask); 423 424 /* Set command to initialize microcontroller */ 425 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 426 MCP_INIT_DMCU); 427 428 /* Notify microcontroller of new command */ 429 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 430 431 /* Ensure command has been executed before continuing */ 432 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 433 434 // Check state is initialized 435 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 436 437 // If microcontroller is not in running state, fail 438 if (dmcu->dmcu_state == DMCU_RUNNING) { 439 /* Retrieve and cache the DMCU firmware version. */ 440 dcn10_get_dmcu_version(dmcu); 441 442 /* Initialize DMCU to use fractional PWM or not */ 443 dcn10_dmcu_enable_fractional_pwm(dmcu, 444 (config->disable_fractional_pwm == false) ? 1 : 0); 445 status = true; 446 } else { 447 status = false; 448 } 449 450 break; 451 case DMCU_RUNNING: 452 status = true; 453 break; 454 default: 455 status = false; 456 break; 457 } 458 459 PERF_TRACE(); 460 return status; 461 } 462 463 static bool dcn21_dmcu_init(struct dmcu *dmcu) 464 { 465 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 466 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); 467 468 if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) { 469 return false; 470 } 471 472 return dcn10_dmcu_init(dmcu); 473 } 474 475 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 476 unsigned int start_offset, 477 const char *src, 478 unsigned int bytes) 479 { 480 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 481 unsigned int count = 0; 482 483 /* If microcontroller is not running, do nothing */ 484 if (dmcu->dmcu_state != DMCU_RUNNING) 485 return false; 486 487 /* Enable write access to IRAM */ 488 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 489 IRAM_HOST_ACCESS_EN, 1, 490 IRAM_WR_ADDR_AUTO_INC, 1); 491 492 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 493 494 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 495 496 for (count = 0; count < bytes; count++) 497 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 498 499 /* Disable write access to IRAM to allow dynamic sleep state */ 500 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 501 IRAM_HOST_ACCESS_EN, 0, 502 IRAM_WR_ADDR_AUTO_INC, 0); 503 504 /* Wait until microcontroller is ready to process interrupt */ 505 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 506 507 /* Set command to signal IRAM is loaded and to initialize IRAM */ 508 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 509 MCP_INIT_IRAM); 510 511 /* Notify microcontroller of new command */ 512 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 513 514 /* Ensure command has been executed before continuing */ 515 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 516 517 return true; 518 } 519 520 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state) 521 { 522 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 523 524 uint32_t psr_state_offset = 0xf0; 525 526 /* If microcontroller is not running, do nothing */ 527 if (dmcu->dmcu_state != DMCU_RUNNING) 528 return; 529 530 /* Enable write access to IRAM */ 531 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 532 533 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 534 535 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 536 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 537 538 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 539 *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA); 540 541 /* Disable write access to IRAM after finished using IRAM 542 * in order to allow dynamic sleep state 543 */ 544 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 545 } 546 547 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 548 { 549 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 550 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 551 unsigned int dmcu_wait_reg_ready_interval = 100; 552 553 unsigned int retryCount; 554 enum dc_psr_state state = PSR_STATE0; 555 556 /* If microcontroller is not running, do nothing */ 557 if (dmcu->dmcu_state != DMCU_RUNNING) 558 return; 559 560 /* waitDMCUReadyForCmd */ 561 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 562 dmcu_wait_reg_ready_interval, 563 dmcu_max_retry_on_wait_reg_ready); 564 565 /* setDMCUParam_Cmd */ 566 if (enable) 567 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 568 PSR_ENABLE); 569 else 570 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 571 PSR_EXIT); 572 573 /* notifyDMCUMsg */ 574 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 575 576 /* Below loops 1000 x 500us = 500 ms. 577 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 578 * least a few frames. Should never hit the max retry assert below. 579 */ 580 if (wait == true) { 581 for (retryCount = 0; retryCount <= 1000; retryCount++) { 582 dcn10_get_dmcu_psr_state(dmcu, &state); 583 if (enable) { 584 if (state != PSR_STATE0) 585 break; 586 } else { 587 if (state == PSR_STATE0) 588 break; 589 } 590 /* must *not* be fsleep - this can be called from high irq levels */ 591 udelay(500); 592 } 593 594 /* assert if max retry hit */ 595 if (retryCount >= 1000) 596 ASSERT(0); 597 } 598 } 599 600 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 601 struct dc_link *link, 602 struct psr_context *psr_context) 603 { 604 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 605 606 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 607 unsigned int dmcu_wait_reg_ready_interval = 100; 608 609 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 610 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 611 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 612 613 /* If microcontroller is not running, do nothing */ 614 if (dmcu->dmcu_state != DMCU_RUNNING) 615 return false; 616 617 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 618 psr_context->psrExitLinkTrainingRequired); 619 620 /* Enable static screen interrupts for PSR supported display */ 621 /* Disable the interrupt coming from other displays. */ 622 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 623 STATIC_SCREEN1_INT_TO_UC_EN, 0, 624 STATIC_SCREEN2_INT_TO_UC_EN, 0, 625 STATIC_SCREEN3_INT_TO_UC_EN, 0, 626 STATIC_SCREEN4_INT_TO_UC_EN, 0); 627 628 switch (psr_context->controllerId) { 629 /* Driver uses case 1 for unconfigured */ 630 case 1: 631 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 632 STATIC_SCREEN1_INT_TO_UC_EN, 1); 633 break; 634 case 2: 635 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 636 STATIC_SCREEN2_INT_TO_UC_EN, 1); 637 break; 638 case 3: 639 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 640 STATIC_SCREEN3_INT_TO_UC_EN, 1); 641 break; 642 case 4: 643 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 644 STATIC_SCREEN4_INT_TO_UC_EN, 1); 645 break; 646 case 5: 647 /* CZ/NL only has 4 CRTC!! 648 * really valid. 649 * There is no interrupt enable mask for these instances. 650 */ 651 break; 652 case 6: 653 /* CZ/NL only has 4 CRTC!! 654 * These are here because they are defined in HW regspec, 655 * but not really valid. There is no interrupt enable mask 656 * for these instances. 657 */ 658 break; 659 default: 660 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 661 STATIC_SCREEN1_INT_TO_UC_EN, 1); 662 break; 663 } 664 665 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 666 psr_context->sdpTransmitLineNumDeadline); 667 668 if (psr_context->allow_smu_optimizations) 669 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 670 671 /* waitDMCUReadyForCmd */ 672 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 673 dmcu_wait_reg_ready_interval, 674 dmcu_max_retry_on_wait_reg_ready); 675 676 /* setDMCUParam_PSRHostConfigData */ 677 masterCmdData1.u32All = 0; 678 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 679 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 680 masterCmdData1.bits.rfb_update_auto_en = 681 psr_context->rfb_update_auto_en; 682 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 683 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 684 masterCmdData1.bits.phy_type = psr_context->phyType; 685 masterCmdData1.bits.frame_cap_ind = 686 psr_context->psrFrameCaptureIndicationReq; 687 masterCmdData1.bits.aux_chan = psr_context->channel; 688 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 689 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 690 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 691 masterCmdData1.u32All); 692 693 masterCmdData2.u32All = 0; 694 masterCmdData2.bits.dig_fe = psr_context->engineId; 695 masterCmdData2.bits.dig_be = psr_context->transmitterId; 696 masterCmdData2.bits.skip_wait_for_pll_lock = 697 psr_context->skipPsrWaitForPllLock; 698 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 699 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 700 masterCmdData2.bits.num_of_controllers = 701 psr_context->numberOfControllers; 702 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 703 masterCmdData2.u32All); 704 705 masterCmdData3.u32All = 0; 706 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 707 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 708 masterCmdData3.u32All); 709 710 711 /* setDMCUParam_Cmd */ 712 REG_UPDATE(MASTER_COMM_CMD_REG, 713 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 714 715 /* notifyDMCUMsg */ 716 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 717 718 /* waitDMCUReadyForCmd */ 719 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 720 721 return true; 722 } 723 724 static void dcn10_psr_wait_loop( 725 struct dmcu *dmcu, 726 unsigned int wait_loop_number) 727 { 728 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 729 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 730 731 /* If microcontroller is not running, do nothing */ 732 if (dmcu->dmcu_state != DMCU_RUNNING) 733 return; 734 735 if (wait_loop_number != 0) { 736 /* waitDMCUReadyForCmd */ 737 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 738 739 masterCmdData1.u32 = 0; 740 masterCmdData1.bits.wait_loop = wait_loop_number; 741 dmcu->cached_wait_loop_number = wait_loop_number; 742 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 743 744 /* setDMCUParam_Cmd */ 745 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 746 747 /* notifyDMCUMsg */ 748 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 749 } 750 } 751 752 static void dcn10_get_psr_wait_loop( 753 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 754 { 755 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 756 return; 757 } 758 759 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 760 { 761 /* microcontroller is not running */ 762 if (dmcu->dmcu_state != DMCU_RUNNING) 763 return false; 764 return true; 765 } 766 767 768 769 static bool dcn20_lock_phy(struct dmcu *dmcu) 770 { 771 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 772 773 /* If microcontroller is not running, do nothing */ 774 if (dmcu->dmcu_state != DMCU_RUNNING) 775 return false; 776 777 /* waitDMCUReadyForCmd */ 778 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 779 780 /* setDMCUParam_Cmd */ 781 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); 782 783 /* notifyDMCUMsg */ 784 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 785 786 /* waitDMCUReadyForCmd */ 787 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 788 789 return true; 790 } 791 792 static bool dcn20_unlock_phy(struct dmcu *dmcu) 793 { 794 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 795 796 /* If microcontroller is not running, do nothing */ 797 if (dmcu->dmcu_state != DMCU_RUNNING) 798 return false; 799 800 /* waitDMCUReadyForCmd */ 801 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 802 803 /* setDMCUParam_Cmd */ 804 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); 805 806 /* notifyDMCUMsg */ 807 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 808 809 /* waitDMCUReadyForCmd */ 810 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 811 812 return true; 813 } 814 815 static bool dcn10_send_edid_cea(struct dmcu *dmcu, 816 int offset, 817 int total_length, 818 uint8_t *data, 819 int length) 820 { 821 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 822 uint32_t header, data1, data2; 823 824 /* If microcontroller is not running, do nothing */ 825 if (dmcu->dmcu_state != DMCU_RUNNING) 826 return false; 827 828 if (length > 8 || length <= 0) 829 return false; 830 831 header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF); 832 data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | 833 (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); 834 data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | 835 (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); 836 837 /* waitDMCUReadyForCmd */ 838 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 839 840 /* setDMCUParam_Cmd */ 841 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA); 842 843 REG_WRITE(MASTER_COMM_DATA_REG1, header); 844 REG_WRITE(MASTER_COMM_DATA_REG2, data1); 845 REG_WRITE(MASTER_COMM_DATA_REG3, data2); 846 847 /* notifyDMCUMsg */ 848 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 849 850 /* waitDMCUReadyForCmd */ 851 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 852 853 return true; 854 } 855 856 static bool dcn10_get_scp_results(struct dmcu *dmcu, 857 uint32_t *cmd, 858 uint32_t *data1, 859 uint32_t *data2, 860 uint32_t *data3) 861 { 862 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 863 864 /* If microcontroller is not running, do nothing */ 865 if (dmcu->dmcu_state != DMCU_RUNNING) 866 return false; 867 868 *cmd = REG_READ(SLAVE_COMM_CMD_REG); 869 *data1 = REG_READ(SLAVE_COMM_DATA_REG1); 870 *data2 = REG_READ(SLAVE_COMM_DATA_REG2); 871 *data3 = REG_READ(SLAVE_COMM_DATA_REG3); 872 873 /* clear SCP interrupt */ 874 REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0); 875 876 return true; 877 } 878 879 static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, 880 int *version, 881 int *min_frame_rate, 882 int *max_frame_rate) 883 { 884 uint32_t data[4]; 885 int cmd, ack, len; 886 887 if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) 888 return false; 889 890 cmd = data[0] & 0x3FF; 891 len = (data[0] >> 10) & 0x3F; 892 ack = data[1]; 893 894 if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12) 895 return false; 896 897 if ((data[2] & 0xFF)) { 898 *version = (data[2] >> 8) & 0xFF; 899 *min_frame_rate = (data[3] >> 16) & 0xFFFF; 900 *max_frame_rate = data[3] & 0xFFFF; 901 return true; 902 } 903 904 return false; 905 } 906 907 static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) 908 { 909 uint32_t data[4]; 910 int cmd, ack; 911 912 if (!dcn10_get_scp_results(dmcu, 913 &data[0], &data[1], &data[2], &data[3])) 914 return false; 915 916 cmd = data[0] & 0x3FF; 917 ack = data[1]; 918 919 if (cmd != MCP_SEND_EDID_CEA) 920 return false; 921 922 if (ack == EDID_CEA_CMD_ACK) 923 return true; 924 925 *offset = data[2]; /* nack */ 926 return false; 927 } 928 929 930 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 931 static void dcn10_forward_crc_window(struct dmcu *dmcu, 932 struct rect *rect, 933 struct otg_phy_mux *mux_mapping) 934 { 935 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 936 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 937 unsigned int dmcu_wait_reg_ready_interval = 100; 938 unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0; 939 int x_start, y_start, x_end, y_end; 940 941 /* If microcontroller is not running, do nothing */ 942 if (dmcu->dmcu_state != DMCU_RUNNING) 943 return; 944 945 if (!rect) 946 return; 947 948 /* waitDMCUReadyForCmd */ 949 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 950 dmcu_wait_reg_ready_interval, 951 dmcu_max_retry_on_wait_reg_ready); 952 953 x_start = rect->x; 954 y_start = rect->y; 955 x_end = x_start + rect->width; 956 y_end = y_start + rect->height; 957 958 /* build up nitification data */ 959 crc_start = (((unsigned int) x_start) << 16) | y_start; 960 crc_end = (((unsigned int) x_end) << 16) | y_end; 961 otg_phy_mux = 962 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 963 964 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 965 crc_start); 966 967 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 968 crc_end); 969 970 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 971 otg_phy_mux); 972 973 /* setDMCUParam_Cmd */ 974 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 975 CRC_WIN_NOTIFY); 976 977 /* notifyDMCUMsg */ 978 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 979 } 980 981 static void dcn10_stop_crc_win_update(struct dmcu *dmcu, 982 struct otg_phy_mux *mux_mapping) 983 { 984 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 985 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 986 unsigned int dmcu_wait_reg_ready_interval = 100; 987 unsigned int otg_phy_mux = 0; 988 989 /* If microcontroller is not running, do nothing */ 990 if (dmcu->dmcu_state != DMCU_RUNNING) 991 return; 992 993 /* waitDMCUReadyForCmd */ 994 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 995 dmcu_wait_reg_ready_interval, 996 dmcu_max_retry_on_wait_reg_ready); 997 998 /* build up nitification data */ 999 otg_phy_mux = 1000 (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num; 1001 1002 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 1003 otg_phy_mux); 1004 1005 /* setDMCUParam_Cmd */ 1006 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 1007 CRC_STOP_UPDATE); 1008 1009 /* notifyDMCUMsg */ 1010 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 1011 } 1012 #endif 1013 1014 static const struct dmcu_funcs dce_funcs = { 1015 .dmcu_init = dce_dmcu_init, 1016 .load_iram = dce_dmcu_load_iram, 1017 .set_psr_enable = dce_dmcu_set_psr_enable, 1018 .setup_psr = dce_dmcu_setup_psr, 1019 .get_psr_state = dce_get_dmcu_psr_state, 1020 .set_psr_wait_loop = dce_psr_wait_loop, 1021 .get_psr_wait_loop = dce_get_psr_wait_loop, 1022 .is_dmcu_initialized = dce_is_dmcu_initialized 1023 }; 1024 1025 static const struct dmcu_funcs dcn10_funcs = { 1026 .dmcu_init = dcn10_dmcu_init, 1027 .load_iram = dcn10_dmcu_load_iram, 1028 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1029 .setup_psr = dcn10_dmcu_setup_psr, 1030 .get_psr_state = dcn10_get_dmcu_psr_state, 1031 .set_psr_wait_loop = dcn10_psr_wait_loop, 1032 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1033 .send_edid_cea = dcn10_send_edid_cea, 1034 .recv_amd_vsdb = dcn10_recv_amd_vsdb, 1035 .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, 1036 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1037 .forward_crc_window = dcn10_forward_crc_window, 1038 .stop_crc_win_update = dcn10_stop_crc_win_update, 1039 #endif 1040 .is_dmcu_initialized = dcn10_is_dmcu_initialized 1041 }; 1042 1043 static const struct dmcu_funcs dcn20_funcs = { 1044 .dmcu_init = dcn10_dmcu_init, 1045 .load_iram = dcn10_dmcu_load_iram, 1046 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1047 .setup_psr = dcn10_dmcu_setup_psr, 1048 .get_psr_state = dcn10_get_dmcu_psr_state, 1049 .set_psr_wait_loop = dcn10_psr_wait_loop, 1050 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1051 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1052 .lock_phy = dcn20_lock_phy, 1053 .unlock_phy = dcn20_unlock_phy 1054 }; 1055 1056 static const struct dmcu_funcs dcn21_funcs = { 1057 .dmcu_init = dcn21_dmcu_init, 1058 .load_iram = dcn10_dmcu_load_iram, 1059 .set_psr_enable = dcn10_dmcu_set_psr_enable, 1060 .setup_psr = dcn10_dmcu_setup_psr, 1061 .get_psr_state = dcn10_get_dmcu_psr_state, 1062 .set_psr_wait_loop = dcn10_psr_wait_loop, 1063 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 1064 .is_dmcu_initialized = dcn10_is_dmcu_initialized, 1065 .lock_phy = dcn20_lock_phy, 1066 .unlock_phy = dcn20_unlock_phy 1067 }; 1068 1069 static void dce_dmcu_construct( 1070 struct dce_dmcu *dmcu_dce, 1071 struct dc_context *ctx, 1072 const struct dce_dmcu_registers *regs, 1073 const struct dce_dmcu_shift *dmcu_shift, 1074 const struct dce_dmcu_mask *dmcu_mask) 1075 { 1076 struct dmcu *base = &dmcu_dce->base; 1077 1078 base->ctx = ctx; 1079 base->funcs = &dce_funcs; 1080 base->cached_wait_loop_number = 0; 1081 1082 dmcu_dce->regs = regs; 1083 dmcu_dce->dmcu_shift = dmcu_shift; 1084 dmcu_dce->dmcu_mask = dmcu_mask; 1085 } 1086 1087 static void dcn21_dmcu_construct( 1088 struct dce_dmcu *dmcu_dce, 1089 struct dc_context *ctx, 1090 const struct dce_dmcu_registers *regs, 1091 const struct dce_dmcu_shift *dmcu_shift, 1092 const struct dce_dmcu_mask *dmcu_mask) 1093 { 1094 uint32_t psp_version = 0; 1095 1096 dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1097 1098 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); 1099 dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029); 1100 dmcu_dce->base.psp_version = psp_version; 1101 } 1102 1103 struct dmcu *dce_dmcu_create( 1104 struct dc_context *ctx, 1105 const struct dce_dmcu_registers *regs, 1106 const struct dce_dmcu_shift *dmcu_shift, 1107 const struct dce_dmcu_mask *dmcu_mask) 1108 { 1109 struct dce_dmcu *dmcu_dce = kzalloc_obj(*dmcu_dce); 1110 1111 if (dmcu_dce == NULL) { 1112 BREAK_TO_DEBUGGER(); 1113 return NULL; 1114 } 1115 1116 dce_dmcu_construct( 1117 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1118 1119 dmcu_dce->base.funcs = &dce_funcs; 1120 1121 return &dmcu_dce->base; 1122 } 1123 1124 struct dmcu *dcn10_dmcu_create( 1125 struct dc_context *ctx, 1126 const struct dce_dmcu_registers *regs, 1127 const struct dce_dmcu_shift *dmcu_shift, 1128 const struct dce_dmcu_mask *dmcu_mask) 1129 { 1130 struct dce_dmcu *dmcu_dce = kzalloc_obj(*dmcu_dce); 1131 1132 if (dmcu_dce == NULL) { 1133 BREAK_TO_DEBUGGER(); 1134 return NULL; 1135 } 1136 1137 dce_dmcu_construct( 1138 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1139 1140 dmcu_dce->base.funcs = &dcn10_funcs; 1141 1142 return &dmcu_dce->base; 1143 } 1144 1145 struct dmcu *dcn20_dmcu_create( 1146 struct dc_context *ctx, 1147 const struct dce_dmcu_registers *regs, 1148 const struct dce_dmcu_shift *dmcu_shift, 1149 const struct dce_dmcu_mask *dmcu_mask) 1150 { 1151 struct dce_dmcu *dmcu_dce = kzalloc_obj(*dmcu_dce); 1152 1153 if (dmcu_dce == NULL) { 1154 BREAK_TO_DEBUGGER(); 1155 return NULL; 1156 } 1157 1158 dce_dmcu_construct( 1159 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1160 1161 dmcu_dce->base.funcs = &dcn20_funcs; 1162 1163 return &dmcu_dce->base; 1164 } 1165 1166 struct dmcu *dcn21_dmcu_create( 1167 struct dc_context *ctx, 1168 const struct dce_dmcu_registers *regs, 1169 const struct dce_dmcu_shift *dmcu_shift, 1170 const struct dce_dmcu_mask *dmcu_mask) 1171 { 1172 struct dce_dmcu *dmcu_dce = kzalloc_obj(*dmcu_dce); 1173 1174 if (dmcu_dce == NULL) { 1175 BREAK_TO_DEBUGGER(); 1176 return NULL; 1177 } 1178 1179 dcn21_dmcu_construct( 1180 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 1181 1182 dmcu_dce->base.funcs = &dcn21_funcs; 1183 1184 return &dmcu_dce->base; 1185 } 1186 1187 void dce_dmcu_destroy(struct dmcu **dmcu) 1188 { 1189 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 1190 1191 kfree(dmcu_dce); 1192 *dmcu = NULL; 1193 } 1194