1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "link_encoder.h" 28 #include "dce_dmcu.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #define TO_DCE_DMCU(dmcu)\ 35 container_of(dmcu, struct dce_dmcu, base) 36 37 #define REG(reg) \ 38 (dmcu_dce->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name 43 44 #define CTX \ 45 dmcu_dce->base.ctx 46 47 /* PSR related commands */ 48 #define PSR_ENABLE 0x20 49 #define PSR_EXIT 0x21 50 #define PSR_SET 0x23 51 #define PSR_SET_WAITLOOP 0x31 52 #define MCP_INIT_DMCU 0x88 53 #define MCP_INIT_IRAM 0x89 54 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 55 56 static bool dce_dmcu_init(struct dmcu *dmcu) 57 { 58 // Do nothing 59 return true; 60 } 61 62 bool dce_dmcu_load_iram(struct dmcu *dmcu, 63 unsigned int start_offset, 64 const char *src, 65 unsigned int bytes) 66 { 67 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 68 unsigned int count = 0; 69 70 /* Enable write access to IRAM */ 71 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 72 IRAM_HOST_ACCESS_EN, 1, 73 IRAM_WR_ADDR_AUTO_INC, 1); 74 75 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 76 77 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 78 79 for (count = 0; count < bytes; count++) 80 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 81 82 /* Disable write access to IRAM to allow dynamic sleep state */ 83 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 84 IRAM_HOST_ACCESS_EN, 0, 85 IRAM_WR_ADDR_AUTO_INC, 0); 86 87 return true; 88 } 89 90 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 91 { 92 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 93 94 uint32_t psr_state_offset = 0xf0; 95 96 /* Enable write access to IRAM */ 97 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 98 99 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 100 101 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 102 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 103 104 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 105 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 106 107 /* Disable write access to IRAM after finished using IRAM 108 * in order to allow dynamic sleep state 109 */ 110 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 111 } 112 113 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 114 { 115 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 116 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 117 unsigned int dmcu_wait_reg_ready_interval = 100; 118 119 unsigned int retryCount; 120 uint32_t psr_state = 0; 121 122 /* waitDMCUReadyForCmd */ 123 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 124 dmcu_wait_reg_ready_interval, 125 dmcu_max_retry_on_wait_reg_ready); 126 127 /* setDMCUParam_Cmd */ 128 if (enable) 129 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 130 PSR_ENABLE); 131 else 132 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 133 PSR_EXIT); 134 135 /* notifyDMCUMsg */ 136 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 137 if (wait == true) { 138 for (retryCount = 0; retryCount <= 100; retryCount++) { 139 dce_get_dmcu_psr_state(dmcu, &psr_state); 140 if (enable) { 141 if (psr_state != 0) 142 break; 143 } else { 144 if (psr_state == 0) 145 break; 146 } 147 udelay(10); 148 } 149 } 150 } 151 152 static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 153 struct dc_link *link, 154 struct psr_context *psr_context) 155 { 156 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 157 158 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 159 unsigned int dmcu_wait_reg_ready_interval = 100; 160 161 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 162 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 163 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 164 165 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 166 psr_context->psrExitLinkTrainingRequired); 167 168 /* Enable static screen interrupts for PSR supported display */ 169 /* Disable the interrupt coming from other displays. */ 170 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 171 STATIC_SCREEN1_INT_TO_UC_EN, 0, 172 STATIC_SCREEN2_INT_TO_UC_EN, 0, 173 STATIC_SCREEN3_INT_TO_UC_EN, 0, 174 STATIC_SCREEN4_INT_TO_UC_EN, 0); 175 176 switch (psr_context->controllerId) { 177 /* Driver uses case 1 for unconfigured */ 178 case 1: 179 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 180 STATIC_SCREEN1_INT_TO_UC_EN, 1); 181 break; 182 case 2: 183 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 184 STATIC_SCREEN2_INT_TO_UC_EN, 1); 185 break; 186 case 3: 187 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 188 STATIC_SCREEN3_INT_TO_UC_EN, 1); 189 break; 190 case 4: 191 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 192 STATIC_SCREEN4_INT_TO_UC_EN, 1); 193 break; 194 case 5: 195 /* CZ/NL only has 4 CRTC!! 196 * really valid. 197 * There is no interrupt enable mask for these instances. 198 */ 199 break; 200 case 6: 201 /* CZ/NL only has 4 CRTC!! 202 * These are here because they are defined in HW regspec, 203 * but not really valid. There is no interrupt enable mask 204 * for these instances. 205 */ 206 break; 207 default: 208 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 209 STATIC_SCREEN1_INT_TO_UC_EN, 1); 210 break; 211 } 212 213 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 214 psr_context->sdpTransmitLineNumDeadline); 215 216 /* waitDMCUReadyForCmd */ 217 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 218 dmcu_wait_reg_ready_interval, 219 dmcu_max_retry_on_wait_reg_ready); 220 221 /* setDMCUParam_PSRHostConfigData */ 222 masterCmdData1.u32All = 0; 223 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 224 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 225 masterCmdData1.bits.rfb_update_auto_en = 226 psr_context->rfb_update_auto_en; 227 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 228 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 229 masterCmdData1.bits.phy_type = psr_context->phyType; 230 masterCmdData1.bits.frame_cap_ind = 231 psr_context->psrFrameCaptureIndicationReq; 232 masterCmdData1.bits.aux_chan = psr_context->channel; 233 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 234 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 235 masterCmdData1.u32All); 236 237 masterCmdData2.u32All = 0; 238 masterCmdData2.bits.dig_fe = psr_context->engineId; 239 masterCmdData2.bits.dig_be = psr_context->transmitterId; 240 masterCmdData2.bits.skip_wait_for_pll_lock = 241 psr_context->skipPsrWaitForPllLock; 242 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 243 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 244 masterCmdData2.bits.num_of_controllers = 245 psr_context->numberOfControllers; 246 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 247 masterCmdData2.u32All); 248 249 masterCmdData3.u32All = 0; 250 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 251 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 252 masterCmdData3.u32All); 253 254 /* setDMCUParam_Cmd */ 255 REG_UPDATE(MASTER_COMM_CMD_REG, 256 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 257 258 /* notifyDMCUMsg */ 259 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 260 261 return true; 262 } 263 264 static bool dce_is_dmcu_initialized(struct dmcu *dmcu) 265 { 266 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 267 unsigned int dmcu_uc_reset; 268 269 /* microcontroller is not running */ 270 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); 271 272 /* DMCU is not running */ 273 if (dmcu_uc_reset) 274 return false; 275 276 return true; 277 } 278 279 static void dce_psr_wait_loop( 280 struct dmcu *dmcu, 281 unsigned int wait_loop_number) 282 { 283 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 284 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 285 286 if (dmcu->cached_wait_loop_number == wait_loop_number) 287 return; 288 289 /* DMCU is not running */ 290 if (!dce_is_dmcu_initialized(dmcu)) 291 return; 292 293 /* waitDMCUReadyForCmd */ 294 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 295 296 masterCmdData1.u32 = 0; 297 masterCmdData1.bits.wait_loop = wait_loop_number; 298 dmcu->cached_wait_loop_number = wait_loop_number; 299 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 300 301 /* setDMCUParam_Cmd */ 302 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 303 304 /* notifyDMCUMsg */ 305 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 306 } 307 308 static void dce_get_psr_wait_loop( 309 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 310 { 311 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 312 return; 313 } 314 315 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 316 static void dcn10_get_dmcu_version(struct dmcu *dmcu) 317 { 318 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 319 uint32_t dmcu_version_offset = 0xf1; 320 321 /* Enable write access to IRAM */ 322 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 323 IRAM_HOST_ACCESS_EN, 1, 324 IRAM_RD_ADDR_AUTO_INC, 1); 325 326 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 327 328 /* Write address to IRAM_RD_ADDR and read from DATA register */ 329 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); 330 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); 331 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); 332 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); 333 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | 334 REG_READ(DMCU_IRAM_RD_DATA)); 335 336 /* Disable write access to IRAM to allow dynamic sleep state */ 337 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 338 IRAM_HOST_ACCESS_EN, 0, 339 IRAM_RD_ADDR_AUTO_INC, 0); 340 } 341 342 static bool dcn10_dmcu_init(struct dmcu *dmcu) 343 { 344 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 345 bool status = false; 346 347 /* Definition of DC_DMCU_SCRATCH 348 * 0 : firmare not loaded 349 * 1 : PSP load DMCU FW but not initialized 350 * 2 : Firmware already initialized 351 */ 352 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 353 354 switch (dmcu->dmcu_state) { 355 case DMCU_UNLOADED: 356 status = false; 357 break; 358 case DMCU_LOADED_UNINITIALIZED: 359 /* Wait until microcontroller is ready to process interrupt */ 360 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 361 362 /* Set initialized ramping boundary value */ 363 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); 364 365 /* Set command to initialize microcontroller */ 366 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 367 MCP_INIT_DMCU); 368 369 /* Notify microcontroller of new command */ 370 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 371 372 /* Ensure command has been executed before continuing */ 373 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 374 375 // Check state is initialized 376 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); 377 378 // If microcontroller is not in running state, fail 379 if (dmcu->dmcu_state == DMCU_RUNNING) { 380 /* Retrieve and cache the DMCU firmware version. */ 381 dcn10_get_dmcu_version(dmcu); 382 status = true; 383 } else 384 status = false; 385 386 break; 387 case DMCU_RUNNING: 388 status = true; 389 break; 390 default: 391 status = false; 392 break; 393 } 394 395 return status; 396 } 397 398 399 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, 400 unsigned int start_offset, 401 const char *src, 402 unsigned int bytes) 403 { 404 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 405 unsigned int count = 0; 406 407 /* If microcontroller is not running, do nothing */ 408 if (dmcu->dmcu_state != DMCU_RUNNING) 409 return false; 410 411 /* Enable write access to IRAM */ 412 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 413 IRAM_HOST_ACCESS_EN, 1, 414 IRAM_WR_ADDR_AUTO_INC, 1); 415 416 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 417 418 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); 419 420 for (count = 0; count < bytes; count++) 421 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); 422 423 /* Disable write access to IRAM to allow dynamic sleep state */ 424 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, 425 IRAM_HOST_ACCESS_EN, 0, 426 IRAM_WR_ADDR_AUTO_INC, 0); 427 428 /* Wait until microcontroller is ready to process interrupt */ 429 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 430 431 /* Set command to signal IRAM is loaded and to initialize IRAM */ 432 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 433 MCP_INIT_IRAM); 434 435 /* Notify microcontroller of new command */ 436 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 437 438 /* Ensure command has been executed before continuing */ 439 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); 440 441 return true; 442 } 443 444 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) 445 { 446 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 447 448 uint32_t psr_state_offset = 0xf0; 449 450 /* If microcontroller is not running, do nothing */ 451 if (dmcu->dmcu_state != DMCU_RUNNING) 452 return; 453 454 /* Enable write access to IRAM */ 455 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); 456 457 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); 458 459 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ 460 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); 461 462 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ 463 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); 464 465 /* Disable write access to IRAM after finished using IRAM 466 * in order to allow dynamic sleep state 467 */ 468 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); 469 } 470 471 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) 472 { 473 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 474 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 475 unsigned int dmcu_wait_reg_ready_interval = 100; 476 477 unsigned int retryCount; 478 uint32_t psr_state = 0; 479 480 /* If microcontroller is not running, do nothing */ 481 if (dmcu->dmcu_state != DMCU_RUNNING) 482 return; 483 484 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 485 if (psr_state == 0 && !enable) 486 return; 487 /* waitDMCUReadyForCmd */ 488 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 489 dmcu_wait_reg_ready_interval, 490 dmcu_max_retry_on_wait_reg_ready); 491 492 /* setDMCUParam_Cmd */ 493 if (enable) 494 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 495 PSR_ENABLE); 496 else 497 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 498 PSR_EXIT); 499 500 /* notifyDMCUMsg */ 501 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 502 503 /* Below loops 1000 x 500us = 500 ms. 504 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 505 * least a few frames. Should never hit the max retry assert below. 506 */ 507 if (wait == true) { 508 for (retryCount = 0; retryCount <= 1000; retryCount++) { 509 dcn10_get_dmcu_psr_state(dmcu, &psr_state); 510 if (enable) { 511 if (psr_state != 0) 512 break; 513 } else { 514 if (psr_state == 0) 515 break; 516 } 517 udelay(500); 518 } 519 520 /* assert if max retry hit */ 521 if (retryCount >= 1000) 522 ASSERT(0); 523 } 524 } 525 526 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 527 struct dc_link *link, 528 struct psr_context *psr_context) 529 { 530 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 531 532 unsigned int dmcu_max_retry_on_wait_reg_ready = 801; 533 unsigned int dmcu_wait_reg_ready_interval = 100; 534 535 union dce_dmcu_psr_config_data_reg1 masterCmdData1; 536 union dce_dmcu_psr_config_data_reg2 masterCmdData2; 537 union dce_dmcu_psr_config_data_reg3 masterCmdData3; 538 539 /* If microcontroller is not running, do nothing */ 540 if (dmcu->dmcu_state != DMCU_RUNNING) 541 return false; 542 543 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 544 psr_context->psrExitLinkTrainingRequired); 545 546 /* Enable static screen interrupts for PSR supported display */ 547 /* Disable the interrupt coming from other displays. */ 548 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, 549 STATIC_SCREEN1_INT_TO_UC_EN, 0, 550 STATIC_SCREEN2_INT_TO_UC_EN, 0, 551 STATIC_SCREEN3_INT_TO_UC_EN, 0, 552 STATIC_SCREEN4_INT_TO_UC_EN, 0); 553 554 switch (psr_context->controllerId) { 555 /* Driver uses case 1 for unconfigured */ 556 case 1: 557 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 558 STATIC_SCREEN1_INT_TO_UC_EN, 1); 559 break; 560 case 2: 561 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 562 STATIC_SCREEN2_INT_TO_UC_EN, 1); 563 break; 564 case 3: 565 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 566 STATIC_SCREEN3_INT_TO_UC_EN, 1); 567 break; 568 case 4: 569 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 570 STATIC_SCREEN4_INT_TO_UC_EN, 1); 571 break; 572 case 5: 573 /* CZ/NL only has 4 CRTC!! 574 * really valid. 575 * There is no interrupt enable mask for these instances. 576 */ 577 break; 578 case 6: 579 /* CZ/NL only has 4 CRTC!! 580 * These are here because they are defined in HW regspec, 581 * but not really valid. There is no interrupt enable mask 582 * for these instances. 583 */ 584 break; 585 default: 586 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, 587 STATIC_SCREEN1_INT_TO_UC_EN, 1); 588 break; 589 } 590 591 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 592 psr_context->sdpTransmitLineNumDeadline); 593 594 if (psr_context->allow_smu_optimizations) 595 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); 596 597 /* waitDMCUReadyForCmd */ 598 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 599 dmcu_wait_reg_ready_interval, 600 dmcu_max_retry_on_wait_reg_ready); 601 602 /* setDMCUParam_PSRHostConfigData */ 603 masterCmdData1.u32All = 0; 604 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; 605 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; 606 masterCmdData1.bits.rfb_update_auto_en = 607 psr_context->rfb_update_auto_en; 608 masterCmdData1.bits.dp_port_num = psr_context->transmitterId; 609 masterCmdData1.bits.dcp_sel = psr_context->controllerId; 610 masterCmdData1.bits.phy_type = psr_context->phyType; 611 masterCmdData1.bits.frame_cap_ind = 612 psr_context->psrFrameCaptureIndicationReq; 613 masterCmdData1.bits.aux_chan = psr_context->channel; 614 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; 615 masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations; 616 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), 617 masterCmdData1.u32All); 618 619 masterCmdData2.u32All = 0; 620 masterCmdData2.bits.dig_fe = psr_context->engineId; 621 masterCmdData2.bits.dig_be = psr_context->transmitterId; 622 masterCmdData2.bits.skip_wait_for_pll_lock = 623 psr_context->skipPsrWaitForPllLock; 624 masterCmdData2.bits.frame_delay = psr_context->frame_delay; 625 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; 626 masterCmdData2.bits.num_of_controllers = 627 psr_context->numberOfControllers; 628 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), 629 masterCmdData2.u32All); 630 631 masterCmdData3.u32All = 0; 632 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; 633 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), 634 masterCmdData3.u32All); 635 636 637 /* setDMCUParam_Cmd */ 638 REG_UPDATE(MASTER_COMM_CMD_REG, 639 MASTER_COMM_CMD_REG_BYTE0, PSR_SET); 640 641 /* notifyDMCUMsg */ 642 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 643 644 /* waitDMCUReadyForCmd */ 645 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 646 647 return true; 648 } 649 650 static void dcn10_psr_wait_loop( 651 struct dmcu *dmcu, 652 unsigned int wait_loop_number) 653 { 654 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); 655 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; 656 657 /* If microcontroller is not running, do nothing */ 658 if (dmcu->dmcu_state != DMCU_RUNNING) 659 return; 660 661 if (wait_loop_number != 0) { 662 /* waitDMCUReadyForCmd */ 663 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); 664 665 masterCmdData1.u32 = 0; 666 masterCmdData1.bits.wait_loop = wait_loop_number; 667 dmcu->cached_wait_loop_number = wait_loop_number; 668 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); 669 670 /* setDMCUParam_Cmd */ 671 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); 672 673 /* notifyDMCUMsg */ 674 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 675 } 676 } 677 678 static void dcn10_get_psr_wait_loop( 679 struct dmcu *dmcu, unsigned int *psr_wait_loop_number) 680 { 681 *psr_wait_loop_number = dmcu->cached_wait_loop_number; 682 return; 683 } 684 685 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 686 { 687 /* microcontroller is not running */ 688 if (dmcu->dmcu_state != DMCU_RUNNING) 689 return false; 690 return true; 691 } 692 693 #endif 694 695 static const struct dmcu_funcs dce_funcs = { 696 .dmcu_init = dce_dmcu_init, 697 .load_iram = dce_dmcu_load_iram, 698 .set_psr_enable = dce_dmcu_set_psr_enable, 699 .setup_psr = dce_dmcu_setup_psr, 700 .get_psr_state = dce_get_dmcu_psr_state, 701 .set_psr_wait_loop = dce_psr_wait_loop, 702 .get_psr_wait_loop = dce_get_psr_wait_loop, 703 .is_dmcu_initialized = dce_is_dmcu_initialized 704 }; 705 706 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 707 static const struct dmcu_funcs dcn10_funcs = { 708 .dmcu_init = dcn10_dmcu_init, 709 .load_iram = dcn10_dmcu_load_iram, 710 .set_psr_enable = dcn10_dmcu_set_psr_enable, 711 .setup_psr = dcn10_dmcu_setup_psr, 712 .get_psr_state = dcn10_get_dmcu_psr_state, 713 .set_psr_wait_loop = dcn10_psr_wait_loop, 714 .get_psr_wait_loop = dcn10_get_psr_wait_loop, 715 .is_dmcu_initialized = dcn10_is_dmcu_initialized 716 }; 717 #endif 718 719 static void dce_dmcu_construct( 720 struct dce_dmcu *dmcu_dce, 721 struct dc_context *ctx, 722 const struct dce_dmcu_registers *regs, 723 const struct dce_dmcu_shift *dmcu_shift, 724 const struct dce_dmcu_mask *dmcu_mask) 725 { 726 struct dmcu *base = &dmcu_dce->base; 727 728 base->ctx = ctx; 729 base->funcs = &dce_funcs; 730 base->cached_wait_loop_number = 0; 731 732 dmcu_dce->regs = regs; 733 dmcu_dce->dmcu_shift = dmcu_shift; 734 dmcu_dce->dmcu_mask = dmcu_mask; 735 } 736 737 struct dmcu *dce_dmcu_create( 738 struct dc_context *ctx, 739 const struct dce_dmcu_registers *regs, 740 const struct dce_dmcu_shift *dmcu_shift, 741 const struct dce_dmcu_mask *dmcu_mask) 742 { 743 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 744 745 if (dmcu_dce == NULL) { 746 BREAK_TO_DEBUGGER(); 747 return NULL; 748 } 749 750 dce_dmcu_construct( 751 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 752 753 dmcu_dce->base.funcs = &dce_funcs; 754 755 return &dmcu_dce->base; 756 } 757 758 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 759 struct dmcu *dcn10_dmcu_create( 760 struct dc_context *ctx, 761 const struct dce_dmcu_registers *regs, 762 const struct dce_dmcu_shift *dmcu_shift, 763 const struct dce_dmcu_mask *dmcu_mask) 764 { 765 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); 766 767 if (dmcu_dce == NULL) { 768 BREAK_TO_DEBUGGER(); 769 return NULL; 770 } 771 772 dce_dmcu_construct( 773 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); 774 775 dmcu_dce->base.funcs = &dcn10_funcs; 776 777 return &dmcu_dce->base; 778 } 779 #endif 780 781 void dce_dmcu_destroy(struct dmcu **dmcu) 782 { 783 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); 784 785 kfree(dmcu_dce); 786 *dmcu = NULL; 787 } 788