1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 37 #define DC_LOGGER_INIT() 38 39 #define REG(reg)\ 40 (aud->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 aud->shifts->field_name, aud->masks->field_name 45 46 #define IX_REG(reg)\ 47 ix ## reg 48 49 #define AZ_REG_READ(reg_name) \ 50 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 51 52 #define AZ_REG_WRITE(reg_name, value) \ 53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 54 55 static void write_indirect_azalia_reg(struct audio *audio, 56 uint32_t reg_index, 57 uint32_t reg_data) 58 { 59 struct dce_audio *aud = DCE_AUD(audio); 60 61 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 63 AZALIA_ENDPOINT_REG_INDEX, reg_index); 64 65 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 67 AZALIA_ENDPOINT_REG_DATA, reg_data); 68 } 69 70 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 71 { 72 struct dce_audio *aud = DCE_AUD(audio); 73 74 uint32_t value = 0; 75 76 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 77 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 78 AZALIA_ENDPOINT_REG_INDEX, reg_index); 79 80 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 82 83 return value; 84 } 85 86 static bool is_audio_format_supported( 87 const struct audio_info *audio_info, 88 enum audio_format_code audio_format_code, 89 uint32_t *format_index) 90 { 91 uint32_t index; 92 uint32_t max_channe_index = 0; 93 bool found = false; 94 95 if (audio_info == NULL) 96 return found; 97 98 /* pass through whole array */ 99 for (index = 0; index < audio_info->mode_count; index++) { 100 if (audio_info->modes[index].format_code == audio_format_code) { 101 if (found) { 102 /* format has multiply entries, choose one with 103 * highst number of channels */ 104 if (audio_info->modes[index].channel_count > 105 audio_info->modes[max_channe_index].channel_count) { 106 max_channe_index = index; 107 } 108 } else { 109 /* format found, save it's index */ 110 found = true; 111 max_channe_index = index; 112 } 113 } 114 } 115 116 /* return index */ 117 if (found && format_index != NULL) 118 *format_index = max_channe_index; 119 120 return found; 121 } 122 123 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 124 static void check_audio_bandwidth_hdmi( 125 const struct audio_crtc_info *crtc_info, 126 uint32_t channel_count, 127 union audio_sample_rates *sample_rates) 128 { 129 uint32_t samples; 130 uint32_t h_blank; 131 bool limit_freq_to_48_khz = false; 132 bool limit_freq_to_88_2_khz = false; 133 bool limit_freq_to_96_khz = false; 134 bool limit_freq_to_174_4_khz = false; 135 if (!crtc_info) 136 return; 137 138 /* For two channels supported return whatever sink support,unmodified*/ 139 if (channel_count > 2) { 140 141 /* Based on HDMI spec 1.3 Table 7.5 */ 142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 143 (crtc_info->v_active <= 576) && 144 !(crtc_info->interlaced) && 145 !(crtc_info->pixel_repetition == 2 || 146 crtc_info->pixel_repetition == 4)) { 147 limit_freq_to_48_khz = true; 148 149 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 150 (crtc_info->v_active <= 576) && 151 (crtc_info->interlaced) && 152 (crtc_info->pixel_repetition == 2)) { 153 limit_freq_to_88_2_khz = true; 154 155 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 156 (crtc_info->v_active <= 576) && 157 !(crtc_info->interlaced)) { 158 limit_freq_to_174_4_khz = true; 159 } 160 } 161 162 /* Also do some calculation for the available Audio Bandwidth for the 163 * 8 ch (i.e. for the Layout 1 => ch > 2) 164 */ 165 h_blank = crtc_info->h_total - crtc_info->h_active; 166 167 if (crtc_info->pixel_repetition) 168 h_blank *= crtc_info->pixel_repetition; 169 170 /*based on HDMI spec 1.3 Table 7.5 */ 171 h_blank -= 58; 172 /*for Control Period */ 173 h_blank -= 16; 174 175 samples = h_blank * 10; 176 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 177 * of Audio samples per line multiplied by 10 - Layout 1) 178 */ 179 samples /= 32; 180 samples *= crtc_info->v_active; 181 /*Number of samples multiplied by 10, per second */ 182 samples *= crtc_info->refresh_rate; 183 /*Number of Audio samples per second */ 184 samples /= 10; 185 186 /* @todo do it after deep color is implemented 187 * 8xx - deep color bandwidth scaling 188 * Extra bandwidth is avaliable in deep color b/c link runs faster than 189 * pixel rate. This has the effect of allowing more tmds characters to 190 * be transmitted during blank 191 */ 192 193 switch (crtc_info->color_depth) { 194 case COLOR_DEPTH_888: 195 samples *= 4; 196 break; 197 case COLOR_DEPTH_101010: 198 samples *= 5; 199 break; 200 case COLOR_DEPTH_121212: 201 samples *= 6; 202 break; 203 default: 204 samples *= 4; 205 break; 206 } 207 208 samples /= 4; 209 210 /*check limitation*/ 211 if (samples < 88200) 212 limit_freq_to_48_khz = true; 213 else if (samples < 96000) 214 limit_freq_to_88_2_khz = true; 215 else if (samples < 176400) 216 limit_freq_to_96_khz = true; 217 else if (samples < 192000) 218 limit_freq_to_174_4_khz = true; 219 220 if (sample_rates != NULL) { 221 /* limit frequencies */ 222 if (limit_freq_to_174_4_khz) 223 sample_rates->rate.RATE_192 = 0; 224 225 if (limit_freq_to_96_khz) { 226 sample_rates->rate.RATE_192 = 0; 227 sample_rates->rate.RATE_176_4 = 0; 228 } 229 if (limit_freq_to_88_2_khz) { 230 sample_rates->rate.RATE_192 = 0; 231 sample_rates->rate.RATE_176_4 = 0; 232 sample_rates->rate.RATE_96 = 0; 233 } 234 if (limit_freq_to_48_khz) { 235 sample_rates->rate.RATE_192 = 0; 236 sample_rates->rate.RATE_176_4 = 0; 237 sample_rates->rate.RATE_96 = 0; 238 sample_rates->rate.RATE_88_2 = 0; 239 } 240 } 241 } 242 243 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 244 static void check_audio_bandwidth_dpsst( 245 const struct audio_crtc_info *crtc_info, 246 uint32_t channel_count, 247 union audio_sample_rates *sample_rates) 248 { 249 /* do nothing */ 250 } 251 252 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 253 static void check_audio_bandwidth_dpmst( 254 const struct audio_crtc_info *crtc_info, 255 uint32_t channel_count, 256 union audio_sample_rates *sample_rates) 257 { 258 /* do nothing */ 259 } 260 261 static void check_audio_bandwidth( 262 const struct audio_crtc_info *crtc_info, 263 uint32_t channel_count, 264 enum signal_type signal, 265 union audio_sample_rates *sample_rates) 266 { 267 switch (signal) { 268 case SIGNAL_TYPE_HDMI_TYPE_A: 269 check_audio_bandwidth_hdmi( 270 crtc_info, channel_count, sample_rates); 271 break; 272 case SIGNAL_TYPE_EDP: 273 case SIGNAL_TYPE_DISPLAY_PORT: 274 check_audio_bandwidth_dpsst( 275 crtc_info, channel_count, sample_rates); 276 break; 277 case SIGNAL_TYPE_DISPLAY_PORT_MST: 278 check_audio_bandwidth_dpmst( 279 crtc_info, channel_count, sample_rates); 280 break; 281 default: 282 break; 283 } 284 } 285 286 /* expose/not expose HBR capability to Audio driver */ 287 static void set_high_bit_rate_capable( 288 struct audio *audio, 289 bool capable) 290 { 291 uint32_t value = 0; 292 293 /* set high bit rate audio capable*/ 294 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 295 296 set_reg_field_value(value, capable, 297 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 298 HBR_CAPABLE); 299 300 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 301 } 302 303 /* set video latency in ms/2+1 */ 304 static void set_video_latency( 305 struct audio *audio, 306 int latency_in_ms) 307 { 308 uint32_t value = 0; 309 310 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 311 return; 312 313 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 314 315 set_reg_field_value(value, latency_in_ms, 316 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 317 VIDEO_LIPSYNC); 318 319 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 320 value); 321 } 322 323 /* set audio latency in ms/2+1 */ 324 static void set_audio_latency( 325 struct audio *audio, 326 int latency_in_ms) 327 { 328 uint32_t value = 0; 329 330 if (latency_in_ms < 0) 331 latency_in_ms = 0; 332 333 if (latency_in_ms > 255) 334 latency_in_ms = 255; 335 336 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 337 338 set_reg_field_value(value, latency_in_ms, 339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 340 AUDIO_LIPSYNC); 341 342 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 343 value); 344 } 345 346 void dce_aud_az_enable(struct audio *audio) 347 { 348 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 349 DC_LOGGER_INIT(); 350 351 set_reg_field_value(value, 1, 352 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 353 CLOCK_GATING_DISABLE); 354 set_reg_field_value(value, 1, 355 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 356 AUDIO_ENABLED); 357 358 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 359 set_reg_field_value(value, 0, 360 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 361 CLOCK_GATING_DISABLE); 362 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 363 364 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 365 audio->inst, value); 366 } 367 368 void dce_aud_az_disable(struct audio *audio) 369 { 370 uint32_t value; 371 DC_LOGGER_INIT(); 372 373 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 374 set_reg_field_value(value, 1, 375 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 376 CLOCK_GATING_DISABLE); 377 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 378 379 set_reg_field_value(value, 0, 380 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 381 AUDIO_ENABLED); 382 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 383 384 set_reg_field_value(value, 0, 385 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 386 CLOCK_GATING_DISABLE); 387 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 388 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 389 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 390 audio->inst, value); 391 } 392 393 void dce_aud_az_configure( 394 struct audio *audio, 395 enum signal_type signal, 396 const struct audio_crtc_info *crtc_info, 397 const struct audio_info *audio_info) 398 { 399 struct dce_audio *aud = DCE_AUD(audio); 400 401 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 402 uint32_t value; 403 uint32_t field = 0; 404 enum audio_format_code audio_format_code; 405 uint32_t format_index; 406 uint32_t index; 407 bool is_ac3_supported = false; 408 union audio_sample_rates sample_rate; 409 uint32_t strlen = 0; 410 411 if (signal == SIGNAL_TYPE_VIRTUAL) 412 return; 413 414 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 415 set_reg_field_value(value, 1, 416 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 417 CLOCK_GATING_DISABLE); 418 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 419 420 /* Speaker Allocation */ 421 /* 422 uint32_t value; 423 uint32_t field = 0;*/ 424 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 425 426 set_reg_field_value(value, 427 speakers, 428 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 429 SPEAKER_ALLOCATION); 430 431 /* LFE_PLAYBACK_LEVEL = LFEPBL 432 * LFEPBL = 0 : Unknown or refer to other information 433 * LFEPBL = 1 : 0dB playback 434 * LFEPBL = 2 : +10dB playback 435 * LFE_BL = 3 : Reserved 436 */ 437 set_reg_field_value(value, 438 0, 439 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 440 LFE_PLAYBACK_LEVEL); 441 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 442 * why are we writing to it? DCE8 does not write this */ 443 444 445 set_reg_field_value(value, 446 0, 447 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 448 HDMI_CONNECTION); 449 450 set_reg_field_value(value, 451 0, 452 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 453 DP_CONNECTION); 454 455 field = get_reg_field_value(value, 456 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 457 EXTRA_CONNECTION_INFO); 458 459 field &= ~0x1; 460 461 set_reg_field_value(value, 462 field, 463 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 464 EXTRA_CONNECTION_INFO); 465 466 /* set audio for output signal */ 467 switch (signal) { 468 case SIGNAL_TYPE_HDMI_TYPE_A: 469 set_reg_field_value(value, 470 1, 471 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 472 HDMI_CONNECTION); 473 474 break; 475 476 case SIGNAL_TYPE_EDP: 477 case SIGNAL_TYPE_DISPLAY_PORT: 478 case SIGNAL_TYPE_DISPLAY_PORT_MST: 479 set_reg_field_value(value, 480 1, 481 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 482 DP_CONNECTION); 483 break; 484 default: 485 BREAK_TO_DEBUGGER(); 486 break; 487 } 488 489 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 490 491 /* ACP Data - Supports AI */ 492 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); 493 494 set_reg_field_value( 495 value, 496 audio_info->flags.info.SUPPORT_AI, 497 AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, 498 SUPPORTS_AI); 499 500 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); 501 502 /* Audio Descriptors */ 503 /* pass through all formats */ 504 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 505 format_index++) { 506 audio_format_code = 507 (AUDIO_FORMAT_CODE_FIRST + format_index); 508 509 /* those are unsupported, skip programming */ 510 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 511 audio_format_code == AUDIO_FORMAT_CODE_DST) 512 continue; 513 514 value = 0; 515 516 /* check if supported */ 517 if (is_audio_format_supported( 518 audio_info, audio_format_code, &index)) { 519 const struct audio_mode *audio_mode = 520 &audio_info->modes[index]; 521 union audio_sample_rates sample_rates = 522 audio_mode->sample_rates; 523 uint8_t byte2 = audio_mode->max_bit_rate; 524 uint8_t channel_count = audio_mode->channel_count; 525 526 /* adjust specific properties */ 527 switch (audio_format_code) { 528 case AUDIO_FORMAT_CODE_LINEARPCM: { 529 530 check_audio_bandwidth( 531 crtc_info, 532 channel_count, 533 signal, 534 &sample_rates); 535 536 byte2 = audio_mode->sample_size; 537 538 set_reg_field_value(value, 539 sample_rates.all, 540 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 541 SUPPORTED_FREQUENCIES_STEREO); 542 } 543 break; 544 case AUDIO_FORMAT_CODE_AC3: 545 is_ac3_supported = true; 546 break; 547 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 548 case AUDIO_FORMAT_CODE_DTS_HD: 549 case AUDIO_FORMAT_CODE_MAT_MLP: 550 case AUDIO_FORMAT_CODE_DST: 551 case AUDIO_FORMAT_CODE_WMAPRO: 552 byte2 = audio_mode->vendor_specific; 553 break; 554 default: 555 break; 556 } 557 558 /* fill audio format data */ 559 set_reg_field_value(value, 560 channel_count - 1, 561 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 562 MAX_CHANNELS); 563 564 set_reg_field_value(value, 565 sample_rates.all, 566 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 567 SUPPORTED_FREQUENCIES); 568 569 set_reg_field_value(value, 570 byte2, 571 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 572 DESCRIPTOR_BYTE_2); 573 } /* if */ 574 575 AZ_REG_WRITE( 576 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 577 value); 578 } /* for */ 579 580 if (is_ac3_supported) 581 /* todo: this reg global. why program global register? */ 582 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 583 0x05); 584 585 /* check for 192khz/8-Ch support for HBR requirements */ 586 sample_rate.all = 0; 587 sample_rate.rate.RATE_192 = 1; 588 589 check_audio_bandwidth( 590 crtc_info, 591 8, 592 signal, 593 &sample_rate); 594 595 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 596 597 /* Audio and Video Lipsync */ 598 set_video_latency(audio, audio_info->video_latency); 599 set_audio_latency(audio, audio_info->audio_latency); 600 601 value = 0; 602 set_reg_field_value(value, audio_info->manufacture_id, 603 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 604 MANUFACTURER_ID); 605 606 set_reg_field_value(value, audio_info->product_id, 607 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 608 PRODUCT_ID); 609 610 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 611 value); 612 613 value = 0; 614 615 /*get display name string length */ 616 while (audio_info->display_name[strlen++] != '\0') { 617 if (strlen >= 618 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 619 break; 620 } 621 set_reg_field_value(value, strlen, 622 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 623 SINK_DESCRIPTION_LEN); 624 625 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 626 value); 627 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 628 audio->inst, value, audio_info->display_name); 629 630 /* 631 *write the port ID: 632 *PORT_ID0 = display index 633 *PORT_ID1 = 16bit BDF 634 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 635 */ 636 637 value = 0; 638 639 set_reg_field_value(value, audio_info->port_id[0], 640 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 641 PORT_ID0); 642 643 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 644 645 value = 0; 646 set_reg_field_value(value, audio_info->port_id[1], 647 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 648 PORT_ID1); 649 650 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 651 652 /*write the 18 char monitor string */ 653 654 value = 0; 655 set_reg_field_value(value, audio_info->display_name[0], 656 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 657 DESCRIPTION0); 658 659 set_reg_field_value(value, audio_info->display_name[1], 660 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 661 DESCRIPTION1); 662 663 set_reg_field_value(value, audio_info->display_name[2], 664 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 665 DESCRIPTION2); 666 667 set_reg_field_value(value, audio_info->display_name[3], 668 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 669 DESCRIPTION3); 670 671 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 672 673 value = 0; 674 set_reg_field_value(value, audio_info->display_name[4], 675 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 676 DESCRIPTION4); 677 678 set_reg_field_value(value, audio_info->display_name[5], 679 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 680 DESCRIPTION5); 681 682 set_reg_field_value(value, audio_info->display_name[6], 683 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 684 DESCRIPTION6); 685 686 set_reg_field_value(value, audio_info->display_name[7], 687 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 688 DESCRIPTION7); 689 690 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 691 692 value = 0; 693 set_reg_field_value(value, audio_info->display_name[8], 694 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 695 DESCRIPTION8); 696 697 set_reg_field_value(value, audio_info->display_name[9], 698 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 699 DESCRIPTION9); 700 701 set_reg_field_value(value, audio_info->display_name[10], 702 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 703 DESCRIPTION10); 704 705 set_reg_field_value(value, audio_info->display_name[11], 706 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 707 DESCRIPTION11); 708 709 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 710 711 value = 0; 712 set_reg_field_value(value, audio_info->display_name[12], 713 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 714 DESCRIPTION12); 715 716 set_reg_field_value(value, audio_info->display_name[13], 717 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 718 DESCRIPTION13); 719 720 set_reg_field_value(value, audio_info->display_name[14], 721 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 722 DESCRIPTION14); 723 724 set_reg_field_value(value, audio_info->display_name[15], 725 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 726 DESCRIPTION15); 727 728 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 729 730 value = 0; 731 set_reg_field_value(value, audio_info->display_name[16], 732 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 733 DESCRIPTION16); 734 735 set_reg_field_value(value, audio_info->display_name[17], 736 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 737 DESCRIPTION17); 738 739 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 740 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 741 set_reg_field_value(value, 0, 742 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 743 CLOCK_GATING_DISABLE); 744 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 745 } 746 747 /* 748 * todo: wall clk related functionality probably belong to clock_src. 749 */ 750 751 /* search pixel clock value for Azalia HDMI Audio */ 752 static void get_azalia_clock_info_hdmi( 753 uint32_t crtc_pixel_clock_100hz, 754 uint32_t actual_pixel_clock_100Hz, 755 struct azalia_clock_info *azalia_clock_info) 756 { 757 /* audio_dto_phase= 24 * 10,000; 758 * 24MHz in [100Hz] units */ 759 azalia_clock_info->audio_dto_phase = 760 24 * 10000; 761 762 /* audio_dto_module = PCLKFrequency * 10,000; 763 * [khz] -> [100Hz] */ 764 azalia_clock_info->audio_dto_module = 765 actual_pixel_clock_100Hz; 766 } 767 768 static void get_azalia_clock_info_dp( 769 uint32_t requested_pixel_clock_100Hz, 770 const struct audio_pll_info *pll_info, 771 struct azalia_clock_info *azalia_clock_info) 772 { 773 /* Reported dpDtoSourceClockInkhz value for 774 * DCE8 already adjusted for SS, do not need any 775 * adjustment here anymore 776 */ 777 778 /*audio_dto_phase = 24 * 10,000; 779 * 24MHz in [100Hz] units */ 780 azalia_clock_info->audio_dto_phase = 24 * 10000; 781 782 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 783 * [khz] ->[100Hz] */ 784 azalia_clock_info->audio_dto_module = 785 pll_info->audio_dto_source_clock_in_khz * 10; 786 } 787 788 void dce_aud_wall_dto_setup( 789 struct audio *audio, 790 enum signal_type signal, 791 const struct audio_crtc_info *crtc_info, 792 const struct audio_pll_info *pll_info) 793 { 794 struct dce_audio *aud = DCE_AUD(audio); 795 796 struct azalia_clock_info clock_info = { 0 }; 797 798 if (dc_is_hdmi_tmds_signal(signal)) { 799 uint32_t src_sel; 800 801 /*DTO0 Programming goal: 802 -generate 24MHz, 128*Fs from 24MHz 803 -use DTO0 when an active HDMI port is connected 804 (optionally a DP is connected) */ 805 806 /* calculate DTO settings */ 807 get_azalia_clock_info_hdmi( 808 crtc_info->requested_pixel_clock_100Hz, 809 crtc_info->calculated_pixel_clock_100Hz, 810 &clock_info); 811 812 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 813 "calculated_pixel_clock_100Hz =%d\n"\ 814 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 815 crtc_info->requested_pixel_clock_100Hz,\ 816 crtc_info->calculated_pixel_clock_100Hz,\ 817 clock_info.audio_dto_module,\ 818 clock_info.audio_dto_phase); 819 820 /* On TN/SI, Program DTO source select and DTO select before 821 programming DTO modulo and DTO phase. These bits must be 822 programmed first, otherwise there will be no HDMI audio at boot 823 up. This is a HW sequence change (different from old ASICs). 824 Caution when changing this programming sequence. 825 826 HDMI enabled, using DTO0 827 program master CRTC for DTO0 */ 828 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 829 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 830 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 831 DCCG_AUDIO_DTO_SEL, 0); 832 833 /* module */ 834 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 835 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 836 837 /* phase */ 838 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 839 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 840 } else { 841 /*DTO1 Programming goal: 842 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 843 -default is to used DTO1, and switch to DTO0 when an audio 844 master HDMI port is connected 845 -use as default for DP 846 847 calculate DTO settings */ 848 get_azalia_clock_info_dp( 849 crtc_info->requested_pixel_clock_100Hz, 850 pll_info, 851 &clock_info); 852 853 /* Program DTO select before programming DTO modulo and DTO 854 phase. default to use DTO1 */ 855 856 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 857 DCCG_AUDIO_DTO_SEL, 1); 858 859 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 860 * Select 512fs for DP TODO: web register definition 861 * does not match register header file 862 * DCE11 version it's commented out while DCE8 it's set to 1 863 */ 864 865 /* module */ 866 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 867 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 868 869 /* phase */ 870 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 871 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 872 873 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 874 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 875 876 } 877 } 878 879 #if defined(CONFIG_DRM_AMD_DC_SI) 880 static void dce60_aud_wall_dto_setup( 881 struct audio *audio, 882 enum signal_type signal, 883 const struct audio_crtc_info *crtc_info, 884 const struct audio_pll_info *pll_info) 885 { 886 struct dce_audio *aud = DCE_AUD(audio); 887 888 struct azalia_clock_info clock_info = { 0 }; 889 890 if (dc_is_hdmi_signal(signal)) { 891 uint32_t src_sel; 892 893 /*DTO0 Programming goal: 894 -generate 24MHz, 128*Fs from 24MHz 895 -use DTO0 when an active HDMI port is connected 896 (optionally a DP is connected) */ 897 898 /* calculate DTO settings */ 899 get_azalia_clock_info_hdmi( 900 crtc_info->requested_pixel_clock_100Hz, 901 crtc_info->calculated_pixel_clock_100Hz, 902 &clock_info); 903 904 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 905 "calculated_pixel_clock_100Hz =%d\n"\ 906 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 907 crtc_info->requested_pixel_clock_100Hz,\ 908 crtc_info->calculated_pixel_clock_100Hz,\ 909 clock_info.audio_dto_module,\ 910 clock_info.audio_dto_phase); 911 912 /* On TN/SI, Program DTO source select and DTO select before 913 programming DTO modulo and DTO phase. These bits must be 914 programmed first, otherwise there will be no HDMI audio at boot 915 up. This is a HW sequence change (different from old ASICs). 916 Caution when changing this programming sequence. 917 918 HDMI enabled, using DTO0 919 program master CRTC for DTO0 */ 920 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 921 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 922 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 923 DCCG_AUDIO_DTO_SEL, 0); 924 925 /* module */ 926 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 927 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 928 929 /* phase */ 930 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 931 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 932 } else { 933 /*DTO1 Programming goal: 934 -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) 935 -default is to used DTO1, and switch to DTO0 when an audio 936 master HDMI port is connected 937 -use as default for DP 938 939 calculate DTO settings */ 940 get_azalia_clock_info_dp( 941 crtc_info->requested_pixel_clock_100Hz, 942 pll_info, 943 &clock_info); 944 945 /* Program DTO select before programming DTO modulo and DTO 946 phase. default to use DTO1 */ 947 948 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 949 DCCG_AUDIO_DTO_SEL, 1); 950 951 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 952 * Cannot select 512fs for DP 953 * 954 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask 955 */ 956 957 /* module */ 958 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 959 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 960 961 /* phase */ 962 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 963 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 964 965 /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ 966 967 } 968 } 969 #endif 970 971 static bool dce_aud_endpoint_valid(struct audio *audio) 972 { 973 uint32_t value; 974 uint32_t port_connectivity; 975 976 value = AZ_REG_READ( 977 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 978 979 port_connectivity = get_reg_field_value(value, 980 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 981 PORT_CONNECTIVITY); 982 983 return !(port_connectivity == 1); 984 } 985 986 /* initialize HW state */ 987 void dce_aud_hw_init( 988 struct audio *audio) 989 { 990 uint32_t value; 991 struct dce_audio *aud = DCE_AUD(audio); 992 993 /* we only need to program the following registers once, so we only do 994 it for the inst 0*/ 995 if (audio->inst != 0) 996 return; 997 998 /* Suport R5 - 32khz 999 * Suport R6 - 44.1khz 1000 * Suport R7 - 48khz 1001 */ 1002 /*disable clock gating before write to endpoint register*/ 1003 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1004 set_reg_field_value(value, 1, 1005 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1006 CLOCK_GATING_DISABLE); 1007 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1008 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 1009 AUDIO_RATE_CAPABILITIES, 0x70); 1010 1011 /*Keep alive bit to verify HW block in BU. */ 1012 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 1013 CLKSTOP, 1, 1014 EPSS, 1); 1015 set_reg_field_value(value, 0, 1016 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1017 CLOCK_GATING_DISABLE); 1018 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1019 } 1020 1021 static const struct audio_funcs funcs = { 1022 .endpoint_valid = dce_aud_endpoint_valid, 1023 .hw_init = dce_aud_hw_init, 1024 .wall_dto_setup = dce_aud_wall_dto_setup, 1025 .az_enable = dce_aud_az_enable, 1026 .az_disable = dce_aud_az_disable, 1027 .az_configure = dce_aud_az_configure, 1028 .destroy = dce_aud_destroy, 1029 }; 1030 1031 #if defined(CONFIG_DRM_AMD_DC_SI) 1032 static const struct audio_funcs dce60_funcs = { 1033 .endpoint_valid = dce_aud_endpoint_valid, 1034 .hw_init = dce_aud_hw_init, 1035 .wall_dto_setup = dce60_aud_wall_dto_setup, 1036 .az_enable = dce_aud_az_enable, 1037 .az_disable = dce_aud_az_disable, 1038 .az_configure = dce_aud_az_configure, 1039 .destroy = dce_aud_destroy, 1040 }; 1041 #endif 1042 1043 void dce_aud_destroy(struct audio **audio) 1044 { 1045 struct dce_audio *aud = DCE_AUD(*audio); 1046 1047 kfree(aud); 1048 *audio = NULL; 1049 } 1050 1051 struct audio *dce_audio_create( 1052 struct dc_context *ctx, 1053 unsigned int inst, 1054 const struct dce_audio_registers *reg, 1055 const struct dce_audio_shift *shifts, 1056 const struct dce_audio_mask *masks 1057 ) 1058 { 1059 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1060 1061 if (audio == NULL) { 1062 ASSERT_CRITICAL(audio); 1063 return NULL; 1064 } 1065 1066 audio->base.ctx = ctx; 1067 audio->base.inst = inst; 1068 audio->base.funcs = &funcs; 1069 1070 audio->regs = reg; 1071 audio->shifts = shifts; 1072 audio->masks = masks; 1073 return &audio->base; 1074 } 1075 1076 #if defined(CONFIG_DRM_AMD_DC_SI) 1077 struct audio *dce60_audio_create( 1078 struct dc_context *ctx, 1079 unsigned int inst, 1080 const struct dce_audio_registers *reg, 1081 const struct dce_audio_shift *shifts, 1082 const struct dce_audio_mask *masks 1083 ) 1084 { 1085 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1086 1087 if (audio == NULL) { 1088 ASSERT_CRITICAL(audio); 1089 return NULL; 1090 } 1091 1092 audio->base.ctx = ctx; 1093 audio->base.inst = inst; 1094 audio->base.funcs = &dce60_funcs; 1095 1096 audio->regs = reg; 1097 audio->shifts = shifts; 1098 audio->masks = masks; 1099 return &audio->base; 1100 } 1101 #endif 1102