1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 37 #define DC_LOGGER_INIT() 38 39 #define REG(reg)\ 40 (aud->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 aud->shifts->field_name, aud->masks->field_name 45 46 #define IX_REG(reg)\ 47 ix ## reg 48 49 #define AZ_REG_READ(reg_name) \ 50 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 51 52 #define AZ_REG_WRITE(reg_name, value) \ 53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 54 55 static void write_indirect_azalia_reg(struct audio *audio, 56 uint32_t reg_index, 57 uint32_t reg_data) 58 { 59 struct dce_audio *aud = DCE_AUD(audio); 60 61 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 63 AZALIA_ENDPOINT_REG_INDEX, reg_index); 64 65 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 67 AZALIA_ENDPOINT_REG_DATA, reg_data); 68 } 69 70 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 71 { 72 struct dce_audio *aud = DCE_AUD(audio); 73 74 uint32_t value = 0; 75 76 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 77 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 78 AZALIA_ENDPOINT_REG_INDEX, reg_index); 79 80 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 82 83 return value; 84 } 85 86 static bool is_audio_format_supported( 87 const struct audio_info *audio_info, 88 enum audio_format_code audio_format_code, 89 uint32_t *format_index) 90 { 91 uint32_t index; 92 uint32_t max_channe_index = 0; 93 bool found = false; 94 95 if (audio_info == NULL) 96 return found; 97 98 /* pass through whole array */ 99 for (index = 0; index < audio_info->mode_count; index++) { 100 if (audio_info->modes[index].format_code == audio_format_code) { 101 if (found) { 102 /* format has multiply entries, choose one with 103 * highst number of channels */ 104 if (audio_info->modes[index].channel_count > 105 audio_info->modes[max_channe_index].channel_count) { 106 max_channe_index = index; 107 } 108 } else { 109 /* format found, save it's index */ 110 found = true; 111 max_channe_index = index; 112 } 113 } 114 } 115 116 /* return index */ 117 if (found && format_index != NULL) 118 *format_index = max_channe_index; 119 120 return found; 121 } 122 123 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 124 static void check_audio_bandwidth_hdmi( 125 const struct audio_crtc_info *crtc_info, 126 uint32_t channel_count, 127 union audio_sample_rates *sample_rates) 128 { 129 uint32_t samples; 130 uint32_t h_blank; 131 bool limit_freq_to_48_khz = false; 132 bool limit_freq_to_88_2_khz = false; 133 bool limit_freq_to_96_khz = false; 134 bool limit_freq_to_174_4_khz = false; 135 if (!crtc_info) 136 return; 137 138 /* For two channels supported return whatever sink support,unmodified*/ 139 if (channel_count > 2) { 140 141 /* Based on HDMI spec 1.3 Table 7.5 */ 142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 143 (crtc_info->v_active <= 576) && 144 !(crtc_info->interlaced) && 145 !(crtc_info->pixel_repetition == 2 || 146 crtc_info->pixel_repetition == 4)) { 147 limit_freq_to_48_khz = true; 148 149 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 150 (crtc_info->v_active <= 576) && 151 (crtc_info->interlaced) && 152 (crtc_info->pixel_repetition == 2)) { 153 limit_freq_to_88_2_khz = true; 154 155 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 156 (crtc_info->v_active <= 576) && 157 !(crtc_info->interlaced)) { 158 limit_freq_to_174_4_khz = true; 159 } 160 } 161 162 /* Also do some calculation for the available Audio Bandwidth for the 163 * 8 ch (i.e. for the Layout 1 => ch > 2) 164 */ 165 h_blank = crtc_info->h_total - crtc_info->h_active; 166 167 if (crtc_info->pixel_repetition) 168 h_blank *= crtc_info->pixel_repetition; 169 170 /*based on HDMI spec 1.3 Table 7.5 */ 171 h_blank -= 58; 172 /*for Control Period */ 173 h_blank -= 16; 174 175 samples = h_blank * 10; 176 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 177 * of Audio samples per line multiplied by 10 - Layout 1) 178 */ 179 samples /= 32; 180 samples *= crtc_info->v_active; 181 /*Number of samples multiplied by 10, per second */ 182 samples *= crtc_info->refresh_rate; 183 /*Number of Audio samples per second */ 184 samples /= 10; 185 186 /* @todo do it after deep color is implemented 187 * 8xx - deep color bandwidth scaling 188 * Extra bandwidth is avaliable in deep color b/c link runs faster than 189 * pixel rate. This has the effect of allowing more tmds characters to 190 * be transmitted during blank 191 */ 192 193 switch (crtc_info->color_depth) { 194 case COLOR_DEPTH_888: 195 samples *= 4; 196 break; 197 case COLOR_DEPTH_101010: 198 samples *= 5; 199 break; 200 case COLOR_DEPTH_121212: 201 samples *= 6; 202 break; 203 default: 204 samples *= 4; 205 break; 206 } 207 208 samples /= 4; 209 210 /*check limitation*/ 211 if (samples < 88200) 212 limit_freq_to_48_khz = true; 213 else if (samples < 96000) 214 limit_freq_to_88_2_khz = true; 215 else if (samples < 176400) 216 limit_freq_to_96_khz = true; 217 else if (samples < 192000) 218 limit_freq_to_174_4_khz = true; 219 220 if (sample_rates != NULL) { 221 /* limit frequencies */ 222 if (limit_freq_to_174_4_khz) 223 sample_rates->rate.RATE_192 = 0; 224 225 if (limit_freq_to_96_khz) { 226 sample_rates->rate.RATE_192 = 0; 227 sample_rates->rate.RATE_176_4 = 0; 228 } 229 if (limit_freq_to_88_2_khz) { 230 sample_rates->rate.RATE_192 = 0; 231 sample_rates->rate.RATE_176_4 = 0; 232 sample_rates->rate.RATE_96 = 0; 233 } 234 if (limit_freq_to_48_khz) { 235 sample_rates->rate.RATE_192 = 0; 236 sample_rates->rate.RATE_176_4 = 0; 237 sample_rates->rate.RATE_96 = 0; 238 sample_rates->rate.RATE_88_2 = 0; 239 } 240 } 241 } 242 static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate) 243 { 244 switch (link_rate) { 245 case LINK_RATE_LOW: 246 return dc_fixpt_from_int(162); /* 162 MHz */ 247 case LINK_RATE_HIGH: 248 return dc_fixpt_from_int(270); /* 270 MHz */ 249 case LINK_RATE_HIGH2: 250 return dc_fixpt_from_int(540); /* 540 MHz */ 251 case LINK_RATE_HIGH3: 252 return dc_fixpt_from_int(810); /* 810 MHz */ 253 case LINK_RATE_UHBR10: 254 return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */ 255 case LINK_RATE_UHBR13_5: 256 return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */ 257 case LINK_RATE_UHBR20: 258 return dc_fixpt_from_int(625); /* 625 MHz */ 259 default: 260 /* Unexpected case, this requires debug if encountered. */ 261 ASSERT(0); 262 return dc_fixpt_from_int(0); 263 } 264 } 265 266 struct dp_audio_layout_config { 267 uint8_t layouts_per_sample_denom; 268 uint8_t symbols_per_layout; 269 uint8_t max_layouts_per_audio_sdp; 270 }; 271 272 static void get_audio_layout_config( 273 uint32_t channel_count, 274 enum dp_link_encoding encoding, 275 struct dp_audio_layout_config *output) 276 { 277 /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, 278 * with each layout being the same size (8ch layout). 279 */ 280 if (encoding == DP_8b_10b_ENCODING) { 281 if (channel_count == 2) { 282 output->layouts_per_sample_denom = 4; 283 output->symbols_per_layout = 40; 284 output->max_layouts_per_audio_sdp = 1; 285 } else if (channel_count == 8 || channel_count == 6) { 286 output->layouts_per_sample_denom = 1; 287 output->symbols_per_layout = 40; 288 output->max_layouts_per_audio_sdp = 1; 289 } 290 } else if (encoding == DP_128b_132b_ENCODING) { 291 if (channel_count == 2) { 292 output->layouts_per_sample_denom = 4; 293 output->symbols_per_layout = 10; 294 output->max_layouts_per_audio_sdp = 1; 295 } else if (channel_count == 8 || channel_count == 6) { 296 output->layouts_per_sample_denom = 1; 297 output->symbols_per_layout = 10; 298 output->max_layouts_per_audio_sdp = 1; 299 } 300 } 301 } 302 303 static uint32_t get_av_stream_map_lane_count( 304 enum dp_link_encoding encoding, 305 enum dc_lane_count lane_count, 306 bool is_mst) 307 { 308 uint32_t av_stream_map_lane_count = 0; 309 310 if (encoding == DP_8b_10b_ENCODING) { 311 if (!is_mst) 312 av_stream_map_lane_count = lane_count; 313 else 314 av_stream_map_lane_count = 4; 315 } else if (encoding == DP_128b_132b_ENCODING) { 316 av_stream_map_lane_count = 4; 317 } 318 319 ASSERT(av_stream_map_lane_count != 0); 320 321 return av_stream_map_lane_count; 322 } 323 324 static uint32_t get_audio_sdp_overhead( 325 enum dp_link_encoding encoding, 326 enum dc_lane_count lane_count, 327 bool is_mst) 328 { 329 uint32_t audio_sdp_overhead = 0; 330 331 if (encoding == DP_8b_10b_ENCODING) { 332 if (is_mst) 333 audio_sdp_overhead = 16; /* 4 * 2 + 8 */ 334 else 335 audio_sdp_overhead = lane_count * 2 + 8; 336 } else if (encoding == DP_128b_132b_ENCODING) { 337 audio_sdp_overhead = 10; /* 4 x 2.5 */ 338 } 339 340 ASSERT(audio_sdp_overhead != 0); 341 342 return audio_sdp_overhead; 343 } 344 345 static uint32_t calculate_required_audio_bw_in_symbols( 346 const struct audio_crtc_info *crtc_info, 347 const struct dp_audio_layout_config *layout_config, 348 uint32_t channel_count, 349 uint32_t sample_rate_hz, 350 uint32_t av_stream_map_lane_count, 351 uint32_t audio_sdp_overhead) 352 { 353 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ 354 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); 355 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( 356 crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10); 357 struct fixed31_32 samples_per_line; 358 struct fixed31_32 layouts_per_line; 359 struct fixed31_32 symbols_per_sdp_max_layout; 360 struct fixed31_32 remainder; 361 uint32_t num_sdp_with_max_layouts; 362 uint32_t required_symbols_per_hblank; 363 364 samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000); 365 samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz); 366 layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom); 367 368 num_sdp_with_max_layouts = dc_fixpt_floor( 369 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp)); 370 symbols_per_sdp_max_layout = dc_fixpt_from_int( 371 layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout); 372 symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead); 373 symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin); 374 required_symbols_per_hblank = num_sdp_with_max_layouts; 375 required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) / 376 av_stream_map_lane_count) * av_stream_map_lane_count; 377 378 if (num_sdp_with_max_layouts != dc_fixpt_ceil( 379 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) { 380 remainder = dc_fixpt_sub_int(layouts_per_line, 381 num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp); 382 remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout); 383 remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead); 384 remainder = dc_fixpt_mul(remainder, audio_sdp_margin); 385 required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) / 386 av_stream_map_lane_count) * av_stream_map_lane_count; 387 } 388 389 return required_symbols_per_hblank; 390 } 391 392 /* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. 393 */ 394 static uint32_t calculate_available_hblank_bw_in_symbols( 395 const struct audio_crtc_info *crtc_info, 396 const struct audio_dp_link_info *dp_link_info) 397 { 398 uint64_t hblank = crtc_info->h_total - crtc_info->h_active; 399 struct fixed31_32 hblank_time_msec = 400 dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz); 401 struct fixed31_32 lsclkfreq_mhz = 402 get_link_symbol_clk_freq_mhz(dp_link_info->link_rate); 403 struct fixed31_32 average_stream_sym_bw_frac; 404 struct fixed31_32 peak_stream_bw_kbps; 405 struct fixed31_32 bits_per_pixel; 406 struct fixed31_32 link_bw_kbps; 407 struct fixed31_32 available_stream_sym_count; 408 uint32_t available_hblank_bw = 0; /* in stream symbols */ 409 410 if (crtc_info->dsc_bits_per_pixel) { 411 bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16); 412 } else { 413 switch (crtc_info->color_depth) { 414 case COLOR_DEPTH_666: 415 bits_per_pixel = dc_fixpt_from_int(6); 416 break; 417 case COLOR_DEPTH_888: 418 bits_per_pixel = dc_fixpt_from_int(8); 419 break; 420 case COLOR_DEPTH_101010: 421 bits_per_pixel = dc_fixpt_from_int(10); 422 break; 423 case COLOR_DEPTH_121212: 424 bits_per_pixel = dc_fixpt_from_int(12); 425 break; 426 default: 427 /* Default to commonly supported color depth. */ 428 bits_per_pixel = dc_fixpt_from_int(8); 429 break; 430 } 431 432 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3); 433 434 if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 435 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3); 436 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2); 437 } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) { 438 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2); 439 } 440 } 441 442 /* Use simple stream BW calculation because mainlink overhead is 443 * accounted for separately in the audio BW calculations. 444 */ 445 peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10); 446 peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel); 447 link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps); 448 average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps); 449 450 available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000); 451 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz); 452 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac); 453 available_hblank_bw = dc_fixpt_floor(available_stream_sym_count); 454 available_hblank_bw *= dp_link_info->lane_count; 455 available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */ 456 457 if (available_hblank_bw < dp_link_info->hblank_min_symbol_width) 458 /* Each symbol takes 4 frames */ 459 available_hblank_bw = 4 * dp_link_info->hblank_min_symbol_width; 460 461 if (available_hblank_bw < 12) 462 available_hblank_bw = 0; 463 else 464 available_hblank_bw -= 12; /* Main link overhead */ 465 466 return available_hblank_bw; 467 } 468 469 static void check_audio_bandwidth_dp( 470 const struct audio_crtc_info *crtc_info, 471 const struct audio_dp_link_info *dp_link_info, 472 uint32_t channel_count, 473 union audio_sample_rates *sample_rates) 474 { 475 struct dp_audio_layout_config layout_config = {0}; 476 uint32_t available_hblank_bw; 477 uint32_t av_stream_map_lane_count; 478 uint32_t audio_sdp_overhead; 479 480 /* TODO: Add validation for SST 8b/10 case */ 481 if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING) 482 return; 483 484 available_hblank_bw = calculate_available_hblank_bw_in_symbols( 485 crtc_info, dp_link_info); 486 av_stream_map_lane_count = get_av_stream_map_lane_count( 487 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 488 audio_sdp_overhead = get_audio_sdp_overhead( 489 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 490 get_audio_layout_config( 491 channel_count, dp_link_info->encoding, &layout_config); 492 493 if (layout_config.max_layouts_per_audio_sdp == 0 || 494 layout_config.symbols_per_layout == 0 || 495 layout_config.layouts_per_sample_denom == 0) { 496 return; 497 } 498 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 499 crtc_info, &layout_config, channel_count, 192000, 500 av_stream_map_lane_count, audio_sdp_overhead)) 501 sample_rates->rate.RATE_192 = 0; 502 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 503 crtc_info, &layout_config, channel_count, 176400, 504 av_stream_map_lane_count, audio_sdp_overhead)) 505 sample_rates->rate.RATE_176_4 = 0; 506 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 507 crtc_info, &layout_config, channel_count, 96000, 508 av_stream_map_lane_count, audio_sdp_overhead)) 509 sample_rates->rate.RATE_96 = 0; 510 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 511 crtc_info, &layout_config, channel_count, 88200, 512 av_stream_map_lane_count, audio_sdp_overhead)) 513 sample_rates->rate.RATE_88_2 = 0; 514 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 515 crtc_info, &layout_config, channel_count, 48000, 516 av_stream_map_lane_count, audio_sdp_overhead)) 517 sample_rates->rate.RATE_48 = 0; 518 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 519 crtc_info, &layout_config, channel_count, 44100, 520 av_stream_map_lane_count, audio_sdp_overhead)) 521 sample_rates->rate.RATE_44_1 = 0; 522 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 523 crtc_info, &layout_config, channel_count, 32000, 524 av_stream_map_lane_count, audio_sdp_overhead)) 525 sample_rates->rate.RATE_32 = 0; 526 } 527 528 static void check_audio_bandwidth( 529 const struct audio_crtc_info *crtc_info, 530 const struct audio_dp_link_info *dp_link_info, 531 uint32_t channel_count, 532 enum signal_type signal, 533 union audio_sample_rates *sample_rates) 534 { 535 switch (signal) { 536 case SIGNAL_TYPE_HDMI_TYPE_A: 537 check_audio_bandwidth_hdmi( 538 crtc_info, channel_count, sample_rates); 539 break; 540 case SIGNAL_TYPE_EDP: 541 case SIGNAL_TYPE_DISPLAY_PORT: 542 case SIGNAL_TYPE_DISPLAY_PORT_MST: 543 check_audio_bandwidth_dp( 544 crtc_info, dp_link_info, channel_count, sample_rates); 545 break; 546 default: 547 break; 548 } 549 } 550 551 /* expose/not expose HBR capability to Audio driver */ 552 static void set_high_bit_rate_capable( 553 struct audio *audio, 554 bool capable) 555 { 556 uint32_t value = 0; 557 558 /* set high bit rate audio capable*/ 559 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 560 561 set_reg_field_value(value, capable, 562 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 563 HBR_CAPABLE); 564 565 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 566 } 567 568 /* set video latency in ms/2+1 */ 569 static void set_video_latency( 570 struct audio *audio, 571 int latency_in_ms) 572 { 573 uint32_t value = 0; 574 575 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 576 return; 577 578 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 579 580 set_reg_field_value(value, latency_in_ms, 581 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 582 VIDEO_LIPSYNC); 583 584 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 585 value); 586 } 587 588 /* set audio latency in ms/2+1 */ 589 static void set_audio_latency( 590 struct audio *audio, 591 int latency_in_ms) 592 { 593 uint32_t value = 0; 594 595 if (latency_in_ms < 0) 596 latency_in_ms = 0; 597 598 if (latency_in_ms > 255) 599 latency_in_ms = 255; 600 601 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 602 603 set_reg_field_value(value, latency_in_ms, 604 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 605 AUDIO_LIPSYNC); 606 607 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 608 value); 609 } 610 611 void dce_aud_az_enable(struct audio *audio) 612 { 613 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 614 DC_LOGGER_INIT(); 615 616 set_reg_field_value(value, 1, 617 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 618 CLOCK_GATING_DISABLE); 619 set_reg_field_value(value, 1, 620 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 621 AUDIO_ENABLED); 622 623 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 624 set_reg_field_value(value, 0, 625 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 626 CLOCK_GATING_DISABLE); 627 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 628 629 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 630 audio->inst, value); 631 } 632 633 void dce_aud_az_disable(struct audio *audio) 634 { 635 uint32_t value; 636 DC_LOGGER_INIT(); 637 638 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 639 set_reg_field_value(value, 1, 640 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 641 CLOCK_GATING_DISABLE); 642 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 643 644 set_reg_field_value(value, 0, 645 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 646 AUDIO_ENABLED); 647 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 648 649 set_reg_field_value(value, 0, 650 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 651 CLOCK_GATING_DISABLE); 652 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 653 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 654 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 655 audio->inst, value); 656 } 657 658 void dce_aud_az_configure( 659 struct audio *audio, 660 enum signal_type signal, 661 const struct audio_crtc_info *crtc_info, 662 const struct audio_info *audio_info, 663 const struct audio_dp_link_info *dp_link_info) 664 { 665 struct dce_audio *aud = DCE_AUD(audio); 666 667 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 668 uint32_t value; 669 uint32_t field = 0; 670 enum audio_format_code audio_format_code; 671 uint32_t format_index; 672 uint32_t index; 673 bool is_ac3_supported = false; 674 union audio_sample_rates sample_rate; 675 uint32_t strlen = 0; 676 677 if (signal == SIGNAL_TYPE_VIRTUAL) 678 return; 679 680 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 681 set_reg_field_value(value, 1, 682 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 683 CLOCK_GATING_DISABLE); 684 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 685 686 /* Speaker Allocation */ 687 /* 688 uint32_t value; 689 uint32_t field = 0;*/ 690 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 691 692 set_reg_field_value(value, 693 speakers, 694 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 695 SPEAKER_ALLOCATION); 696 697 /* LFE_PLAYBACK_LEVEL = LFEPBL 698 * LFEPBL = 0 : Unknown or refer to other information 699 * LFEPBL = 1 : 0dB playback 700 * LFEPBL = 2 : +10dB playback 701 * LFE_BL = 3 : Reserved 702 */ 703 set_reg_field_value(value, 704 0, 705 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 706 LFE_PLAYBACK_LEVEL); 707 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 708 * why are we writing to it? DCE8 does not write this */ 709 710 711 set_reg_field_value(value, 712 0, 713 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 714 HDMI_CONNECTION); 715 716 set_reg_field_value(value, 717 0, 718 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 719 DP_CONNECTION); 720 721 field = get_reg_field_value(value, 722 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 723 EXTRA_CONNECTION_INFO); 724 725 field &= ~0x1; 726 727 set_reg_field_value(value, 728 field, 729 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 730 EXTRA_CONNECTION_INFO); 731 732 /* set audio for output signal */ 733 switch (signal) { 734 case SIGNAL_TYPE_HDMI_TYPE_A: 735 set_reg_field_value(value, 736 1, 737 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 738 HDMI_CONNECTION); 739 740 break; 741 742 case SIGNAL_TYPE_EDP: 743 case SIGNAL_TYPE_DISPLAY_PORT: 744 case SIGNAL_TYPE_DISPLAY_PORT_MST: 745 set_reg_field_value(value, 746 1, 747 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 748 DP_CONNECTION); 749 break; 750 default: 751 BREAK_TO_DEBUGGER(); 752 break; 753 } 754 755 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 756 757 /* ACP Data - Supports AI */ 758 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); 759 760 set_reg_field_value( 761 value, 762 audio_info->flags.info.SUPPORT_AI, 763 AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, 764 SUPPORTS_AI); 765 766 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); 767 768 /* Audio Descriptors */ 769 /* pass through all formats */ 770 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 771 format_index++) { 772 audio_format_code = 773 (AUDIO_FORMAT_CODE_FIRST + format_index); 774 775 /* those are unsupported, skip programming */ 776 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 777 audio_format_code == AUDIO_FORMAT_CODE_DST) 778 continue; 779 780 value = 0; 781 782 /* check if supported */ 783 if (is_audio_format_supported( 784 audio_info, audio_format_code, &index)) { 785 const struct audio_mode *audio_mode = 786 &audio_info->modes[index]; 787 union audio_sample_rates sample_rates = 788 audio_mode->sample_rates; 789 uint8_t byte2 = audio_mode->max_bit_rate; 790 uint8_t channel_count = audio_mode->channel_count; 791 792 /* adjust specific properties */ 793 switch (audio_format_code) { 794 case AUDIO_FORMAT_CODE_LINEARPCM: { 795 796 check_audio_bandwidth( 797 crtc_info, 798 dp_link_info, 799 channel_count, 800 signal, 801 &sample_rates); 802 803 byte2 = audio_mode->sample_size; 804 805 set_reg_field_value(value, 806 sample_rates.all, 807 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 808 SUPPORTED_FREQUENCIES_STEREO); 809 } 810 break; 811 case AUDIO_FORMAT_CODE_AC3: 812 is_ac3_supported = true; 813 break; 814 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 815 case AUDIO_FORMAT_CODE_DTS_HD: 816 case AUDIO_FORMAT_CODE_MAT_MLP: 817 case AUDIO_FORMAT_CODE_DST: 818 case AUDIO_FORMAT_CODE_WMAPRO: 819 byte2 = audio_mode->vendor_specific; 820 break; 821 default: 822 break; 823 } 824 825 /* fill audio format data */ 826 set_reg_field_value(value, 827 channel_count - 1, 828 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 829 MAX_CHANNELS); 830 831 set_reg_field_value(value, 832 sample_rates.all, 833 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 834 SUPPORTED_FREQUENCIES); 835 836 set_reg_field_value(value, 837 byte2, 838 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 839 DESCRIPTOR_BYTE_2); 840 } /* if */ 841 842 AZ_REG_WRITE( 843 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 844 value); 845 } /* for */ 846 847 if (is_ac3_supported) 848 /* todo: this reg global. why program global register? */ 849 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 850 0x05); 851 852 /* check for 192khz/8-Ch support for HBR requirements */ 853 sample_rate.all = 0; 854 sample_rate.rate.RATE_192 = 1; 855 856 check_audio_bandwidth( 857 crtc_info, 858 dp_link_info, 859 8, 860 signal, 861 &sample_rate); 862 863 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 864 865 /* Audio and Video Lipsync */ 866 set_video_latency(audio, audio_info->video_latency); 867 set_audio_latency(audio, audio_info->audio_latency); 868 869 value = 0; 870 set_reg_field_value(value, audio_info->manufacture_id, 871 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 872 MANUFACTURER_ID); 873 874 set_reg_field_value(value, audio_info->product_id, 875 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 876 PRODUCT_ID); 877 878 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 879 value); 880 881 value = 0; 882 883 /*get display name string length */ 884 while (audio_info->display_name[strlen++] != '\0') { 885 if (strlen >= 886 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 887 break; 888 } 889 set_reg_field_value(value, strlen, 890 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 891 SINK_DESCRIPTION_LEN); 892 893 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 894 value); 895 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 896 audio->inst, value, audio_info->display_name); 897 898 /* 899 *write the port ID: 900 *PORT_ID0 = display index 901 *PORT_ID1 = 16bit BDF 902 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 903 */ 904 905 value = 0; 906 907 set_reg_field_value(value, audio_info->port_id[0], 908 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 909 PORT_ID0); 910 911 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 912 913 value = 0; 914 set_reg_field_value(value, audio_info->port_id[1], 915 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 916 PORT_ID1); 917 918 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 919 920 /*write the 18 char monitor string */ 921 922 value = 0; 923 set_reg_field_value(value, audio_info->display_name[0], 924 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 925 DESCRIPTION0); 926 927 set_reg_field_value(value, audio_info->display_name[1], 928 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 929 DESCRIPTION1); 930 931 set_reg_field_value(value, audio_info->display_name[2], 932 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 933 DESCRIPTION2); 934 935 set_reg_field_value(value, audio_info->display_name[3], 936 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 937 DESCRIPTION3); 938 939 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 940 941 value = 0; 942 set_reg_field_value(value, audio_info->display_name[4], 943 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 944 DESCRIPTION4); 945 946 set_reg_field_value(value, audio_info->display_name[5], 947 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 948 DESCRIPTION5); 949 950 set_reg_field_value(value, audio_info->display_name[6], 951 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 952 DESCRIPTION6); 953 954 set_reg_field_value(value, audio_info->display_name[7], 955 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 956 DESCRIPTION7); 957 958 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 959 960 value = 0; 961 set_reg_field_value(value, audio_info->display_name[8], 962 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 963 DESCRIPTION8); 964 965 set_reg_field_value(value, audio_info->display_name[9], 966 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 967 DESCRIPTION9); 968 969 set_reg_field_value(value, audio_info->display_name[10], 970 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 971 DESCRIPTION10); 972 973 set_reg_field_value(value, audio_info->display_name[11], 974 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 975 DESCRIPTION11); 976 977 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 978 979 value = 0; 980 set_reg_field_value(value, audio_info->display_name[12], 981 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 982 DESCRIPTION12); 983 984 set_reg_field_value(value, audio_info->display_name[13], 985 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 986 DESCRIPTION13); 987 988 set_reg_field_value(value, audio_info->display_name[14], 989 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 990 DESCRIPTION14); 991 992 set_reg_field_value(value, audio_info->display_name[15], 993 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 994 DESCRIPTION15); 995 996 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 997 998 value = 0; 999 set_reg_field_value(value, audio_info->display_name[16], 1000 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1001 DESCRIPTION16); 1002 1003 set_reg_field_value(value, audio_info->display_name[17], 1004 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1005 DESCRIPTION17); 1006 1007 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 1008 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1009 set_reg_field_value(value, 0, 1010 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1011 CLOCK_GATING_DISABLE); 1012 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1013 } 1014 1015 /* 1016 * todo: wall clk related functionality probably belong to clock_src. 1017 */ 1018 1019 /* search pixel clock value for Azalia HDMI Audio */ 1020 static void get_azalia_clock_info_hdmi( 1021 uint32_t crtc_pixel_clock_100hz, 1022 uint32_t actual_pixel_clock_100Hz, 1023 struct azalia_clock_info *azalia_clock_info) 1024 { 1025 /* audio_dto_phase= 24 * 10,000; 1026 * 24MHz in [100Hz] units */ 1027 azalia_clock_info->audio_dto_phase = 1028 24 * 10000; 1029 1030 /* audio_dto_module = PCLKFrequency * 10,000; 1031 * [khz] -> [100Hz] */ 1032 azalia_clock_info->audio_dto_module = 1033 actual_pixel_clock_100Hz; 1034 } 1035 1036 static void get_azalia_clock_info_dp( 1037 uint32_t requested_pixel_clock_100Hz, 1038 const struct audio_pll_info *pll_info, 1039 struct azalia_clock_info *azalia_clock_info) 1040 { 1041 /* Reported dpDtoSourceClockInkhz value for 1042 * DCE8 already adjusted for SS, do not need any 1043 * adjustment here anymore 1044 */ 1045 1046 /*audio_dto_phase = 24 * 10,000; 1047 * 24MHz in [100Hz] units */ 1048 azalia_clock_info->audio_dto_phase = 24 * 10000; 1049 1050 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 1051 * [khz] ->[100Hz] */ 1052 azalia_clock_info->audio_dto_module = 1053 pll_info->audio_dto_source_clock_in_khz * 10; 1054 } 1055 1056 void dce_aud_wall_dto_setup( 1057 struct audio *audio, 1058 enum signal_type signal, 1059 const struct audio_crtc_info *crtc_info, 1060 const struct audio_pll_info *pll_info) 1061 { 1062 struct dce_audio *aud = DCE_AUD(audio); 1063 1064 struct azalia_clock_info clock_info = { 0 }; 1065 1066 if (dc_is_hdmi_tmds_signal(signal)) { 1067 uint32_t src_sel; 1068 1069 /*DTO0 Programming goal: 1070 -generate 24MHz, 128*Fs from 24MHz 1071 -use DTO0 when an active HDMI port is connected 1072 (optionally a DP is connected) */ 1073 1074 /* calculate DTO settings */ 1075 get_azalia_clock_info_hdmi( 1076 crtc_info->requested_pixel_clock_100Hz, 1077 crtc_info->calculated_pixel_clock_100Hz, 1078 &clock_info); 1079 1080 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 1081 "calculated_pixel_clock_100Hz =%d\n"\ 1082 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 1083 crtc_info->requested_pixel_clock_100Hz,\ 1084 crtc_info->calculated_pixel_clock_100Hz,\ 1085 clock_info.audio_dto_module,\ 1086 clock_info.audio_dto_phase); 1087 1088 /* On TN/SI, Program DTO source select and DTO select before 1089 programming DTO modulo and DTO phase. These bits must be 1090 programmed first, otherwise there will be no HDMI audio at boot 1091 up. This is a HW sequence change (different from old ASICs). 1092 Caution when changing this programming sequence. 1093 1094 HDMI enabled, using DTO0 1095 program master CRTC for DTO0 */ 1096 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 1097 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 1098 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 1099 DCCG_AUDIO_DTO_SEL, 0); 1100 1101 /* module */ 1102 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 1103 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 1104 1105 /* phase */ 1106 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 1107 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 1108 } else { 1109 /*DTO1 Programming goal: 1110 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 1111 -default is to used DTO1, and switch to DTO0 when an audio 1112 master HDMI port is connected 1113 -use as default for DP 1114 1115 calculate DTO settings */ 1116 get_azalia_clock_info_dp( 1117 crtc_info->requested_pixel_clock_100Hz, 1118 pll_info, 1119 &clock_info); 1120 1121 /* Program DTO select before programming DTO modulo and DTO 1122 phase. default to use DTO1 */ 1123 1124 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1125 DCCG_AUDIO_DTO_SEL, 1); 1126 1127 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 1128 * Select 512fs for DP TODO: web register definition 1129 * does not match register header file 1130 * DCE11 version it's commented out while DCE8 it's set to 1 1131 */ 1132 1133 /* module */ 1134 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 1135 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 1136 1137 /* phase */ 1138 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 1139 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 1140 1141 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1142 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 1143 1144 } 1145 } 1146 1147 #if defined(CONFIG_DRM_AMD_DC_SI) 1148 static void dce60_aud_wall_dto_setup( 1149 struct audio *audio, 1150 enum signal_type signal, 1151 const struct audio_crtc_info *crtc_info, 1152 const struct audio_pll_info *pll_info) 1153 { 1154 struct dce_audio *aud = DCE_AUD(audio); 1155 1156 struct azalia_clock_info clock_info = { 0 }; 1157 1158 if (dc_is_hdmi_signal(signal)) { 1159 uint32_t src_sel; 1160 1161 /*DTO0 Programming goal: 1162 -generate 24MHz, 128*Fs from 24MHz 1163 -use DTO0 when an active HDMI port is connected 1164 (optionally a DP is connected) */ 1165 1166 /* calculate DTO settings */ 1167 get_azalia_clock_info_hdmi( 1168 crtc_info->requested_pixel_clock_100Hz, 1169 crtc_info->calculated_pixel_clock_100Hz, 1170 &clock_info); 1171 1172 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 1173 "calculated_pixel_clock_100Hz =%d\n"\ 1174 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 1175 crtc_info->requested_pixel_clock_100Hz,\ 1176 crtc_info->calculated_pixel_clock_100Hz,\ 1177 clock_info.audio_dto_module,\ 1178 clock_info.audio_dto_phase); 1179 1180 /* On TN/SI, Program DTO source select and DTO select before 1181 programming DTO modulo and DTO phase. These bits must be 1182 programmed first, otherwise there will be no HDMI audio at boot 1183 up. This is a HW sequence change (different from old ASICs). 1184 Caution when changing this programming sequence. 1185 1186 HDMI enabled, using DTO0 1187 program master CRTC for DTO0 */ 1188 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 1189 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 1190 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 1191 DCCG_AUDIO_DTO_SEL, 0); 1192 1193 /* module */ 1194 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 1195 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 1196 1197 /* phase */ 1198 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 1199 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 1200 } else { 1201 /*DTO1 Programming goal: 1202 -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) 1203 -default is to used DTO1, and switch to DTO0 when an audio 1204 master HDMI port is connected 1205 -use as default for DP 1206 1207 calculate DTO settings */ 1208 get_azalia_clock_info_dp( 1209 crtc_info->requested_pixel_clock_100Hz, 1210 pll_info, 1211 &clock_info); 1212 1213 /* Program DTO select before programming DTO modulo and DTO 1214 phase. default to use DTO1 */ 1215 1216 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1217 DCCG_AUDIO_DTO_SEL, 1); 1218 1219 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 1220 * Cannot select 512fs for DP 1221 * 1222 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask 1223 */ 1224 1225 /* module */ 1226 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 1227 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 1228 1229 /* phase */ 1230 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 1231 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 1232 1233 /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ 1234 1235 } 1236 } 1237 #endif 1238 1239 static bool dce_aud_endpoint_valid(struct audio *audio) 1240 { 1241 uint32_t value; 1242 uint32_t port_connectivity; 1243 1244 value = AZ_REG_READ( 1245 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1246 1247 port_connectivity = get_reg_field_value(value, 1248 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1249 PORT_CONNECTIVITY); 1250 1251 return !(port_connectivity == 1); 1252 } 1253 1254 /* initialize HW state */ 1255 void dce_aud_hw_init( 1256 struct audio *audio) 1257 { 1258 uint32_t value; 1259 struct dce_audio *aud = DCE_AUD(audio); 1260 1261 /* we only need to program the following registers once, so we only do 1262 it for the inst 0*/ 1263 if (audio->inst != 0) 1264 return; 1265 1266 /* Suport R5 - 32khz 1267 * Suport R6 - 44.1khz 1268 * Suport R7 - 48khz 1269 */ 1270 /*disable clock gating before write to endpoint register*/ 1271 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1272 set_reg_field_value(value, 1, 1273 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1274 CLOCK_GATING_DISABLE); 1275 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1276 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 1277 AUDIO_RATE_CAPABILITIES, 0x70); 1278 1279 /*Keep alive bit to verify HW block in BU. */ 1280 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 1281 CLKSTOP, 1, 1282 EPSS, 1); 1283 set_reg_field_value(value, 0, 1284 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1285 CLOCK_GATING_DISABLE); 1286 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1287 } 1288 1289 static const struct audio_funcs funcs = { 1290 .endpoint_valid = dce_aud_endpoint_valid, 1291 .hw_init = dce_aud_hw_init, 1292 .wall_dto_setup = dce_aud_wall_dto_setup, 1293 .az_enable = dce_aud_az_enable, 1294 .az_disable = dce_aud_az_disable, 1295 .az_configure = dce_aud_az_configure, 1296 .destroy = dce_aud_destroy, 1297 }; 1298 1299 #if defined(CONFIG_DRM_AMD_DC_SI) 1300 static const struct audio_funcs dce60_funcs = { 1301 .endpoint_valid = dce_aud_endpoint_valid, 1302 .hw_init = dce_aud_hw_init, 1303 .wall_dto_setup = dce60_aud_wall_dto_setup, 1304 .az_enable = dce_aud_az_enable, 1305 .az_disable = dce_aud_az_disable, 1306 .az_configure = dce_aud_az_configure, 1307 .destroy = dce_aud_destroy, 1308 }; 1309 #endif 1310 1311 void dce_aud_destroy(struct audio **audio) 1312 { 1313 struct dce_audio *aud = DCE_AUD(*audio); 1314 1315 kfree(aud); 1316 *audio = NULL; 1317 } 1318 1319 struct audio *dce_audio_create( 1320 struct dc_context *ctx, 1321 unsigned int inst, 1322 const struct dce_audio_registers *reg, 1323 const struct dce_audio_shift *shifts, 1324 const struct dce_audio_mask *masks 1325 ) 1326 { 1327 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1328 1329 if (audio == NULL) { 1330 ASSERT_CRITICAL(audio); 1331 return NULL; 1332 } 1333 1334 audio->base.ctx = ctx; 1335 audio->base.inst = inst; 1336 audio->base.funcs = &funcs; 1337 1338 audio->regs = reg; 1339 audio->shifts = shifts; 1340 audio->masks = masks; 1341 return &audio->base; 1342 } 1343 1344 #if defined(CONFIG_DRM_AMD_DC_SI) 1345 struct audio *dce60_audio_create( 1346 struct dc_context *ctx, 1347 unsigned int inst, 1348 const struct dce_audio_registers *reg, 1349 const struct dce_audio_shift *shifts, 1350 const struct dce_audio_mask *masks 1351 ) 1352 { 1353 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 1354 1355 if (audio == NULL) { 1356 ASSERT_CRITICAL(audio); 1357 return NULL; 1358 } 1359 1360 audio->base.ctx = ctx; 1361 audio->base.inst = inst; 1362 audio->base.funcs = &dce60_funcs; 1363 1364 audio->regs = reg; 1365 audio->shifts = shifts; 1366 audio->masks = masks; 1367 return &audio->base; 1368 } 1369 #endif 1370