1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 37 #define DC_LOGGER_INIT() 38 39 #define REG(reg)\ 40 (aud->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 aud->shifts->field_name, aud->masks->field_name 45 46 #define IX_REG(reg)\ 47 ix ## reg 48 49 #define AZ_REG_READ(reg_name) \ 50 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 51 52 #define AZ_REG_WRITE(reg_name, value) \ 53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 54 55 static void write_indirect_azalia_reg(struct audio *audio, 56 uint32_t reg_index, 57 uint32_t reg_data) 58 { 59 struct dce_audio *aud = DCE_AUD(audio); 60 61 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 63 AZALIA_ENDPOINT_REG_INDEX, reg_index); 64 65 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 67 AZALIA_ENDPOINT_REG_DATA, reg_data); 68 } 69 70 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 71 { 72 struct dce_audio *aud = DCE_AUD(audio); 73 74 uint32_t value = 0; 75 76 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 77 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 78 AZALIA_ENDPOINT_REG_INDEX, reg_index); 79 80 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 82 83 return value; 84 } 85 86 static bool is_audio_format_supported( 87 const struct audio_info *audio_info, 88 enum audio_format_code audio_format_code, 89 uint32_t *format_index) 90 { 91 uint32_t index; 92 uint32_t max_channe_index = 0; 93 bool found = false; 94 95 if (audio_info == NULL) 96 return found; 97 98 /* pass through whole array */ 99 for (index = 0; index < audio_info->mode_count; index++) { 100 if (audio_info->modes[index].format_code == audio_format_code) { 101 if (found) { 102 /* format has multiply entries, choose one with 103 * highst number of channels */ 104 if (audio_info->modes[index].channel_count > 105 audio_info->modes[max_channe_index].channel_count) { 106 max_channe_index = index; 107 } 108 } else { 109 /* format found, save it's index */ 110 found = true; 111 max_channe_index = index; 112 } 113 } 114 } 115 116 /* return index */ 117 if (found && format_index != NULL) 118 *format_index = max_channe_index; 119 120 return found; 121 } 122 123 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 124 static void check_audio_bandwidth_hdmi( 125 const struct audio_crtc_info *crtc_info, 126 uint32_t channel_count, 127 union audio_sample_rates *sample_rates) 128 { 129 uint32_t samples; 130 uint32_t h_blank; 131 bool limit_freq_to_48_khz = false; 132 bool limit_freq_to_88_2_khz = false; 133 bool limit_freq_to_96_khz = false; 134 bool limit_freq_to_174_4_khz = false; 135 if (!crtc_info) 136 return; 137 138 /* For two channels supported return whatever sink support,unmodified*/ 139 if (channel_count > 2) { 140 141 /* Based on HDMI spec 1.3 Table 7.5 */ 142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 143 (crtc_info->v_active <= 576) && 144 !(crtc_info->interlaced) && 145 !(crtc_info->pixel_repetition == 2 || 146 crtc_info->pixel_repetition == 4)) { 147 limit_freq_to_48_khz = true; 148 149 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 150 (crtc_info->v_active <= 576) && 151 (crtc_info->interlaced) && 152 (crtc_info->pixel_repetition == 2)) { 153 limit_freq_to_88_2_khz = true; 154 155 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 156 (crtc_info->v_active <= 576) && 157 !(crtc_info->interlaced)) { 158 limit_freq_to_174_4_khz = true; 159 } 160 } 161 162 /* Also do some calculation for the available Audio Bandwidth for the 163 * 8 ch (i.e. for the Layout 1 => ch > 2) 164 */ 165 h_blank = crtc_info->h_total - crtc_info->h_active; 166 167 if (crtc_info->pixel_repetition) 168 h_blank *= crtc_info->pixel_repetition; 169 170 /*based on HDMI spec 1.3 Table 7.5 */ 171 h_blank -= 58; 172 /*for Control Period */ 173 h_blank -= 16; 174 175 samples = h_blank * 10; 176 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 177 * of Audio samples per line multiplied by 10 - Layout 1) 178 */ 179 samples /= 32; 180 samples *= crtc_info->v_active; 181 /*Number of samples multiplied by 10, per second */ 182 samples *= crtc_info->refresh_rate; 183 /*Number of Audio samples per second */ 184 samples /= 10; 185 186 /* @todo do it after deep color is implemented 187 * 8xx - deep color bandwidth scaling 188 * Extra bandwidth is avaliable in deep color b/c link runs faster than 189 * pixel rate. This has the effect of allowing more tmds characters to 190 * be transmitted during blank 191 */ 192 193 switch (crtc_info->color_depth) { 194 case COLOR_DEPTH_888: 195 samples *= 4; 196 break; 197 case COLOR_DEPTH_101010: 198 samples *= 5; 199 break; 200 case COLOR_DEPTH_121212: 201 samples *= 6; 202 break; 203 default: 204 samples *= 4; 205 break; 206 } 207 208 samples /= 4; 209 210 /*check limitation*/ 211 if (samples < 88200) 212 limit_freq_to_48_khz = true; 213 else if (samples < 96000) 214 limit_freq_to_88_2_khz = true; 215 else if (samples < 176400) 216 limit_freq_to_96_khz = true; 217 else if (samples < 192000) 218 limit_freq_to_174_4_khz = true; 219 220 if (sample_rates != NULL) { 221 /* limit frequencies */ 222 if (limit_freq_to_174_4_khz) 223 sample_rates->rate.RATE_192 = 0; 224 225 if (limit_freq_to_96_khz) { 226 sample_rates->rate.RATE_192 = 0; 227 sample_rates->rate.RATE_176_4 = 0; 228 } 229 if (limit_freq_to_88_2_khz) { 230 sample_rates->rate.RATE_192 = 0; 231 sample_rates->rate.RATE_176_4 = 0; 232 sample_rates->rate.RATE_96 = 0; 233 } 234 if (limit_freq_to_48_khz) { 235 sample_rates->rate.RATE_192 = 0; 236 sample_rates->rate.RATE_176_4 = 0; 237 sample_rates->rate.RATE_96 = 0; 238 sample_rates->rate.RATE_88_2 = 0; 239 } 240 } 241 } 242 static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate) 243 { 244 switch (link_rate) { 245 case LINK_RATE_LOW: 246 return dc_fixpt_from_int(162); /* 162 MHz */ 247 case LINK_RATE_HIGH: 248 return dc_fixpt_from_int(270); /* 270 MHz */ 249 case LINK_RATE_HIGH2: 250 return dc_fixpt_from_int(540); /* 540 MHz */ 251 case LINK_RATE_HIGH3: 252 return dc_fixpt_from_int(810); /* 810 MHz */ 253 case LINK_RATE_UHBR10: 254 return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */ 255 case LINK_RATE_UHBR13_5: 256 return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */ 257 case LINK_RATE_UHBR20: 258 return dc_fixpt_from_int(625); /* 625 MHz */ 259 default: 260 /* Unexpected case, this requires debug if encountered. */ 261 ASSERT(0); 262 return dc_fixpt_from_int(0); 263 } 264 } 265 266 struct dp_audio_layout_config { 267 uint8_t layouts_per_sample_denom; 268 uint8_t symbols_per_layout; 269 uint8_t max_layouts_per_audio_sdp; 270 }; 271 272 static void get_audio_layout_config( 273 uint32_t channel_count, 274 enum dp_link_encoding encoding, 275 struct dp_audio_layout_config *output) 276 { 277 /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, 278 * with each layout being the same size (8ch layout). 279 */ 280 if (encoding == DP_8b_10b_ENCODING) { 281 if (channel_count == 2) { 282 output->layouts_per_sample_denom = 4; 283 output->symbols_per_layout = 40; 284 output->max_layouts_per_audio_sdp = 1; 285 } else if (channel_count == 8 || channel_count == 6) { 286 output->layouts_per_sample_denom = 1; 287 output->symbols_per_layout = 40; 288 output->max_layouts_per_audio_sdp = 1; 289 } 290 } else if (encoding == DP_128b_132b_ENCODING) { 291 if (channel_count == 2) { 292 output->layouts_per_sample_denom = 4; 293 output->symbols_per_layout = 10; 294 output->max_layouts_per_audio_sdp = 1; 295 } else if (channel_count == 8 || channel_count == 6) { 296 output->layouts_per_sample_denom = 1; 297 output->symbols_per_layout = 10; 298 output->max_layouts_per_audio_sdp = 1; 299 } 300 } 301 } 302 303 static uint32_t get_av_stream_map_lane_count( 304 enum dp_link_encoding encoding, 305 enum dc_lane_count lane_count, 306 bool is_mst) 307 { 308 uint32_t av_stream_map_lane_count = 0; 309 310 if (encoding == DP_8b_10b_ENCODING) { 311 if (!is_mst) 312 av_stream_map_lane_count = lane_count; 313 else 314 av_stream_map_lane_count = 4; 315 } else if (encoding == DP_128b_132b_ENCODING) { 316 av_stream_map_lane_count = 4; 317 } 318 319 ASSERT(av_stream_map_lane_count != 0); 320 321 return av_stream_map_lane_count; 322 } 323 324 static uint32_t get_audio_sdp_overhead( 325 enum dp_link_encoding encoding, 326 enum dc_lane_count lane_count, 327 bool is_mst) 328 { 329 uint32_t audio_sdp_overhead = 0; 330 331 if (encoding == DP_8b_10b_ENCODING) { 332 if (is_mst) 333 audio_sdp_overhead = 16; /* 4 * 2 + 8 */ 334 else 335 audio_sdp_overhead = lane_count * 2 + 8; 336 } else if (encoding == DP_128b_132b_ENCODING) { 337 audio_sdp_overhead = 10; /* 4 x 2.5 */ 338 } 339 340 ASSERT(audio_sdp_overhead != 0); 341 342 return audio_sdp_overhead; 343 } 344 345 static uint32_t calculate_required_audio_bw_in_symbols( 346 const struct audio_crtc_info *crtc_info, 347 const struct dp_audio_layout_config *layout_config, 348 uint32_t channel_count, 349 uint32_t sample_rate_hz, 350 uint32_t av_stream_map_lane_count, 351 uint32_t audio_sdp_overhead) 352 { 353 (void)channel_count; 354 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ 355 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); 356 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( 357 crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10); 358 struct fixed31_32 samples_per_line; 359 struct fixed31_32 layouts_per_line; 360 struct fixed31_32 symbols_per_sdp_max_layout; 361 struct fixed31_32 remainder; 362 uint32_t num_sdp_with_max_layouts; 363 uint32_t required_symbols_per_hblank; 364 365 samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000); 366 samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz); 367 layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom); 368 369 num_sdp_with_max_layouts = dc_fixpt_floor( 370 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp)); 371 symbols_per_sdp_max_layout = dc_fixpt_from_int( 372 layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout); 373 symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead); 374 symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin); 375 required_symbols_per_hblank = num_sdp_with_max_layouts; 376 required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) / 377 av_stream_map_lane_count) * av_stream_map_lane_count; 378 379 if (num_sdp_with_max_layouts != dc_fixpt_ceil( 380 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) { 381 remainder = dc_fixpt_sub_int(layouts_per_line, 382 num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp); 383 remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout); 384 remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead); 385 remainder = dc_fixpt_mul(remainder, audio_sdp_margin); 386 required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) / 387 av_stream_map_lane_count) * av_stream_map_lane_count; 388 } 389 390 return required_symbols_per_hblank; 391 } 392 393 /* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. 394 */ 395 static uint32_t calculate_available_hblank_bw_in_symbols( 396 const struct audio_crtc_info *crtc_info, 397 const struct audio_dp_link_info *dp_link_info) 398 { 399 uint64_t hblank = crtc_info->h_total - crtc_info->h_active; 400 struct fixed31_32 hblank_time_msec = 401 dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz); 402 struct fixed31_32 lsclkfreq_mhz = 403 get_link_symbol_clk_freq_mhz(dp_link_info->link_rate); 404 struct fixed31_32 average_stream_sym_bw_frac; 405 struct fixed31_32 peak_stream_bw_kbps; 406 struct fixed31_32 bits_per_pixel; 407 struct fixed31_32 link_bw_kbps; 408 struct fixed31_32 available_stream_sym_count; 409 uint32_t available_hblank_bw = 0; /* in stream symbols */ 410 411 if (crtc_info->dsc_bits_per_pixel) { 412 bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16); 413 } else { 414 switch (crtc_info->color_depth) { 415 case COLOR_DEPTH_666: 416 bits_per_pixel = dc_fixpt_from_int(6); 417 break; 418 case COLOR_DEPTH_888: 419 bits_per_pixel = dc_fixpt_from_int(8); 420 break; 421 case COLOR_DEPTH_101010: 422 bits_per_pixel = dc_fixpt_from_int(10); 423 break; 424 case COLOR_DEPTH_121212: 425 bits_per_pixel = dc_fixpt_from_int(12); 426 break; 427 default: 428 /* Default to commonly supported color depth. */ 429 bits_per_pixel = dc_fixpt_from_int(8); 430 break; 431 } 432 433 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3); 434 435 if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 436 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3); 437 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2); 438 } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) { 439 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2); 440 } 441 } 442 443 /* Use simple stream BW calculation because mainlink overhead is 444 * accounted for separately in the audio BW calculations. 445 */ 446 peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10); 447 peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel); 448 link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps); 449 average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps); 450 451 available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000); 452 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz); 453 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac); 454 available_hblank_bw = dc_fixpt_floor(available_stream_sym_count); 455 available_hblank_bw *= dp_link_info->lane_count; 456 available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */ 457 458 if (available_hblank_bw < dp_link_info->hblank_min_symbol_width) 459 /* Each symbol takes 4 frames */ 460 available_hblank_bw = 4 * dp_link_info->hblank_min_symbol_width; 461 462 if (available_hblank_bw < 12) 463 available_hblank_bw = 0; 464 else 465 available_hblank_bw -= 12; /* Main link overhead */ 466 467 return available_hblank_bw; 468 } 469 470 static void check_audio_bandwidth_dp( 471 const struct audio_crtc_info *crtc_info, 472 const struct audio_dp_link_info *dp_link_info, 473 uint32_t channel_count, 474 union audio_sample_rates *sample_rates) 475 { 476 struct dp_audio_layout_config layout_config = {0}; 477 uint32_t available_hblank_bw; 478 uint32_t av_stream_map_lane_count; 479 uint32_t audio_sdp_overhead; 480 481 /* TODO: Add validation for SST 8b/10 case */ 482 if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING) 483 return; 484 485 available_hblank_bw = calculate_available_hblank_bw_in_symbols( 486 crtc_info, dp_link_info); 487 av_stream_map_lane_count = get_av_stream_map_lane_count( 488 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 489 audio_sdp_overhead = get_audio_sdp_overhead( 490 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 491 get_audio_layout_config( 492 channel_count, dp_link_info->encoding, &layout_config); 493 494 if (layout_config.max_layouts_per_audio_sdp == 0 || 495 layout_config.symbols_per_layout == 0 || 496 layout_config.layouts_per_sample_denom == 0) { 497 return; 498 } 499 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 500 crtc_info, &layout_config, channel_count, 192000, 501 av_stream_map_lane_count, audio_sdp_overhead)) 502 sample_rates->rate.RATE_192 = 0; 503 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 504 crtc_info, &layout_config, channel_count, 176400, 505 av_stream_map_lane_count, audio_sdp_overhead)) 506 sample_rates->rate.RATE_176_4 = 0; 507 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 508 crtc_info, &layout_config, channel_count, 96000, 509 av_stream_map_lane_count, audio_sdp_overhead)) 510 sample_rates->rate.RATE_96 = 0; 511 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 512 crtc_info, &layout_config, channel_count, 88200, 513 av_stream_map_lane_count, audio_sdp_overhead)) 514 sample_rates->rate.RATE_88_2 = 0; 515 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 516 crtc_info, &layout_config, channel_count, 48000, 517 av_stream_map_lane_count, audio_sdp_overhead)) 518 sample_rates->rate.RATE_48 = 0; 519 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 520 crtc_info, &layout_config, channel_count, 44100, 521 av_stream_map_lane_count, audio_sdp_overhead)) 522 sample_rates->rate.RATE_44_1 = 0; 523 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 524 crtc_info, &layout_config, channel_count, 32000, 525 av_stream_map_lane_count, audio_sdp_overhead)) 526 sample_rates->rate.RATE_32 = 0; 527 } 528 529 static void check_audio_bandwidth( 530 const struct audio_crtc_info *crtc_info, 531 const struct audio_dp_link_info *dp_link_info, 532 uint32_t channel_count, 533 enum signal_type signal, 534 union audio_sample_rates *sample_rates) 535 { 536 switch (signal) { 537 case SIGNAL_TYPE_HDMI_TYPE_A: 538 check_audio_bandwidth_hdmi( 539 crtc_info, channel_count, sample_rates); 540 break; 541 case SIGNAL_TYPE_EDP: 542 case SIGNAL_TYPE_DISPLAY_PORT: 543 case SIGNAL_TYPE_DISPLAY_PORT_MST: 544 check_audio_bandwidth_dp( 545 crtc_info, dp_link_info, channel_count, sample_rates); 546 break; 547 default: 548 break; 549 } 550 } 551 552 /* expose/not expose HBR capability to Audio driver */ 553 static void set_high_bit_rate_capable( 554 struct audio *audio, 555 bool capable) 556 { 557 uint32_t value = 0; 558 559 /* set high bit rate audio capable*/ 560 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 561 562 set_reg_field_value(value, capable, 563 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 564 HBR_CAPABLE); 565 566 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 567 } 568 569 /* set video latency in ms/2+1 */ 570 static void set_video_latency( 571 struct audio *audio, 572 int latency_in_ms) 573 { 574 uint32_t value = 0; 575 576 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 577 return; 578 579 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 580 581 set_reg_field_value(value, latency_in_ms, 582 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 583 VIDEO_LIPSYNC); 584 585 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 586 value); 587 } 588 589 /* set audio latency in ms/2+1 */ 590 static void set_audio_latency( 591 struct audio *audio, 592 int latency_in_ms) 593 { 594 uint32_t value = 0; 595 596 if (latency_in_ms < 0) 597 latency_in_ms = 0; 598 599 if (latency_in_ms > 255) 600 latency_in_ms = 255; 601 602 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 603 604 set_reg_field_value(value, latency_in_ms, 605 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 606 AUDIO_LIPSYNC); 607 608 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 609 value); 610 } 611 612 void dce_aud_az_enable(struct audio *audio) 613 { 614 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 615 DC_LOGGER_INIT(); 616 617 set_reg_field_value(value, 1, 618 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 619 CLOCK_GATING_DISABLE); 620 set_reg_field_value(value, 1, 621 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 622 AUDIO_ENABLED); 623 624 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 625 set_reg_field_value(value, 0, 626 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 627 CLOCK_GATING_DISABLE); 628 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 629 630 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 631 audio->inst, value); 632 } 633 634 void dce_aud_az_disable_hbr_audio(struct audio *audio) 635 { 636 set_high_bit_rate_capable(audio, false); 637 } 638 639 void dce_aud_az_disable(struct audio *audio) 640 { 641 uint32_t value; 642 DC_LOGGER_INIT(); 643 644 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 645 set_reg_field_value(value, 1, 646 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 647 CLOCK_GATING_DISABLE); 648 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 649 650 set_reg_field_value(value, 0, 651 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 652 AUDIO_ENABLED); 653 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 654 655 set_reg_field_value(value, 0, 656 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 657 CLOCK_GATING_DISABLE); 658 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 659 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 660 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 661 audio->inst, value); 662 } 663 664 void dce_aud_az_configure( 665 struct audio *audio, 666 enum signal_type signal, 667 const struct audio_crtc_info *crtc_info, 668 const struct audio_info *audio_info, 669 const struct audio_dp_link_info *dp_link_info) 670 { 671 struct dce_audio *aud = DCE_AUD(audio); 672 673 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 674 uint32_t value; 675 uint32_t field = 0; 676 enum audio_format_code audio_format_code; 677 uint32_t format_index; 678 uint32_t index; 679 bool is_ac3_supported = false; 680 union audio_sample_rates sample_rate; 681 uint32_t strlen = 0; 682 683 if (signal == SIGNAL_TYPE_VIRTUAL) 684 return; 685 686 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 687 set_reg_field_value(value, 1, 688 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 689 CLOCK_GATING_DISABLE); 690 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 691 692 /* Speaker Allocation */ 693 /* 694 uint32_t value; 695 uint32_t field = 0;*/ 696 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 697 698 set_reg_field_value(value, 699 speakers, 700 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 701 SPEAKER_ALLOCATION); 702 703 /* LFE_PLAYBACK_LEVEL = LFEPBL 704 * LFEPBL = 0 : Unknown or refer to other information 705 * LFEPBL = 1 : 0dB playback 706 * LFEPBL = 2 : +10dB playback 707 * LFE_BL = 3 : Reserved 708 */ 709 set_reg_field_value(value, 710 0, 711 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 712 LFE_PLAYBACK_LEVEL); 713 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 714 * why are we writing to it? DCE8 does not write this */ 715 716 717 set_reg_field_value(value, 718 0, 719 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 720 HDMI_CONNECTION); 721 722 set_reg_field_value(value, 723 0, 724 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 725 DP_CONNECTION); 726 727 field = get_reg_field_value(value, 728 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 729 EXTRA_CONNECTION_INFO); 730 731 field &= ~0x1; 732 733 set_reg_field_value(value, 734 field, 735 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 736 EXTRA_CONNECTION_INFO); 737 738 /* set audio for output signal */ 739 switch (signal) { 740 case SIGNAL_TYPE_HDMI_TYPE_A: 741 set_reg_field_value(value, 742 1, 743 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 744 HDMI_CONNECTION); 745 746 break; 747 748 case SIGNAL_TYPE_EDP: 749 case SIGNAL_TYPE_DISPLAY_PORT: 750 case SIGNAL_TYPE_DISPLAY_PORT_MST: 751 set_reg_field_value(value, 752 1, 753 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 754 DP_CONNECTION); 755 break; 756 default: 757 BREAK_TO_DEBUGGER(); 758 break; 759 } 760 761 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 762 763 /* ACP Data - Supports AI */ 764 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); 765 766 set_reg_field_value( 767 value, 768 audio_info->flags.info.SUPPORT_AI, 769 AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, 770 SUPPORTS_AI); 771 772 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); 773 774 /* Audio Descriptors */ 775 /* pass through all formats */ 776 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 777 format_index++) { 778 audio_format_code = 779 (AUDIO_FORMAT_CODE_FIRST + format_index); 780 781 /* those are unsupported, skip programming */ 782 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 783 audio_format_code == AUDIO_FORMAT_CODE_DST) 784 continue; 785 786 value = 0; 787 788 /* check if supported */ 789 if (is_audio_format_supported( 790 audio_info, audio_format_code, &index)) { 791 const struct audio_mode *audio_mode = 792 &audio_info->modes[index]; 793 union audio_sample_rates sample_rates = 794 audio_mode->sample_rates; 795 uint8_t byte2 = audio_mode->max_bit_rate; 796 uint8_t channel_count = audio_mode->channel_count; 797 798 /* adjust specific properties */ 799 switch (audio_format_code) { 800 case AUDIO_FORMAT_CODE_LINEARPCM: { 801 802 check_audio_bandwidth( 803 crtc_info, 804 dp_link_info, 805 channel_count, 806 signal, 807 &sample_rates); 808 809 byte2 = audio_mode->sample_size; 810 811 set_reg_field_value(value, 812 sample_rates.all, 813 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 814 SUPPORTED_FREQUENCIES_STEREO); 815 } 816 break; 817 case AUDIO_FORMAT_CODE_AC3: 818 is_ac3_supported = true; 819 break; 820 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 821 case AUDIO_FORMAT_CODE_DTS_HD: 822 case AUDIO_FORMAT_CODE_MAT_MLP: 823 case AUDIO_FORMAT_CODE_DST: 824 case AUDIO_FORMAT_CODE_WMAPRO: 825 byte2 = audio_mode->vendor_specific; 826 break; 827 default: 828 break; 829 } 830 831 /* fill audio format data */ 832 set_reg_field_value(value, 833 channel_count - 1, 834 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 835 MAX_CHANNELS); 836 837 set_reg_field_value(value, 838 sample_rates.all, 839 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 840 SUPPORTED_FREQUENCIES); 841 842 set_reg_field_value(value, 843 byte2, 844 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 845 DESCRIPTOR_BYTE_2); 846 } /* if */ 847 848 AZ_REG_WRITE( 849 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 850 value); 851 } /* for */ 852 853 if (is_ac3_supported) 854 /* todo: this reg global. why program global register? */ 855 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 856 0x05); 857 858 /* check for 192khz/8-Ch support for HBR requirements */ 859 sample_rate.all = 0; 860 sample_rate.rate.RATE_192 = 1; 861 862 check_audio_bandwidth( 863 crtc_info, 864 dp_link_info, 865 8, 866 signal, 867 &sample_rate); 868 869 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 870 871 /* Audio and Video Lipsync */ 872 set_video_latency(audio, audio_info->video_latency); 873 set_audio_latency(audio, audio_info->audio_latency); 874 875 value = 0; 876 set_reg_field_value(value, audio_info->manufacture_id, 877 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 878 MANUFACTURER_ID); 879 880 set_reg_field_value(value, audio_info->product_id, 881 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 882 PRODUCT_ID); 883 884 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 885 value); 886 887 value = 0; 888 889 /*get display name string length */ 890 while (audio_info->display_name[strlen++] != '\0') { 891 if (strlen >= 892 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 893 break; 894 } 895 set_reg_field_value(value, strlen, 896 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 897 SINK_DESCRIPTION_LEN); 898 899 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 900 value); 901 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 902 audio->inst, value, audio_info->display_name); 903 904 /* 905 *write the port ID: 906 *PORT_ID0 = display index 907 *PORT_ID1 = 16bit BDF 908 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 909 */ 910 911 value = 0; 912 913 set_reg_field_value(value, audio_info->port_id[0], 914 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 915 PORT_ID0); 916 917 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 918 919 value = 0; 920 set_reg_field_value(value, audio_info->port_id[1], 921 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 922 PORT_ID1); 923 924 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 925 926 /*write the 18 char monitor string */ 927 928 value = 0; 929 set_reg_field_value(value, audio_info->display_name[0], 930 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 931 DESCRIPTION0); 932 933 set_reg_field_value(value, audio_info->display_name[1], 934 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 935 DESCRIPTION1); 936 937 set_reg_field_value(value, audio_info->display_name[2], 938 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 939 DESCRIPTION2); 940 941 set_reg_field_value(value, audio_info->display_name[3], 942 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 943 DESCRIPTION3); 944 945 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 946 947 value = 0; 948 set_reg_field_value(value, audio_info->display_name[4], 949 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 950 DESCRIPTION4); 951 952 set_reg_field_value(value, audio_info->display_name[5], 953 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 954 DESCRIPTION5); 955 956 set_reg_field_value(value, audio_info->display_name[6], 957 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 958 DESCRIPTION6); 959 960 set_reg_field_value(value, audio_info->display_name[7], 961 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 962 DESCRIPTION7); 963 964 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 965 966 value = 0; 967 set_reg_field_value(value, audio_info->display_name[8], 968 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 969 DESCRIPTION8); 970 971 set_reg_field_value(value, audio_info->display_name[9], 972 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 973 DESCRIPTION9); 974 975 set_reg_field_value(value, audio_info->display_name[10], 976 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 977 DESCRIPTION10); 978 979 set_reg_field_value(value, audio_info->display_name[11], 980 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 981 DESCRIPTION11); 982 983 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 984 985 value = 0; 986 set_reg_field_value(value, audio_info->display_name[12], 987 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 988 DESCRIPTION12); 989 990 set_reg_field_value(value, audio_info->display_name[13], 991 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 992 DESCRIPTION13); 993 994 set_reg_field_value(value, audio_info->display_name[14], 995 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 996 DESCRIPTION14); 997 998 set_reg_field_value(value, audio_info->display_name[15], 999 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 1000 DESCRIPTION15); 1001 1002 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 1003 1004 value = 0; 1005 set_reg_field_value(value, audio_info->display_name[16], 1006 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1007 DESCRIPTION16); 1008 1009 set_reg_field_value(value, audio_info->display_name[17], 1010 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1011 DESCRIPTION17); 1012 1013 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 1014 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1015 set_reg_field_value(value, 0, 1016 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1017 CLOCK_GATING_DISABLE); 1018 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1019 } 1020 1021 /* 1022 * todo: wall clk related functionality probably belong to clock_src. 1023 */ 1024 1025 /* search pixel clock value for Azalia HDMI Audio */ 1026 static void get_azalia_clock_info_hdmi( 1027 uint32_t crtc_pixel_clock_100hz, 1028 uint32_t actual_pixel_clock_100Hz, 1029 struct azalia_clock_info *azalia_clock_info) 1030 { 1031 (void)crtc_pixel_clock_100hz; 1032 /* audio_dto_phase= 24 * 10,000; 1033 * 24MHz in [100Hz] units */ 1034 azalia_clock_info->audio_dto_phase = 1035 24 * 10000; 1036 1037 /* audio_dto_module = PCLKFrequency * 10,000; 1038 * [khz] -> [100Hz] */ 1039 azalia_clock_info->audio_dto_module = 1040 actual_pixel_clock_100Hz; 1041 } 1042 1043 static void get_azalia_clock_info_dp( 1044 uint32_t requested_pixel_clock_100Hz, 1045 const struct audio_pll_info *pll_info, 1046 struct azalia_clock_info *azalia_clock_info) 1047 { 1048 (void)requested_pixel_clock_100Hz; 1049 /* Reported dpDtoSourceClockInkhz value for 1050 * DCE8 already adjusted for SS, do not need any 1051 * adjustment here anymore 1052 */ 1053 1054 /*audio_dto_phase = 24 * 10,000; 1055 * 24MHz in [100Hz] units */ 1056 azalia_clock_info->audio_dto_phase = 24 * 10000; 1057 1058 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 1059 * [khz] ->[100Hz] */ 1060 azalia_clock_info->audio_dto_module = 1061 pll_info->audio_dto_source_clock_in_khz * 10; 1062 } 1063 1064 void dce_aud_wall_dto_setup( 1065 struct audio *audio, 1066 enum signal_type signal, 1067 const struct audio_crtc_info *crtc_info, 1068 const struct audio_pll_info *pll_info) 1069 { 1070 struct dce_audio *aud = DCE_AUD(audio); 1071 1072 struct azalia_clock_info clock_info = { 0 }; 1073 1074 if (dc_is_hdmi_tmds_signal(signal)) { 1075 uint32_t src_sel; 1076 1077 /*DTO0 Programming goal: 1078 -generate 24MHz, 128*Fs from 24MHz 1079 -use DTO0 when an active HDMI port is connected 1080 (optionally a DP is connected) */ 1081 1082 /* calculate DTO settings */ 1083 get_azalia_clock_info_hdmi( 1084 crtc_info->requested_pixel_clock_100Hz, 1085 crtc_info->calculated_pixel_clock_100Hz, 1086 &clock_info); 1087 1088 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 1089 "calculated_pixel_clock_100Hz =%d\n"\ 1090 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 1091 crtc_info->requested_pixel_clock_100Hz,\ 1092 crtc_info->calculated_pixel_clock_100Hz,\ 1093 clock_info.audio_dto_module,\ 1094 clock_info.audio_dto_phase); 1095 1096 /* On TN/SI, Program DTO source select and DTO select before 1097 programming DTO modulo and DTO phase. These bits must be 1098 programmed first, otherwise there will be no HDMI audio at boot 1099 up. This is a HW sequence change (different from old ASICs). 1100 Caution when changing this programming sequence. 1101 1102 HDMI enabled, using DTO0 1103 program master CRTC for DTO0 */ 1104 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 1105 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 1106 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 1107 DCCG_AUDIO_DTO_SEL, 0); 1108 1109 /* module */ 1110 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 1111 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 1112 1113 /* phase */ 1114 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 1115 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 1116 } else { 1117 /*DTO1 Programming goal: 1118 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 1119 -default is to used DTO1, and switch to DTO0 when an audio 1120 master HDMI port is connected 1121 -use as default for DP 1122 1123 calculate DTO settings */ 1124 get_azalia_clock_info_dp( 1125 crtc_info->requested_pixel_clock_100Hz, 1126 pll_info, 1127 &clock_info); 1128 1129 /* Program DTO select before programming DTO modulo and DTO 1130 phase. default to use DTO1 */ 1131 1132 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1133 DCCG_AUDIO_DTO_SEL, 1); 1134 1135 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 1136 * Select 512fs for DP TODO: web register definition 1137 * does not match register header file 1138 * DCE11 version it's commented out while DCE8 it's set to 1 1139 */ 1140 1141 /* module */ 1142 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 1143 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 1144 1145 /* phase */ 1146 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 1147 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 1148 1149 if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO) 1150 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1151 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 1152 1153 } 1154 } 1155 1156 static bool dce_aud_endpoint_valid(struct audio *audio) 1157 { 1158 uint32_t value; 1159 uint32_t port_connectivity; 1160 1161 value = AZ_REG_READ( 1162 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1163 1164 port_connectivity = get_reg_field_value(value, 1165 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1166 PORT_CONNECTIVITY); 1167 1168 return !(port_connectivity == 1); 1169 } 1170 1171 /* initialize HW state */ 1172 void dce_aud_hw_init( 1173 struct audio *audio) 1174 { 1175 uint32_t value; 1176 struct dce_audio *aud = DCE_AUD(audio); 1177 1178 /* we only need to program the following registers once, so we only do 1179 it for the inst 0*/ 1180 if (audio->inst != 0) 1181 return; 1182 1183 /* Suport R5 - 32khz 1184 * Suport R6 - 44.1khz 1185 * Suport R7 - 48khz 1186 */ 1187 /*disable clock gating before write to endpoint register*/ 1188 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1189 set_reg_field_value(value, 1, 1190 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1191 CLOCK_GATING_DISABLE); 1192 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1193 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 1194 AUDIO_RATE_CAPABILITIES, 0x70); 1195 1196 /*Keep alive bit to verify HW block in BU. */ 1197 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 1198 CLKSTOP, 1, 1199 EPSS, 1); 1200 set_reg_field_value(value, 0, 1201 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1202 CLOCK_GATING_DISABLE); 1203 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1204 } 1205 1206 static const struct audio_funcs funcs = { 1207 .endpoint_valid = dce_aud_endpoint_valid, 1208 .hw_init = dce_aud_hw_init, 1209 .wall_dto_setup = dce_aud_wall_dto_setup, 1210 .az_enable = dce_aud_az_enable, 1211 .az_disable = dce_aud_az_disable, 1212 .az_configure = dce_aud_az_configure, 1213 .az_disable_hbr_audio = dce_aud_az_disable_hbr_audio, 1214 .destroy = dce_aud_destroy, 1215 }; 1216 1217 void dce_aud_destroy(struct audio **audio) 1218 { 1219 struct dce_audio *aud = DCE_AUD(*audio); 1220 1221 kfree(aud); 1222 *audio = NULL; 1223 } 1224 1225 struct audio *dce_audio_create( 1226 struct dc_context *ctx, 1227 unsigned int inst, 1228 const struct dce_audio_registers *reg, 1229 const struct dce_audio_shift *shifts, 1230 const struct dce_audio_mask *masks 1231 ) 1232 { 1233 struct dce_audio *audio = kzalloc_obj(*audio); 1234 1235 if (audio == NULL) { 1236 ASSERT_CRITICAL(audio); 1237 return NULL; 1238 } 1239 1240 audio->base.ctx = ctx; 1241 audio->base.inst = inst; 1242 audio->base.funcs = &funcs; 1243 1244 audio->regs = reg; 1245 audio->shifts = shifts; 1246 audio->masks = masks; 1247 return &audio->base; 1248 } 1249