1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 37 #define DC_LOGGER_INIT() 38 39 #define REG(reg)\ 40 (aud->regs->reg) 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 aud->shifts->field_name, aud->masks->field_name 45 46 #define IX_REG(reg)\ 47 ix ## reg 48 49 #define AZ_REG_READ(reg_name) \ 50 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 51 52 #define AZ_REG_WRITE(reg_name, value) \ 53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 54 55 static void write_indirect_azalia_reg(struct audio *audio, 56 uint32_t reg_index, 57 uint32_t reg_data) 58 { 59 struct dce_audio *aud = DCE_AUD(audio); 60 61 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 63 AZALIA_ENDPOINT_REG_INDEX, reg_index); 64 65 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 67 AZALIA_ENDPOINT_REG_DATA, reg_data); 68 } 69 70 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 71 { 72 struct dce_audio *aud = DCE_AUD(audio); 73 74 uint32_t value = 0; 75 76 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 77 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 78 AZALIA_ENDPOINT_REG_INDEX, reg_index); 79 80 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 82 83 return value; 84 } 85 86 static bool is_audio_format_supported( 87 const struct audio_info *audio_info, 88 enum audio_format_code audio_format_code, 89 uint32_t *format_index) 90 { 91 uint32_t index; 92 uint32_t max_channe_index = 0; 93 bool found = false; 94 95 if (audio_info == NULL) 96 return found; 97 98 /* pass through whole array */ 99 for (index = 0; index < audio_info->mode_count; index++) { 100 if (audio_info->modes[index].format_code == audio_format_code) { 101 if (found) { 102 /* format has multiply entries, choose one with 103 * highst number of channels */ 104 if (audio_info->modes[index].channel_count > 105 audio_info->modes[max_channe_index].channel_count) { 106 max_channe_index = index; 107 } 108 } else { 109 /* format found, save it's index */ 110 found = true; 111 max_channe_index = index; 112 } 113 } 114 } 115 116 /* return index */ 117 if (found && format_index != NULL) 118 *format_index = max_channe_index; 119 120 return found; 121 } 122 123 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 124 static void check_audio_bandwidth_hdmi( 125 const struct audio_crtc_info *crtc_info, 126 uint32_t channel_count, 127 union audio_sample_rates *sample_rates) 128 { 129 uint32_t samples; 130 uint32_t h_blank; 131 bool limit_freq_to_48_khz = false; 132 bool limit_freq_to_88_2_khz = false; 133 bool limit_freq_to_96_khz = false; 134 bool limit_freq_to_174_4_khz = false; 135 if (!crtc_info) 136 return; 137 138 /* For two channels supported return whatever sink support,unmodified*/ 139 if (channel_count > 2) { 140 141 /* Based on HDMI spec 1.3 Table 7.5 */ 142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 143 (crtc_info->v_active <= 576) && 144 !(crtc_info->interlaced) && 145 !(crtc_info->pixel_repetition == 2 || 146 crtc_info->pixel_repetition == 4)) { 147 limit_freq_to_48_khz = true; 148 149 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 150 (crtc_info->v_active <= 576) && 151 (crtc_info->interlaced) && 152 (crtc_info->pixel_repetition == 2)) { 153 limit_freq_to_88_2_khz = true; 154 155 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 156 (crtc_info->v_active <= 576) && 157 !(crtc_info->interlaced)) { 158 limit_freq_to_174_4_khz = true; 159 } 160 } 161 162 /* Also do some calculation for the available Audio Bandwidth for the 163 * 8 ch (i.e. for the Layout 1 => ch > 2) 164 */ 165 h_blank = crtc_info->h_total - crtc_info->h_active; 166 167 if (crtc_info->pixel_repetition) 168 h_blank *= crtc_info->pixel_repetition; 169 170 /*based on HDMI spec 1.3 Table 7.5 */ 171 h_blank -= 58; 172 /*for Control Period */ 173 h_blank -= 16; 174 175 samples = h_blank * 10; 176 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 177 * of Audio samples per line multiplied by 10 - Layout 1) 178 */ 179 samples /= 32; 180 samples *= crtc_info->v_active; 181 /*Number of samples multiplied by 10, per second */ 182 samples *= crtc_info->refresh_rate; 183 /*Number of Audio samples per second */ 184 samples /= 10; 185 186 /* @todo do it after deep color is implemented 187 * 8xx - deep color bandwidth scaling 188 * Extra bandwidth is avaliable in deep color b/c link runs faster than 189 * pixel rate. This has the effect of allowing more tmds characters to 190 * be transmitted during blank 191 */ 192 193 switch (crtc_info->color_depth) { 194 case COLOR_DEPTH_888: 195 samples *= 4; 196 break; 197 case COLOR_DEPTH_101010: 198 samples *= 5; 199 break; 200 case COLOR_DEPTH_121212: 201 samples *= 6; 202 break; 203 default: 204 samples *= 4; 205 break; 206 } 207 208 samples /= 4; 209 210 /*check limitation*/ 211 if (samples < 88200) 212 limit_freq_to_48_khz = true; 213 else if (samples < 96000) 214 limit_freq_to_88_2_khz = true; 215 else if (samples < 176400) 216 limit_freq_to_96_khz = true; 217 else if (samples < 192000) 218 limit_freq_to_174_4_khz = true; 219 220 if (sample_rates != NULL) { 221 /* limit frequencies */ 222 if (limit_freq_to_174_4_khz) 223 sample_rates->rate.RATE_192 = 0; 224 225 if (limit_freq_to_96_khz) { 226 sample_rates->rate.RATE_192 = 0; 227 sample_rates->rate.RATE_176_4 = 0; 228 } 229 if (limit_freq_to_88_2_khz) { 230 sample_rates->rate.RATE_192 = 0; 231 sample_rates->rate.RATE_176_4 = 0; 232 sample_rates->rate.RATE_96 = 0; 233 } 234 if (limit_freq_to_48_khz) { 235 sample_rates->rate.RATE_192 = 0; 236 sample_rates->rate.RATE_176_4 = 0; 237 sample_rates->rate.RATE_96 = 0; 238 sample_rates->rate.RATE_88_2 = 0; 239 } 240 } 241 } 242 static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate) 243 { 244 switch (link_rate) { 245 case LINK_RATE_LOW: 246 return dc_fixpt_from_int(162); /* 162 MHz */ 247 case LINK_RATE_HIGH: 248 return dc_fixpt_from_int(270); /* 270 MHz */ 249 case LINK_RATE_HIGH2: 250 return dc_fixpt_from_int(540); /* 540 MHz */ 251 case LINK_RATE_HIGH3: 252 return dc_fixpt_from_int(810); /* 810 MHz */ 253 case LINK_RATE_UHBR10: 254 return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */ 255 case LINK_RATE_UHBR13_5: 256 return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */ 257 case LINK_RATE_UHBR20: 258 return dc_fixpt_from_int(625); /* 625 MHz */ 259 default: 260 /* Unexpected case, this requires debug if encountered. */ 261 ASSERT(0); 262 return dc_fixpt_from_int(0); 263 } 264 } 265 266 struct dp_audio_layout_config { 267 uint8_t layouts_per_sample_denom; 268 uint8_t symbols_per_layout; 269 uint8_t max_layouts_per_audio_sdp; 270 }; 271 272 static void get_audio_layout_config( 273 uint32_t channel_count, 274 enum dp_link_encoding encoding, 275 struct dp_audio_layout_config *output) 276 { 277 /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, 278 * with each layout being the same size (8ch layout). 279 */ 280 if (encoding == DP_8b_10b_ENCODING) { 281 if (channel_count == 2) { 282 output->layouts_per_sample_denom = 4; 283 output->symbols_per_layout = 40; 284 output->max_layouts_per_audio_sdp = 1; 285 } else if (channel_count == 8 || channel_count == 6) { 286 output->layouts_per_sample_denom = 1; 287 output->symbols_per_layout = 40; 288 output->max_layouts_per_audio_sdp = 1; 289 } 290 } else if (encoding == DP_128b_132b_ENCODING) { 291 if (channel_count == 2) { 292 output->layouts_per_sample_denom = 4; 293 output->symbols_per_layout = 10; 294 output->max_layouts_per_audio_sdp = 1; 295 } else if (channel_count == 8 || channel_count == 6) { 296 output->layouts_per_sample_denom = 1; 297 output->symbols_per_layout = 10; 298 output->max_layouts_per_audio_sdp = 1; 299 } 300 } 301 } 302 303 static uint32_t get_av_stream_map_lane_count( 304 enum dp_link_encoding encoding, 305 enum dc_lane_count lane_count, 306 bool is_mst) 307 { 308 uint32_t av_stream_map_lane_count = 0; 309 310 if (encoding == DP_8b_10b_ENCODING) { 311 if (!is_mst) 312 av_stream_map_lane_count = lane_count; 313 else 314 av_stream_map_lane_count = 4; 315 } else if (encoding == DP_128b_132b_ENCODING) { 316 av_stream_map_lane_count = 4; 317 } 318 319 ASSERT(av_stream_map_lane_count != 0); 320 321 return av_stream_map_lane_count; 322 } 323 324 static uint32_t get_audio_sdp_overhead( 325 enum dp_link_encoding encoding, 326 enum dc_lane_count lane_count, 327 bool is_mst) 328 { 329 uint32_t audio_sdp_overhead = 0; 330 331 if (encoding == DP_8b_10b_ENCODING) { 332 if (is_mst) 333 audio_sdp_overhead = 16; /* 4 * 2 + 8 */ 334 else 335 audio_sdp_overhead = lane_count * 2 + 8; 336 } else if (encoding == DP_128b_132b_ENCODING) { 337 audio_sdp_overhead = 10; /* 4 x 2.5 */ 338 } 339 340 ASSERT(audio_sdp_overhead != 0); 341 342 return audio_sdp_overhead; 343 } 344 345 static uint32_t calculate_required_audio_bw_in_symbols( 346 const struct audio_crtc_info *crtc_info, 347 const struct dp_audio_layout_config *layout_config, 348 uint32_t channel_count, 349 uint32_t sample_rate_hz, 350 uint32_t av_stream_map_lane_count, 351 uint32_t audio_sdp_overhead) 352 { 353 (void)channel_count; 354 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ 355 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); 356 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( 357 crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10); 358 struct fixed31_32 samples_per_line; 359 struct fixed31_32 layouts_per_line; 360 struct fixed31_32 symbols_per_sdp_max_layout; 361 struct fixed31_32 remainder; 362 uint32_t num_sdp_with_max_layouts; 363 uint32_t required_symbols_per_hblank; 364 365 samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000); 366 samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz); 367 layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom); 368 369 num_sdp_with_max_layouts = dc_fixpt_floor( 370 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp)); 371 symbols_per_sdp_max_layout = dc_fixpt_from_int( 372 layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout); 373 symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead); 374 symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin); 375 required_symbols_per_hblank = num_sdp_with_max_layouts; 376 required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) / 377 av_stream_map_lane_count) * av_stream_map_lane_count; 378 379 if (num_sdp_with_max_layouts != dc_fixpt_ceil( 380 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) { 381 remainder = dc_fixpt_sub_int(layouts_per_line, 382 num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp); 383 remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout); 384 remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead); 385 remainder = dc_fixpt_mul(remainder, audio_sdp_margin); 386 required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) / 387 av_stream_map_lane_count) * av_stream_map_lane_count; 388 } 389 390 return required_symbols_per_hblank; 391 } 392 393 /* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. 394 */ 395 static uint32_t calculate_available_hblank_bw_in_symbols( 396 const struct audio_crtc_info *crtc_info, 397 const struct audio_dp_link_info *dp_link_info) 398 { 399 uint64_t hblank = crtc_info->h_total - crtc_info->h_active; 400 struct fixed31_32 hblank_time_msec = 401 dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz); 402 struct fixed31_32 lsclkfreq_mhz = 403 get_link_symbol_clk_freq_mhz(dp_link_info->link_rate); 404 struct fixed31_32 average_stream_sym_bw_frac; 405 struct fixed31_32 peak_stream_bw_kbps; 406 struct fixed31_32 bits_per_pixel; 407 struct fixed31_32 link_bw_kbps; 408 struct fixed31_32 available_stream_sym_count; 409 uint32_t available_hblank_bw = 0; /* in stream symbols */ 410 411 if (crtc_info->dsc_bits_per_pixel) { 412 bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16); 413 } else { 414 switch (crtc_info->color_depth) { 415 case COLOR_DEPTH_666: 416 bits_per_pixel = dc_fixpt_from_int(6); 417 break; 418 case COLOR_DEPTH_888: 419 bits_per_pixel = dc_fixpt_from_int(8); 420 break; 421 case COLOR_DEPTH_101010: 422 bits_per_pixel = dc_fixpt_from_int(10); 423 break; 424 case COLOR_DEPTH_121212: 425 bits_per_pixel = dc_fixpt_from_int(12); 426 break; 427 default: 428 /* Default to commonly supported color depth. */ 429 bits_per_pixel = dc_fixpt_from_int(8); 430 break; 431 } 432 433 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3); 434 435 if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 436 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3); 437 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2); 438 } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) { 439 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2); 440 } 441 } 442 443 /* Use simple stream BW calculation because mainlink overhead is 444 * accounted for separately in the audio BW calculations. 445 */ 446 peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10); 447 peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel); 448 link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps); 449 average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps); 450 451 available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000); 452 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz); 453 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac); 454 available_hblank_bw = dc_fixpt_floor(available_stream_sym_count); 455 available_hblank_bw *= dp_link_info->lane_count; 456 available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */ 457 458 if (available_hblank_bw < dp_link_info->hblank_min_symbol_width) 459 /* Each symbol takes 4 frames */ 460 available_hblank_bw = 4 * dp_link_info->hblank_min_symbol_width; 461 462 if (available_hblank_bw < 12) 463 available_hblank_bw = 0; 464 else 465 available_hblank_bw -= 12; /* Main link overhead */ 466 467 return available_hblank_bw; 468 } 469 470 static void check_audio_bandwidth_dp( 471 const struct audio_crtc_info *crtc_info, 472 const struct audio_dp_link_info *dp_link_info, 473 uint32_t channel_count, 474 union audio_sample_rates *sample_rates) 475 { 476 struct dp_audio_layout_config layout_config = {0}; 477 uint32_t available_hblank_bw; 478 uint32_t av_stream_map_lane_count; 479 uint32_t audio_sdp_overhead; 480 481 /* TODO: Add validation for SST 8b/10 case */ 482 if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING) 483 return; 484 485 available_hblank_bw = calculate_available_hblank_bw_in_symbols( 486 crtc_info, dp_link_info); 487 av_stream_map_lane_count = get_av_stream_map_lane_count( 488 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 489 audio_sdp_overhead = get_audio_sdp_overhead( 490 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); 491 get_audio_layout_config( 492 channel_count, dp_link_info->encoding, &layout_config); 493 494 if (layout_config.max_layouts_per_audio_sdp == 0 || 495 layout_config.symbols_per_layout == 0 || 496 layout_config.layouts_per_sample_denom == 0) { 497 return; 498 } 499 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 500 crtc_info, &layout_config, channel_count, 192000, 501 av_stream_map_lane_count, audio_sdp_overhead)) 502 sample_rates->rate.RATE_192 = 0; 503 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 504 crtc_info, &layout_config, channel_count, 176400, 505 av_stream_map_lane_count, audio_sdp_overhead)) 506 sample_rates->rate.RATE_176_4 = 0; 507 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 508 crtc_info, &layout_config, channel_count, 96000, 509 av_stream_map_lane_count, audio_sdp_overhead)) 510 sample_rates->rate.RATE_96 = 0; 511 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 512 crtc_info, &layout_config, channel_count, 88200, 513 av_stream_map_lane_count, audio_sdp_overhead)) 514 sample_rates->rate.RATE_88_2 = 0; 515 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 516 crtc_info, &layout_config, channel_count, 48000, 517 av_stream_map_lane_count, audio_sdp_overhead)) 518 sample_rates->rate.RATE_48 = 0; 519 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 520 crtc_info, &layout_config, channel_count, 44100, 521 av_stream_map_lane_count, audio_sdp_overhead)) 522 sample_rates->rate.RATE_44_1 = 0; 523 if (available_hblank_bw < calculate_required_audio_bw_in_symbols( 524 crtc_info, &layout_config, channel_count, 32000, 525 av_stream_map_lane_count, audio_sdp_overhead)) 526 sample_rates->rate.RATE_32 = 0; 527 } 528 529 static void check_audio_bandwidth( 530 const struct audio_crtc_info *crtc_info, 531 const struct audio_dp_link_info *dp_link_info, 532 uint32_t channel_count, 533 enum signal_type signal, 534 union audio_sample_rates *sample_rates) 535 { 536 switch (signal) { 537 case SIGNAL_TYPE_HDMI_TYPE_A: 538 case SIGNAL_TYPE_HDMI_FRL: 539 check_audio_bandwidth_hdmi( 540 crtc_info, channel_count, sample_rates); 541 break; 542 case SIGNAL_TYPE_EDP: 543 case SIGNAL_TYPE_DISPLAY_PORT: 544 case SIGNAL_TYPE_DISPLAY_PORT_MST: 545 check_audio_bandwidth_dp( 546 crtc_info, dp_link_info, channel_count, sample_rates); 547 break; 548 default: 549 break; 550 } 551 } 552 553 /* expose/not expose HBR capability to Audio driver */ 554 static void set_high_bit_rate_capable( 555 struct audio *audio, 556 bool capable) 557 { 558 uint32_t value = 0; 559 560 /* set high bit rate audio capable*/ 561 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 562 563 set_reg_field_value(value, capable, 564 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 565 HBR_CAPABLE); 566 567 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 568 } 569 570 /* set video latency in ms/2+1 */ 571 static void set_video_latency( 572 struct audio *audio, 573 int latency_in_ms) 574 { 575 uint32_t value = 0; 576 577 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 578 return; 579 580 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 581 582 set_reg_field_value(value, latency_in_ms, 583 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 584 VIDEO_LIPSYNC); 585 586 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 587 value); 588 } 589 590 /* set audio latency in ms/2+1 */ 591 static void set_audio_latency( 592 struct audio *audio, 593 int latency_in_ms) 594 { 595 uint32_t value = 0; 596 597 if (latency_in_ms < 0) 598 latency_in_ms = 0; 599 600 if (latency_in_ms > 255) 601 latency_in_ms = 255; 602 603 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 604 605 set_reg_field_value(value, latency_in_ms, 606 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 607 AUDIO_LIPSYNC); 608 609 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 610 value); 611 } 612 613 void dce_aud_az_enable(struct audio *audio) 614 { 615 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 616 DC_LOGGER_INIT(); 617 618 set_reg_field_value(value, 1, 619 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 620 CLOCK_GATING_DISABLE); 621 set_reg_field_value(value, 1, 622 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 623 AUDIO_ENABLED); 624 625 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 626 set_reg_field_value(value, 0, 627 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 628 CLOCK_GATING_DISABLE); 629 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 630 631 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 632 audio->inst, value); 633 } 634 635 void dce_aud_az_disable_hbr_audio(struct audio *audio) 636 { 637 set_high_bit_rate_capable(audio, false); 638 } 639 640 void dce_aud_az_disable(struct audio *audio) 641 { 642 uint32_t value; 643 DC_LOGGER_INIT(); 644 645 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 646 set_reg_field_value(value, 1, 647 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 648 CLOCK_GATING_DISABLE); 649 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 650 651 set_reg_field_value(value, 0, 652 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 653 AUDIO_ENABLED); 654 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 655 656 set_reg_field_value(value, 0, 657 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 658 CLOCK_GATING_DISABLE); 659 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 660 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 661 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 662 audio->inst, value); 663 } 664 665 void dce_aud_az_configure( 666 struct audio *audio, 667 enum signal_type signal, 668 const struct audio_crtc_info *crtc_info, 669 const struct audio_info *audio_info, 670 const struct audio_dp_link_info *dp_link_info) 671 { 672 struct dce_audio *aud = DCE_AUD(audio); 673 674 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 675 uint32_t value; 676 uint32_t field = 0; 677 enum audio_format_code audio_format_code; 678 uint32_t format_index; 679 uint32_t index; 680 bool is_ac3_supported = false; 681 union audio_sample_rates sample_rate; 682 uint32_t strlen = 0; 683 684 if (signal == SIGNAL_TYPE_VIRTUAL) 685 return; 686 687 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 688 set_reg_field_value(value, 1, 689 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 690 CLOCK_GATING_DISABLE); 691 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 692 693 /* Speaker Allocation */ 694 /* 695 uint32_t value; 696 uint32_t field = 0;*/ 697 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 698 699 set_reg_field_value(value, 700 speakers, 701 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 702 SPEAKER_ALLOCATION); 703 704 /* LFE_PLAYBACK_LEVEL = LFEPBL 705 * LFEPBL = 0 : Unknown or refer to other information 706 * LFEPBL = 1 : 0dB playback 707 * LFEPBL = 2 : +10dB playback 708 * LFE_BL = 3 : Reserved 709 */ 710 set_reg_field_value(value, 711 0, 712 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 713 LFE_PLAYBACK_LEVEL); 714 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 715 * why are we writing to it? DCE8 does not write this */ 716 717 718 set_reg_field_value(value, 719 0, 720 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 721 HDMI_CONNECTION); 722 723 set_reg_field_value(value, 724 0, 725 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 726 DP_CONNECTION); 727 728 field = get_reg_field_value(value, 729 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 730 EXTRA_CONNECTION_INFO); 731 732 field &= ~0x1; 733 734 set_reg_field_value(value, 735 field, 736 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 737 EXTRA_CONNECTION_INFO); 738 739 /* set audio for output signal */ 740 switch (signal) { 741 case SIGNAL_TYPE_HDMI_TYPE_A: 742 case SIGNAL_TYPE_HDMI_FRL: 743 set_reg_field_value(value, 744 1, 745 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 746 HDMI_CONNECTION); 747 748 break; 749 750 case SIGNAL_TYPE_EDP: 751 case SIGNAL_TYPE_DISPLAY_PORT: 752 case SIGNAL_TYPE_DISPLAY_PORT_MST: 753 set_reg_field_value(value, 754 1, 755 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 756 DP_CONNECTION); 757 break; 758 default: 759 BREAK_TO_DEBUGGER(); 760 break; 761 } 762 763 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 764 765 /* ACP Data - Supports AI */ 766 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); 767 768 set_reg_field_value( 769 value, 770 audio_info->flags.info.SUPPORT_AI, 771 AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, 772 SUPPORTS_AI); 773 774 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); 775 776 /* Audio Descriptors */ 777 /* pass through all formats */ 778 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 779 format_index++) { 780 audio_format_code = 781 (AUDIO_FORMAT_CODE_FIRST + format_index); 782 783 /* those are unsupported, skip programming */ 784 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 785 audio_format_code == AUDIO_FORMAT_CODE_DST) 786 continue; 787 788 value = 0; 789 790 /* check if supported */ 791 if (is_audio_format_supported( 792 audio_info, audio_format_code, &index)) { 793 const struct audio_mode *audio_mode = 794 &audio_info->modes[index]; 795 union audio_sample_rates sample_rates = 796 audio_mode->sample_rates; 797 uint8_t byte2 = audio_mode->max_bit_rate; 798 uint8_t channel_count = audio_mode->channel_count; 799 800 /* adjust specific properties */ 801 switch (audio_format_code) { 802 case AUDIO_FORMAT_CODE_LINEARPCM: { 803 if (signal == SIGNAL_TYPE_HDMI_FRL 804 && channel_count > 2 805 && crtc_info != NULL 806 && crtc_info->v_active <= 576) { 807 channel_count = 2; 808 } 809 810 check_audio_bandwidth( 811 crtc_info, 812 dp_link_info, 813 channel_count, 814 signal, 815 &sample_rates); 816 817 byte2 = audio_mode->sample_size; 818 819 set_reg_field_value(value, 820 sample_rates.all, 821 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 822 SUPPORTED_FREQUENCIES_STEREO); 823 } 824 break; 825 case AUDIO_FORMAT_CODE_AC3: 826 is_ac3_supported = true; 827 break; 828 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 829 case AUDIO_FORMAT_CODE_DTS_HD: 830 case AUDIO_FORMAT_CODE_MAT_MLP: 831 case AUDIO_FORMAT_CODE_DST: 832 case AUDIO_FORMAT_CODE_WMAPRO: 833 byte2 = audio_mode->vendor_specific; 834 break; 835 default: 836 break; 837 } 838 839 /* fill audio format data */ 840 set_reg_field_value(value, 841 channel_count - 1, 842 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 843 MAX_CHANNELS); 844 845 set_reg_field_value(value, 846 sample_rates.all, 847 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 848 SUPPORTED_FREQUENCIES); 849 850 set_reg_field_value(value, 851 byte2, 852 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 853 DESCRIPTOR_BYTE_2); 854 } /* if */ 855 856 AZ_REG_WRITE( 857 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 858 value); 859 } /* for */ 860 861 if (is_ac3_supported) 862 /* todo: this reg global. why program global register? */ 863 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 864 0x05); 865 866 /* check for 192khz/8-Ch support for HBR requirements */ 867 sample_rate.all = 0; 868 sample_rate.rate.RATE_192 = 1; 869 870 check_audio_bandwidth( 871 crtc_info, 872 dp_link_info, 873 8, 874 signal, 875 &sample_rate); 876 877 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 878 879 /* Audio and Video Lipsync */ 880 set_video_latency(audio, audio_info->video_latency); 881 set_audio_latency(audio, audio_info->audio_latency); 882 883 value = 0; 884 set_reg_field_value(value, audio_info->manufacture_id, 885 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 886 MANUFACTURER_ID); 887 888 set_reg_field_value(value, audio_info->product_id, 889 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 890 PRODUCT_ID); 891 892 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 893 value); 894 895 value = 0; 896 897 /*get display name string length */ 898 while (audio_info->display_name[strlen++] != '\0') { 899 if (strlen >= 900 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 901 break; 902 } 903 set_reg_field_value(value, strlen, 904 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 905 SINK_DESCRIPTION_LEN); 906 907 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 908 value); 909 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 910 audio->inst, value, audio_info->display_name); 911 912 /* 913 *write the port ID: 914 *PORT_ID0 = display index 915 *PORT_ID1 = 16bit BDF 916 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 917 */ 918 919 value = 0; 920 921 set_reg_field_value(value, audio_info->port_id[0], 922 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 923 PORT_ID0); 924 925 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 926 927 value = 0; 928 set_reg_field_value(value, audio_info->port_id[1], 929 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 930 PORT_ID1); 931 932 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 933 934 /*write the 18 char monitor string */ 935 936 value = 0; 937 set_reg_field_value(value, audio_info->display_name[0], 938 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 939 DESCRIPTION0); 940 941 set_reg_field_value(value, audio_info->display_name[1], 942 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 943 DESCRIPTION1); 944 945 set_reg_field_value(value, audio_info->display_name[2], 946 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 947 DESCRIPTION2); 948 949 set_reg_field_value(value, audio_info->display_name[3], 950 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 951 DESCRIPTION3); 952 953 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 954 955 value = 0; 956 set_reg_field_value(value, audio_info->display_name[4], 957 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 958 DESCRIPTION4); 959 960 set_reg_field_value(value, audio_info->display_name[5], 961 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 962 DESCRIPTION5); 963 964 set_reg_field_value(value, audio_info->display_name[6], 965 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 966 DESCRIPTION6); 967 968 set_reg_field_value(value, audio_info->display_name[7], 969 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 970 DESCRIPTION7); 971 972 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 973 974 value = 0; 975 set_reg_field_value(value, audio_info->display_name[8], 976 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 977 DESCRIPTION8); 978 979 set_reg_field_value(value, audio_info->display_name[9], 980 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 981 DESCRIPTION9); 982 983 set_reg_field_value(value, audio_info->display_name[10], 984 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 985 DESCRIPTION10); 986 987 set_reg_field_value(value, audio_info->display_name[11], 988 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 989 DESCRIPTION11); 990 991 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 992 993 value = 0; 994 set_reg_field_value(value, audio_info->display_name[12], 995 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 996 DESCRIPTION12); 997 998 set_reg_field_value(value, audio_info->display_name[13], 999 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 1000 DESCRIPTION13); 1001 1002 set_reg_field_value(value, audio_info->display_name[14], 1003 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 1004 DESCRIPTION14); 1005 1006 set_reg_field_value(value, audio_info->display_name[15], 1007 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 1008 DESCRIPTION15); 1009 1010 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 1011 1012 value = 0; 1013 set_reg_field_value(value, audio_info->display_name[16], 1014 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1015 DESCRIPTION16); 1016 1017 set_reg_field_value(value, audio_info->display_name[17], 1018 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 1019 DESCRIPTION17); 1020 1021 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 1022 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1023 set_reg_field_value(value, 0, 1024 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1025 CLOCK_GATING_DISABLE); 1026 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1027 } 1028 1029 /* 1030 * todo: wall clk related functionality probably belong to clock_src. 1031 */ 1032 1033 /* search pixel clock value for Azalia HDMI Audio */ 1034 static void get_azalia_clock_info_hdmi( 1035 uint32_t crtc_pixel_clock_100hz, 1036 uint32_t actual_pixel_clock_100Hz, 1037 struct azalia_clock_info *azalia_clock_info) 1038 { 1039 (void)crtc_pixel_clock_100hz; 1040 /* audio_dto_phase= 24 * 10,000; 1041 * 24MHz in [100Hz] units */ 1042 azalia_clock_info->audio_dto_phase = 1043 24 * 10000; 1044 1045 /* audio_dto_module = PCLKFrequency * 10,000; 1046 * [khz] -> [100Hz] */ 1047 azalia_clock_info->audio_dto_module = 1048 actual_pixel_clock_100Hz; 1049 } 1050 1051 static void get_azalia_clock_info_dp( 1052 uint32_t requested_pixel_clock_100Hz, 1053 const struct audio_pll_info *pll_info, 1054 struct azalia_clock_info *azalia_clock_info) 1055 { 1056 (void)requested_pixel_clock_100Hz; 1057 /* Reported dpDtoSourceClockInkhz value for 1058 * DCE8 already adjusted for SS, do not need any 1059 * adjustment here anymore 1060 */ 1061 1062 /*audio_dto_phase = 24 * 10,000; 1063 * 24MHz in [100Hz] units */ 1064 azalia_clock_info->audio_dto_phase = 24 * 10000; 1065 1066 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 1067 * [khz] ->[100Hz] */ 1068 azalia_clock_info->audio_dto_module = 1069 pll_info->audio_dto_source_clock_in_khz * 10; 1070 } 1071 1072 void dce_aud_wall_dto_setup( 1073 struct audio *audio, 1074 enum signal_type signal, 1075 const struct audio_crtc_info *crtc_info, 1076 const struct audio_pll_info *pll_info) 1077 { 1078 struct dce_audio *aud = DCE_AUD(audio); 1079 1080 struct azalia_clock_info clock_info = { 0 }; 1081 1082 if (dc_is_hdmi_tmds_signal(signal)) { 1083 uint32_t src_sel; 1084 1085 /*DTO0 Programming goal: 1086 -generate 24MHz, 128*Fs from 24MHz 1087 -use DTO0 when an active HDMI port is connected 1088 (optionally a DP is connected) */ 1089 1090 /* calculate DTO settings */ 1091 get_azalia_clock_info_hdmi( 1092 crtc_info->requested_pixel_clock_100Hz, 1093 crtc_info->calculated_pixel_clock_100Hz, 1094 &clock_info); 1095 1096 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 1097 "calculated_pixel_clock_100Hz =%d\n"\ 1098 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 1099 crtc_info->requested_pixel_clock_100Hz,\ 1100 crtc_info->calculated_pixel_clock_100Hz,\ 1101 clock_info.audio_dto_module,\ 1102 clock_info.audio_dto_phase); 1103 1104 /* On TN/SI, Program DTO source select and DTO select before 1105 programming DTO modulo and DTO phase. These bits must be 1106 programmed first, otherwise there will be no HDMI audio at boot 1107 up. This is a HW sequence change (different from old ASICs). 1108 Caution when changing this programming sequence. 1109 1110 HDMI enabled, using DTO0 1111 program master CRTC for DTO0 */ 1112 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 1113 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 1114 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 1115 DCCG_AUDIO_DTO_SEL, 0); 1116 1117 /* module */ 1118 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 1119 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 1120 1121 /* phase */ 1122 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 1123 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 1124 } else { 1125 /*DTO1 Programming goal: 1126 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 1127 -default is to used DTO1, and switch to DTO0 when an audio 1128 master HDMI port is connected 1129 -use as default for DP 1130 1131 calculate DTO settings */ 1132 get_azalia_clock_info_dp( 1133 crtc_info->requested_pixel_clock_100Hz, 1134 pll_info, 1135 &clock_info); 1136 1137 /* Program DTO select before programming DTO modulo and DTO 1138 phase. default to use DTO1 */ 1139 1140 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1141 DCCG_AUDIO_DTO_SEL, 1); 1142 1143 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 1144 * Select 512fs for DP TODO: web register definition 1145 * does not match register header file 1146 * DCE11 version it's commented out while DCE8 it's set to 1 1147 */ 1148 1149 /* module */ 1150 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 1151 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 1152 1153 /* phase */ 1154 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 1155 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 1156 1157 if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO) 1158 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 1159 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 1160 1161 } 1162 } 1163 1164 static bool dce_aud_endpoint_valid(struct audio *audio) 1165 { 1166 uint32_t value; 1167 uint32_t port_connectivity; 1168 1169 value = AZ_REG_READ( 1170 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1171 1172 port_connectivity = get_reg_field_value(value, 1173 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1174 PORT_CONNECTIVITY); 1175 1176 return !(port_connectivity == 1); 1177 } 1178 1179 /* initialize HW state */ 1180 void dce_aud_hw_init( 1181 struct audio *audio) 1182 { 1183 uint32_t value; 1184 struct dce_audio *aud = DCE_AUD(audio); 1185 1186 /* we only need to program the following registers once, so we only do 1187 it for the inst 0*/ 1188 if (audio->inst != 0) 1189 return; 1190 1191 /* Suport R5 - 32khz 1192 * Suport R6 - 44.1khz 1193 * Suport R7 - 48khz 1194 */ 1195 /*disable clock gating before write to endpoint register*/ 1196 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 1197 set_reg_field_value(value, 1, 1198 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1199 CLOCK_GATING_DISABLE); 1200 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1201 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 1202 AUDIO_RATE_CAPABILITIES, 0x70); 1203 1204 /*Keep alive bit to verify HW block in BU. */ 1205 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 1206 CLKSTOP, 1, 1207 EPSS, 1); 1208 set_reg_field_value(value, 0, 1209 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1210 CLOCK_GATING_DISABLE); 1211 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 1212 } 1213 1214 static const struct audio_funcs funcs = { 1215 .endpoint_valid = dce_aud_endpoint_valid, 1216 .hw_init = dce_aud_hw_init, 1217 .wall_dto_setup = dce_aud_wall_dto_setup, 1218 .az_enable = dce_aud_az_enable, 1219 .az_disable = dce_aud_az_disable, 1220 .az_configure = dce_aud_az_configure, 1221 .az_disable_hbr_audio = dce_aud_az_disable_hbr_audio, 1222 .destroy = dce_aud_destroy, 1223 }; 1224 1225 void dce_aud_destroy(struct audio **audio) 1226 { 1227 struct dce_audio *aud = DCE_AUD(*audio); 1228 1229 kfree(aud); 1230 *audio = NULL; 1231 } 1232 1233 struct audio *dce_audio_create( 1234 struct dc_context *ctx, 1235 unsigned int inst, 1236 const struct dce_audio_registers *reg, 1237 const struct dce_audio_shift *shifts, 1238 const struct dce_audio_mask *masks 1239 ) 1240 { 1241 struct dce_audio *audio = kzalloc_obj(*audio); 1242 1243 if (audio == NULL) { 1244 ASSERT_CRITICAL(audio); 1245 return NULL; 1246 } 1247 1248 audio->base.ctx = ctx; 1249 audio->base.inst = inst; 1250 audio->base.funcs = &funcs; 1251 1252 audio->regs = reg; 1253 audio->shifts = shifts; 1254 audio->masks = masks; 1255 return &audio->base; 1256 } 1257