1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_ABM_H_ 28 #define _DCE_ABM_H_ 29 30 #include "abm.h" 31 32 #define ABM_COMMON_REG_LIST_DCE_BASE() \ 33 SR(MASTER_COMM_CNTL_REG), \ 34 SR(MASTER_COMM_CMD_REG), \ 35 SR(MASTER_COMM_DATA_REG1) 36 37 #define ABM_DCE110_COMMON_REG_LIST() \ 38 ABM_COMMON_REG_LIST_DCE_BASE(), \ 39 SR(DC_ABM1_HG_SAMPLE_RATE), \ 40 SR(DC_ABM1_LS_SAMPLE_RATE), \ 41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 42 SR(DC_ABM1_HG_MISC_CTRL), \ 43 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 45 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 46 SR(BL1_PWM_USER_LEVEL), \ 47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 49 SR(BIOS_SCRATCH_2) 50 51 #define ABM_DCN10_REG_LIST(id)\ 52 ABM_COMMON_REG_LIST_DCE_BASE(), \ 53 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 54 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 55 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 56 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 57 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 58 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 59 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 60 SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 61 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 62 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 63 NBIO_SR(BIOS_SCRATCH_2) 64 65 #define ABM_DCN20_REG_LIST() \ 66 ABM_COMMON_REG_LIST_DCE_BASE(), \ 67 SR(DC_ABM1_HG_SAMPLE_RATE), \ 68 SR(DC_ABM1_LS_SAMPLE_RATE), \ 69 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 70 SR(DC_ABM1_HG_MISC_CTRL), \ 71 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 72 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 73 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 74 SR(BL1_PWM_USER_LEVEL), \ 75 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 76 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 77 NBIO_SR(BIOS_SCRATCH_2) 78 79 #define ABM_SF(reg_name, field_name, post_fix)\ 80 .field_name = reg_name ## __ ## field_name ## post_fix 81 82 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 83 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 84 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 85 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 86 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) 87 88 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ 89 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 90 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 91 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 92 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 93 ABM1_HG_VMAX_SEL, mask_sh), \ 94 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 95 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 96 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 97 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 98 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 99 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 100 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 101 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 102 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ 103 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 104 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ 105 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 106 ABM_SF(BL1_PWM_USER_LEVEL, \ 107 BL1_PWM_USER_LEVEL, mask_sh), \ 108 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 109 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 110 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 111 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 112 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 113 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 114 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 115 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 116 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 117 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 118 119 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ 120 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 121 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 122 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 123 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 124 ABM1_HG_VMAX_SEL, mask_sh), \ 125 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 126 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 127 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 128 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 129 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 130 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 131 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 132 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 133 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 134 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 135 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 136 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 137 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 138 BL1_PWM_USER_LEVEL, mask_sh), \ 139 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 140 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 141 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 142 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 143 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 144 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 145 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 146 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 147 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 148 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 149 150 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) 151 152 #define ABM_REG_FIELD_LIST(type) \ 153 type ABM1_HG_NUM_OF_BINS_SEL; \ 154 type ABM1_HG_VMAX_SEL; \ 155 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ 156 type ABM1_IPCSC_COEFF_SEL_R; \ 157 type ABM1_IPCSC_COEFF_SEL_G; \ 158 type ABM1_IPCSC_COEFF_SEL_B; \ 159 type BL1_PWM_CURRENT_ABM_LEVEL; \ 160 type BL1_PWM_TARGET_ABM_LEVEL; \ 161 type BL1_PWM_USER_LEVEL; \ 162 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ 163 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ 164 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ 165 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ 166 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ 167 type MASTER_COMM_INTERRUPT; \ 168 type MASTER_COMM_CMD_REG_BYTE0; \ 169 type MASTER_COMM_CMD_REG_BYTE1; \ 170 type MASTER_COMM_CMD_REG_BYTE2 171 172 struct dce_abm_shift { 173 ABM_REG_FIELD_LIST(uint8_t); 174 }; 175 176 struct dce_abm_mask { 177 ABM_REG_FIELD_LIST(uint32_t); 178 }; 179 180 struct dce_abm_registers { 181 uint32_t DC_ABM1_HG_SAMPLE_RATE; 182 uint32_t DC_ABM1_LS_SAMPLE_RATE; 183 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 184 uint32_t DC_ABM1_HG_MISC_CTRL; 185 uint32_t DC_ABM1_IPCSC_COEFF_SEL; 186 uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 187 uint32_t BL1_PWM_TARGET_ABM_LEVEL; 188 uint32_t BL1_PWM_USER_LEVEL; 189 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; 190 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; 191 uint32_t MASTER_COMM_CNTL_REG; 192 uint32_t MASTER_COMM_CMD_REG; 193 uint32_t MASTER_COMM_DATA_REG1; 194 uint32_t BIOS_SCRATCH_2; 195 }; 196 197 struct dce_abm { 198 struct abm base; 199 const struct dce_abm_registers *regs; 200 const struct dce_abm_shift *abm_shift; 201 const struct dce_abm_mask *abm_mask; 202 }; 203 204 struct abm *dce_abm_create( 205 struct dc_context *ctx, 206 const struct dce_abm_registers *regs, 207 const struct dce_abm_shift *abm_shift, 208 const struct dce_abm_mask *abm_mask); 209 210 void dce_abm_destroy(struct abm **abm); 211 212 #endif /* _DCE_ABM_H_ */ 213