1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce_abm.h" 29 #include "dm_services.h" 30 #include "reg_helper.h" 31 #include "fixed31_32.h" 32 #include "dc.h" 33 34 #include "atom.h" 35 36 37 #define TO_DCE_ABM(abm)\ 38 container_of(abm, struct dce_abm, base) 39 40 #define REG(reg) \ 41 (abm_dce->regs->reg) 42 43 #undef FN 44 #define FN(reg_name, field_name) \ 45 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name 46 47 #define DC_LOGGER \ 48 abm->ctx->logger 49 #define CTX \ 50 abm_dce->base.ctx 51 52 #define MCP_ABM_LEVEL_SET 0x65 53 #define MCP_ABM_PIPE_SET 0x66 54 #define MCP_BL_SET 0x67 55 56 #define MCP_DISABLE_ABM_IMMEDIATELY 255 57 58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) 59 { 60 (void)panel_inst; 61 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 62 uint32_t rampingBoundary = 0xFFFF; 63 64 if (abm->dmcu_is_running == false) 65 return true; 66 67 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 68 1, 80000); 69 70 /* set ramping boundary */ 71 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); 72 73 /* setDMCUParam_Pipe */ 74 REG_UPDATE_2(MASTER_COMM_CMD_REG, 75 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, 76 MASTER_COMM_CMD_REG_BYTE1, controller_id); 77 78 /* notifyDMCUMsg */ 79 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 80 81 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 82 1, 80000); 83 84 return true; 85 } 86 87 static void dmcu_set_backlight_level( 88 struct dce_abm *abm_dce, 89 uint32_t backlight_pwm_u16_16, 90 uint32_t frame_ramp, 91 uint32_t controller_id, 92 uint32_t panel_id) 93 { 94 unsigned int backlight_8_bit = 0; 95 uint32_t s2; 96 97 if (backlight_pwm_u16_16 & 0x10000) 98 // Check for max backlight condition 99 backlight_8_bit = 0xFF; 100 else 101 // Take MSB of fractional part since backlight is not max 102 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF; 103 104 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); 105 106 /* waitDMCUReadyForCmd */ 107 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 108 0, 1, 80000); 109 110 /* setDMCUParam_BL */ 111 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16); 112 113 /* write ramp */ 114 if (controller_id == 0) 115 frame_ramp = 0; 116 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); 117 118 /* setDMCUParam_Cmd */ 119 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); 120 121 /* notifyDMCUMsg */ 122 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 123 124 /* UpdateRequestedBacklightLevel */ 125 s2 = REG_READ(BIOS_SCRATCH_2); 126 127 s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 128 backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >> 129 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 130 s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 131 132 REG_WRITE(BIOS_SCRATCH_2, s2); 133 134 /* waitDMCUReadyForCmd */ 135 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 136 0, 1, 80000); 137 } 138 139 static void dce_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level) 140 { 141 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 142 143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); 144 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); 145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); 146 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); 147 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); 148 149 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, 150 ABM1_HG_NUM_OF_BINS_SEL, 0, 151 ABM1_HG_VMAX_SEL, 1, 152 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); 153 154 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, 155 ABM1_IPCSC_COEFF_SEL_R, 2, 156 ABM1_IPCSC_COEFF_SEL_G, 4, 157 ABM1_IPCSC_COEFF_SEL_B, 2); 158 159 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, 160 BL1_PWM_CURRENT_ABM_LEVEL, backlight); 161 162 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, 163 BL1_PWM_TARGET_ABM_LEVEL, backlight); 164 165 REG_UPDATE(BL1_PWM_USER_LEVEL, 166 BL1_PWM_USER_LEVEL, user_level); 167 168 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, 169 ABM1_LS_MIN_PIXEL_VALUE_THRES, 0, 170 ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000); 171 172 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, 173 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1, 174 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1, 175 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); 176 } 177 178 static unsigned int dce_abm_get_current_backlight(struct abm *abm) 179 { 180 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 181 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); 182 183 /* return backlight in hardware format which is unsigned 17 bits, with 184 * 1 bit integer and 16 bit fractional 185 */ 186 return backlight; 187 } 188 189 static unsigned int dce_abm_get_target_backlight(struct abm *abm) 190 { 191 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 192 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); 193 194 /* return backlight in hardware format which is unsigned 17 bits, with 195 * 1 bit integer and 16 bit fractional 196 */ 197 return backlight; 198 } 199 200 static bool dce_abm_set_level(struct abm *abm, uint32_t level) 201 { 202 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 203 204 if (abm->dmcu_is_running == false) 205 return true; 206 207 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 208 1, 80000); 209 210 /* setDMCUParam_ABMLevel */ 211 REG_UPDATE_2(MASTER_COMM_CMD_REG, 212 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, 213 MASTER_COMM_CMD_REG_BYTE2, level); 214 215 /* notifyDMCUMsg */ 216 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); 217 218 return true; 219 } 220 221 static bool dce_abm_immediate_disable(struct abm *abm, uint32_t panel_inst) 222 { 223 if (abm->dmcu_is_running == false) 224 return true; 225 226 dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY, panel_inst); 227 228 return true; 229 } 230 231 static bool dce_abm_set_backlight_level_pwm( 232 struct abm *abm, 233 unsigned int backlight_pwm_u16_16, 234 unsigned int frame_ramp, 235 unsigned int controller_id, 236 unsigned int panel_inst) 237 { 238 struct dce_abm *abm_dce = TO_DCE_ABM(abm); 239 240 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", 241 backlight_pwm_u16_16, backlight_pwm_u16_16); 242 243 dmcu_set_backlight_level(abm_dce, 244 backlight_pwm_u16_16, 245 frame_ramp, 246 controller_id, 247 panel_inst); 248 249 return true; 250 } 251 252 static const struct abm_funcs dce_funcs = { 253 .abm_init = dce_abm_init, 254 .set_abm_level = dce_abm_set_level, 255 .set_pipe = dce_abm_set_pipe, 256 .set_backlight_level_pwm = dce_abm_set_backlight_level_pwm, 257 .get_current_backlight = dce_abm_get_current_backlight, 258 .get_target_backlight = dce_abm_get_target_backlight, 259 .init_abm_config = NULL, 260 .set_abm_immediate_disable = dce_abm_immediate_disable, 261 }; 262 263 static void dce_abm_construct( 264 struct dce_abm *abm_dce, 265 struct dc_context *ctx, 266 const struct dce_abm_registers *regs, 267 const struct dce_abm_shift *abm_shift, 268 const struct dce_abm_mask *abm_mask) 269 { 270 struct abm *base = &abm_dce->base; 271 272 base->ctx = ctx; 273 base->funcs = &dce_funcs; 274 base->dmcu_is_running = false; 275 276 abm_dce->regs = regs; 277 abm_dce->abm_shift = abm_shift; 278 abm_dce->abm_mask = abm_mask; 279 } 280 281 struct abm *dce_abm_create( 282 struct dc_context *ctx, 283 const struct dce_abm_registers *regs, 284 const struct dce_abm_shift *abm_shift, 285 const struct dce_abm_mask *abm_mask) 286 { 287 struct dce_abm *abm_dce = kzalloc_obj(*abm_dce); 288 289 if (abm_dce == NULL) { 290 BREAK_TO_DEBUGGER(); 291 return NULL; 292 } 293 294 dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask); 295 296 abm_dce->base.funcs = &dce_funcs; 297 298 return &abm_dce->base; 299 } 300 301 void dce_abm_destroy(struct abm **abm) 302 { 303 struct dce_abm *abm_dce = TO_DCE_ABM(*abm); 304 305 kfree(abm_dce); 306 *abm = NULL; 307 } 308