1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct mall_stream_config { 42 /* MALL stream config to indicate if the stream is phantom or not. 43 * We will use a phantom stream to indicate that the pipe is phantom. 44 */ 45 enum mall_stream_type type; 46 struct dc_stream_state *paired_stream; // master / slave stream 47 bool subvp_limit_cursor_size; /* stream has/is using subvp limiting hw cursor support */ 48 bool cursor_size_limit_subvp; /* stream is using hw cursor config preventing subvp */ 49 }; 50 51 struct dc_stream_status { 52 int primary_otg_inst; 53 int stream_enc_inst; 54 55 /** 56 * @plane_count: Total of planes attached to a single stream 57 */ 58 int plane_count; 59 int audio_inst; 60 struct timing_sync_info timing_sync_info; 61 struct dc_plane_state *plane_states[MAX_SURFACES]; 62 bool is_abm_supported; 63 struct mall_stream_config mall_stream_config; 64 bool fpo_in_use; 65 }; 66 67 68 struct dc_writeback_info { 69 bool wb_enabled; 70 int dwb_pipe_inst; 71 struct dc_dwb_params dwb_params; 72 struct mcif_buf_params mcif_buf_params; 73 struct mcif_warmup_params mcif_warmup_params; 74 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 75 struct dc_plane_state *writeback_source_plane; 76 /* source MPCC instance. for use by internally by dc */ 77 int mpcc_inst; 78 }; 79 80 struct dc_writeback_update { 81 unsigned int num_wb_info; 82 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 83 }; 84 85 enum vertical_interrupt_ref_point { 86 START_V_UPDATE = 0, 87 START_V_SYNC, 88 INVALID_POINT 89 90 //For now, only v_update interrupt is used. 91 //START_V_BLANK, 92 //START_V_ACTIVE 93 }; 94 95 struct periodic_interrupt_config { 96 enum vertical_interrupt_ref_point ref_point; 97 int lines_offset; 98 }; 99 100 struct dc_mst_stream_bw_update { 101 bool is_increase; // is bandwidth reduced or increased 102 uint32_t mst_stream_bw; // new mst bandwidth in kbps 103 }; 104 105 union stream_update_flags { 106 struct { 107 uint32_t scaling:1; 108 uint32_t out_tf:1; 109 uint32_t out_csc:1; 110 uint32_t abm_level:1; 111 uint32_t dpms_off:1; 112 uint32_t gamut_remap:1; 113 uint32_t wb_update:1; 114 uint32_t dsc_changed : 1; 115 uint32_t mst_bw : 1; 116 uint32_t crtc_timing_adjust : 1; 117 uint32_t fams_changed : 1; 118 uint32_t scaler_sharpener : 1; 119 uint32_t sharpening_required : 1; 120 uint32_t cursor_attr : 1; 121 uint32_t cursor_pos : 1; 122 uint32_t periodic_interrupt : 1; 123 uint32_t info_frame : 1; 124 uint32_t dmdata : 1; 125 uint32_t dither : 1; 126 } bits; 127 128 uint32_t raw; 129 }; 130 131 static inline void stream_update_flags_clear(union stream_update_flags *flags) 132 { 133 flags->raw = 0; 134 } 135 136 static inline void stream_update_flags_set_full(union stream_update_flags *flags) 137 { 138 stream_update_flags_clear(flags); 139 flags->bits.scaling = 1; 140 flags->bits.out_tf = 1; 141 flags->bits.out_csc = 1; 142 flags->bits.abm_level = 1; 143 flags->bits.dpms_off = 1; 144 flags->bits.gamut_remap = 1; 145 flags->bits.wb_update = 1; 146 flags->bits.dsc_changed = 1; 147 flags->bits.mst_bw = 1; 148 flags->bits.crtc_timing_adjust = 1; 149 flags->bits.fams_changed = 1; 150 flags->bits.scaler_sharpener = 1; 151 flags->bits.sharpening_required = 1; 152 flags->bits.cursor_attr = 1; 153 flags->bits.cursor_pos = 1; 154 flags->bits.periodic_interrupt = 1; 155 flags->bits.info_frame = 1; 156 flags->bits.dmdata = 1; 157 flags->bits.dither = 1; 158 } 159 160 struct test_pattern { 161 enum dp_test_pattern type; 162 enum dp_test_pattern_color_space color_space; 163 struct link_training_settings const *p_link_settings; 164 unsigned char const *p_custom_pattern; 165 unsigned int cust_pattern_size; 166 }; 167 168 #define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR) 169 170 struct dc_stream_debug_options { 171 uint8_t force_odm_combine_segments; 172 /* 173 * When force_odm_combine_segments is non zero, allow dc to 174 * temporarily transition to ODM bypass when minimal transition state 175 * is required to prevent visual glitches showing on the screen 176 */ 177 uint8_t allow_transition_for_forced_odm; 178 }; 179 180 #define LUMINANCE_DATA_TABLE_SIZE 10 181 182 struct luminance_data { 183 bool is_valid; 184 int refresh_rate_hz[LUMINANCE_DATA_TABLE_SIZE]; 185 int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE]; 186 int flicker_criteria_milli_nits_GAMING; 187 int flicker_criteria_milli_nits_STATIC; 188 unsigned int nominal_refresh_rate; 189 unsigned int dm_max_decrease_from_nominal; 190 }; 191 192 enum dc_drr_trigger_mode { 193 DRR_TRIGGER_ON_FLIP = 0, 194 DRR_TRIGGER_ON_FLIP_AND_CURSOR, 195 }; 196 197 struct dc_stream_state { 198 // sink is deprecated, new code should not reference 199 // this pointer 200 struct dc_sink *sink; 201 202 struct dc_link *link; 203 /* For dynamic link encoder assignment, update the link encoder assigned to 204 * a stream via the volatile dc_state rather than the static dc_link. 205 */ 206 struct link_encoder *link_enc; 207 struct dc_stream_debug_options debug; 208 struct dc_panel_patch sink_patches; 209 struct dc_crtc_timing timing; 210 struct dc_crtc_timing_adjust adjust; 211 struct dc_info_packet vrr_infopacket; 212 struct dc_info_packet vsc_infopacket; 213 struct dc_info_packet vsp_infopacket; 214 struct dc_info_packet hfvsif_infopacket; 215 struct dc_info_packet vtem_infopacket; 216 struct dc_info_packet adaptive_sync_infopacket; 217 struct dc_info_packet avi_infopacket; 218 uint8_t dsc_packed_pps[128]; 219 struct rect src; /* composition area */ 220 struct rect dst; /* stream addressable area */ 221 222 struct audio_info audio_info; 223 224 struct dc_info_packet hdr_static_metadata; 225 PHYSICAL_ADDRESS_LOC dmdata_address; 226 bool use_dynamic_meta; 227 228 struct dc_transfer_func out_transfer_func; 229 struct colorspace_transform gamut_remap_matrix; 230 struct dc_csc_transform csc_color_matrix; 231 232 enum dc_color_space output_color_space; 233 enum display_content_type content_type; 234 enum dc_dither_option dither_option; 235 236 enum view_3d_format view_format; 237 238 bool use_vsc_sdp_for_colorimetry; 239 bool ignore_msa_timing_param; 240 241 /** 242 * @allow_freesync: 243 * 244 * It say if Freesync is enabled or not. 245 */ 246 bool allow_freesync; 247 248 /** 249 * @vrr_active_variable: 250 * 251 * It describes if VRR is in use. 252 */ 253 bool vrr_active_variable; 254 bool freesync_on_desktop; 255 bool vrr_active_fixed; 256 257 bool converter_disable_audio; 258 uint8_t qs_bit; 259 uint8_t qy_bit; 260 261 /* TODO: custom INFO packets */ 262 /* TODO: ABM info (DMCU) */ 263 /* TODO: CEA VIC */ 264 265 /* DMCU info */ 266 unsigned int abm_level; 267 268 struct periodic_interrupt_config periodic_interrupt; 269 270 /* from core_stream struct */ 271 struct dc_context *ctx; 272 273 /* used by DCP and FMT */ 274 struct bit_depth_reduction_params bit_depth_params; 275 struct clamping_and_pixel_encoding_params clamping; 276 277 int phy_pix_clk; 278 enum signal_type signal; 279 bool dpms_off; 280 281 void *dm_stream_context; 282 283 struct dc_cursor_attributes cursor_attributes; 284 struct dc_cursor_position cursor_position; 285 bool hw_cursor_req; 286 287 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 288 289 /* from stream struct */ 290 struct kref refcount; 291 292 struct crtc_trigger_info triggered_crtc_reset; 293 294 /* writeback */ 295 unsigned int num_wb_info; 296 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 297 const struct dc_transfer_func *func_shaper; 298 const struct dc_3dlut *lut3d_func; 299 /* Computed state bits */ 300 bool mode_changed : 1; 301 302 /* Output from DC when stream state is committed or altered 303 * DC may only access these values during: 304 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 305 * values may not change outside of those calls 306 */ 307 struct { 308 // For interrupt management, some hardware instance 309 // offsets need to be exposed to DM 310 uint8_t otg_offset; 311 } out; 312 313 bool apply_edp_fast_boot_optimization; 314 bool apply_seamless_boot_optimization; 315 uint32_t apply_boot_odm_mode; 316 317 uint32_t stream_id; 318 319 struct test_pattern test_pattern; 320 union stream_update_flags update_flags; 321 322 bool has_non_synchronizable_pclk; 323 bool vblank_synchronized; 324 bool is_phantom; 325 326 struct luminance_data lumin_data; 327 bool scaler_sharpener_update; 328 bool sharpening_required; 329 330 enum dc_drr_trigger_mode drr_trigger_mode; 331 332 bool firmware_controlled_hdr_info_packet; 333 }; 334 335 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 336 337 struct dc_stream_update { 338 struct dc_stream_state *stream; 339 340 struct rect src; 341 struct rect dst; 342 struct dc_transfer_func *out_transfer_func; 343 struct dc_info_packet *hdr_static_metadata; 344 unsigned int *abm_level; 345 346 struct periodic_interrupt_config *periodic_interrupt; 347 348 struct dc_info_packet *vrr_infopacket; 349 struct dc_info_packet *vsc_infopacket; 350 struct dc_info_packet *vsp_infopacket; 351 struct dc_info_packet *hfvsif_infopacket; 352 struct dc_info_packet *vtem_infopacket; 353 struct dc_info_packet *adaptive_sync_infopacket; 354 struct dc_info_packet *avi_infopacket; 355 356 bool *dpms_off; 357 bool integer_scaling_update; 358 bool *allow_freesync; 359 bool *vrr_active_variable; 360 bool *vrr_active_fixed; 361 362 struct colorspace_transform *gamut_remap; 363 enum dc_color_space *output_color_space; 364 enum dc_dither_option *dither_option; 365 366 struct dc_csc_transform *output_csc_transform; 367 368 struct dc_writeback_update *wb_update; 369 struct dc_dsc_config *dsc_config; 370 struct dc_mst_stream_bw_update *mst_bw_update; 371 struct dc_transfer_func *func_shaper; 372 struct dc_3dlut *lut3d_func; 373 374 struct test_pattern *pending_test_pattern; 375 struct dc_crtc_timing_adjust *crtc_timing_adjust; 376 377 struct dc_cursor_attributes *cursor_attributes; 378 struct dc_cursor_position *cursor_position; 379 bool *hw_cursor_req; 380 bool *scaler_sharpener_update; 381 bool *sharpening_required; 382 383 enum dc_drr_trigger_mode *drr_trigger_mode; 384 }; 385 386 bool dc_is_stream_unchanged( 387 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 388 bool dc_is_stream_scaling_unchanged( 389 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 390 391 /* 392 * Setup stream attributes if no stream updates are provided 393 * there will be no impact on the stream parameters 394 * 395 * Set up surface attributes and associate to a stream 396 * The surfaces parameter is an absolute set of all surface active for the stream. 397 * If no surfaces are provided, the stream will be blanked; no memory read. 398 * Any flip related attribute changes must be done through this interface. 399 * 400 * After this call: 401 * Surfaces attributes are programmed and configured to be composed into stream. 402 * This does not trigger a flip. No surface address is programmed. 403 * 404 */ 405 bool dc_update_planes_and_stream(struct dc *dc, 406 struct dc_surface_update *surface_updates, int surface_count, 407 struct dc_stream_state *dc_stream, 408 struct dc_stream_update *stream_update); 409 410 struct dc_state_update; 411 412 413 /* 414 * Set up surface attributes and associate to a stream 415 * The surfaces parameter is an absolute set of all surface active for the stream. 416 * If no surfaces are provided, the stream will be blanked; no memory read. 417 * Any flip related attribute changes must be done through this interface. 418 * 419 * After this call: 420 * Surfaces attributes are programmed and configured to be composed into stream. 421 * This does not trigger a flip. No surface address is programmed. 422 */ 423 void dc_commit_updates_for_stream(struct dc *dc, 424 struct dc_surface_update *srf_updates, 425 int surface_count, 426 struct dc_stream_state *stream, 427 struct dc_stream_update *stream_update, 428 struct dc_state *state); 429 /* 430 * Log the current stream state. 431 */ 432 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 433 434 uint8_t dc_get_current_stream_count(struct dc *dc); 435 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 436 437 /* 438 * Return the current frame counter. 439 */ 440 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 441 442 /* 443 * Send dp sdp message. 444 */ 445 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 446 const uint8_t *custom_sdp_message, 447 unsigned int sdp_message_size); 448 449 /* TODO: Return parsed values rather than direct register read 450 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 451 * being refactored properly to be dce-specific 452 */ 453 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 454 uint32_t *v_blank_start, 455 uint32_t *v_blank_end, 456 uint32_t *h_position, 457 uint32_t *v_position); 458 459 bool dc_stream_add_writeback(struct dc *dc, 460 struct dc_stream_state *stream, 461 struct dc_writeback_info *wb_info); 462 463 bool dc_stream_fc_disable_writeback(struct dc *dc, 464 struct dc_stream_state *stream, 465 uint32_t dwb_pipe_inst); 466 467 bool dc_stream_remove_writeback(struct dc *dc, 468 struct dc_stream_state *stream, 469 uint32_t dwb_pipe_inst); 470 471 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 472 struct dc_state *state, 473 struct dc_stream_state *stream); 474 475 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 476 477 bool dc_stream_set_dynamic_metadata(struct dc *dc, 478 struct dc_stream_state *stream, 479 struct dc_dmdata_attributes *dmdata_attr); 480 481 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 482 483 /* 484 * Enable stereo when commit_streams is not required, 485 * for example, frame alternate. 486 */ 487 void dc_enable_stereo( 488 struct dc *dc, 489 struct dc_state *context, 490 struct dc_stream_state *streams[], 491 uint8_t stream_count); 492 493 /* Triggers multi-stream synchronization. */ 494 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 495 496 /* Shim: packs args into dc_state_update and calls dc_check_state_update(). */ 497 struct dc_update_descriptor dc_check_update_surfaces_for_stream( 498 const struct dc_check_config *check_config, 499 struct dc_surface_update *updates, 500 int surface_count, 501 struct dc_stream_update *stream_update); 502 503 struct dc_link *dc_stream_get_link( 504 const struct dc_stream_state *dc_stream); 505 506 /** 507 * Create a new default stream for the requested sink 508 */ 509 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 510 511 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 512 513 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 514 515 void dc_stream_retain(struct dc_stream_state *dc_stream); 516 void dc_stream_release(struct dc_stream_state *dc_stream); 517 518 struct dc_stream_status *dc_stream_get_status(struct dc_stream_state *dc_stream); 519 const struct dc_stream_status *dc_stream_get_status_const(const struct dc_stream_state *dc_stream); 520 521 /******************************************************************************* 522 * Cursor interfaces - To manages the cursor within a stream 523 ******************************************************************************/ 524 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 525 526 void program_cursor_attributes( 527 struct dc *dc, 528 struct dc_stream_state *stream); 529 530 void program_cursor_position( 531 struct dc *dc, 532 struct dc_stream_state *stream); 533 534 bool dc_stream_check_cursor_attributes( 535 const struct dc_stream_state *stream, 536 struct dc_state *state, 537 const struct dc_cursor_attributes *attributes); 538 539 bool dc_stream_set_cursor_attributes( 540 struct dc_stream_state *stream, 541 const struct dc_cursor_attributes *attributes); 542 543 bool dc_stream_program_cursor_attributes( 544 struct dc_stream_state *stream, 545 const struct dc_cursor_attributes *attributes); 546 547 bool dc_stream_set_cursor_position( 548 struct dc_stream_state *stream, 549 const struct dc_cursor_position *position); 550 551 bool dc_stream_program_cursor_position( 552 struct dc_stream_state *stream, 553 const struct dc_cursor_position *position); 554 555 556 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 557 struct dc_stream_state *stream, 558 struct dc_crtc_timing_adjust *adjust); 559 560 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 561 struct dc_stream_state *stream, 562 uint32_t *refresh_rate); 563 564 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 565 bool dc_stream_forward_crc_window(struct dc_stream_state *stream, 566 struct rect *rect, 567 uint8_t phy_id, 568 bool is_stop); 569 570 bool dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream, 571 struct crc_window *window, 572 uint8_t phy_id, 573 bool stop); 574 #endif 575 576 bool dc_stream_configure_crc(struct dc *dc, 577 struct dc_stream_state *stream, 578 struct crc_params *crc_window, 579 bool enable, 580 bool continuous, 581 uint8_t idx, 582 bool reset, 583 enum crc_poly_mode crc_poly_mode); 584 585 bool dc_stream_get_crc(struct dc *dc, 586 struct dc_stream_state *stream, 587 uint8_t idx, 588 uint32_t *r_cr, 589 uint32_t *g_y, 590 uint32_t *b_cb); 591 592 void dc_stream_set_static_screen_params(struct dc *dc, 593 struct dc_stream_state **stream, 594 int num_streams, 595 const struct dc_static_screen_params *params); 596 597 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 598 enum dc_dynamic_expansion option); 599 600 void dc_stream_set_dither_option(struct dc_stream_state *stream, 601 enum dc_dither_option option); 602 603 bool dc_stream_set_gamut_remap(struct dc *dc, 604 const struct dc_stream_state *stream); 605 606 bool dc_stream_program_csc_matrix(struct dc *dc, 607 struct dc_stream_state *stream); 608 609 struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream( 610 const struct dc *dc, 611 const struct dc_stream_state *stream, 612 bool allocate_one); 613 614 void dc_stream_release_3dlut_for_stream( 615 const struct dc *dc, 616 const struct dc_stream_state *stream); 617 618 void dc_stream_init_rmcm_3dlut(struct dc *dc); 619 620 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); 621 622 void dc_dmub_update_dirty_rect(struct dc *dc, 623 int surface_count, 624 struct dc_stream_state *stream, 625 const struct dc_surface_update *srf_updates, 626 struct dc_state *context); 627 628 bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream); 629 bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream); 630 631 #endif /* DC_STREAM_H_ */ 632