xref: /linux/drivers/gpu/drm/amd/display/dc/dc_helper.c (revision a4a755c422242c27cb0f7900ac00cf33ac17b1ce)
1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 /*
24  * dc_helper.c
25  *
26  *  Created on: Aug 30, 2016
27  *      Author: agrodzov
28  */
29 
30 #include <linux/delay.h>
31 #include <linux/stdarg.h>
32 
33 #include "dm_services.h"
34 
35 #include "dc.h"
36 #include "dc_dmub_srv.h"
37 #include "reg_helper.h"
38 
39 #define DC_LOGGER \
40 	ctx->logger
41 
42 static inline void submit_dmub_read_modify_write(
43 	struct dc_reg_helper_state *offload,
44 	const struct dc_context *ctx)
45 {
46 	struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
47 
48 	offload->should_burst_write =
49 			(offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1));
50 	cmd_buf->header.payload_bytes =
51 			sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count;
52 
53 	dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
54 
55 	memset(cmd_buf, 0, sizeof(*cmd_buf));
56 
57 	offload->reg_seq_count = 0;
58 	offload->same_addr_count = 0;
59 }
60 
61 static inline void submit_dmub_burst_write(
62 	struct dc_reg_helper_state *offload,
63 	const struct dc_context *ctx)
64 {
65 	struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
66 
67 	cmd_buf->header.payload_bytes =
68 			sizeof(uint32_t) * offload->reg_seq_count;
69 
70 	dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
71 
72 	memset(cmd_buf, 0, sizeof(*cmd_buf));
73 
74 	offload->reg_seq_count = 0;
75 }
76 
77 static inline void submit_dmub_reg_wait(
78 		struct dc_reg_helper_state *offload,
79 		const struct dc_context *ctx)
80 {
81 	struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
82 
83 	dc_wake_and_execute_dmub_cmd(ctx, &offload->cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);
84 
85 	memset(cmd_buf, 0, sizeof(*cmd_buf));
86 	offload->reg_seq_count = 0;
87 }
88 
89 struct dc_reg_value_masks {
90 	uint32_t value;
91 	uint32_t mask;
92 };
93 
94 struct dc_reg_sequence {
95 	uint32_t addr;
96 	struct dc_reg_value_masks value_masks;
97 };
98 
99 static inline void set_reg_field_value_masks(
100 	struct dc_reg_value_masks *field_value_mask,
101 	uint32_t value,
102 	uint32_t mask,
103 	uint8_t shift)
104 {
105 	ASSERT(mask != 0);
106 
107 	field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift));
108 	field_value_mask->mask = field_value_mask->mask | mask;
109 }
110 
111 static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
112 		uint32_t addr, int n,
113 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
114 		va_list ap)
115 {
116 	uint32_t shift, mask, field_value;
117 	int i = 1;
118 
119 	/* gather all bits value/mask getting updated in this register */
120 	set_reg_field_value_masks(field_value_mask,
121 			field_value1, mask1, shift1);
122 
123 	while (i < n) {
124 		shift = va_arg(ap, uint32_t);
125 		mask = va_arg(ap, uint32_t);
126 		field_value = va_arg(ap, uint32_t);
127 
128 		set_reg_field_value_masks(field_value_mask,
129 				field_value, mask, shift);
130 		i++;
131 	}
132 }
133 
134 static void dmub_flush_buffer_execute(
135 		struct dc_reg_helper_state *offload,
136 		const struct dc_context *ctx)
137 {
138 	submit_dmub_read_modify_write(offload, ctx);
139 }
140 
141 static void dmub_flush_burst_write_buffer_execute(
142 		struct dc_reg_helper_state *offload,
143 		const struct dc_context *ctx)
144 {
145 	submit_dmub_burst_write(offload, ctx);
146 }
147 
148 static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
149 		uint32_t reg_val)
150 {
151 	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
152 	struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
153 
154 	/* flush command if buffer is full */
155 	if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX)
156 		dmub_flush_burst_write_buffer_execute(offload, ctx);
157 
158 	if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE &&
159 			addr != cmd_buf->addr) {
160 		dmub_flush_burst_write_buffer_execute(offload, ctx);
161 		return false;
162 	}
163 
164 	cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
165 	cmd_buf->header.sub_type = 0;
166 	cmd_buf->addr = addr;
167 	cmd_buf->write_values[offload->reg_seq_count] = reg_val;
168 	offload->reg_seq_count++;
169 
170 	return true;
171 }
172 
173 static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
174 		struct dc_reg_value_masks *field_value_mask)
175 {
176 	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
177 	struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
178 	struct dmub_cmd_read_modify_write_sequence *seq;
179 
180 	/* flush command if buffer is full */
181 	if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE &&
182 			offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
183 		dmub_flush_buffer_execute(offload, ctx);
184 
185 	if (offload->should_burst_write) {
186 		if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value))
187 			return field_value_mask->value;
188 		else
189 			offload->should_burst_write = false;
190 	}
191 
192 	/* pack commands */
193 	cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
194 	cmd_buf->header.sub_type = 0;
195 	seq = &cmd_buf->seq[offload->reg_seq_count];
196 
197 	if (offload->reg_seq_count) {
198 		if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr)
199 			offload->same_addr_count++;
200 		else
201 			offload->same_addr_count = 0;
202 	}
203 
204 	seq->addr = addr;
205 	seq->modify_mask = field_value_mask->mask;
206 	seq->modify_value = field_value_mask->value;
207 	offload->reg_seq_count++;
208 
209 	return field_value_mask->value;
210 }
211 
212 static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
213 		uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)
214 {
215 	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
216 	struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
217 
218 	cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
219 	cmd_buf->header.sub_type = 0;
220 	cmd_buf->reg_wait.addr = addr;
221 	cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
222 	cmd_buf->reg_wait.mask = mask;
223 	cmd_buf->reg_wait.time_out_us = time_out_us;
224 }
225 
226 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
227 		uint32_t addr, int n,
228 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
229 		...)
230 {
231 	struct dc_reg_value_masks field_value_mask = {0};
232 	uint32_t reg_val;
233 	va_list ap;
234 
235 	va_start(ap, field_value1);
236 
237 	set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
238 			field_value1, ap);
239 
240 	va_end(ap);
241 
242 	if (ctx->dmub_srv &&
243 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress)
244 		return dmub_reg_value_pack(ctx, addr, &field_value_mask);
245 		/* todo: return void so we can decouple code running in driver from register states */
246 
247 	/* mmio write directly */
248 	reg_val = dm_read_reg(ctx, addr);
249 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
250 	dm_write_reg(ctx, addr, reg_val);
251 	return reg_val;
252 }
253 
254 uint32_t generic_reg_set_ex(const struct dc_context *ctx,
255 		uint32_t addr, uint32_t reg_val, int n,
256 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
257 		...)
258 {
259 	struct dc_reg_value_masks field_value_mask = {0};
260 	va_list ap;
261 
262 	va_start(ap, field_value1);
263 
264 	set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
265 			field_value1, ap);
266 
267 	va_end(ap);
268 
269 	/* mmio write directly */
270 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
271 
272 	if (ctx->dmub_srv &&
273 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
274 		return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
275 		/* todo: return void so we can decouple code running in driver from register states */
276 	}
277 
278 	dm_write_reg(ctx, addr, reg_val);
279 	return reg_val;
280 }
281 
282 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
283 		uint8_t shift, uint32_t mask, uint32_t *field_value)
284 {
285 	uint32_t reg_val = dm_read_reg(ctx, addr);
286 	*field_value = get_reg_field_value_ex(reg_val, mask, shift);
287 	return reg_val;
288 }
289 
290 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
291 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
292 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
293 {
294 	uint32_t reg_val = dm_read_reg(ctx, addr);
295 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
296 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
297 	return reg_val;
298 }
299 
300 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
301 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
302 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
303 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
304 {
305 	uint32_t reg_val = dm_read_reg(ctx, addr);
306 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
307 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
308 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
309 	return reg_val;
310 }
311 
312 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
313 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
314 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
315 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
316 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
317 {
318 	uint32_t reg_val = dm_read_reg(ctx, addr);
319 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
320 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
321 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
322 	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
323 	return reg_val;
324 }
325 
326 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
327 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
328 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
329 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
330 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
331 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
332 {
333 	uint32_t reg_val = dm_read_reg(ctx, addr);
334 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
335 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
336 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
337 	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
338 	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
339 	return reg_val;
340 }
341 
342 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
343 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
344 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
345 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
346 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
347 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
348 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
349 {
350 	uint32_t reg_val = dm_read_reg(ctx, addr);
351 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
352 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
353 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
354 	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
355 	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
356 	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
357 	return reg_val;
358 }
359 
360 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
361 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
362 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
363 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
364 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
365 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
366 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
367 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
368 {
369 	uint32_t reg_val = dm_read_reg(ctx, addr);
370 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
371 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
372 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
373 	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
374 	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
375 	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
376 	*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
377 	return reg_val;
378 }
379 
380 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
381 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
382 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
383 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
384 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
385 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
386 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
387 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
388 		uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
389 {
390 	uint32_t reg_val = dm_read_reg(ctx, addr);
391 	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
392 	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
393 	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
394 	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
395 	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
396 	*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
397 	*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
398 	*field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
399 	return reg_val;
400 }
401 /* note:  va version of this is pretty bad idea, since there is a output parameter pass by pointer
402  * compiler won't be able to check for size match and is prone to stack corruption type of bugs
403 
404 uint32_t generic_reg_get(const struct dc_context *ctx,
405 		uint32_t addr, int n, ...)
406 {
407 	uint32_t shift, mask;
408 	uint32_t *field_value;
409 	uint32_t reg_val;
410 	int i = 0;
411 
412 	reg_val = dm_read_reg(ctx, addr);
413 
414 	va_list ap;
415 	va_start(ap, n);
416 
417 	while (i < n) {
418 		shift = va_arg(ap, uint32_t);
419 		mask = va_arg(ap, uint32_t);
420 		field_value = va_arg(ap, uint32_t *);
421 
422 		*field_value = get_reg_field_value_ex(reg_val, mask, shift);
423 		i++;
424 	}
425 
426 	va_end(ap);
427 
428 	return reg_val;
429 }
430 */
431 
432 void generic_reg_wait(const struct dc_context *ctx,
433 	uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
434 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
435 	const char *func_name, int line)
436 {
437 	uint32_t field_value;
438 	uint32_t reg_val;
439 	int i;
440 
441 	if (ctx->dmub_srv &&
442 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
443 		dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
444 				delay_between_poll_us * time_out_num_tries);
445 		return;
446 	}
447 
448 	/*
449 	 * Something is terribly wrong if time out is > 3000ms.
450 	 * 3000ms is the maximum time needed for SMU to pass values back.
451 	 * This value comes from experiments.
452 	 *
453 	 */
454 	ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
455 
456 	for (i = 0; i <= time_out_num_tries; i++) {
457 		if (i) {
458 			if (delay_between_poll_us >= 1000)
459 				msleep(delay_between_poll_us/1000);
460 			else if (delay_between_poll_us > 0)
461 				udelay(delay_between_poll_us);
462 		}
463 
464 		reg_val = dm_read_reg(ctx, addr);
465 
466 		field_value = get_reg_field_value_ex(reg_val, mask, shift);
467 
468 		if (field_value == condition_value) {
469 			if (i * delay_between_poll_us > 1000)
470 				DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n",
471 						delay_between_poll_us * i / 1000,
472 						func_name, line);
473 			return;
474 		}
475 	}
476 
477 	DC_LOG_WARNING("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
478 			delay_between_poll_us, time_out_num_tries,
479 			func_name, line);
480 
481 	BREAK_TO_DEBUGGER();
482 }
483 
484 void generic_write_indirect_reg(const struct dc_context *ctx,
485 		uint32_t addr_index, uint32_t addr_data,
486 		uint32_t index, uint32_t data)
487 {
488 	dm_write_reg(ctx, addr_index, index);
489 	dm_write_reg(ctx, addr_data, data);
490 }
491 
492 uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
493 		uint32_t addr_index, uint32_t addr_data,
494 		uint32_t index)
495 {
496 	uint32_t value = 0;
497 
498 	// when reg read, there should not be any offload.
499 	if (ctx->dmub_srv &&
500 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
501 		ASSERT(false);
502 	}
503 
504 	dm_write_reg(ctx, addr_index, index);
505 	value = dm_read_reg(ctx, addr_data);
506 
507 	return value;
508 }
509 
510 uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
511 		uint32_t addr_index, uint32_t addr_data,
512 		uint32_t index, int n,
513 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
514 		...)
515 {
516 	uint32_t shift, mask, *field_value;
517 	uint32_t value = 0;
518 	int i = 1;
519 
520 	va_list ap;
521 
522 	va_start(ap, field_value1);
523 
524 	value = generic_read_indirect_reg(ctx, addr_index, addr_data, index);
525 	*field_value1 = get_reg_field_value_ex(value, mask1, shift1);
526 
527 	while (i < n) {
528 		shift = va_arg(ap, uint32_t);
529 		mask = va_arg(ap, uint32_t);
530 		field_value = va_arg(ap, uint32_t *);
531 
532 		*field_value = get_reg_field_value_ex(value, mask, shift);
533 		i++;
534 	}
535 
536 	va_end(ap);
537 
538 	return value;
539 }
540 
541 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
542 		uint32_t addr_index, uint32_t addr_data,
543 		uint32_t index, uint32_t reg_val, int n,
544 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
545 		...)
546 {
547 	uint32_t shift, mask, field_value;
548 	int i = 1;
549 
550 	va_list ap;
551 
552 	va_start(ap, field_value1);
553 
554 	reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
555 
556 	while (i < n) {
557 		shift = va_arg(ap, uint32_t);
558 		mask = va_arg(ap, uint32_t);
559 		field_value = va_arg(ap, uint32_t);
560 
561 		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
562 		i++;
563 	}
564 
565 	generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val);
566 	va_end(ap);
567 
568 	return reg_val;
569 }
570 
571 
572 uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
573 		uint32_t index, uint32_t reg_val, int n,
574 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
575 		...)
576 {
577 	uint32_t shift, mask, field_value;
578 	int i = 1;
579 
580 	va_list ap;
581 
582 	va_start(ap, field_value1);
583 
584 	reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
585 
586 	while (i < n) {
587 		shift = va_arg(ap, uint32_t);
588 		mask = va_arg(ap, uint32_t);
589 		field_value = va_arg(ap, uint32_t);
590 
591 		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
592 		i++;
593 	}
594 
595 	dm_write_index_reg(ctx, CGS_IND_REG__PCIE, index, reg_val);
596 	va_end(ap);
597 
598 	return reg_val;
599 }
600 
601 uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
602 		uint32_t index, int n,
603 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
604 		...)
605 {
606 	uint32_t shift, mask, *field_value;
607 	uint32_t value = 0;
608 	int i = 1;
609 
610 	va_list ap;
611 
612 	va_start(ap, field_value1);
613 
614 	value = dm_read_index_reg(ctx, CGS_IND_REG__PCIE, index);
615 	*field_value1 = get_reg_field_value_ex(value, mask1, shift1);
616 
617 	while (i < n) {
618 		shift = va_arg(ap, uint32_t);
619 		mask = va_arg(ap, uint32_t);
620 		field_value = va_arg(ap, uint32_t *);
621 
622 		*field_value = get_reg_field_value_ex(value, mask, shift);
623 		i++;
624 	}
625 
626 	va_end(ap);
627 
628 	return value;
629 }
630 
631 void reg_sequence_start_gather(const struct dc_context *ctx)
632 {
633 	/* if reg sequence is supported and enabled, set flag to
634 	 * indicate we want to have REG_SET, REG_UPDATE macro build
635 	 * reg sequence command buffer rather than MMIO directly.
636 	 */
637 
638 	if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {
639 		struct dc_reg_helper_state *offload =
640 			&ctx->dmub_srv->reg_helper_offload;
641 
642 		/* caller sequence mismatch.  need to debug caller.  offload will not work!!! */
643 		ASSERT(!offload->gather_in_progress);
644 
645 		offload->gather_in_progress = true;
646 	}
647 }
648 
649 void reg_sequence_start_execute(const struct dc_context *ctx)
650 {
651 	struct dc_reg_helper_state *offload;
652 
653 	if (!ctx->dmub_srv)
654 		return;
655 
656 	offload = &ctx->dmub_srv->reg_helper_offload;
657 
658 	if (offload && offload->gather_in_progress) {
659 		offload->gather_in_progress = false;
660 		offload->should_burst_write = false;
661 		switch (offload->cmd_data.cmd_common.header.type) {
662 		case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
663 			submit_dmub_read_modify_write(offload, ctx);
664 			break;
665 		case DMUB_CMD__REG_REG_WAIT:
666 			submit_dmub_reg_wait(offload, ctx);
667 			break;
668 		case DMUB_CMD__REG_SEQ_BURST_WRITE:
669 			submit_dmub_burst_write(offload, ctx);
670 			break;
671 		default:
672 			return;
673 		}
674 	}
675 }
676 
677 void reg_sequence_wait_done(const struct dc_context *ctx)
678 {
679 	/* callback to DM to poll for last submission done*/
680 	struct dc_reg_helper_state *offload;
681 
682 	if (!ctx->dmub_srv)
683 		return;
684 
685 	offload = &ctx->dmub_srv->reg_helper_offload;
686 
687 	if (offload &&
688 	    ctx->dc->debug.dmub_offload_enabled &&
689 	    !ctx->dc->debug.dmcub_emulation) {
690 		dc_dmub_srv_wait_idle(ctx->dmub_srv);
691 	}
692 }
693 
694 char *dce_version_to_string(const int version)
695 {
696 	switch (version) {
697 	case DCE_VERSION_8_0:
698 		return "DCE 8.0";
699 	case DCE_VERSION_8_1:
700 		return "DCE 8.1";
701 	case DCE_VERSION_8_3:
702 		return "DCE 8.3";
703 	case DCE_VERSION_10_0:
704 		return "DCE 10.0";
705 	case DCE_VERSION_11_0:
706 		return "DCE 11.0";
707 	case DCE_VERSION_11_2:
708 		return "DCE 11.2";
709 	case DCE_VERSION_11_22:
710 		return "DCE 11.22";
711 	case DCE_VERSION_12_0:
712 		return "DCE 12.0";
713 	case DCE_VERSION_12_1:
714 		return "DCE 12.1";
715 	case DCN_VERSION_1_0:
716 		return "DCN 1.0";
717 	case DCN_VERSION_1_01:
718 		return "DCN 1.0.1";
719 	case DCN_VERSION_2_0:
720 		return "DCN 2.0";
721 	case DCN_VERSION_2_1:
722 		return "DCN 2.1";
723 	case DCN_VERSION_2_01:
724 		return "DCN 2.0.1";
725 	case DCN_VERSION_3_0:
726 		return "DCN 3.0";
727 	case DCN_VERSION_3_01:
728 		return "DCN 3.0.1";
729 	case DCN_VERSION_3_02:
730 		return "DCN 3.0.2";
731 	case DCN_VERSION_3_03:
732 		return "DCN 3.0.3";
733 	case DCN_VERSION_3_1:
734 		return "DCN 3.1";
735 	case DCN_VERSION_3_14:
736 		return "DCN 3.1.4";
737 	case DCN_VERSION_3_15:
738 		return "DCN 3.1.5";
739 	case DCN_VERSION_3_16:
740 		return "DCN 3.1.6";
741 	case DCN_VERSION_3_2:
742 		return "DCN 3.2";
743 	case DCN_VERSION_3_21:
744 		return "DCN 3.2.1";
745 	case DCN_VERSION_3_5:
746 		return "DCN 3.5";
747 	case DCN_VERSION_3_51:
748 		return "DCN 3.5.1";
749 	case DCN_VERSION_4_01:
750 		return "DCN 4.0.1";
751 	default:
752 		return "Unknown";
753 	}
754 }
755