1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_DC_SRV_H_ 27 #define _DMUB_DC_SRV_H_ 28 29 #include "dm_services_types.h" 30 #include "dmub/dmub_srv.h" 31 32 struct dmub_srv; 33 struct dc; 34 struct pipe_ctx; 35 struct dc_crtc_timing_adjust; 36 struct dc_crtc_timing; 37 struct dc_state; 38 struct dc_surface_update; 39 40 struct dc_reg_helper_state { 41 bool gather_in_progress; 42 uint32_t same_addr_count; 43 bool should_burst_write; 44 union dmub_rb_cmd cmd_data; 45 unsigned int reg_seq_count; 46 }; 47 48 struct dc_dmub_srv { 49 struct dmub_srv *dmub; 50 struct dc_reg_helper_state reg_helper_offload; 51 52 struct dc_context *ctx; 53 void *dm; 54 55 int32_t idle_exit_counter; 56 union dmub_shared_state_ips_driver_signals driver_signals; 57 bool idle_allowed; 58 bool needs_idle_wake; 59 }; 60 61 bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv); 62 63 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv); 64 65 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 66 unsigned int count, 67 union dmub_rb_cmd *cmd_list); 68 69 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 70 enum dm_dmub_wait_type wait_type, 71 union dmub_rb_cmd *cmd_list); 72 73 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 74 75 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type); 76 77 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 78 unsigned int stream_mask); 79 80 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv); 81 82 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry); 83 84 void dc_dmub_trace_event_control(struct dc *dc, bool enable); 85 86 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max); 87 88 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst); 89 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context); 90 91 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv); 92 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx); 93 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv); 94 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv); 95 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); 96 97 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); 98 99 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable); 100 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); 101 102 void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx); 103 bool dc_dmub_check_min_version(struct dmub_srv *srv); 104 105 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc); 106 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index); 107 108 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait); 109 110 void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle); 111 112 /** 113 * dc_dmub_srv_set_power_state() - Sets the power state for DMUB service. 114 * 115 * Controls whether messaging the DMCUB or interfacing with it via HW register 116 * interaction is permittable. 117 * 118 * @dc_dmub_srv - The DC DMUB service pointer 119 * @power_state - the DC power state 120 */ 121 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state); 122 123 /** 124 * dc_dmub_srv_notify_fw_dc_power_state() - Notifies firmware of the DC power state. 125 * 126 * Differs from dc_dmub_srv_set_power_state in that it needs to access HW in order 127 * to message DMCUB of the state transition. Should come after the D0 exit and 128 * before D3 set power state. 129 * 130 * @dc_dmub_srv - The DC DMUB service pointer 131 * @power_state - the DC power state 132 */ 133 void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, 134 enum dc_acpi_cm_power_state power_state); 135 136 /** 137 * @dc_dmub_srv_should_detect() - Checks if link detection is required. 138 * 139 * While in idle power states we may need driver to manually redetect in 140 * the case of a missing hotplug. Should be called from a polling timer. 141 * 142 * Return: true if redetection is required. 143 */ 144 bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv); 145 146 /** 147 * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution. 148 * 149 * Refer to dc_wake_and_execute_dmub_cmd_list() for usage and limitations, 150 * This function is a convenience wrapper for a single command execution. 151 * 152 * @ctx: DC context 153 * @cmd: The command to send/receive 154 * @wait_type: The wait behavior for the execution 155 * 156 * Return: true on command submission success, false otherwise 157 */ 158 bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, 159 enum dm_dmub_wait_type wait_type); 160 161 /** 162 * dc_wake_and_execute_dmub_cmd_list() - Wrapper for DMUB command list execution. 163 * 164 * If the DMCUB hardware was asleep then it wakes the DMUB before 165 * executing the command and attempts to re-enter if the command 166 * submission was successful. 167 * 168 * This should be the preferred command submission interface provided 169 * the DC lock is acquired. 170 * 171 * Entry/exit out of idle power optimizations would need to be 172 * manually performed otherwise through dc_allow_idle_optimizations(). 173 * 174 * @ctx: DC context 175 * @count: Number of commands to send/receive 176 * @cmd: Array of commands to send 177 * @wait_type: The wait behavior for the execution 178 * 179 * Return: true on command submission success, false otherwise 180 */ 181 bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, 182 union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 183 184 /** 185 * dc_wake_and_execute_gpint() 186 * 187 * @ctx: DC context 188 * @command_code: The command ID to send to DMCUB 189 * @param: The parameter to message DMCUB 190 * @response: Optional response out value - may be NULL. 191 * @wait_type: The wait behavior for the execution 192 */ 193 bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 194 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type); 195 196 void dc_dmub_srv_fams2_update_config(struct dc *dc, 197 struct dc_state *context, 198 bool enable); 199 void dc_dmub_srv_fams2_drr_update(struct dc *dc, 200 uint32_t tg_inst, 201 uint32_t vtotal_min, 202 uint32_t vtotal_max, 203 uint32_t vtotal_mid, 204 uint32_t vtotal_mid_frame_num, 205 bool program_manual_trigger); 206 void dc_dmub_srv_fams2_passthrough_flip( 207 struct dc *dc, 208 struct dc_state *state, 209 struct dc_stream_state *stream, 210 struct dc_surface_update *srf_updates, 211 int surface_count); 212 213 bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv); 214 bool dmub_lsdma_send_linear_copy_command( 215 struct dc_dmub_srv *dc_dmub_srv, 216 uint64_t src_addr, 217 uint64_t dst_addr, 218 uint32_t count); 219 220 struct lsdma_linear_sub_window_copy_params { 221 uint32_t src_lo; 222 uint32_t src_hi; 223 224 uint32_t dst_lo; 225 uint32_t dst_hi; 226 227 uint32_t src_x : 16; 228 uint32_t src_y : 16; 229 230 uint32_t dst_x : 16; 231 uint32_t dst_y : 16; 232 233 uint32_t rect_x : 16; 234 uint32_t rect_y : 16; 235 236 uint32_t src_pitch : 16; 237 uint32_t dst_pitch : 16; 238 239 uint32_t src_slice_pitch; 240 uint32_t dst_slice_pitch; 241 242 uint32_t tmz : 1; 243 uint32_t element_size : 3; 244 uint32_t src_cache_policy : 3; 245 uint32_t dst_cache_policy : 3; 246 uint32_t padding : 22; 247 }; 248 249 bool dmub_lsdma_send_linear_sub_window_copy_command( 250 struct dc_dmub_srv *dc_dmub_srv, 251 struct lsdma_linear_sub_window_copy_params copy_data 252 ); 253 bool dmub_lsdma_send_pio_copy_command( 254 struct dc_dmub_srv *dc_dmub_srv, 255 uint64_t src_addr, 256 uint64_t dst_addr, 257 uint32_t byte_count, 258 uint32_t overlap_disable); 259 bool dmub_lsdma_send_pio_constfill_command( 260 struct dc_dmub_srv *dc_dmub_srv, 261 uint64_t dst_addr, 262 uint32_t byte_count, 263 uint32_t data); 264 265 struct lsdma_send_tiled_to_tiled_copy_command_params { 266 uint64_t src_addr; 267 uint64_t dst_addr; 268 269 uint32_t src_x : 16; 270 uint32_t src_y : 16; 271 272 uint32_t dst_x : 16; 273 uint32_t dst_y : 16; 274 275 uint32_t src_width : 16; 276 uint32_t dst_width : 16; 277 278 uint32_t rect_x : 16; 279 uint32_t rect_y : 16; 280 281 uint32_t src_height : 16; 282 uint32_t dst_height : 16; 283 284 uint32_t data_format : 6; 285 uint32_t swizzle_mode : 5; 286 uint32_t element_size : 3; 287 uint32_t dcc : 1; 288 uint32_t tmz : 1; 289 uint32_t read_compress : 2; 290 uint32_t write_compress : 2; 291 uint32_t max_com : 2; 292 uint32_t max_uncom : 1; 293 uint32_t padding : 9; 294 }; 295 296 bool dmub_lsdma_send_tiled_to_tiled_copy_command( 297 struct dc_dmub_srv *dc_dmub_srv, 298 struct lsdma_send_tiled_to_tiled_copy_command_params params); 299 bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data); 300 301 /** 302 * struct ips_residency_info - struct containing info from dmub_ips_residency_stats 303 * 304 * @ips_mode: The mode of IPS that the follow stats appertain to 305 * @residency_percent: The percentage of time spent in given IPS mode in millipercent 306 * @entry_counter: The number of entries made in to this IPS state 307 * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode 308 * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. 309 * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode 310 * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. 311 * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c 312 */ 313 struct ips_residency_info { 314 enum ips_residency_mode ips_mode; 315 unsigned int residency_percent; 316 unsigned int entry_counter; 317 unsigned int total_active_time_us[2]; 318 unsigned int total_inactive_time_us[2]; 319 unsigned int histogram[16]; 320 }; 321 322 bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement); 323 324 bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, 325 struct dmub_ips_residency_info *driver_info, 326 enum ips_residency_mode ips_mode); 327 328 /** 329 * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required. 330 * 331 * @dc - pointer to DC object 332 */ 333 void dc_dmub_srv_release_hw(const struct dc *dc); 334 #endif /* _DMUB_DC_SRV_H_ */ 335