1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_DC_SRV_H_ 27 #define _DMUB_DC_SRV_H_ 28 29 #include "dm_services_types.h" 30 #include "dmub/dmub_srv.h" 31 32 struct dmub_srv; 33 struct dc; 34 struct pipe_ctx; 35 struct dc_crtc_timing_adjust; 36 struct dc_crtc_timing; 37 struct dc_state; 38 struct dc_surface_update; 39 40 struct dc_dmub_srv { 41 struct dmub_srv *dmub; 42 43 struct dc_context *ctx; 44 void *dm; 45 46 int32_t idle_exit_counter; 47 union dmub_shared_state_ips_driver_signals driver_signals; 48 bool idle_allowed; 49 bool needs_idle_wake; 50 bool cursor_offload_enabled; 51 }; 52 53 bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv); 54 55 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv); 56 57 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 58 unsigned int count, 59 union dmub_rb_cmd *cmd_list); 60 61 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 62 enum dm_dmub_wait_type wait_type, 63 union dmub_rb_cmd *cmd_list); 64 65 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 66 67 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type); 68 69 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 70 unsigned int stream_mask); 71 72 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv); 73 74 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry); 75 76 void dc_dmub_trace_event_control(struct dc *dc, bool enable); 77 78 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max); 79 80 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst); 81 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context); 82 83 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv); 84 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx); 85 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv); 86 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv); 87 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data); 88 89 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); 90 91 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable); 92 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); 93 94 void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx); 95 bool dc_dmub_check_min_version(struct dmub_srv *srv); 96 97 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc); 98 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index); 99 100 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait); 101 102 void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle); 103 104 /** 105 * dc_dmub_srv_set_power_state() - Sets the power state for DMUB service. 106 * 107 * Controls whether messaging the DMCUB or interfacing with it via HW register 108 * interaction is permittable. 109 * 110 * @dc_dmub_srv - The DC DMUB service pointer 111 * @power_state - the DC power state 112 */ 113 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state); 114 115 /** 116 * dc_dmub_srv_notify_fw_dc_power_state() - Notifies firmware of the DC power state. 117 * 118 * Differs from dc_dmub_srv_set_power_state in that it needs to access HW in order 119 * to message DMCUB of the state transition. Should come after the D0 exit and 120 * before D3 set power state. 121 * 122 * @dc_dmub_srv - The DC DMUB service pointer 123 * @power_state - the DC power state 124 */ 125 void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, 126 enum dc_acpi_cm_power_state power_state); 127 128 /** 129 * @dc_dmub_srv_should_detect() - Checks if link detection is required. 130 * 131 * While in idle power states we may need driver to manually redetect in 132 * the case of a missing hotplug. Should be called from a polling timer. 133 * 134 * Return: true if redetection is required. 135 */ 136 bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv); 137 138 /** 139 * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution. 140 * 141 * Refer to dc_wake_and_execute_dmub_cmd_list() for usage and limitations, 142 * This function is a convenience wrapper for a single command execution. 143 * 144 * @ctx: DC context 145 * @cmd: The command to send/receive 146 * @wait_type: The wait behavior for the execution 147 * 148 * Return: true on command submission success, false otherwise 149 */ 150 bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, 151 enum dm_dmub_wait_type wait_type); 152 153 /** 154 * dc_wake_and_execute_dmub_cmd_list() - Wrapper for DMUB command list execution. 155 * 156 * If the DMCUB hardware was asleep then it wakes the DMUB before 157 * executing the command and attempts to re-enter if the command 158 * submission was successful. 159 * 160 * This should be the preferred command submission interface provided 161 * the DC lock is acquired. 162 * 163 * Entry/exit out of idle power optimizations would need to be 164 * manually performed otherwise through dc_allow_idle_optimizations(). 165 * 166 * @ctx: DC context 167 * @count: Number of commands to send/receive 168 * @cmd: Array of commands to send 169 * @wait_type: The wait behavior for the execution 170 * 171 * Return: true on command submission success, false otherwise 172 */ 173 bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, 174 union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 175 176 /** 177 * dc_wake_and_execute_gpint() 178 * 179 * @ctx: DC context 180 * @command_code: The command ID to send to DMCUB 181 * @param: The parameter to message DMCUB 182 * @response: Optional response out value - may be NULL. 183 * @wait_type: The wait behavior for the execution 184 */ 185 bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 186 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type); 187 188 void dc_dmub_srv_fams2_update_config(struct dc *dc, 189 struct dc_state *context, 190 bool enable); 191 void dc_dmub_srv_fams2_drr_update(struct dc *dc, 192 uint32_t tg_inst, 193 uint32_t vtotal_min, 194 uint32_t vtotal_max, 195 uint32_t vtotal_mid, 196 uint32_t vtotal_mid_frame_num, 197 bool program_manual_trigger); 198 void dc_dmub_srv_fams2_passthrough_flip( 199 struct dc *dc, 200 struct dc_state *state, 201 struct dc_stream_state *stream, 202 struct dc_surface_update *srf_updates, 203 int surface_count); 204 205 bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv); 206 207 struct lsdma_linear_copy_params { 208 uint32_t src_lo; 209 uint32_t src_hi; 210 211 uint32_t dst_lo; 212 uint32_t dst_hi; 213 214 uint32_t count : 30; 215 uint32_t read_compress : 2; 216 217 uint32_t tmz : 4; 218 uint32_t cache_policy_src : 3; 219 uint32_t cache_policy_dst : 3; 220 uint32_t data_format : 6; 221 uint32_t num_type : 3; 222 uint32_t write_compress : 2; 223 uint32_t max_com : 2; 224 uint32_t max_uncom : 1; 225 uint32_t reserved0 : 8; 226 }; 227 228 bool dmub_lsdma_send_linear_copy_command( 229 struct dc_dmub_srv *dc_dmub_srv, 230 struct lsdma_linear_copy_params copy_data); 231 232 struct lsdma_linear_sub_window_copy_params { 233 uint32_t src_lo; 234 uint32_t src_hi; 235 236 uint32_t dst_lo; 237 uint32_t dst_hi; 238 239 uint32_t src_x : 16; 240 uint32_t src_y : 16; 241 242 uint32_t dst_x : 16; 243 uint32_t dst_y : 16; 244 245 uint32_t rect_x : 16; 246 uint32_t rect_y : 16; 247 248 uint32_t src_pitch : 16; 249 uint32_t dst_pitch : 16; 250 251 uint32_t src_slice_pitch; 252 uint32_t dst_slice_pitch; 253 254 uint32_t tmz : 4; 255 uint32_t element_size : 3; 256 uint32_t src_cache_policy : 3; 257 uint32_t dst_cache_policy : 3; 258 uint32_t data_format : 6; 259 uint32_t num_type : 3; 260 uint32_t read_compress : 2; 261 uint32_t write_compress : 2; 262 uint32_t max_com : 2; 263 uint32_t max_uncom : 1; 264 uint32_t reserved0 : 3; 265 }; 266 267 bool dmub_lsdma_send_linear_sub_window_copy_command( 268 struct dc_dmub_srv *dc_dmub_srv, 269 struct lsdma_linear_sub_window_copy_params copy_data 270 ); 271 bool dmub_lsdma_send_pio_copy_command( 272 struct dc_dmub_srv *dc_dmub_srv, 273 uint64_t src_addr, 274 uint64_t dst_addr, 275 uint32_t byte_count, 276 uint32_t overlap_disable); 277 bool dmub_lsdma_send_pio_constfill_command( 278 struct dc_dmub_srv *dc_dmub_srv, 279 uint64_t dst_addr, 280 uint32_t byte_count, 281 uint32_t data); 282 283 struct lsdma_send_tiled_to_tiled_copy_command_params { 284 uint64_t src_addr; 285 uint64_t dst_addr; 286 287 uint32_t src_x : 16; 288 uint32_t src_y : 16; 289 290 uint32_t dst_x : 16; 291 uint32_t dst_y : 16; 292 293 uint32_t src_width : 16; 294 uint32_t dst_width : 16; 295 296 uint32_t rect_x : 16; 297 uint32_t rect_y : 16; 298 299 uint32_t src_height : 16; 300 uint32_t dst_height : 16; 301 302 uint32_t data_format : 6; 303 uint32_t swizzle_mode : 5; 304 uint32_t element_size : 3; 305 uint32_t dcc : 1; 306 uint32_t tmz : 4; 307 uint32_t read_compress : 2; 308 uint32_t write_compress : 2; 309 uint32_t max_com : 2; 310 uint32_t max_uncom : 1; 311 uint32_t src_cache_policy : 3; 312 uint32_t dst_cache_policy : 3; 313 }; 314 315 bool dmub_lsdma_send_tiled_to_tiled_copy_command( 316 struct dc_dmub_srv *dc_dmub_srv, 317 struct lsdma_send_tiled_to_tiled_copy_command_params params); 318 bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data); 319 320 /** 321 * struct ips_residency_info - struct containing info from dmub_ips_residency_stats 322 * 323 * @ips_mode: The mode of IPS that the follow stats appertain to 324 * @residency_percent: The percentage of time spent in given IPS mode in millipercent 325 * @entry_counter: The number of entries made in to this IPS state 326 * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode 327 * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. 328 * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode 329 * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. 330 * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c 331 */ 332 struct ips_residency_info { 333 enum ips_residency_mode ips_mode; 334 unsigned int residency_percent; 335 unsigned int entry_counter; 336 unsigned int total_active_time_us[2]; 337 unsigned int total_inactive_time_us[2]; 338 unsigned int histogram[16]; 339 }; 340 341 bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement); 342 343 bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, 344 struct dmub_ips_residency_info *driver_info, 345 enum ips_residency_mode ips_mode); 346 347 /** 348 * dc_dmub_srv_cursor_offload_init() - Enables or disables cursor offloading for a stream. 349 * 350 * @dc: pointer to DC object 351 */ 352 void dc_dmub_srv_cursor_offload_init(struct dc *dc); 353 354 /** 355 * dc_dmub_srv_control_cursor_offload() - Enables or disables cursor offloading for a stream. 356 * 357 * @dc: pointer to DC object 358 * @context: the DC context to reference for pipe allocations 359 * @stream: the stream to control 360 * @enable: true to enable cursor offload, false to disable 361 */ 362 void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context, 363 const struct dc_stream_state *stream, bool enable); 364 365 /** 366 * dc_dmub_srv_program_cursor_now() - Requests immediate cursor programming for a given pipe. 367 * 368 * @dc: pointer to DC object 369 * @pipe: top-most pipe for a stream. 370 */ 371 void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe); 372 373 /** 374 * dc_dmub_srv_is_cursor_offload_enabled() - Checks if cursor offload is supported. 375 * 376 * @dc: pointer to DC object 377 * 378 * Return: true if cursor offload is supported, false otherwise 379 */ 380 bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc); 381 382 /** 383 * dc_dmub_srv_boot_time_crc_init() - Initializes DMUB boot time CRC. 384 * 385 * @dc - pointer to DC object 386 * @gpu_addr - address for the boot time CRC buffer 387 * @size - size of the boot time CRC buffer 388 */ 389 void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size); 390 391 /** 392 * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required. 393 * 394 * @dc - pointer to DC object 395 */ 396 void dc_dmub_srv_release_hw(const struct dc *dc); 397 398 /** 399 * dc_dmub_srv_log_preos_dmcub_info() - Logs preos dmcub fw info. 400 * 401 * @dc - pointer to DC object 402 */ 403 void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv); 404 405 /** 406 * dc_dmub_srv_ihc_set_dig_hdcp_interrupt_dest() - Configure IHC interrupt destination. 407 * @dc_dmub_srv: DMUB service handle 408 * @dig_id: DIG engine ID (0-3) 409 * @to_dmu: Route interrupt to DMU (true) or not (false) 410 * 411 * Sends command to DMUB firmware to configure IHC interrupt routing 412 * for HDCP I2C transfer requests. 413 * 414 * Return: true on success, false on failure 415 */ 416 bool dc_dmub_srv_ihc_set_dig_hdcp_interrupt_dest( 417 struct dc_dmub_srv *dc_dmub_srv, 418 uint8_t dig_id, 419 bool to_dmu); 420 421 /** 422 * dc_dmub_srv_get_fams2_debug_meta() - Queries for FAMS2 debug metadata from DMUB and logs it. 423 * 424 * @dc_dmub_srv - pointer to DMUB service object 425 */ 426 void dc_dmub_srv_get_fams2_debug_meta(struct dc_dmub_srv *dc_dmub_srv); 427 #endif /* _DMUB_DC_SRV_H_ */ 428