1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "dc_dmub_srv.h" 29 #include "../dmub/dmub_srv.h" 30 #include "dm_helpers.h" 31 #include "dc_hw_types.h" 32 #include "core_types.h" 33 #include "../basics/conversion.h" 34 #include "cursor_reg_cache.h" 35 #include "resource.h" 36 #include "clk_mgr.h" 37 #include "dc_state_priv.h" 38 #include "dc_plane_priv.h" 39 40 #define CTX dc_dmub_srv->ctx 41 #define DC_LOGGER CTX->logger 42 43 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, 44 struct dmub_srv *dmub) 45 { 46 dc_srv->dmub = dmub; 47 dc_srv->ctx = dc->ctx; 48 } 49 50 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) 51 { 52 struct dc_dmub_srv *dc_srv = 53 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL); 54 55 if (dc_srv == NULL) { 56 BREAK_TO_DEBUGGER(); 57 return NULL; 58 } 59 60 dc_dmub_srv_construct(dc_srv, dc, dmub); 61 62 return dc_srv; 63 } 64 65 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) 66 { 67 if (*dmub_srv) { 68 kfree(*dmub_srv); 69 *dmub_srv = NULL; 70 } 71 } 72 73 bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv) 74 { 75 struct dmub_srv *dmub; 76 struct dc_context *dc_ctx; 77 enum dmub_status status; 78 79 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 80 return false; 81 82 dc_ctx = dc_dmub_srv->ctx; 83 dmub = dc_dmub_srv->dmub; 84 85 do { 86 status = dmub_srv_wait_for_pending(dmub, 100000); 87 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 88 89 if (status != DMUB_STATUS_OK) { 90 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); 91 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 92 } 93 94 return status == DMUB_STATUS_OK; 95 } 96 97 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) 98 { 99 struct dmub_srv *dmub = dc_dmub_srv->dmub; 100 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 101 enum dmub_status status = DMUB_STATUS_OK; 102 103 status = dmub_srv_clear_inbox0_ack(dmub); 104 if (status != DMUB_STATUS_OK) { 105 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); 106 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 107 } 108 } 109 110 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) 111 { 112 struct dmub_srv *dmub = dc_dmub_srv->dmub; 113 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 114 enum dmub_status status = DMUB_STATUS_OK; 115 116 status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); 117 if (status != DMUB_STATUS_OK) { 118 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); 119 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 120 } 121 } 122 123 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv, 124 union dmub_inbox0_data_register data) 125 { 126 struct dmub_srv *dmub = dc_dmub_srv->dmub; 127 struct dc_context *dc_ctx = dc_dmub_srv->ctx; 128 enum dmub_status status = DMUB_STATUS_OK; 129 130 status = dmub_srv_send_inbox0_cmd(dmub, data); 131 if (status != DMUB_STATUS_OK) { 132 DC_ERROR("Error sending INBOX0 cmd\n"); 133 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 134 } 135 } 136 137 static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 138 unsigned int count, 139 union dmub_rb_cmd *cmd_list) 140 { 141 struct dc_context *dc_ctx; 142 struct dmub_srv *dmub; 143 enum dmub_status status = DMUB_STATUS_OK; 144 int i; 145 146 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 147 return false; 148 149 dc_ctx = dc_dmub_srv->ctx; 150 dmub = dc_dmub_srv->dmub; 151 152 for (i = 0 ; i < count; i++) { 153 /* confirm no messages pending */ 154 do { 155 status = dmub_srv_wait_for_idle(dmub, 100000); 156 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 157 158 /* queue command */ 159 if (status == DMUB_STATUS_OK) 160 status = dmub_srv_reg_cmd_execute(dmub, &cmd_list[i]); 161 162 /* check for errors */ 163 if (status != DMUB_STATUS_OK) { 164 break; 165 } 166 } 167 168 if (status != DMUB_STATUS_OK) { 169 if (status != DMUB_STATUS_POWER_STATE_D3) { 170 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 171 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 172 } 173 return false; 174 } 175 176 return true; 177 } 178 179 static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 180 unsigned int count, 181 union dmub_rb_cmd *cmd_list) 182 { 183 struct dc_context *dc_ctx; 184 struct dmub_srv *dmub; 185 enum dmub_status status; 186 int i; 187 188 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 189 return false; 190 191 dc_ctx = dc_dmub_srv->ctx; 192 dmub = dc_dmub_srv->dmub; 193 194 for (i = 0 ; i < count; i++) { 195 // Queue command 196 if (!cmd_list[i].cmd_common.header.multi_cmd_pending || 197 dmub_rb_num_free(&dmub->inbox1.rb) >= count - i) { 198 status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 199 } else { 200 status = DMUB_STATUS_QUEUE_FULL; 201 } 202 203 if (status == DMUB_STATUS_QUEUE_FULL) { 204 /* Execute and wait for queue to become empty again. */ 205 status = dmub_srv_fb_cmd_execute(dmub); 206 if (status == DMUB_STATUS_POWER_STATE_D3) 207 return false; 208 209 do { 210 status = dmub_srv_wait_for_inbox_free(dmub, 100000, count - i); 211 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 212 213 /* Requeue the command. */ 214 status = dmub_srv_fb_cmd_queue(dmub, &cmd_list[i]); 215 } 216 217 if (status != DMUB_STATUS_OK) { 218 if (status != DMUB_STATUS_POWER_STATE_D3) { 219 DC_ERROR("Error queueing DMUB command: status=%d\n", status); 220 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 221 } 222 return false; 223 } 224 } 225 226 status = dmub_srv_fb_cmd_execute(dmub); 227 if (status != DMUB_STATUS_OK) { 228 if (status != DMUB_STATUS_POWER_STATE_D3) { 229 DC_ERROR("Error starting DMUB execution: status=%d\n", status); 230 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 231 } 232 return false; 233 } 234 235 return true; 236 } 237 238 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 239 unsigned int count, 240 union dmub_rb_cmd *cmd_list) 241 { 242 bool res = false; 243 244 if (dc_dmub_srv && dc_dmub_srv->dmub) { 245 if (dc_dmub_srv->dmub->inbox_type == DMUB_CMD_INTERFACE_REG) { 246 res = dc_dmub_srv_reg_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 247 } else { 248 res = dc_dmub_srv_fb_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list); 249 } 250 251 if (res) 252 res = dmub_srv_update_inbox_status(dc_dmub_srv->dmub) == DMUB_STATUS_OK; 253 } 254 255 return res; 256 } 257 258 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 259 enum dm_dmub_wait_type wait_type, 260 union dmub_rb_cmd *cmd_list) 261 { 262 struct dmub_srv *dmub; 263 enum dmub_status status; 264 265 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 266 return false; 267 268 dmub = dc_dmub_srv->dmub; 269 270 // Wait for DMUB to process command 271 if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 272 do { 273 status = dmub_srv_wait_for_idle(dmub, 100000); 274 } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); 275 276 if (status != DMUB_STATUS_OK) { 277 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 278 if (!dmub->debug.timeout_info.timeout_occured) { 279 dmub->debug.timeout_info.timeout_occured = true; 280 if (cmd_list) 281 dmub->debug.timeout_info.timeout_cmd = *cmd_list; 282 dmub->debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv->ctx); 283 } 284 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 285 return false; 286 } 287 288 // Copy data back from ring buffer into command 289 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY && cmd_list) { 290 dmub_srv_cmd_get_response(dc_dmub_srv->dmub, cmd_list); 291 } 292 } 293 294 return true; 295 } 296 297 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 298 { 299 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type); 300 } 301 302 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type) 303 { 304 if (!dc_dmub_srv_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list)) 305 return false; 306 307 return dc_dmub_srv_wait_for_idle(dc_dmub_srv, wait_type, cmd_list); 308 } 309 310 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) 311 { 312 struct dmub_srv *dmub; 313 struct dc_context *dc_ctx; 314 union dmub_fw_boot_status boot_status; 315 enum dmub_status status; 316 317 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 318 return false; 319 320 dmub = dc_dmub_srv->dmub; 321 dc_ctx = dc_dmub_srv->ctx; 322 323 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 324 if (status != DMUB_STATUS_OK) { 325 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 326 return false; 327 } 328 329 return boot_status.bits.optimized_init_done; 330 } 331 332 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 333 unsigned int stream_mask) 334 { 335 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 336 return false; 337 338 return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 339 stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); 340 } 341 342 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 343 { 344 struct dmub_srv *dmub; 345 struct dc_context *dc_ctx; 346 union dmub_fw_boot_status boot_status; 347 enum dmub_status status; 348 349 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 350 return false; 351 352 dmub = dc_dmub_srv->dmub; 353 dc_ctx = dc_dmub_srv->ctx; 354 355 status = dmub_srv_get_fw_boot_status(dmub, &boot_status); 356 if (status != DMUB_STATUS_OK) { 357 DC_ERROR("Error querying DMUB boot status: error=%d\n", status); 358 return false; 359 } 360 361 return boot_status.bits.restore_required; 362 } 363 364 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 365 { 366 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; 367 return dmub_srv_get_outbox0_msg(dmub, entry); 368 } 369 370 void dc_dmub_trace_event_control(struct dc *dc, bool enable) 371 { 372 dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); 373 } 374 375 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) 376 { 377 union dmub_rb_cmd cmd = { 0 }; 378 379 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 380 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; 381 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 382 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 383 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 384 385 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 386 387 // Send the command to the DMCUB. 388 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 389 } 390 391 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 392 { 393 union dmub_rb_cmd cmd = { 0 }; 394 395 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 396 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; 397 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; 398 399 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); 400 401 // Send the command to the DMCUB. 402 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 403 } 404 405 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) 406 { 407 uint8_t pipes = 0; 408 int i = 0; 409 410 for (i = 0; i < MAX_PIPES; i++) { 411 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 412 413 if (pipe->stream == stream && pipe->stream_res.tg) 414 pipes = i; 415 } 416 return pipes; 417 } 418 419 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context, 420 struct pipe_ctx *head_pipe, 421 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) 422 { 423 int j; 424 int pipe_idx = 0; 425 426 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; 427 for (j = 0; j < dc->res_pool->pipe_count; j++) { 428 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; 429 430 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { 431 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; 432 } 433 } 434 fams_pipe_data->pipe_count = pipe_idx; 435 } 436 437 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) 438 { 439 union dmub_rb_cmd cmd = { 0 }; 440 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; 441 int i = 0, k = 0; 442 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. 443 uint8_t visual_confirm_enabled; 444 int pipe_idx = 0; 445 struct dc_stream_status *stream_status = NULL; 446 447 if (dc == NULL) 448 return false; 449 450 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; 451 452 // Format command. 453 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 454 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; 455 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; 456 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; 457 458 if (should_manage_pstate) { 459 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 460 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 461 462 if (!pipe->stream) 463 continue; 464 465 /* If FAMS is being used to support P-State and there is a stream 466 * that does not use FAMS, we are in an FPO + VActive scenario. 467 * Assign vactive stretch margin in this case. 468 */ 469 stream_status = dc_state_get_stream_status(context, pipe->stream); 470 if (stream_status && !stream_status->fpo_in_use) { 471 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; 472 break; 473 } 474 pipe_idx++; 475 } 476 } 477 478 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { 479 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 480 481 if (!resource_is_pipe_type(pipe, OTG_MASTER)) 482 continue; 483 484 stream_status = dc_state_get_stream_status(context, pipe->stream); 485 if (stream_status && stream_status->fpo_in_use) { 486 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 487 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 488 489 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 490 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; 491 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; 492 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); 493 dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); 494 k++; 495 } 496 } 497 cmd.fw_assisted_mclk_switch.header.payload_bytes = 498 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); 499 500 // Send the command to the DMCUB. 501 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 502 503 return true; 504 } 505 506 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv) 507 { 508 union dmub_rb_cmd cmd = { 0 }; 509 510 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 511 return; 512 513 memset(&cmd, 0, sizeof(cmd)); 514 515 /* Prepare fw command */ 516 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; 517 cmd.query_feature_caps.header.sub_type = 0; 518 cmd.query_feature_caps.header.ret_status = 1; 519 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); 520 521 /* If command was processed, copy feature caps to dmub srv */ 522 if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 523 cmd.query_feature_caps.header.ret_status == 0) { 524 memcpy(&dc_dmub_srv->dmub->feature_caps, 525 &cmd.query_feature_caps.query_feature_caps_data, 526 sizeof(struct dmub_feature_caps)); 527 } 528 } 529 530 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) 531 { 532 union dmub_rb_cmd cmd = { 0 }; 533 unsigned int panel_inst = 0; 534 535 if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) && 536 dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE) 537 return; 538 539 memset(&cmd, 0, sizeof(cmd)); 540 541 // Prepare fw command 542 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; 543 cmd.visual_confirm_color.header.sub_type = 0; 544 cmd.visual_confirm_color.header.ret_status = 1; 545 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); 546 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; 547 548 // If command was processed, copy feature caps to dmub srv 549 if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 550 cmd.visual_confirm_color.header.ret_status == 0) { 551 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color, 552 &cmd.visual_confirm_color.visual_confirm_color_data, 553 sizeof(struct dmub_visual_confirm_color)); 554 } 555 } 556 557 /** 558 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command 559 * 560 * @dc: [in] pointer to dc object 561 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 562 * @vblank_pipe: [in] pipe_ctx for the DRR pipe 563 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info 564 * @context: [in] DC state for access to phantom stream 565 * 566 * Populate the DMCUB SubVP command with DRR pipe info. All the information 567 * required for calculating the SubVP + DRR microschedule is populated here. 568 * 569 * High level algorithm: 570 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 571 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule 572 * 3. Populate the drr_info with the min and max supported vtotal values 573 */ 574 static void populate_subvp_cmd_drr_info(struct dc *dc, 575 struct dc_state *context, 576 struct pipe_ctx *subvp_pipe, 577 struct pipe_ctx *vblank_pipe, 578 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) 579 { 580 struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream); 581 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 582 struct dc_crtc_timing *phantom_timing; 583 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 584 uint16_t drr_frame_us = 0; 585 uint16_t min_drr_supported_us = 0; 586 uint16_t max_drr_supported_us = 0; 587 uint16_t max_drr_vblank_us = 0; 588 uint16_t max_drr_mallregion_us = 0; 589 uint16_t mall_region_us = 0; 590 uint16_t prefetch_us = 0; 591 uint16_t subvp_active_us = 0; 592 uint16_t drr_active_us = 0; 593 uint16_t min_vtotal_supported = 0; 594 uint16_t max_vtotal_supported = 0; 595 596 if (!phantom_stream) 597 return; 598 599 phantom_timing = &phantom_stream->timing; 600 601 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; 602 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping 603 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now 604 605 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), 606 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 607 // P-State allow width and FW delays already included phantom_timing->v_addressable 608 mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), 609 (((uint64_t)phantom_timing->pix_clk_100hz * 100))); 610 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; 611 min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), 612 (((uint64_t)drr_timing->h_total * 1000000))); 613 614 prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), 615 (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 616 subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), 617 (((uint64_t)main_timing->pix_clk_100hz * 100))); 618 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), 619 (((uint64_t)drr_timing->pix_clk_100hz * 100))); 620 max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - 621 dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us; 622 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us; 623 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; 624 max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), 625 (((uint64_t)drr_timing->h_total * 1000000))); 626 627 /* When calculating the max vtotal supported for SubVP + DRR cases, add 628 * margin due to possible rounding errors (being off by 1 line in the 629 * FW calculation can incorrectly push the P-State switch to wait 1 frame 630 * longer). 631 */ 632 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; 633 634 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; 635 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; 636 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; 637 } 638 639 /** 640 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command 641 * 642 * @dc: [in] current dc state 643 * @context: [in] new dc state 644 * @cmd: [in] DMUB cmd to be populated with SubVP info 645 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe 646 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 647 * 648 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information 649 * required to calculate the microschedule for SubVP + VBLANK case is stored in 650 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe 651 * is a DRR display -- if it is make a call to populate drr_info. 652 */ 653 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, 654 struct dc_state *context, 655 union dmub_rb_cmd *cmd, 656 struct pipe_ctx *vblank_pipe, 657 uint8_t cmd_pipe_index) 658 { 659 uint32_t i; 660 struct pipe_ctx *pipe = NULL; 661 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 662 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 663 664 // Find the SubVP pipe 665 for (i = 0; i < dc->res_pool->pipe_count; i++) { 666 pipe = &context->res_ctx.pipe_ctx[i]; 667 668 // We check for master pipe, but it shouldn't matter since we only need 669 // the pipe for timing info (stream should be same for any pipe splits) 670 if (!resource_is_pipe_type(pipe, OTG_MASTER) || 671 !resource_is_pipe_type(pipe, DPP_PIPE)) 672 continue; 673 674 // Find the SubVP pipe 675 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) 676 break; 677 } 678 679 pipe_data->mode = VBLANK; 680 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 681 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 682 vblank_pipe->stream->timing.v_front_porch; 683 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; 684 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; 685 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; 686 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; 687 pipe_data->pipe_config.vblank_data.vblank_end = 688 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; 689 690 if (vblank_pipe->stream->ignore_msa_timing_param && 691 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed)) 692 populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data); 693 } 694 695 /** 696 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case 697 * 698 * @dc: [in] current dc state 699 * @context: [in] new dc state 700 * @cmd: [in] DMUB cmd to be populated with SubVP info 701 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2) 702 * 703 * For SubVP + SubVP, we use a single vertical interrupt to start the 704 * microschedule for both SubVP pipes. In order for this to work correctly, the 705 * MALL REGION of both SubVP pipes must start at the same time. This function 706 * lengthens the prefetch end to mall start delay of the SubVP pipe that has 707 * the shorter prefetch so that both MALL REGION's will start at the same time. 708 */ 709 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, 710 struct dc_state *context, 711 union dmub_rb_cmd *cmd, 712 struct pipe_ctx *subvp_pipes[]) 713 { 714 uint32_t subvp0_prefetch_us = 0; 715 uint32_t subvp1_prefetch_us = 0; 716 uint32_t prefetch_delta_us = 0; 717 struct dc_stream_state *phantom_stream0 = NULL; 718 struct dc_stream_state *phantom_stream1 = NULL; 719 struct dc_crtc_timing *phantom_timing0 = NULL; 720 struct dc_crtc_timing *phantom_timing1 = NULL; 721 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL; 722 723 phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]->stream); 724 if (!phantom_stream0) 725 return; 726 727 phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]->stream); 728 if (!phantom_stream1) 729 return; 730 731 phantom_timing0 = &phantom_stream0->timing; 732 phantom_timing1 = &phantom_stream1->timing; 733 734 subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * 735 (uint64_t)phantom_timing0->h_total * 1000000), 736 (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 737 subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * 738 (uint64_t)phantom_timing1->h_total * 1000000), 739 (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); 740 741 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) 742 // should increase it's prefetch time to match the other 743 if (subvp0_prefetch_us > subvp1_prefetch_us) { 744 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; 745 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; 746 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 747 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 748 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), 749 ((uint64_t)phantom_timing1->h_total * 1000000)); 750 751 } else if (subvp1_prefetch_us > subvp0_prefetch_us) { 752 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; 753 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; 754 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 755 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * 756 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), 757 ((uint64_t)phantom_timing0->h_total * 1000000)); 758 } 759 } 760 761 /** 762 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command 763 * 764 * @dc: [in] current dc state 765 * @context: [in] new dc state 766 * @cmd: [in] DMUB cmd to be populated with SubVP info 767 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe 768 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd 769 * 770 * Populate the DMCUB SubVP command with SubVP pipe info. All the information 771 * required to calculate the microschedule for the SubVP pipe is stored in the 772 * pipe_data of the DMCUB SubVP command. 773 */ 774 static void populate_subvp_cmd_pipe_info(struct dc *dc, 775 struct dc_state *context, 776 union dmub_rb_cmd *cmd, 777 struct pipe_ctx *subvp_pipe, 778 uint8_t cmd_pipe_index) 779 { 780 uint32_t j; 781 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = 782 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; 783 struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream); 784 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 785 struct dc_crtc_timing *phantom_timing; 786 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; 787 788 if (!phantom_stream) 789 return; 790 791 phantom_timing = &phantom_stream->timing; 792 793 pipe_data->mode = SUBVP; 794 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; 795 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; 796 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; 797 pipe_data->pipe_config.subvp_data.main_vblank_start = 798 main_timing->v_total - main_timing->v_front_porch; 799 pipe_data->pipe_config.subvp_data.main_vblank_end = 800 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; 801 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; 802 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; 803 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param && 804 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed); 805 806 /* Calculate the scaling factor from the src and dst height. 807 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. 808 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" 809 * 810 * Make sure to combine stream and plane scaling together. 811 */ 812 reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, 813 &out_num_stream, &out_den_stream); 814 reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, 815 &out_num_plane, &out_den_plane); 816 reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); 817 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; 818 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; 819 820 // Prefetch lines is equal to VACTIVE + BP + VSYNC 821 pipe_data->pipe_config.subvp_data.prefetch_lines = 822 phantom_timing->v_total - phantom_timing->v_front_porch; 823 824 // Round up 825 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = 826 div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 827 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 828 pipe_data->pipe_config.subvp_data.processing_delay_lines = 829 div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + 830 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); 831 832 if (subvp_pipe->bottom_pipe) { 833 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; 834 } else if (subvp_pipe->next_odm_pipe) { 835 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; 836 } else { 837 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF; 838 } 839 840 // Find phantom pipe index based on phantom stream 841 for (j = 0; j < dc->res_pool->pipe_count; j++) { 842 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; 843 844 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && 845 phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { 846 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; 847 if (phantom_pipe->bottom_pipe) { 848 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; 849 } else if (phantom_pipe->next_odm_pipe) { 850 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; 851 } else { 852 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF; 853 } 854 break; 855 } 856 } 857 } 858 859 /** 860 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command 861 * 862 * @dc: [in] current dc state 863 * @context: [in] new dc state 864 * @enable: [in] if true enables the pipes population 865 * 866 * This function loops through each pipe and populates the DMUB SubVP CMD info 867 * based on the pipe (e.g. SubVP, VBLANK). 868 */ 869 void dc_dmub_setup_subvp_dmub_command(struct dc *dc, 870 struct dc_state *context, 871 bool enable) 872 { 873 uint8_t cmd_pipe_index = 0; 874 uint32_t i, pipe_idx; 875 uint8_t subvp_count = 0; 876 union dmub_rb_cmd cmd; 877 struct pipe_ctx *subvp_pipes[2]; 878 uint32_t wm_val_refclk = 0; 879 enum mall_stream_type pipe_mall_type; 880 881 memset(&cmd, 0, sizeof(cmd)); 882 // FW command for SUBVP 883 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 884 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; 885 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = 886 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); 887 888 for (i = 0; i < dc->res_pool->pipe_count; i++) { 889 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 890 891 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe 892 */ 893 if (resource_is_pipe_type(pipe, OTG_MASTER) && 894 resource_is_pipe_type(pipe, DPP_PIPE) && 895 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) 896 subvp_pipes[subvp_count++] = pipe; 897 } 898 899 if (enable) { 900 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd 901 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 902 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 903 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe); 904 905 if (!pipe->stream) 906 continue; 907 908 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. 909 * Any ODM or MPC splits being used in SubVP will be handled internally in 910 * populate_subvp_cmd_pipe_info 911 */ 912 if (resource_is_pipe_type(pipe, OTG_MASTER) && 913 resource_is_pipe_type(pipe, DPP_PIPE) && 914 pipe_mall_type == SUBVP_MAIN) { 915 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 916 } else if (resource_is_pipe_type(pipe, OTG_MASTER) && 917 resource_is_pipe_type(pipe, DPP_PIPE) && 918 pipe_mall_type == SUBVP_NONE) { 919 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where 920 // we run through DML without calculating "natural" P-state support 921 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); 922 923 } 924 pipe_idx++; 925 } 926 if (subvp_count == 2) { 927 update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); 928 } 929 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 930 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; 931 932 // Store the original watermark value for this SubVP config so we can lower it when the 933 // MCLK switch starts 934 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * 935 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; 936 937 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; 938 } 939 940 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 941 } 942 943 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 944 { 945 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 946 return false; 947 return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub); 948 } 949 950 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) 951 { 952 uint32_t i; 953 954 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 955 DC_LOG_ERROR("%s: invalid parameters.", __func__); 956 return; 957 } 958 959 DC_LOG_ERROR("%s: DMCUB error - collecting diagnostic data\n", __func__); 960 961 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv)) { 962 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__); 963 return; 964 } 965 966 DC_LOG_DEBUG("DMCUB STATE:"); 967 DC_LOG_DEBUG(" dmcub_version : %08x", dc_dmub_srv->dmub->debug.dmcub_version); 968 DC_LOG_DEBUG(" scratch [0] : %08x", dc_dmub_srv->dmub->debug.scratch[0]); 969 DC_LOG_DEBUG(" scratch [1] : %08x", dc_dmub_srv->dmub->debug.scratch[1]); 970 DC_LOG_DEBUG(" scratch [2] : %08x", dc_dmub_srv->dmub->debug.scratch[2]); 971 DC_LOG_DEBUG(" scratch [3] : %08x", dc_dmub_srv->dmub->debug.scratch[3]); 972 DC_LOG_DEBUG(" scratch [4] : %08x", dc_dmub_srv->dmub->debug.scratch[4]); 973 DC_LOG_DEBUG(" scratch [5] : %08x", dc_dmub_srv->dmub->debug.scratch[5]); 974 DC_LOG_DEBUG(" scratch [6] : %08x", dc_dmub_srv->dmub->debug.scratch[6]); 975 DC_LOG_DEBUG(" scratch [7] : %08x", dc_dmub_srv->dmub->debug.scratch[7]); 976 DC_LOG_DEBUG(" scratch [8] : %08x", dc_dmub_srv->dmub->debug.scratch[8]); 977 DC_LOG_DEBUG(" scratch [9] : %08x", dc_dmub_srv->dmub->debug.scratch[9]); 978 DC_LOG_DEBUG(" scratch [10] : %08x", dc_dmub_srv->dmub->debug.scratch[10]); 979 DC_LOG_DEBUG(" scratch [11] : %08x", dc_dmub_srv->dmub->debug.scratch[11]); 980 DC_LOG_DEBUG(" scratch [12] : %08x", dc_dmub_srv->dmub->debug.scratch[12]); 981 DC_LOG_DEBUG(" scratch [13] : %08x", dc_dmub_srv->dmub->debug.scratch[13]); 982 DC_LOG_DEBUG(" scratch [14] : %08x", dc_dmub_srv->dmub->debug.scratch[14]); 983 DC_LOG_DEBUG(" scratch [15] : %08x", dc_dmub_srv->dmub->debug.scratch[15]); 984 for (i = 0; i < DMUB_PC_SNAPSHOT_COUNT; i++) 985 DC_LOG_DEBUG(" pc[%d] : %08x", i, dc_dmub_srv->dmub->debug.pc[i]); 986 DC_LOG_DEBUG(" unk_fault_addr : %08x", dc_dmub_srv->dmub->debug.undefined_address_fault_addr); 987 DC_LOG_DEBUG(" inst_fault_addr : %08x", dc_dmub_srv->dmub->debug.inst_fetch_fault_addr); 988 DC_LOG_DEBUG(" data_fault_addr : %08x", dc_dmub_srv->dmub->debug.data_write_fault_addr); 989 DC_LOG_DEBUG(" inbox1_rptr : %08x", dc_dmub_srv->dmub->debug.inbox1_rptr); 990 DC_LOG_DEBUG(" inbox1_wptr : %08x", dc_dmub_srv->dmub->debug.inbox1_wptr); 991 DC_LOG_DEBUG(" inbox1_size : %08x", dc_dmub_srv->dmub->debug.inbox1_size); 992 DC_LOG_DEBUG(" inbox0_rptr : %08x", dc_dmub_srv->dmub->debug.inbox0_rptr); 993 DC_LOG_DEBUG(" inbox0_wptr : %08x", dc_dmub_srv->dmub->debug.inbox0_wptr); 994 DC_LOG_DEBUG(" inbox0_size : %08x", dc_dmub_srv->dmub->debug.inbox0_size); 995 DC_LOG_DEBUG(" outbox1_rptr : %08x", dc_dmub_srv->dmub->debug.outbox1_rptr); 996 DC_LOG_DEBUG(" outbox1_wptr : %08x", dc_dmub_srv->dmub->debug.outbox1_wptr); 997 DC_LOG_DEBUG(" outbox1_size : %08x", dc_dmub_srv->dmub->debug.outbox1_size); 998 DC_LOG_DEBUG(" is_enabled : %d", dc_dmub_srv->dmub->debug.is_dmcub_enabled); 999 DC_LOG_DEBUG(" is_soft_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_soft_reset); 1000 DC_LOG_DEBUG(" is_secure_reset : %d", dc_dmub_srv->dmub->debug.is_dmcub_secure_reset); 1001 DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en); 1002 DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled); 1003 DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled); 1004 } 1005 1006 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) 1007 { 1008 if (pipe_ctx->plane_state != NULL) { 1009 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 1010 resource_can_pipe_disable_cursor(pipe_ctx)) 1011 return false; 1012 } 1013 1014 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || 1015 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && 1016 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) 1017 return true; 1018 1019 if (pipe_ctx->stream->link->replay_settings.config.replay_supported) 1020 return true; 1021 1022 return false; 1023 } 1024 1025 static void dc_build_cursor_update_payload0( 1026 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 1027 struct dmub_cmd_update_cursor_payload0 *payload) 1028 { 1029 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1030 unsigned int panel_inst = 0; 1031 1032 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 1033 pipe_ctx->stream->link, &panel_inst)) 1034 return; 1035 1036 /* Payload: Cursor Rect is built from position & attribute 1037 * x & y are obtained from postion 1038 */ 1039 payload->cursor_rect.x = hubp->cur_rect.x; 1040 payload->cursor_rect.y = hubp->cur_rect.y; 1041 /* w & h are obtained from attribute */ 1042 payload->cursor_rect.width = hubp->cur_rect.w; 1043 payload->cursor_rect.height = hubp->cur_rect.h; 1044 1045 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 1046 payload->pipe_idx = p_idx; 1047 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 1048 payload->panel_inst = panel_inst; 1049 } 1050 1051 static void dc_build_cursor_position_update_payload0( 1052 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, 1053 const struct hubp *hubp, const struct dpp *dpp) 1054 { 1055 /* Hubp */ 1056 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; 1057 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; 1058 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; 1059 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; 1060 1061 /* dpp */ 1062 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; 1063 pl->position_cfg.pipe_idx = p_idx; 1064 } 1065 1066 static void dc_build_cursor_attribute_update_payload1( 1067 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, 1068 const struct hubp *hubp, const struct dpp *dpp) 1069 { 1070 /* Hubp */ 1071 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; 1072 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; 1073 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; 1074 pl_A->aHubp.size.raw = hubp->att.size.raw; 1075 pl_A->aHubp.settings.raw = hubp->att.settings.raw; 1076 1077 /* dpp */ 1078 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; 1079 } 1080 1081 /** 1082 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command 1083 * 1084 * @pCtx: [in] pipe context 1085 * @pipe_idx: [in] pipe index 1086 * 1087 * This function would store the cursor related information and pass it into 1088 * dmub 1089 */ 1090 void dc_send_update_cursor_info_to_dmu( 1091 struct pipe_ctx *pCtx, uint8_t pipe_idx) 1092 { 1093 union dmub_rb_cmd cmd[2]; 1094 union dmub_cmd_update_cursor_info_data *update_cursor_info_0 = 1095 &cmd[0].update_cursor_info.update_cursor_info_data; 1096 1097 memset(cmd, 0, sizeof(cmd)); 1098 1099 if (!dc_dmub_should_update_cursor_data(pCtx)) 1100 return; 1101 /* 1102 * Since we use multi_cmd_pending for dmub command, the 2nd command is 1103 * only assigned to store cursor attributes info. 1104 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other 1105 * is to store cursor position info. 1106 * 1107 * Command heaer type must be the same type if using multi_cmd_pending. 1108 * Besides, while process 2nd command in DMU, the sub type is useless. 1109 * So it's meanless to pass the sub type header with different type. 1110 */ 1111 1112 { 1113 /* Build Payload#0 Header */ 1114 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1115 cmd[0].update_cursor_info.header.payload_bytes = 1116 sizeof(cmd[0].update_cursor_info.update_cursor_info_data); 1117 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd 1118 1119 /* Prepare Payload */ 1120 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0); 1121 1122 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx, 1123 pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1124 } 1125 { 1126 /* Build Payload#1 Header */ 1127 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; 1128 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); 1129 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command. 1130 1131 dc_build_cursor_attribute_update_payload1( 1132 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, 1133 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); 1134 1135 /* Combine 2nd cmds update_curosr_info to DMU */ 1136 dc_wake_and_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1137 } 1138 } 1139 1140 bool dc_dmub_check_min_version(struct dmub_srv *srv) 1141 { 1142 if (!srv->hw_funcs.is_psrsu_supported) 1143 return true; 1144 return srv->hw_funcs.is_psrsu_supported(srv); 1145 } 1146 1147 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc) 1148 { 1149 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1150 1151 if (!dc_dmub_srv || !dc_dmub_srv->dmub) { 1152 DC_LOG_ERROR("%s: invalid parameters.", __func__); 1153 return; 1154 } 1155 1156 if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 1157 0x0010, NULL, DM_DMUB_WAIT_TYPE_WAIT)) { 1158 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1159 return; 1160 } 1161 1162 if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 1163 0x0000, NULL, DM_DMUB_WAIT_TYPE_WAIT)) { 1164 DC_LOG_ERROR("timeout updating trace buffer mask word\n"); 1165 return; 1166 } 1167 1168 DC_LOG_DEBUG("Enabled DPIA trace\n"); 1169 } 1170 1171 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index) 1172 { 1173 dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index); 1174 } 1175 1176 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait) 1177 { 1178 struct dc_context *dc_ctx; 1179 enum dmub_status status; 1180 1181 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1182 return true; 1183 1184 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation) 1185 return true; 1186 1187 dc_ctx = dc_dmub_srv->ctx; 1188 1189 if (wait) { 1190 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) { 1191 do { 1192 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000); 1193 } while (status != DMUB_STATUS_OK); 1194 } else { 1195 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000); 1196 if (status != DMUB_STATUS_OK) { 1197 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status); 1198 return false; 1199 } 1200 } 1201 } else 1202 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub); 1203 1204 return true; 1205 } 1206 1207 static int count_active_streams(const struct dc *dc) 1208 { 1209 int i, count = 0; 1210 1211 for (i = 0; i < dc->current_state->stream_count; ++i) { 1212 struct dc_stream_state *stream = dc->current_state->streams[i]; 1213 1214 if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off)) 1215 count += 1; 1216 } 1217 1218 return count; 1219 } 1220 1221 static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) 1222 { 1223 volatile const struct dmub_shared_state_ips_fw *ips_fw; 1224 struct dc_dmub_srv *dc_dmub_srv; 1225 union dmub_rb_cmd cmd = {0}; 1226 1227 if (dc->debug.dmcub_emulation) 1228 return; 1229 1230 if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub) 1231 return; 1232 1233 dc_dmub_srv = dc->ctx->dmub_srv; 1234 ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1235 1236 memset(&cmd, 0, sizeof(cmd)); 1237 cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT; 1238 cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE; 1239 cmd.idle_opt_notify_idle.header.payload_bytes = 1240 sizeof(cmd.idle_opt_notify_idle) - 1241 sizeof(cmd.idle_opt_notify_idle.header); 1242 1243 cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle; 1244 1245 if (dc->work_arounds.skip_psr_ips_crtc_disable) 1246 cmd.idle_opt_notify_idle.cntl_data.skip_otg_disable = true; 1247 1248 if (allow_idle) { 1249 volatile struct dmub_shared_state_ips_driver *ips_driver = 1250 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver; 1251 union dmub_shared_state_ips_driver_signals new_signals; 1252 1253 DC_LOG_IPS( 1254 "%s wait idle (ips1_commit=%u ips2_commit=%u)", 1255 __func__, 1256 ips_fw->signals.bits.ips1_commit, 1257 ips_fw->signals.bits.ips2_commit); 1258 1259 dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL); 1260 1261 memset(&new_signals, 0, sizeof(new_signals)); 1262 1263 new_signals.bits.allow_idle = 1; /* always set */ 1264 1265 if (dc->config.disable_ips == DMUB_IPS_ENABLE || 1266 dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) { 1267 new_signals.bits.allow_pg = 1; 1268 new_signals.bits.allow_ips1 = 1; 1269 new_signals.bits.allow_ips2 = 1; 1270 new_signals.bits.allow_z10 = 1; 1271 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) { 1272 new_signals.bits.allow_ips1 = 1; 1273 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) { 1274 new_signals.bits.allow_pg = 1; 1275 new_signals.bits.allow_ips1 = 1; 1276 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) { 1277 new_signals.bits.allow_pg = 1; 1278 new_signals.bits.allow_ips1 = 1; 1279 new_signals.bits.allow_ips2 = 1; 1280 } else if (dc->config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) { 1281 /* TODO: Move this logic out to hwseq */ 1282 if (count_active_streams(dc) == 0) { 1283 /* IPS2 - Display off */ 1284 new_signals.bits.allow_pg = 1; 1285 new_signals.bits.allow_ips1 = 1; 1286 new_signals.bits.allow_ips2 = 1; 1287 new_signals.bits.allow_z10 = 1; 1288 } else { 1289 /* RCG only */ 1290 new_signals.bits.allow_pg = 0; 1291 new_signals.bits.allow_ips1 = 1; 1292 new_signals.bits.allow_ips2 = 0; 1293 new_signals.bits.allow_z10 = 0; 1294 } 1295 } 1296 1297 ips_driver->signals = new_signals; 1298 dc_dmub_srv->driver_signals = ips_driver->signals; 1299 } 1300 1301 DC_LOG_IPS( 1302 "%s send allow_idle=%d (ips1_commit=%u ips2_commit=%u)", 1303 __func__, 1304 allow_idle, 1305 ips_fw->signals.bits.ips1_commit, 1306 ips_fw->signals.bits.ips2_commit); 1307 1308 /* NOTE: This does not use the "wake" interface since this is part of the wake path. */ 1309 /* We also do not perform a wait since DMCUB could enter idle after the notification. */ 1310 dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT); 1311 1312 /* Register access should stop at this point. */ 1313 if (allow_idle) 1314 dc_dmub_srv->needs_idle_wake = true; 1315 } 1316 1317 static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) 1318 { 1319 struct dc_dmub_srv *dc_dmub_srv; 1320 uint32_t rcg_exit_count = 0, ips1_exit_count = 0, ips2_exit_count = 0; 1321 1322 if (dc->debug.dmcub_emulation) 1323 return; 1324 1325 if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub) 1326 return; 1327 1328 dc_dmub_srv = dc->ctx->dmub_srv; 1329 1330 if (dc->clk_mgr->funcs->exit_low_power_state) { 1331 volatile const struct dmub_shared_state_ips_fw *ips_fw = 1332 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1333 volatile struct dmub_shared_state_ips_driver *ips_driver = 1334 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver; 1335 union dmub_shared_state_ips_driver_signals prev_driver_signals = ips_driver->signals; 1336 1337 rcg_exit_count = ips_fw->rcg_exit_count; 1338 ips1_exit_count = ips_fw->ips1_exit_count; 1339 ips2_exit_count = ips_fw->ips2_exit_count; 1340 1341 ips_driver->signals.all = 0; 1342 dc_dmub_srv->driver_signals = ips_driver->signals; 1343 1344 DC_LOG_IPS( 1345 "%s (allow ips1=%u ips2=%u) (commit ips1=%u ips2=%u) (count rcg=%u ips1=%u ips2=%u)", 1346 __func__, 1347 ips_driver->signals.bits.allow_ips1, 1348 ips_driver->signals.bits.allow_ips2, 1349 ips_fw->signals.bits.ips1_commit, 1350 ips_fw->signals.bits.ips2_commit, 1351 ips_fw->rcg_entry_count, 1352 ips_fw->ips1_entry_count, 1353 ips_fw->ips2_entry_count); 1354 1355 /* Note: register access has technically not resumed for DCN here, but we 1356 * need to be message PMFW through our standard register interface. 1357 */ 1358 dc_dmub_srv->needs_idle_wake = false; 1359 1360 if ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) && 1361 (!dc->debug.optimize_ips_handshake || 1362 ips_fw->signals.bits.ips2_commit || !ips_fw->signals.bits.in_idle)) { 1363 DC_LOG_IPS( 1364 "wait IPS2 eval (ips1_commit=%u ips2_commit=%u)", 1365 ips_fw->signals.bits.ips1_commit, 1366 ips_fw->signals.bits.ips2_commit); 1367 1368 if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit) 1369 udelay(dc->debug.ips2_eval_delay_us); 1370 1371 DC_LOG_IPS( 1372 "exit IPS2 #1 (ips1_commit=%u ips2_commit=%u)", 1373 ips_fw->signals.bits.ips1_commit, 1374 ips_fw->signals.bits.ips2_commit); 1375 1376 // Tell PMFW to exit low power state 1377 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr); 1378 1379 if (ips_fw->signals.bits.ips2_commit) { 1380 1381 DC_LOG_IPS( 1382 "wait IPS2 entry delay (ips1_commit=%u ips2_commit=%u)", 1383 ips_fw->signals.bits.ips1_commit, 1384 ips_fw->signals.bits.ips2_commit); 1385 1386 // Wait for IPS2 entry upper bound 1387 udelay(dc->debug.ips2_entry_delay_us); 1388 1389 DC_LOG_IPS( 1390 "exit IPS2 #2 (ips1_commit=%u ips2_commit=%u)", 1391 ips_fw->signals.bits.ips1_commit, 1392 ips_fw->signals.bits.ips2_commit); 1393 1394 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr); 1395 1396 DC_LOG_IPS( 1397 "wait IPS2 commit clear (ips1_commit=%u ips2_commit=%u)", 1398 ips_fw->signals.bits.ips1_commit, 1399 ips_fw->signals.bits.ips2_commit); 1400 1401 while (ips_fw->signals.bits.ips2_commit) 1402 udelay(1); 1403 1404 DC_LOG_IPS( 1405 "wait hw_pwr_up (ips1_commit=%u ips2_commit=%u)", 1406 ips_fw->signals.bits.ips1_commit, 1407 ips_fw->signals.bits.ips2_commit); 1408 1409 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true)) 1410 ASSERT(0); 1411 1412 DC_LOG_IPS( 1413 "resync inbox1 (ips1_commit=%u ips2_commit=%u)", 1414 ips_fw->signals.bits.ips1_commit, 1415 ips_fw->signals.bits.ips2_commit); 1416 1417 dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub); 1418 } 1419 } 1420 1421 dc_dmub_srv_notify_idle(dc, false); 1422 if (prev_driver_signals.bits.allow_ips1 || prev_driver_signals.all == 0) { 1423 DC_LOG_IPS( 1424 "wait for IPS1 commit clear (ips1_commit=%u ips2_commit=%u)", 1425 ips_fw->signals.bits.ips1_commit, 1426 ips_fw->signals.bits.ips2_commit); 1427 1428 while (ips_fw->signals.bits.ips1_commit) 1429 udelay(1); 1430 1431 DC_LOG_IPS( 1432 "wait for IPS1 commit clear done (ips1_commit=%u ips2_commit=%u)", 1433 ips_fw->signals.bits.ips1_commit, 1434 ips_fw->signals.bits.ips2_commit); 1435 } 1436 } 1437 1438 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true)) 1439 ASSERT(0); 1440 1441 DC_LOG_IPS("%s exit (count rcg=%u ips1=%u ips2=%u)", 1442 __func__, 1443 rcg_exit_count, 1444 ips1_exit_count, 1445 ips2_exit_count); 1446 } 1447 1448 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state) 1449 { 1450 struct dmub_srv *dmub; 1451 1452 if (!dc_dmub_srv) 1453 return; 1454 1455 dmub = dc_dmub_srv->dmub; 1456 1457 if (power_state == DC_ACPI_CM_POWER_STATE_D0) 1458 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0); 1459 else 1460 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3); 1461 } 1462 1463 void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, 1464 enum dc_acpi_cm_power_state power_state) 1465 { 1466 union dmub_rb_cmd cmd; 1467 1468 if (!dc_dmub_srv) 1469 return; 1470 1471 memset(&cmd, 0, sizeof(cmd)); 1472 1473 cmd.idle_opt_set_dc_power_state.header.type = DMUB_CMD__IDLE_OPT; 1474 cmd.idle_opt_set_dc_power_state.header.sub_type = DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE; 1475 cmd.idle_opt_set_dc_power_state.header.payload_bytes = 1476 sizeof(cmd.idle_opt_set_dc_power_state) - sizeof(cmd.idle_opt_set_dc_power_state.header); 1477 1478 if (power_state == DC_ACPI_CM_POWER_STATE_D0) { 1479 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D0; 1480 } else if (power_state == DC_ACPI_CM_POWER_STATE_D3) { 1481 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D3; 1482 } else { 1483 cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN; 1484 } 1485 1486 dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1487 } 1488 1489 bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) 1490 { 1491 volatile const struct dmub_shared_state_ips_fw *ips_fw; 1492 bool reallow_idle = false, should_detect = false; 1493 1494 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1495 return false; 1496 1497 if (dc_dmub_srv->dmub->shared_state && 1498 dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) { 1499 ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 1500 return ips_fw->signals.bits.detection_required; 1501 } 1502 1503 /* Detection may require reading scratch 0 - exit out of idle prior to the read. */ 1504 if (dc_dmub_srv->idle_allowed) { 1505 dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false); 1506 reallow_idle = true; 1507 } 1508 1509 should_detect = dmub_srv_should_detect(dc_dmub_srv->dmub); 1510 1511 /* Re-enter idle if we're not about to immediately redetect links. */ 1512 if (!should_detect && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1513 !dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle) 1514 dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true); 1515 1516 return should_detect; 1517 } 1518 1519 void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle) 1520 { 1521 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; 1522 1523 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1524 return; 1525 1526 allow_idle &= (!dc->debug.ips_disallow_entry); 1527 1528 if (dc_dmub_srv->idle_allowed == allow_idle) 1529 return; 1530 1531 DC_LOG_IPS("%s state change: old=%d new=%d", __func__, dc_dmub_srv->idle_allowed, allow_idle); 1532 1533 /* 1534 * Entering a low power state requires a driver notification. 1535 * Powering up the hardware requires notifying PMFW and DMCUB. 1536 * Clearing the driver idle allow requires a DMCUB command. 1537 * DMCUB commands requires the DMCUB to be powered up and restored. 1538 */ 1539 1540 if (!allow_idle) { 1541 dc_dmub_srv->idle_exit_counter += 1; 1542 1543 dc_dmub_srv_exit_low_power_state(dc); 1544 /* 1545 * Idle is considered fully exited only after the sequence above 1546 * fully completes. If we have a race of two threads exiting 1547 * at the same time then it's safe to perform the sequence 1548 * twice as long as we're not re-entering. 1549 * 1550 * Infinite command submission is avoided by using the 1551 * dm_execute_dmub_cmd submission instead of the "wake" helpers. 1552 */ 1553 dc_dmub_srv->idle_allowed = false; 1554 1555 dc_dmub_srv->idle_exit_counter -= 1; 1556 if (dc_dmub_srv->idle_exit_counter < 0) { 1557 ASSERT(0); 1558 dc_dmub_srv->idle_exit_counter = 0; 1559 } 1560 } else { 1561 /* Consider idle as notified prior to the actual submission to 1562 * prevent multiple entries. */ 1563 dc_dmub_srv->idle_allowed = true; 1564 1565 dc_dmub_srv_notify_idle(dc, allow_idle); 1566 } 1567 } 1568 1569 bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, 1570 enum dm_dmub_wait_type wait_type) 1571 { 1572 return dc_wake_and_execute_dmub_cmd_list(ctx, 1, cmd, wait_type); 1573 } 1574 1575 bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, 1576 union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 1577 { 1578 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1579 bool result = false, reallow_idle = false; 1580 1581 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1582 return false; 1583 1584 if (count == 0) 1585 return true; 1586 1587 if (dc_dmub_srv->idle_allowed) { 1588 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false); 1589 reallow_idle = true; 1590 } 1591 1592 /* 1593 * These may have different implementations in DM, so ensure 1594 * that we guide it to the expected helper. 1595 */ 1596 if (count > 1) 1597 result = dm_execute_dmub_cmd_list(ctx, count, cmd, wait_type); 1598 else 1599 result = dm_execute_dmub_cmd(ctx, cmd, wait_type); 1600 1601 if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1602 !ctx->dc->debug.disable_dmub_reallow_idle) 1603 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); 1604 1605 return result; 1606 } 1607 1608 static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 1609 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type) 1610 { 1611 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1612 const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30; 1613 enum dmub_status status; 1614 1615 if (response) 1616 *response = 0; 1617 1618 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1619 return false; 1620 1621 status = dmub_srv_send_gpint_command(dc_dmub_srv->dmub, command_code, param, wait_us); 1622 if (status != DMUB_STATUS_OK) { 1623 if (status == DMUB_STATUS_TIMEOUT && wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT) 1624 return true; 1625 1626 return false; 1627 } 1628 1629 if (response && wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 1630 dmub_srv_get_gpint_response(dc_dmub_srv->dmub, response); 1631 1632 return true; 1633 } 1634 1635 bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code, 1636 uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type) 1637 { 1638 struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv; 1639 bool result = false, reallow_idle = false; 1640 1641 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1642 return false; 1643 1644 if (dc_dmub_srv->idle_allowed) { 1645 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false); 1646 reallow_idle = true; 1647 } 1648 1649 result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type); 1650 1651 if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && 1652 !ctx->dc->debug.disable_dmub_reallow_idle) 1653 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); 1654 1655 return result; 1656 } 1657 1658 void dc_dmub_srv_fams2_update_config(struct dc *dc, 1659 struct dc_state *context, 1660 bool enable) 1661 { 1662 uint8_t num_cmds = 1; 1663 uint32_t i; 1664 union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1]; 1665 struct dmub_rb_cmd_fams2 *global_cmd = &cmd[0].fams2_config; 1666 1667 memset(cmd, 0, sizeof(union dmub_rb_cmd) * (2 * MAX_STREAMS + 1)); 1668 /* fill in generic command header */ 1669 global_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1670 global_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1671 global_cmd->header.payload_bytes = 1672 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1673 1674 if (enable) { 1675 /* send global configuration parameters */ 1676 memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub_cmd_fams2_global_config)); 1677 1678 /* copy static feature configuration overrides */ 1679 global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery; 1680 global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug; 1681 global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip; 1682 1683 /* construct per-stream configs */ 1684 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { 1685 struct dmub_rb_cmd_fams2 *stream_base_cmd = &cmd[i+1].fams2_config; 1686 struct dmub_rb_cmd_fams2 *stream_sub_state_cmd = &cmd[i+1+context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config; 1687 1688 /* configure command header */ 1689 stream_base_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1690 stream_base_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1691 stream_base_cmd->header.payload_bytes = 1692 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1693 stream_base_cmd->header.multi_cmd_pending = 1; 1694 stream_sub_state_cmd->header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1695 stream_sub_state_cmd->header.sub_type = DMUB_CMD__FAMS2_CONFIG; 1696 stream_sub_state_cmd->header.payload_bytes = 1697 sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header); 1698 stream_sub_state_cmd->header.multi_cmd_pending = 1; 1699 /* copy stream static base state */ 1700 memcpy(&stream_base_cmd->config, 1701 &context->bw_ctx.bw.dcn.fams2_stream_base_params[i], 1702 sizeof(union dmub_cmd_fams2_config)); 1703 /* copy stream static sub state */ 1704 memcpy(&stream_sub_state_cmd->config, 1705 &context->bw_ctx.bw.dcn.fams2_stream_sub_params[i], 1706 sizeof(union dmub_cmd_fams2_config)); 1707 } 1708 } 1709 1710 /* apply feature configuration based on current driver state */ 1711 global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2; 1712 global_cmd->config.global.features.bits.enable = enable; 1713 1714 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { 1715 /* set multi pending for global, and unset for last stream cmd */ 1716 global_cmd->header.multi_cmd_pending = 1; 1717 cmd[2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending = 0; 1718 num_cmds += 2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams; 1719 } 1720 1721 dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmd, DM_DMUB_WAIT_TYPE_WAIT); 1722 } 1723 1724 void dc_dmub_srv_fams2_drr_update(struct dc *dc, 1725 uint32_t tg_inst, 1726 uint32_t vtotal_min, 1727 uint32_t vtotal_max, 1728 uint32_t vtotal_mid, 1729 uint32_t vtotal_mid_frame_num, 1730 bool program_manual_trigger) 1731 { 1732 union dmub_rb_cmd cmd = { 0 }; 1733 1734 cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1735 cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE; 1736 cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst; 1737 cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max; 1738 cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min; 1739 cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid; 1740 cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid_frame_num = vtotal_mid_frame_num; 1741 cmd.fams2_drr_update.dmub_optc_state_req.program_manual_trigger = program_manual_trigger; 1742 1743 cmd.fams2_drr_update.header.payload_bytes = 1744 sizeof(cmd.fams2_drr_update) - sizeof(cmd.fams2_drr_update.header); 1745 1746 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1747 } 1748 1749 void dc_dmub_srv_fams2_passthrough_flip( 1750 struct dc *dc, 1751 struct dc_state *state, 1752 struct dc_stream_state *stream, 1753 struct dc_surface_update *srf_updates, 1754 int surface_count) 1755 { 1756 int plane_index; 1757 union dmub_rb_cmd cmds[MAX_PLANES]; 1758 struct dc_plane_address *address; 1759 struct dc_plane_state *plane_state; 1760 int num_cmds = 0; 1761 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 1762 1763 if (surface_count <= 0 || stream_status == NULL) 1764 return; 1765 1766 memset(cmds, 0, sizeof(union dmub_rb_cmd) * MAX_PLANES); 1767 1768 /* build command for each surface update */ 1769 for (plane_index = 0; plane_index < surface_count; plane_index++) { 1770 plane_state = srf_updates[plane_index].surface; 1771 address = &plane_state->address; 1772 1773 /* skip if there is no address update for plane */ 1774 if (!srf_updates[plane_index].flip_addr) 1775 continue; 1776 1777 /* build command header */ 1778 cmds[num_cmds].fams2_flip.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; 1779 cmds[num_cmds].fams2_flip.header.sub_type = DMUB_CMD__FAMS2_FLIP; 1780 cmds[num_cmds].fams2_flip.header.payload_bytes = 1781 sizeof(struct dmub_rb_cmd_fams2_flip) - sizeof(struct dmub_cmd_header); 1782 1783 /* for chaining multiple commands, all but last command should set to 1 */ 1784 cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1; 1785 1786 /* set topology info */ 1787 cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state); 1788 if (stream_status) 1789 cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst; 1790 1791 cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate; 1792 1793 /* build address info for command */ 1794 switch (address->type) { 1795 case PLN_ADDR_TYPE_GRAPHICS: 1796 if (address->grph.addr.quad_part == 0) { 1797 BREAK_TO_DEBUGGER(); 1798 break; 1799 } 1800 1801 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo = 1802 address->grph.meta_addr.low_part; 1803 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi = 1804 (uint16_t)address->grph.meta_addr.high_part; 1805 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo = 1806 address->grph.addr.low_part; 1807 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi = 1808 (uint16_t)address->grph.addr.high_part; 1809 break; 1810 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 1811 if (address->video_progressive.luma_addr.quad_part == 0 || 1812 address->video_progressive.chroma_addr.quad_part == 0) { 1813 BREAK_TO_DEBUGGER(); 1814 break; 1815 } 1816 1817 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo = 1818 address->video_progressive.luma_meta_addr.low_part; 1819 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi = 1820 (uint16_t)address->video_progressive.luma_meta_addr.high_part; 1821 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_lo = 1822 address->video_progressive.chroma_meta_addr.low_part; 1823 cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_hi = 1824 (uint16_t)address->video_progressive.chroma_meta_addr.high_part; 1825 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo = 1826 address->video_progressive.luma_addr.low_part; 1827 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi = 1828 (uint16_t)address->video_progressive.luma_addr.high_part; 1829 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_lo = 1830 address->video_progressive.chroma_addr.low_part; 1831 cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_hi = 1832 (uint16_t)address->video_progressive.chroma_addr.high_part; 1833 break; 1834 default: 1835 // Should never be hit 1836 BREAK_TO_DEBUGGER(); 1837 break; 1838 } 1839 1840 num_cmds++; 1841 } 1842 1843 if (num_cmds > 0) { 1844 cmds[num_cmds - 1].fams2_flip.header.multi_cmd_pending = 0; 1845 dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT); 1846 } 1847 } 1848 1849 bool dc_dmub_srv_ips_residency_cntl(struct dc_dmub_srv *dc_dmub_srv, bool start_measurement) 1850 { 1851 bool result; 1852 1853 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1854 return false; 1855 1856 result = dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IPS_RESIDENCY, 1857 start_measurement, NULL, DM_DMUB_WAIT_TYPE_WAIT); 1858 1859 return result; 1860 } 1861 1862 void dc_dmub_srv_ips_query_residency_info(struct dc_dmub_srv *dc_dmub_srv, struct ips_residency_info *output) 1863 { 1864 uint32_t i; 1865 enum dmub_gpint_command command_code; 1866 1867 if (!dc_dmub_srv || !dc_dmub_srv->dmub) 1868 return; 1869 1870 switch (output->ips_mode) { 1871 case DMUB_IPS_MODE_IPS1_MAX: 1872 command_code = DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER; 1873 break; 1874 case DMUB_IPS_MODE_IPS2: 1875 command_code = DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER; 1876 break; 1877 case DMUB_IPS_MODE_IPS1_RCG: 1878 command_code = DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER; 1879 break; 1880 case DMUB_IPS_MODE_IPS1_ONO2_ON: 1881 command_code = DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER; 1882 break; 1883 default: 1884 command_code = DMUB_GPINT__INVALID_COMMAND; 1885 break; 1886 } 1887 1888 if (command_code == DMUB_GPINT__INVALID_COMMAND) 1889 return; 1890 1891 // send gpint commands and wait for ack 1892 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT, 1893 (uint16_t)(output->ips_mode), 1894 &output->residency_percent, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1895 output->residency_percent = 0; 1896 1897 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER, 1898 (uint16_t)(output->ips_mode), 1899 &output->entry_counter, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1900 output->entry_counter = 0; 1901 1902 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO, 1903 (uint16_t)(output->ips_mode), 1904 &output->total_active_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1905 output->total_active_time_us[0] = 0; 1906 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI, 1907 (uint16_t)(output->ips_mode), 1908 &output->total_active_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1909 output->total_active_time_us[1] = 0; 1910 1911 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO, 1912 (uint16_t)(output->ips_mode), 1913 &output->total_inactive_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1914 output->total_inactive_time_us[0] = 0; 1915 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI, 1916 (uint16_t)(output->ips_mode), 1917 &output->total_inactive_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1918 output->total_inactive_time_us[1] = 0; 1919 1920 // NUM_IPS_HISTOGRAM_BUCKETS = 16 1921 for (i = 0; i < 16; i++) 1922 if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, command_code, i, &output->histogram[i], 1923 DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 1924 output->histogram[i] = 0; 1925 } 1926