1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.157" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 struct dc_plane_cap { 79 enum dc_plane_type type; 80 uint32_t blends_with_above : 1; 81 uint32_t blends_with_below : 1; 82 uint32_t per_pixel_alpha : 1; 83 struct { 84 uint32_t argb8888 : 1; 85 uint32_t nv12 : 1; 86 uint32_t fp16 : 1; 87 uint32_t p010 : 1; 88 uint32_t ayuv : 1; 89 } pixel_format_support; 90 // max upscaling factor x1000 91 // upscaling factors are always >= 1 92 // for example, 1080p -> 8K is 4.0, or 4000 raw value 93 struct { 94 uint32_t argb8888; 95 uint32_t nv12; 96 uint32_t fp16; 97 } max_upscale_factor; 98 // max downscale factor x1000 99 // downscale factors are always <= 1 100 // for example, 8K -> 1080p is 0.25, or 250 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_downscale_factor; 106 // minimal width/height 107 uint32_t min_width; 108 uint32_t min_height; 109 }; 110 111 // Color management caps (DPP and MPC) 112 struct rom_curve_caps { 113 uint16_t srgb : 1; 114 uint16_t bt2020 : 1; 115 uint16_t gamma2_2 : 1; 116 uint16_t pq : 1; 117 uint16_t hlg : 1; 118 }; 119 120 struct dpp_color_caps { 121 uint16_t dcn_arch : 1; // all DCE generations treated the same 122 // input lut is different than most LUTs, just plain 256-entry lookup 123 uint16_t input_lut_shared : 1; // shared with DGAM 124 uint16_t icsc : 1; 125 uint16_t dgam_ram : 1; 126 uint16_t post_csc : 1; // before gamut remap 127 uint16_t gamma_corr : 1; 128 129 // hdr_mult and gamut remap always available in DPP (in that order) 130 // 3d lut implies shaper LUT, 131 // it may be shared with MPC - check MPC:shared_3d_lut flag 132 uint16_t hw_3d_lut : 1; 133 uint16_t ogam_ram : 1; // blnd gam 134 uint16_t ocsc : 1; 135 uint16_t dgam_rom_for_yuv : 1; 136 struct rom_curve_caps dgam_rom_caps; 137 struct rom_curve_caps ogam_rom_caps; 138 }; 139 140 struct mpc_color_caps { 141 uint16_t gamut_remap : 1; 142 uint16_t ogam_ram : 1; 143 uint16_t ocsc : 1; 144 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 145 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 146 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct dc_color_caps { 151 struct dpp_color_caps dpp; 152 struct mpc_color_caps mpc; 153 }; 154 155 struct dc_caps { 156 uint32_t max_streams; 157 uint32_t max_links; 158 uint32_t max_audios; 159 uint32_t max_slave_planes; 160 uint32_t max_slave_yuv_planes; 161 uint32_t max_slave_rgb_planes; 162 uint32_t max_planes; 163 uint32_t max_downscale_ratio; 164 uint32_t i2c_speed_in_khz; 165 uint32_t i2c_speed_in_khz_hdcp; 166 uint32_t dmdata_alloc_size; 167 unsigned int max_cursor_size; 168 unsigned int max_video_width; 169 unsigned int min_horizontal_blanking_period; 170 int linear_pitch_alignment; 171 bool dcc_const_color; 172 bool dynamic_audio; 173 bool is_apu; 174 bool dual_link_dvi; 175 bool post_blend_color_processing; 176 bool force_dp_tps4_for_cp2520; 177 bool disable_dp_clk_share; 178 bool psp_setup_panel_mode; 179 bool extended_aux_timeout_support; 180 bool dmcub_support; 181 uint32_t num_of_internal_disp; 182 enum dp_protocol_version max_dp_protocol_version; 183 unsigned int mall_size_per_mem_channel; 184 unsigned int mall_size_total; 185 unsigned int cursor_cache_size; 186 struct dc_plane_cap planes[MAX_PLANES]; 187 struct dc_color_caps color; 188 #if defined(CONFIG_DRM_AMD_DC_DCN) 189 bool dp_hpo; 190 #endif 191 bool vbios_lttpr_aware; 192 bool vbios_lttpr_enable; 193 }; 194 195 struct dc_bug_wa { 196 bool no_connect_phy_config; 197 bool dedcn20_305_wa; 198 bool skip_clock_update; 199 bool lt_early_cr_pattern; 200 }; 201 202 struct dc_dcc_surface_param { 203 struct dc_size surface_size; 204 enum surface_pixel_format format; 205 enum swizzle_mode_values swizzle_mode; 206 enum dc_scan_direction scan; 207 }; 208 209 struct dc_dcc_setting { 210 unsigned int max_compressed_blk_size; 211 unsigned int max_uncompressed_blk_size; 212 bool independent_64b_blks; 213 #if defined(CONFIG_DRM_AMD_DC_DCN) 214 //These bitfields to be used starting with DCN 215 struct { 216 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 217 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 218 uint32_t dcc_256_128_128 : 1; //available starting with DCN 219 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 220 } dcc_controls; 221 #endif 222 }; 223 224 struct dc_surface_dcc_cap { 225 union { 226 struct { 227 struct dc_dcc_setting rgb; 228 } grph; 229 230 struct { 231 struct dc_dcc_setting luma; 232 struct dc_dcc_setting chroma; 233 } video; 234 }; 235 236 bool capable; 237 bool const_color_support; 238 }; 239 240 struct dc_static_screen_params { 241 struct { 242 bool force_trigger; 243 bool cursor_update; 244 bool surface_update; 245 bool overlay_update; 246 } triggers; 247 unsigned int num_frames; 248 }; 249 250 251 /* Surface update type is used by dc_update_surfaces_and_stream 252 * The update type is determined at the very beginning of the function based 253 * on parameters passed in and decides how much programming (or updating) is 254 * going to be done during the call. 255 * 256 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 257 * logical calculations or hardware register programming. This update MUST be 258 * ISR safe on windows. Currently fast update will only be used to flip surface 259 * address. 260 * 261 * UPDATE_TYPE_MED is used for slower updates which require significant hw 262 * re-programming however do not affect bandwidth consumption or clock 263 * requirements. At present, this is the level at which front end updates 264 * that do not require us to run bw_calcs happen. These are in/out transfer func 265 * updates, viewport offset changes, recout size changes and pixel depth changes. 266 * This update can be done at ISR, but we want to minimize how often this happens. 267 * 268 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 269 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 270 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 271 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 272 * a full update. This cannot be done at ISR level and should be a rare event. 273 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 274 * underscan we don't expect to see this call at all. 275 */ 276 277 enum surface_update_type { 278 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 279 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 280 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 281 }; 282 283 /* Forward declaration*/ 284 struct dc; 285 struct dc_plane_state; 286 struct dc_state; 287 288 289 struct dc_cap_funcs { 290 bool (*get_dcc_compression_cap)(const struct dc *dc, 291 const struct dc_dcc_surface_param *input, 292 struct dc_surface_dcc_cap *output); 293 }; 294 295 struct link_training_settings; 296 297 #if defined(CONFIG_DRM_AMD_DC_DCN) 298 union allow_lttpr_non_transparent_mode { 299 struct { 300 bool DP1_4A : 1; 301 bool DP2_0 : 1; 302 } bits; 303 unsigned char raw; 304 }; 305 #endif 306 /* Structure to hold configuration flags set by dm at dc creation. */ 307 struct dc_config { 308 bool gpu_vm_support; 309 bool disable_disp_pll_sharing; 310 bool fbc_support; 311 bool disable_fractional_pwm; 312 bool allow_seamless_boot_optimization; 313 bool power_down_display_on_boot; 314 bool edp_not_connected; 315 bool edp_no_power_sequencing; 316 bool force_enum_edp; 317 bool forced_clocks; 318 #if defined(CONFIG_DRM_AMD_DC_DCN) 319 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 320 #else 321 bool allow_lttpr_non_transparent_mode; 322 #endif 323 bool multi_mon_pp_mclk_switch; 324 bool disable_dmcu; 325 bool enable_4to1MPC; 326 bool allow_edp_hotplug_detection; 327 #if defined(CONFIG_DRM_AMD_DC_DCN) 328 bool clamp_min_dcfclk; 329 #endif 330 uint64_t vblank_alignment_dto_params; 331 uint8_t vblank_alignment_max_frame_time_diff; 332 bool is_asymmetric_memory; 333 bool is_single_rank_dimm; 334 }; 335 336 enum visual_confirm { 337 VISUAL_CONFIRM_DISABLE = 0, 338 VISUAL_CONFIRM_SURFACE = 1, 339 VISUAL_CONFIRM_HDR = 2, 340 VISUAL_CONFIRM_MPCTREE = 4, 341 VISUAL_CONFIRM_PSR = 5, 342 VISUAL_CONFIRM_SWIZZLE = 9, 343 }; 344 345 enum dc_psr_power_opts { 346 psr_power_opt_invalid = 0x0, 347 psr_power_opt_smu_opt_static_screen = 0x1, 348 psr_power_opt_z10_static_screen = 0x10, 349 }; 350 351 enum dcc_option { 352 DCC_ENABLE = 0, 353 DCC_DISABLE = 1, 354 DCC_HALF_REQ_DISALBE = 2, 355 }; 356 357 enum pipe_split_policy { 358 MPC_SPLIT_DYNAMIC = 0, 359 MPC_SPLIT_AVOID = 1, 360 MPC_SPLIT_AVOID_MULT_DISP = 2, 361 }; 362 363 enum wm_report_mode { 364 WM_REPORT_DEFAULT = 0, 365 WM_REPORT_OVERRIDE = 1, 366 }; 367 enum dtm_pstate{ 368 dtm_level_p0 = 0,/*highest voltage*/ 369 dtm_level_p1, 370 dtm_level_p2, 371 dtm_level_p3, 372 dtm_level_p4,/*when active_display_count = 0*/ 373 }; 374 375 enum dcn_pwr_state { 376 DCN_PWR_STATE_UNKNOWN = -1, 377 DCN_PWR_STATE_MISSION_MODE = 0, 378 DCN_PWR_STATE_LOW_POWER = 3, 379 }; 380 381 #if defined(CONFIG_DRM_AMD_DC_DCN) 382 enum dcn_zstate_support_state { 383 DCN_ZSTATE_SUPPORT_UNKNOWN, 384 DCN_ZSTATE_SUPPORT_ALLOW, 385 DCN_ZSTATE_SUPPORT_DISALLOW, 386 }; 387 #endif 388 /* 389 * For any clocks that may differ per pipe 390 * only the max is stored in this structure 391 */ 392 struct dc_clocks { 393 int dispclk_khz; 394 int actual_dispclk_khz; 395 int dppclk_khz; 396 int actual_dppclk_khz; 397 int disp_dpp_voltage_level_khz; 398 int dcfclk_khz; 399 int socclk_khz; 400 int dcfclk_deep_sleep_khz; 401 int fclk_khz; 402 int phyclk_khz; 403 int dramclk_khz; 404 bool p_state_change_support; 405 #if defined(CONFIG_DRM_AMD_DC_DCN) 406 enum dcn_zstate_support_state zstate_support; 407 bool dtbclk_en; 408 #endif 409 enum dcn_pwr_state pwr_state; 410 /* 411 * Elements below are not compared for the purposes of 412 * optimization required 413 */ 414 bool prev_p_state_change_support; 415 enum dtm_pstate dtm_level; 416 int max_supported_dppclk_khz; 417 int max_supported_dispclk_khz; 418 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 419 int bw_dispclk_khz; 420 }; 421 422 struct dc_bw_validation_profile { 423 bool enable; 424 425 unsigned long long total_ticks; 426 unsigned long long voltage_level_ticks; 427 unsigned long long watermark_ticks; 428 unsigned long long rq_dlg_ticks; 429 430 unsigned long long total_count; 431 unsigned long long skip_fast_count; 432 unsigned long long skip_pass_count; 433 unsigned long long skip_fail_count; 434 }; 435 436 #define BW_VAL_TRACE_SETUP() \ 437 unsigned long long end_tick = 0; \ 438 unsigned long long voltage_level_tick = 0; \ 439 unsigned long long watermark_tick = 0; \ 440 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 441 dm_get_timestamp(dc->ctx) : 0 442 443 #define BW_VAL_TRACE_COUNT() \ 444 if (dc->debug.bw_val_profile.enable) \ 445 dc->debug.bw_val_profile.total_count++ 446 447 #define BW_VAL_TRACE_SKIP(status) \ 448 if (dc->debug.bw_val_profile.enable) { \ 449 if (!voltage_level_tick) \ 450 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 451 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 452 } 453 454 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 455 if (dc->debug.bw_val_profile.enable) \ 456 voltage_level_tick = dm_get_timestamp(dc->ctx) 457 458 #define BW_VAL_TRACE_END_WATERMARKS() \ 459 if (dc->debug.bw_val_profile.enable) \ 460 watermark_tick = dm_get_timestamp(dc->ctx) 461 462 #define BW_VAL_TRACE_FINISH() \ 463 if (dc->debug.bw_val_profile.enable) { \ 464 end_tick = dm_get_timestamp(dc->ctx); \ 465 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 466 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 467 if (watermark_tick) { \ 468 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 469 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 470 } \ 471 } 472 473 union mem_low_power_enable_options { 474 struct { 475 bool vga: 1; 476 bool i2c: 1; 477 bool dmcu: 1; 478 bool dscl: 1; 479 bool cm: 1; 480 bool mpc: 1; 481 bool optc: 1; 482 bool vpg: 1; 483 bool afmt: 1; 484 } bits; 485 uint32_t u32All; 486 }; 487 488 union root_clock_optimization_options { 489 struct { 490 bool dpp: 1; 491 bool dsc: 1; 492 bool hdmistream: 1; 493 bool hdmichar: 1; 494 bool dpstream: 1; 495 bool symclk32_se: 1; 496 bool symclk32_le: 1; 497 bool symclk_fe: 1; 498 bool physymclk: 1; 499 bool dpiasymclk: 1; 500 uint32_t reserved: 22; 501 } bits; 502 uint32_t u32All; 503 }; 504 505 union dpia_debug_options { 506 struct { 507 uint32_t disable_dpia:1; 508 uint32_t force_non_lttpr:1; 509 uint32_t extend_aux_rd_interval:1; 510 uint32_t reserved:29; 511 } bits; 512 uint32_t raw; 513 }; 514 515 struct dc_debug_data { 516 uint32_t ltFailCount; 517 uint32_t i2cErrorCount; 518 uint32_t auxErrorCount; 519 }; 520 521 struct dc_phy_addr_space_config { 522 struct { 523 uint64_t start_addr; 524 uint64_t end_addr; 525 uint64_t fb_top; 526 uint64_t fb_offset; 527 uint64_t fb_base; 528 uint64_t agp_top; 529 uint64_t agp_bot; 530 uint64_t agp_base; 531 } system_aperture; 532 533 struct { 534 uint64_t page_table_start_addr; 535 uint64_t page_table_end_addr; 536 uint64_t page_table_base_addr; 537 bool base_addr_is_mc_addr; 538 } gart_config; 539 540 bool valid; 541 bool is_hvm_enabled; 542 uint64_t page_table_default_page_addr; 543 }; 544 545 struct dc_virtual_addr_space_config { 546 uint64_t page_table_base_addr; 547 uint64_t page_table_start_addr; 548 uint64_t page_table_end_addr; 549 uint32_t page_table_block_size_in_bytes; 550 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 551 }; 552 553 struct dc_bounding_box_overrides { 554 int sr_exit_time_ns; 555 int sr_enter_plus_exit_time_ns; 556 int urgent_latency_ns; 557 int percent_of_ideal_drambw; 558 int dram_clock_change_latency_ns; 559 int dummy_clock_change_latency_ns; 560 /* This forces a hard min on the DCFCLK we use 561 * for DML. Unlike the debug option for forcing 562 * DCFCLK, this override affects watermark calculations 563 */ 564 int min_dcfclk_mhz; 565 }; 566 567 struct dc_state; 568 struct resource_pool; 569 struct dce_hwseq; 570 571 struct dc_debug_options { 572 bool native422_support; 573 bool disable_dsc; 574 enum visual_confirm visual_confirm; 575 bool sanity_checks; 576 bool max_disp_clk; 577 bool surface_trace; 578 bool timing_trace; 579 bool clock_trace; 580 bool validation_trace; 581 bool bandwidth_calcs_trace; 582 int max_downscale_src_width; 583 584 /* stutter efficiency related */ 585 bool disable_stutter; 586 bool use_max_lb; 587 enum dcc_option disable_dcc; 588 enum pipe_split_policy pipe_split_policy; 589 bool force_single_disp_pipe_split; 590 bool voltage_align_fclk; 591 bool disable_min_fclk; 592 593 bool disable_dfs_bypass; 594 bool disable_dpp_power_gate; 595 bool disable_hubp_power_gate; 596 bool disable_dsc_power_gate; 597 int dsc_min_slice_height_override; 598 int dsc_bpp_increment_div; 599 bool disable_pplib_wm_range; 600 enum wm_report_mode pplib_wm_report_mode; 601 unsigned int min_disp_clk_khz; 602 unsigned int min_dpp_clk_khz; 603 unsigned int min_dram_clk_khz; 604 int sr_exit_time_dpm0_ns; 605 int sr_enter_plus_exit_time_dpm0_ns; 606 int sr_exit_time_ns; 607 int sr_enter_plus_exit_time_ns; 608 int urgent_latency_ns; 609 uint32_t underflow_assert_delay_us; 610 int percent_of_ideal_drambw; 611 int dram_clock_change_latency_ns; 612 bool optimized_watermark; 613 int always_scale; 614 bool disable_pplib_clock_request; 615 bool disable_clock_gate; 616 bool disable_mem_low_power; 617 #if defined(CONFIG_DRM_AMD_DC_DCN) 618 bool pstate_enabled; 619 #endif 620 bool disable_dmcu; 621 bool disable_psr; 622 bool force_abm_enable; 623 bool disable_stereo_support; 624 bool vsr_support; 625 bool performance_trace; 626 bool az_endpoint_mute_only; 627 bool always_use_regamma; 628 bool recovery_enabled; 629 bool avoid_vbios_exec_table; 630 bool scl_reset_length10; 631 bool hdmi20_disable; 632 bool skip_detection_link_training; 633 uint32_t edid_read_retry_times; 634 bool remove_disconnect_edp; 635 unsigned int force_odm_combine; //bit vector based on otg inst 636 #if defined(CONFIG_DRM_AMD_DC_DCN) 637 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 638 bool disable_z9_mpc; 639 #endif 640 unsigned int force_fclk_khz; 641 bool enable_tri_buf; 642 bool dmub_offload_enabled; 643 bool dmcub_emulation; 644 #if defined(CONFIG_DRM_AMD_DC_DCN) 645 bool disable_idle_power_optimizations; 646 unsigned int mall_size_override; 647 unsigned int mall_additional_timer_percent; 648 bool mall_error_as_fatal; 649 #endif 650 bool dmub_command_table; /* for testing only */ 651 struct dc_bw_validation_profile bw_val_profile; 652 bool disable_fec; 653 bool disable_48mhz_pwrdwn; 654 /* This forces a hard min on the DCFCLK requested to SMU/PP 655 * watermarks are not affected. 656 */ 657 unsigned int force_min_dcfclk_mhz; 658 #if defined(CONFIG_DRM_AMD_DC_DCN) 659 int dwb_fi_phase; 660 #endif 661 bool disable_timing_sync; 662 bool cm_in_bypass; 663 int force_clock_mode;/*every mode change.*/ 664 665 bool disable_dram_clock_change_vactive_support; 666 bool validate_dml_output; 667 bool enable_dmcub_surface_flip; 668 bool usbc_combo_phy_reset_wa; 669 bool enable_dram_clock_change_one_display_vactive; 670 #if defined(CONFIG_DRM_AMD_DC_DCN) 671 /* TODO - remove once tested */ 672 bool legacy_dp2_lt; 673 bool set_mst_en_for_sst; 674 #endif 675 union mem_low_power_enable_options enable_mem_low_power; 676 union root_clock_optimization_options root_clock_optimization; 677 bool force_vblank_alignment; 678 679 /* Enable dmub aux for legacy ddc */ 680 bool enable_dmub_aux_for_legacy_ddc; 681 bool optimize_edp_link_rate; /* eDP ILR */ 682 /* FEC/PSR1 sequence enable delay in 100us */ 683 uint8_t fec_enable_delay_in100us; 684 bool enable_driver_sequence_debug; 685 #if defined(CONFIG_DRM_AMD_DC_DCN) 686 bool disable_z10; 687 bool enable_sw_cntl_psr; 688 union dpia_debug_options dpia_debug; 689 #endif 690 }; 691 692 struct gpu_info_soc_bounding_box_v1_0; 693 struct dc { 694 struct dc_debug_options debug; 695 struct dc_versions versions; 696 struct dc_caps caps; 697 struct dc_cap_funcs cap_funcs; 698 struct dc_config config; 699 struct dc_bounding_box_overrides bb_overrides; 700 struct dc_bug_wa work_arounds; 701 struct dc_context *ctx; 702 struct dc_phy_addr_space_config vm_pa_config; 703 704 uint8_t link_count; 705 struct dc_link *links[MAX_PIPES * 2]; 706 707 struct dc_state *current_state; 708 struct resource_pool *res_pool; 709 710 struct clk_mgr *clk_mgr; 711 712 /* Display Engine Clock levels */ 713 struct dm_pp_clock_levels sclk_lvls; 714 715 /* Inputs into BW and WM calculations. */ 716 struct bw_calcs_dceip *bw_dceip; 717 struct bw_calcs_vbios *bw_vbios; 718 #ifdef CONFIG_DRM_AMD_DC_DCN 719 struct dcn_soc_bounding_box *dcn_soc; 720 struct dcn_ip_params *dcn_ip; 721 struct display_mode_lib dml; 722 #endif 723 724 /* HW functions */ 725 struct hw_sequencer_funcs hwss; 726 struct dce_hwseq *hwseq; 727 728 /* Require to optimize clocks and bandwidth for added/removed planes */ 729 bool optimized_required; 730 bool wm_optimized_required; 731 #if defined(CONFIG_DRM_AMD_DC_DCN) 732 bool idle_optimizations_allowed; 733 #endif 734 #if defined(CONFIG_DRM_AMD_DC_DCN) 735 bool enable_c20_dtm_b0; 736 #endif 737 738 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 739 740 /* FBC compressor */ 741 struct compressor *fbc_compressor; 742 743 struct dc_debug_data debug_data; 744 struct dpcd_vendor_signature vendor_signature; 745 746 const char *build_id; 747 struct vm_helper *vm_helper; 748 }; 749 750 enum frame_buffer_mode { 751 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 752 FRAME_BUFFER_MODE_ZFB_ONLY, 753 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 754 } ; 755 756 struct dchub_init_data { 757 int64_t zfb_phys_addr_base; 758 int64_t zfb_mc_base_addr; 759 uint64_t zfb_size_in_byte; 760 enum frame_buffer_mode fb_mode; 761 bool dchub_initialzied; 762 bool dchub_info_valid; 763 }; 764 765 struct dc_init_data { 766 struct hw_asic_id asic_id; 767 void *driver; /* ctx */ 768 struct cgs_device *cgs_device; 769 struct dc_bounding_box_overrides bb_overrides; 770 771 int num_virtual_links; 772 /* 773 * If 'vbios_override' not NULL, it will be called instead 774 * of the real VBIOS. Intended use is Diagnostics on FPGA. 775 */ 776 struct dc_bios *vbios_override; 777 enum dce_environment dce_environment; 778 779 struct dmub_offload_funcs *dmub_if; 780 struct dc_reg_helper_state *dmub_offload; 781 782 struct dc_config flags; 783 uint64_t log_mask; 784 785 struct dpcd_vendor_signature vendor_signature; 786 #if defined(CONFIG_DRM_AMD_DC_DCN) 787 bool force_smu_not_present; 788 #endif 789 }; 790 791 struct dc_callback_init { 792 #ifdef CONFIG_DRM_AMD_DC_HDCP 793 struct cp_psp cp_psp; 794 #else 795 uint8_t reserved; 796 #endif 797 }; 798 799 struct dc *dc_create(const struct dc_init_data *init_params); 800 void dc_hardware_init(struct dc *dc); 801 802 int dc_get_vmid_use_vector(struct dc *dc); 803 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 804 /* Returns the number of vmids supported */ 805 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 806 void dc_init_callbacks(struct dc *dc, 807 const struct dc_callback_init *init_params); 808 void dc_deinit_callbacks(struct dc *dc); 809 void dc_destroy(struct dc **dc); 810 811 /******************************************************************************* 812 * Surface Interfaces 813 ******************************************************************************/ 814 815 enum { 816 TRANSFER_FUNC_POINTS = 1025 817 }; 818 819 struct dc_hdr_static_metadata { 820 /* display chromaticities and white point in units of 0.00001 */ 821 unsigned int chromaticity_green_x; 822 unsigned int chromaticity_green_y; 823 unsigned int chromaticity_blue_x; 824 unsigned int chromaticity_blue_y; 825 unsigned int chromaticity_red_x; 826 unsigned int chromaticity_red_y; 827 unsigned int chromaticity_white_point_x; 828 unsigned int chromaticity_white_point_y; 829 830 uint32_t min_luminance; 831 uint32_t max_luminance; 832 uint32_t maximum_content_light_level; 833 uint32_t maximum_frame_average_light_level; 834 }; 835 836 enum dc_transfer_func_type { 837 TF_TYPE_PREDEFINED, 838 TF_TYPE_DISTRIBUTED_POINTS, 839 TF_TYPE_BYPASS, 840 TF_TYPE_HWPWL 841 }; 842 843 struct dc_transfer_func_distributed_points { 844 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 845 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 846 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 847 848 uint16_t end_exponent; 849 uint16_t x_point_at_y1_red; 850 uint16_t x_point_at_y1_green; 851 uint16_t x_point_at_y1_blue; 852 }; 853 854 enum dc_transfer_func_predefined { 855 TRANSFER_FUNCTION_SRGB, 856 TRANSFER_FUNCTION_BT709, 857 TRANSFER_FUNCTION_PQ, 858 TRANSFER_FUNCTION_LINEAR, 859 TRANSFER_FUNCTION_UNITY, 860 TRANSFER_FUNCTION_HLG, 861 TRANSFER_FUNCTION_HLG12, 862 TRANSFER_FUNCTION_GAMMA22, 863 TRANSFER_FUNCTION_GAMMA24, 864 TRANSFER_FUNCTION_GAMMA26 865 }; 866 867 868 struct dc_transfer_func { 869 struct kref refcount; 870 enum dc_transfer_func_type type; 871 enum dc_transfer_func_predefined tf; 872 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 873 uint32_t sdr_ref_white_level; 874 union { 875 struct pwl_params pwl; 876 struct dc_transfer_func_distributed_points tf_pts; 877 }; 878 }; 879 880 881 union dc_3dlut_state { 882 struct { 883 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 884 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 885 uint32_t rmu_mux_num:3; /*index of mux to use*/ 886 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 887 uint32_t mpc_rmu1_mux:4; 888 uint32_t mpc_rmu2_mux:4; 889 uint32_t reserved:15; 890 } bits; 891 uint32_t raw; 892 }; 893 894 895 struct dc_3dlut { 896 struct kref refcount; 897 struct tetrahedral_params lut_3d; 898 struct fixed31_32 hdr_multiplier; 899 union dc_3dlut_state state; 900 }; 901 /* 902 * This structure is filled in by dc_surface_get_status and contains 903 * the last requested address and the currently active address so the called 904 * can determine if there are any outstanding flips 905 */ 906 struct dc_plane_status { 907 struct dc_plane_address requested_address; 908 struct dc_plane_address current_address; 909 bool is_flip_pending; 910 bool is_right_eye; 911 }; 912 913 union surface_update_flags { 914 915 struct { 916 uint32_t addr_update:1; 917 /* Medium updates */ 918 uint32_t dcc_change:1; 919 uint32_t color_space_change:1; 920 uint32_t horizontal_mirror_change:1; 921 uint32_t per_pixel_alpha_change:1; 922 uint32_t global_alpha_change:1; 923 uint32_t hdr_mult:1; 924 uint32_t rotation_change:1; 925 uint32_t swizzle_change:1; 926 uint32_t scaling_change:1; 927 uint32_t position_change:1; 928 uint32_t in_transfer_func_change:1; 929 uint32_t input_csc_change:1; 930 uint32_t coeff_reduction_change:1; 931 uint32_t output_tf_change:1; 932 uint32_t pixel_format_change:1; 933 uint32_t plane_size_change:1; 934 uint32_t gamut_remap_change:1; 935 936 /* Full updates */ 937 uint32_t new_plane:1; 938 uint32_t bpp_change:1; 939 uint32_t gamma_change:1; 940 uint32_t bandwidth_change:1; 941 uint32_t clock_change:1; 942 uint32_t stereo_format_change:1; 943 uint32_t full_update:1; 944 } bits; 945 946 uint32_t raw; 947 }; 948 949 struct dc_plane_state { 950 struct dc_plane_address address; 951 struct dc_plane_flip_time time; 952 bool triplebuffer_flips; 953 struct scaling_taps scaling_quality; 954 struct rect src_rect; 955 struct rect dst_rect; 956 struct rect clip_rect; 957 958 struct plane_size plane_size; 959 union dc_tiling_info tiling_info; 960 961 struct dc_plane_dcc_param dcc; 962 963 struct dc_gamma *gamma_correction; 964 struct dc_transfer_func *in_transfer_func; 965 struct dc_bias_and_scale *bias_and_scale; 966 struct dc_csc_transform input_csc_color_matrix; 967 struct fixed31_32 coeff_reduction_factor; 968 struct fixed31_32 hdr_mult; 969 struct colorspace_transform gamut_remap_matrix; 970 971 // TODO: No longer used, remove 972 struct dc_hdr_static_metadata hdr_static_ctx; 973 974 enum dc_color_space color_space; 975 976 struct dc_3dlut *lut3d_func; 977 struct dc_transfer_func *in_shaper_func; 978 struct dc_transfer_func *blend_tf; 979 980 #if defined(CONFIG_DRM_AMD_DC_DCN) 981 struct dc_transfer_func *gamcor_tf; 982 #endif 983 enum surface_pixel_format format; 984 enum dc_rotation_angle rotation; 985 enum plane_stereo_format stereo_format; 986 987 bool is_tiling_rotated; 988 bool per_pixel_alpha; 989 bool global_alpha; 990 int global_alpha_value; 991 bool visible; 992 bool flip_immediate; 993 bool horizontal_mirror; 994 int layer_index; 995 996 union surface_update_flags update_flags; 997 bool flip_int_enabled; 998 bool skip_manual_trigger; 999 1000 /* private to DC core */ 1001 struct dc_plane_status status; 1002 struct dc_context *ctx; 1003 1004 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1005 bool force_full_update; 1006 1007 /* private to dc_surface.c */ 1008 enum dc_irq_source irq_source; 1009 struct kref refcount; 1010 }; 1011 1012 struct dc_plane_info { 1013 struct plane_size plane_size; 1014 union dc_tiling_info tiling_info; 1015 struct dc_plane_dcc_param dcc; 1016 enum surface_pixel_format format; 1017 enum dc_rotation_angle rotation; 1018 enum plane_stereo_format stereo_format; 1019 enum dc_color_space color_space; 1020 bool horizontal_mirror; 1021 bool visible; 1022 bool per_pixel_alpha; 1023 bool global_alpha; 1024 int global_alpha_value; 1025 bool input_csc_enabled; 1026 int layer_index; 1027 }; 1028 1029 struct dc_scaling_info { 1030 struct rect src_rect; 1031 struct rect dst_rect; 1032 struct rect clip_rect; 1033 struct scaling_taps scaling_quality; 1034 }; 1035 1036 struct dc_surface_update { 1037 struct dc_plane_state *surface; 1038 1039 /* isr safe update parameters. null means no updates */ 1040 const struct dc_flip_addrs *flip_addr; 1041 const struct dc_plane_info *plane_info; 1042 const struct dc_scaling_info *scaling_info; 1043 struct fixed31_32 hdr_mult; 1044 /* following updates require alloc/sleep/spin that is not isr safe, 1045 * null means no updates 1046 */ 1047 const struct dc_gamma *gamma; 1048 const struct dc_transfer_func *in_transfer_func; 1049 1050 const struct dc_csc_transform *input_csc_color_matrix; 1051 const struct fixed31_32 *coeff_reduction_factor; 1052 const struct dc_transfer_func *func_shaper; 1053 const struct dc_3dlut *lut3d_func; 1054 const struct dc_transfer_func *blend_tf; 1055 const struct colorspace_transform *gamut_remap_matrix; 1056 }; 1057 1058 /* 1059 * Create a new surface with default parameters; 1060 */ 1061 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1062 const struct dc_plane_status *dc_plane_get_status( 1063 const struct dc_plane_state *plane_state); 1064 1065 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1066 void dc_plane_state_release(struct dc_plane_state *plane_state); 1067 1068 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1069 void dc_gamma_release(struct dc_gamma **dc_gamma); 1070 struct dc_gamma *dc_create_gamma(void); 1071 1072 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1073 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1074 struct dc_transfer_func *dc_create_transfer_func(void); 1075 1076 struct dc_3dlut *dc_create_3dlut_func(void); 1077 void dc_3dlut_func_release(struct dc_3dlut *lut); 1078 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1079 /* 1080 * This structure holds a surface address. There could be multiple addresses 1081 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1082 * as frame durations and DCC format can also be set. 1083 */ 1084 struct dc_flip_addrs { 1085 struct dc_plane_address address; 1086 unsigned int flip_timestamp_in_us; 1087 bool flip_immediate; 1088 /* TODO: add flip duration for FreeSync */ 1089 bool triplebuffer_flips; 1090 }; 1091 1092 void dc_post_update_surfaces_to_stream( 1093 struct dc *dc); 1094 1095 #include "dc_stream.h" 1096 1097 /* 1098 * Structure to store surface/stream associations for validation 1099 */ 1100 struct dc_validation_set { 1101 struct dc_stream_state *stream; 1102 struct dc_plane_state *plane_states[MAX_SURFACES]; 1103 uint8_t plane_count; 1104 }; 1105 1106 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1107 const struct dc_sink *sink, 1108 struct dc_crtc_timing *crtc_timing); 1109 1110 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1111 1112 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1113 1114 bool dc_set_generic_gpio_for_stereo(bool enable, 1115 struct gpio_service *gpio_service); 1116 1117 /* 1118 * fast_validate: we return after determining if we can support the new state, 1119 * but before we populate the programming info 1120 */ 1121 enum dc_status dc_validate_global_state( 1122 struct dc *dc, 1123 struct dc_state *new_ctx, 1124 bool fast_validate); 1125 1126 1127 void dc_resource_state_construct( 1128 const struct dc *dc, 1129 struct dc_state *dst_ctx); 1130 1131 #if defined(CONFIG_DRM_AMD_DC_DCN) 1132 bool dc_acquire_release_mpc_3dlut( 1133 struct dc *dc, bool acquire, 1134 struct dc_stream_state *stream, 1135 struct dc_3dlut **lut, 1136 struct dc_transfer_func **shaper); 1137 #endif 1138 1139 void dc_resource_state_copy_construct( 1140 const struct dc_state *src_ctx, 1141 struct dc_state *dst_ctx); 1142 1143 void dc_resource_state_copy_construct_current( 1144 const struct dc *dc, 1145 struct dc_state *dst_ctx); 1146 1147 void dc_resource_state_destruct(struct dc_state *context); 1148 1149 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1150 1151 /* 1152 * TODO update to make it about validation sets 1153 * Set up streams and links associated to drive sinks 1154 * The streams parameter is an absolute set of all active streams. 1155 * 1156 * After this call: 1157 * Phy, Encoder, Timing Generator are programmed and enabled. 1158 * New streams are enabled with blank stream; no memory read. 1159 */ 1160 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1161 1162 struct dc_state *dc_create_state(struct dc *dc); 1163 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1164 void dc_retain_state(struct dc_state *context); 1165 void dc_release_state(struct dc_state *context); 1166 1167 /******************************************************************************* 1168 * Link Interfaces 1169 ******************************************************************************/ 1170 1171 struct dpcd_caps { 1172 union dpcd_rev dpcd_rev; 1173 union max_lane_count max_ln_count; 1174 union max_down_spread max_down_spread; 1175 union dprx_feature dprx_feature; 1176 1177 /* valid only for eDP v1.4 or higher*/ 1178 uint8_t edp_supported_link_rates_count; 1179 enum dc_link_rate edp_supported_link_rates[8]; 1180 1181 /* dongle type (DP converter, CV smart dongle) */ 1182 enum display_dongle_type dongle_type; 1183 /* branch device or sink device */ 1184 bool is_branch_dev; 1185 /* Dongle's downstream count. */ 1186 union sink_count sink_count; 1187 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1188 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1189 struct dc_dongle_caps dongle_caps; 1190 1191 uint32_t sink_dev_id; 1192 int8_t sink_dev_id_str[6]; 1193 int8_t sink_hw_revision; 1194 int8_t sink_fw_revision[2]; 1195 1196 uint32_t branch_dev_id; 1197 int8_t branch_dev_name[6]; 1198 int8_t branch_hw_revision; 1199 int8_t branch_fw_revision[2]; 1200 1201 bool allow_invalid_MSA_timing_param; 1202 bool panel_mode_edp; 1203 bool dpcd_display_control_capable; 1204 bool ext_receiver_cap_field_present; 1205 bool dynamic_backlight_capable_edp; 1206 union dpcd_fec_capability fec_cap; 1207 struct dpcd_dsc_capabilities dsc_caps; 1208 struct dc_lttpr_caps lttpr_caps; 1209 struct psr_caps psr_caps; 1210 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1211 1212 #if defined(CONFIG_DRM_AMD_DC_DCN) 1213 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1214 union dp_main_line_channel_coding_cap channel_coding_cap; 1215 union dp_sink_video_fallback_formats fallback_formats; 1216 union dp_fec_capability1 fec_cap1; 1217 #endif 1218 }; 1219 1220 union dpcd_sink_ext_caps { 1221 struct { 1222 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1223 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1224 */ 1225 uint8_t sdr_aux_backlight_control : 1; 1226 uint8_t hdr_aux_backlight_control : 1; 1227 uint8_t reserved_1 : 2; 1228 uint8_t oled : 1; 1229 uint8_t reserved : 3; 1230 } bits; 1231 uint8_t raw; 1232 }; 1233 1234 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1235 union hdcp_rx_caps { 1236 struct { 1237 uint8_t version; 1238 uint8_t reserved; 1239 struct { 1240 uint8_t repeater : 1; 1241 uint8_t hdcp_capable : 1; 1242 uint8_t reserved : 6; 1243 } byte0; 1244 } fields; 1245 uint8_t raw[3]; 1246 }; 1247 1248 union hdcp_bcaps { 1249 struct { 1250 uint8_t HDCP_CAPABLE:1; 1251 uint8_t REPEATER:1; 1252 uint8_t RESERVED:6; 1253 } bits; 1254 uint8_t raw; 1255 }; 1256 1257 struct hdcp_caps { 1258 union hdcp_rx_caps rx_caps; 1259 union hdcp_bcaps bcaps; 1260 }; 1261 #endif 1262 1263 #include "dc_link.h" 1264 1265 #if defined(CONFIG_DRM_AMD_DC_DCN) 1266 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1267 1268 #endif 1269 /******************************************************************************* 1270 * Sink Interfaces - A sink corresponds to a display output device 1271 ******************************************************************************/ 1272 1273 struct dc_container_id { 1274 // 128bit GUID in binary form 1275 unsigned char guid[16]; 1276 // 8 byte port ID -> ELD.PortID 1277 unsigned int portId[2]; 1278 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1279 unsigned short manufacturerName; 1280 // 2 byte product code -> ELD.ProductCode 1281 unsigned short productCode; 1282 }; 1283 1284 1285 struct dc_sink_dsc_caps { 1286 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1287 // 'false' if they are sink's DSC caps 1288 bool is_virtual_dpcd_dsc; 1289 struct dsc_dec_dpcd_caps dsc_dec_caps; 1290 }; 1291 1292 struct dc_sink_fec_caps { 1293 bool is_rx_fec_supported; 1294 bool is_topology_fec_supported; 1295 }; 1296 1297 /* 1298 * The sink structure contains EDID and other display device properties 1299 */ 1300 struct dc_sink { 1301 enum signal_type sink_signal; 1302 struct dc_edid dc_edid; /* raw edid */ 1303 struct dc_edid_caps edid_caps; /* parse display caps */ 1304 struct dc_container_id *dc_container_id; 1305 uint32_t dongle_max_pix_clk; 1306 void *priv; 1307 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1308 bool converter_disable_audio; 1309 1310 struct dc_sink_dsc_caps dsc_caps; 1311 struct dc_sink_fec_caps fec_caps; 1312 1313 bool is_vsc_sdp_colorimetry_supported; 1314 1315 /* private to DC core */ 1316 struct dc_link *link; 1317 struct dc_context *ctx; 1318 1319 uint32_t sink_id; 1320 1321 /* private to dc_sink.c */ 1322 // refcount must be the last member in dc_sink, since we want the 1323 // sink structure to be logically cloneable up to (but not including) 1324 // refcount 1325 struct kref refcount; 1326 }; 1327 1328 void dc_sink_retain(struct dc_sink *sink); 1329 void dc_sink_release(struct dc_sink *sink); 1330 1331 struct dc_sink_init_data { 1332 enum signal_type sink_signal; 1333 struct dc_link *link; 1334 uint32_t dongle_max_pix_clk; 1335 bool converter_disable_audio; 1336 }; 1337 1338 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1339 1340 /* Newer interfaces */ 1341 struct dc_cursor { 1342 struct dc_plane_address address; 1343 struct dc_cursor_attributes attributes; 1344 }; 1345 1346 1347 /******************************************************************************* 1348 * Interrupt interfaces 1349 ******************************************************************************/ 1350 enum dc_irq_source dc_interrupt_to_irq_source( 1351 struct dc *dc, 1352 uint32_t src_id, 1353 uint32_t ext_id); 1354 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1355 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1356 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1357 struct dc *dc, uint32_t link_index); 1358 1359 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1360 1361 /******************************************************************************* 1362 * Power Interfaces 1363 ******************************************************************************/ 1364 1365 void dc_set_power_state( 1366 struct dc *dc, 1367 enum dc_acpi_cm_power_state power_state); 1368 void dc_resume(struct dc *dc); 1369 1370 void dc_power_down_on_boot(struct dc *dc); 1371 1372 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1373 /* 1374 * HDCP Interfaces 1375 */ 1376 enum hdcp_message_status dc_process_hdcp_msg( 1377 enum signal_type signal, 1378 struct dc_link *link, 1379 struct hdcp_protection_message *message_info); 1380 #endif 1381 bool dc_is_dmcu_initialized(struct dc *dc); 1382 1383 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1384 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1385 #if defined(CONFIG_DRM_AMD_DC_DCN) 1386 1387 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1388 struct dc_cursor_attributes *cursor_attr); 1389 1390 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1391 1392 /* 1393 * blank all streams, and set min and max memory clock to 1394 * lowest and highest DPM level, respectively 1395 */ 1396 void dc_unlock_memory_clock_frequency(struct dc *dc); 1397 1398 /* 1399 * set min memory clock to the min required for current mode, 1400 * max to maxDPM, and unblank streams 1401 */ 1402 void dc_lock_memory_clock_frequency(struct dc *dc); 1403 1404 /* cleanup on driver unload */ 1405 void dc_hardware_release(struct dc *dc); 1406 1407 #endif 1408 1409 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1410 #if defined(CONFIG_DRM_AMD_DC_DCN) 1411 void dc_z10_restore(const struct dc *dc); 1412 void dc_z10_save_init(struct dc *dc); 1413 #endif 1414 1415 bool dc_enable_dmub_notifications(struct dc *dc); 1416 1417 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1418 uint32_t link_index, 1419 struct aux_payload *payload); 1420 1421 /* Get dc link index from dpia port index */ 1422 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1423 uint8_t dpia_port_index); 1424 1425 bool dc_process_dmub_set_config_async(struct dc *dc, 1426 uint32_t link_index, 1427 struct set_config_cmd_payload *payload, 1428 struct dmub_notification *notify); 1429 /******************************************************************************* 1430 * DSC Interfaces 1431 ******************************************************************************/ 1432 #include "dc_dsc.h" 1433 1434 /******************************************************************************* 1435 * Disable acc mode Interfaces 1436 ******************************************************************************/ 1437 void dc_disable_accelerated_mode(struct dc *dc); 1438 1439 #endif /* DC_INTERFACE_H_ */ 1440