1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2_0/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "sspl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 struct dcn_hubbub_reg_state; 58 struct dcn_hubp_reg_state; 59 struct dcn_dpp_reg_state; 60 struct dcn_mpc_reg_state; 61 struct dcn_opp_reg_state; 62 struct dcn_dsc_reg_state; 63 struct dcn_optc_reg_state; 64 struct dcn_dccg_reg_state; 65 66 #define DC_VER "3.2.356" 67 68 /** 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 70 */ 71 #define MAX_SURFACES 4 72 /** 73 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 74 */ 75 #define MAX_PLANES 6 76 #define MAX_STREAMS 6 77 #define MIN_VIEWPORT_SIZE 12 78 #define MAX_NUM_EDP 2 79 #define MAX_SUPPORTED_FORMATS 7 80 81 #define MAX_HOST_ROUTERS_NUM 3 82 #define MAX_DPIA_PER_HOST_ROUTER 3 83 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 84 85 /* Display Core Interfaces */ 86 struct dc_versions { 87 const char *dc_ver; 88 struct dmcu_version dmcu_version; 89 }; 90 91 enum dp_protocol_version { 92 DP_VERSION_1_4 = 0, 93 DP_VERSION_2_1, 94 DP_VERSION_UNKNOWN, 95 }; 96 97 enum dc_plane_type { 98 DC_PLANE_TYPE_INVALID, 99 DC_PLANE_TYPE_DCE_RGB, 100 DC_PLANE_TYPE_DCE_UNDERLAY, 101 DC_PLANE_TYPE_DCN_UNIVERSAL, 102 }; 103 104 // Sizes defined as multiples of 64KB 105 enum det_size { 106 DET_SIZE_DEFAULT = 0, 107 DET_SIZE_192KB = 3, 108 DET_SIZE_256KB = 4, 109 DET_SIZE_320KB = 5, 110 DET_SIZE_384KB = 6 111 }; 112 113 114 struct dc_plane_cap { 115 enum dc_plane_type type; 116 uint32_t per_pixel_alpha : 1; 117 struct { 118 uint32_t argb8888 : 1; 119 uint32_t nv12 : 1; 120 uint32_t fp16 : 1; 121 uint32_t p010 : 1; 122 uint32_t ayuv : 1; 123 } pixel_format_support; 124 // max upscaling factor x1000 125 // upscaling factors are always >= 1 126 // for example, 1080p -> 8K is 4.0, or 4000 raw value 127 struct { 128 uint32_t argb8888; 129 uint32_t nv12; 130 uint32_t fp16; 131 } max_upscale_factor; 132 // max downscale factor x1000 133 // downscale factors are always <= 1 134 // for example, 8K -> 1080p is 0.25, or 250 raw value 135 struct { 136 uint32_t argb8888; 137 uint32_t nv12; 138 uint32_t fp16; 139 } max_downscale_factor; 140 // minimal width/height 141 uint32_t min_width; 142 uint32_t min_height; 143 }; 144 145 /** 146 * DOC: color-management-caps 147 * 148 * **Color management caps (DPP and MPC)** 149 * 150 * Modules/color calculates various color operations which are translated to 151 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 152 * DCN1, every new generation comes with fairly major differences in color 153 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 154 * decide mapping to HW block based on logical capabilities. 155 */ 156 157 /** 158 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 159 * @srgb: RGB color space transfer func 160 * @bt2020: BT.2020 transfer func 161 * @gamma2_2: standard gamma 162 * @pq: perceptual quantizer transfer function 163 * @hlg: hybrid log–gamma transfer function 164 */ 165 struct rom_curve_caps { 166 uint16_t srgb : 1; 167 uint16_t bt2020 : 1; 168 uint16_t gamma2_2 : 1; 169 uint16_t pq : 1; 170 uint16_t hlg : 1; 171 }; 172 173 /** 174 * struct dpp_color_caps - color pipeline capabilities for display pipe and 175 * plane blocks 176 * 177 * @dcn_arch: all DCE generations treated the same 178 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 179 * just plain 256-entry lookup 180 * @icsc: input color space conversion 181 * @dgam_ram: programmable degamma LUT 182 * @post_csc: post color space conversion, before gamut remap 183 * @gamma_corr: degamma correction 184 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 185 * with MPC by setting mpc:shared_3d_lut flag 186 * @ogam_ram: programmable out/blend gamma LUT 187 * @ocsc: output color space conversion 188 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 189 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 190 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 191 * 192 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 193 */ 194 struct dpp_color_caps { 195 uint16_t dcn_arch : 1; 196 uint16_t input_lut_shared : 1; 197 uint16_t icsc : 1; 198 uint16_t dgam_ram : 1; 199 uint16_t post_csc : 1; 200 uint16_t gamma_corr : 1; 201 uint16_t hw_3d_lut : 1; 202 uint16_t ogam_ram : 1; 203 uint16_t ocsc : 1; 204 uint16_t dgam_rom_for_yuv : 1; 205 struct rom_curve_caps dgam_rom_caps; 206 struct rom_curve_caps ogam_rom_caps; 207 }; 208 209 /* Below structure is to describe the HW support for mem layout, extend support 210 range to match what OS could handle in the roadmap */ 211 struct lut3d_caps { 212 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 213 struct { 214 uint32_t swizzle_3d_rgb : 1; 215 uint32_t swizzle_3d_bgr : 1; 216 uint32_t linear_1d : 1; 217 } mem_layout_support; 218 struct { 219 uint32_t unorm_12msb : 1; 220 uint32_t unorm_12lsb : 1; 221 uint32_t float_fp1_5_10 : 1; 222 } mem_format_support; 223 struct { 224 uint32_t order_rgba : 1; 225 uint32_t order_bgra : 1; 226 } mem_pixel_order_support; 227 /*< size options are 9, 17, 33, 45, 65 */ 228 struct { 229 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 230 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 231 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 232 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 233 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 234 } lut_dim_caps; 235 }; 236 237 /** 238 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 239 * plane combined blocks 240 * 241 * @gamut_remap: color transformation matrix 242 * @ogam_ram: programmable out gamma LUT 243 * @ocsc: output color space conversion matrix 244 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 245 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 246 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 247 * instance 248 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 249 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 250 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 251 * @preblend: whether color manager supports preblend with MPC 252 */ 253 struct mpc_color_caps { 254 uint16_t gamut_remap : 1; 255 uint16_t ogam_ram : 1; 256 uint16_t ocsc : 1; 257 uint16_t num_3dluts : 3; 258 uint16_t num_rmcm_3dluts : 3; 259 uint16_t shared_3d_lut:1; 260 struct rom_curve_caps ogam_rom_caps; 261 struct lut3d_caps mcm_3d_lut_caps; 262 struct lut3d_caps rmcm_3d_lut_caps; 263 bool preblend; 264 }; 265 266 /** 267 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 268 * @dpp: color pipes caps for DPP 269 * @mpc: color pipes caps for MPC 270 */ 271 struct dc_color_caps { 272 struct dpp_color_caps dpp; 273 struct mpc_color_caps mpc; 274 }; 275 276 struct dc_dmub_caps { 277 bool psr; 278 bool mclk_sw; 279 bool subvp_psr; 280 bool gecc_enable; 281 uint8_t fams_ver; 282 bool aux_backlight_support; 283 }; 284 285 struct dc_scl_caps { 286 bool sharpener_support; 287 }; 288 289 struct dc_check_config { 290 /** 291 * max video plane width that can be safely assumed to be always 292 * supported by single DPP pipe. 293 */ 294 unsigned int max_optimizable_video_width; 295 bool enable_legacy_fast_update; 296 }; 297 298 struct dc_caps { 299 uint32_t max_streams; 300 uint32_t max_links; 301 uint32_t max_audios; 302 uint32_t max_slave_planes; 303 uint32_t max_slave_yuv_planes; 304 uint32_t max_slave_rgb_planes; 305 uint32_t max_planes; 306 uint32_t max_downscale_ratio; 307 uint32_t i2c_speed_in_khz; 308 uint32_t i2c_speed_in_khz_hdcp; 309 uint32_t dmdata_alloc_size; 310 unsigned int max_cursor_size; 311 unsigned int max_buffered_cursor_size; 312 unsigned int max_video_width; 313 unsigned int min_horizontal_blanking_period; 314 int linear_pitch_alignment; 315 bool dcc_const_color; 316 bool dynamic_audio; 317 bool is_apu; 318 bool dual_link_dvi; 319 bool post_blend_color_processing; 320 bool force_dp_tps4_for_cp2520; 321 bool disable_dp_clk_share; 322 bool psp_setup_panel_mode; 323 bool extended_aux_timeout_support; 324 bool dmcub_support; 325 bool zstate_support; 326 bool ips_support; 327 bool ips_v2_support; 328 uint32_t num_of_internal_disp; 329 enum dp_protocol_version max_dp_protocol_version; 330 unsigned int mall_size_per_mem_channel; 331 unsigned int mall_size_total; 332 unsigned int cursor_cache_size; 333 struct dc_plane_cap planes[MAX_PLANES]; 334 struct dc_color_caps color; 335 struct dc_dmub_caps dmub_caps; 336 bool dp_hpo; 337 bool dp_hdmi21_pcon_support; 338 bool edp_dsc_support; 339 bool vbios_lttpr_aware; 340 bool vbios_lttpr_enable; 341 bool fused_io_supported; 342 uint32_t max_otg_num; 343 uint32_t max_cab_allocation_bytes; 344 uint32_t cache_line_size; 345 uint32_t cache_num_ways; 346 uint16_t subvp_fw_processing_delay_us; 347 uint8_t subvp_drr_max_vblank_margin_us; 348 uint16_t subvp_prefetch_end_to_mall_start_us; 349 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 350 uint16_t subvp_pstate_allow_width_us; 351 uint16_t subvp_vertical_int_margin_us; 352 bool seamless_odm; 353 uint32_t max_v_total; 354 bool vtotal_limited_by_fp2; 355 uint32_t max_disp_clock_khz_at_vmin; 356 uint8_t subvp_drr_vblank_start_margin_us; 357 bool cursor_not_scaled; 358 bool dcmode_power_limits_present; 359 bool sequential_ono; 360 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 361 uint32_t dcc_plane_width_limit; 362 struct dc_scl_caps scl_caps; 363 uint8_t num_of_host_routers; 364 uint8_t num_of_dpias_per_host_router; 365 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 366 uint8_t max_odm_combine_factor; 367 }; 368 369 struct dc_bug_wa { 370 bool no_connect_phy_config; 371 bool dedcn20_305_wa; 372 bool skip_clock_update; 373 bool lt_early_cr_pattern; 374 struct { 375 uint8_t uclk : 1; 376 uint8_t fclk : 1; 377 uint8_t dcfclk : 1; 378 uint8_t dcfclk_ds: 1; 379 } clock_update_disable_mask; 380 bool skip_psr_ips_crtc_disable; 381 }; 382 struct dc_dcc_surface_param { 383 struct dc_size surface_size; 384 enum surface_pixel_format format; 385 unsigned int plane0_pitch; 386 struct dc_size plane1_size; 387 unsigned int plane1_pitch; 388 union { 389 enum swizzle_mode_values swizzle_mode; 390 enum swizzle_mode_addr3_values swizzle_mode_addr3; 391 }; 392 enum dc_scan_direction scan; 393 }; 394 395 struct dc_dcc_setting { 396 unsigned int max_compressed_blk_size; 397 unsigned int max_uncompressed_blk_size; 398 bool independent_64b_blks; 399 //These bitfields to be used starting with DCN 3.0 400 struct { 401 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 402 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 403 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 404 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 405 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 406 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 407 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 408 } dcc_controls; 409 }; 410 411 struct dc_surface_dcc_cap { 412 union { 413 struct { 414 struct dc_dcc_setting rgb; 415 } grph; 416 417 struct { 418 struct dc_dcc_setting luma; 419 struct dc_dcc_setting chroma; 420 } video; 421 }; 422 423 bool capable; 424 bool const_color_support; 425 }; 426 427 struct dc_static_screen_params { 428 struct { 429 bool force_trigger; 430 bool cursor_update; 431 bool surface_update; 432 bool overlay_update; 433 } triggers; 434 unsigned int num_frames; 435 }; 436 437 438 /* Surface update type is used by dc_update_surfaces_and_stream 439 * The update type is determined at the very beginning of the function based 440 * on parameters passed in and decides how much programming (or updating) is 441 * going to be done during the call. 442 * 443 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 444 * logical calculations or hardware register programming. This update MUST be 445 * ISR safe on windows. Currently fast update will only be used to flip surface 446 * address. 447 * 448 * UPDATE_TYPE_MED is used for slower updates which require significant hw 449 * re-programming however do not affect bandwidth consumption or clock 450 * requirements. At present, this is the level at which front end updates 451 * that do not require us to run bw_calcs happen. These are in/out transfer func 452 * updates, viewport offset changes, recout size changes and pixel depth changes. 453 * This update can be done at ISR, but we want to minimize how often this happens. 454 * 455 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 456 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 457 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 458 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 459 * a full update. This cannot be done at ISR level and should be a rare event. 460 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 461 * underscan we don't expect to see this call at all. 462 */ 463 464 enum surface_update_type { 465 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 466 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 467 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 468 }; 469 470 enum dc_lock_descriptor { 471 LOCK_DESCRIPTOR_NONE = 0x0, 472 LOCK_DESCRIPTOR_STATE = 0x1, 473 LOCK_DESCRIPTOR_LINK = 0x2, 474 LOCK_DESCRIPTOR_STREAM = 0x4, 475 LOCK_DESCRIPTOR_PLANE = 0x8, 476 }; 477 478 struct surface_update_descriptor { 479 enum surface_update_type update_type; 480 enum dc_lock_descriptor lock_descriptor; 481 }; 482 483 /* Forward declaration*/ 484 struct dc; 485 struct dc_plane_state; 486 struct dc_state; 487 488 struct dc_cap_funcs { 489 bool (*get_dcc_compression_cap)(const struct dc *dc, 490 const struct dc_dcc_surface_param *input, 491 struct dc_surface_dcc_cap *output); 492 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 493 }; 494 495 struct link_training_settings; 496 497 union allow_lttpr_non_transparent_mode { 498 struct { 499 bool DP1_4A : 1; 500 bool DP2_0 : 1; 501 } bits; 502 unsigned char raw; 503 }; 504 505 /* Structure to hold configuration flags set by dm at dc creation. */ 506 struct dc_config { 507 bool gpu_vm_support; 508 bool disable_disp_pll_sharing; 509 bool fbc_support; 510 bool disable_fractional_pwm; 511 bool allow_seamless_boot_optimization; 512 bool seamless_boot_edp_requested; 513 bool edp_not_connected; 514 bool edp_no_power_sequencing; 515 bool force_enum_edp; 516 bool forced_clocks; 517 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 518 bool multi_mon_pp_mclk_switch; 519 bool disable_dmcu; 520 bool enable_4to1MPC; 521 bool enable_windowed_mpo_odm; 522 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 523 uint32_t allow_edp_hotplug_detection; 524 bool skip_riommu_prefetch_wa; 525 bool clamp_min_dcfclk; 526 uint64_t vblank_alignment_dto_params; 527 uint8_t vblank_alignment_max_frame_time_diff; 528 bool is_asymmetric_memory; 529 bool is_single_rank_dimm; 530 bool is_vmin_only_asic; 531 bool use_spl; 532 bool prefer_easf; 533 bool use_pipe_ctx_sync_logic; 534 int smart_mux_version; 535 bool ignore_dpref_ss; 536 bool enable_mipi_converter_optimization; 537 bool use_default_clock_table; 538 bool force_bios_enable_lttpr; 539 uint8_t force_bios_fixed_vs; 540 int sdpif_request_limit_words_per_umc; 541 bool dc_mode_clk_limit_support; 542 bool EnableMinDispClkODM; 543 bool enable_auto_dpm_test_logs; 544 unsigned int disable_ips; 545 unsigned int disable_ips_rcg; 546 unsigned int disable_ips_in_vpb; 547 bool disable_ips_in_dpms_off; 548 bool usb4_bw_alloc_support; 549 bool allow_0_dtb_clk; 550 bool use_assr_psp_message; 551 bool support_edp0_on_dp1; 552 unsigned int enable_fpo_flicker_detection; 553 bool disable_hbr_audio_dp2; 554 bool consolidated_dpia_dp_lt; 555 bool set_pipe_unlock_order; 556 bool enable_dpia_pre_training; 557 bool unify_link_enc_assignment; 558 bool enable_cursor_offload; 559 struct spl_sharpness_range dcn_sharpness_range; 560 struct spl_sharpness_range dcn_override_sharpness_range; 561 }; 562 563 enum visual_confirm { 564 VISUAL_CONFIRM_DISABLE = 0, 565 VISUAL_CONFIRM_SURFACE = 1, 566 VISUAL_CONFIRM_HDR = 2, 567 VISUAL_CONFIRM_MPCTREE = 4, 568 VISUAL_CONFIRM_PSR = 5, 569 VISUAL_CONFIRM_SWAPCHAIN = 6, 570 VISUAL_CONFIRM_FAMS = 7, 571 VISUAL_CONFIRM_SWIZZLE = 9, 572 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 573 VISUAL_CONFIRM_REPLAY = 12, 574 VISUAL_CONFIRM_SUBVP = 14, 575 VISUAL_CONFIRM_MCLK_SWITCH = 16, 576 VISUAL_CONFIRM_FAMS2 = 19, 577 VISUAL_CONFIRM_HW_CURSOR = 20, 578 VISUAL_CONFIRM_VABC = 21, 579 VISUAL_CONFIRM_DCC = 22, 580 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 581 }; 582 583 enum dc_psr_power_opts { 584 psr_power_opt_invalid = 0x0, 585 psr_power_opt_smu_opt_static_screen = 0x1, 586 psr_power_opt_z10_static_screen = 0x10, 587 psr_power_opt_ds_disable_allow = 0x100, 588 }; 589 590 enum dml_hostvm_override_opts { 591 DML_HOSTVM_NO_OVERRIDE = 0x0, 592 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 593 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 594 }; 595 596 enum dc_replay_power_opts { 597 replay_power_opt_invalid = 0x0, 598 replay_power_opt_smu_opt_static_screen = 0x1, 599 replay_power_opt_z10_static_screen = 0x10, 600 }; 601 602 enum dcc_option { 603 DCC_ENABLE = 0, 604 DCC_DISABLE = 1, 605 DCC_HALF_REQ_DISALBE = 2, 606 }; 607 608 enum in_game_fams_config { 609 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 610 INGAME_FAMS_DISABLE, // disable in-game fams 611 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 612 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 613 }; 614 615 /** 616 * enum pipe_split_policy - Pipe split strategy supported by DCN 617 * 618 * This enum is used to define the pipe split policy supported by DCN. By 619 * default, DC favors MPC_SPLIT_DYNAMIC. 620 */ 621 enum pipe_split_policy { 622 /** 623 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 624 * pipe in order to bring the best trade-off between performance and 625 * power consumption. This is the recommended option. 626 */ 627 MPC_SPLIT_DYNAMIC = 0, 628 629 /** 630 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 631 * try any sort of split optimization. 632 */ 633 MPC_SPLIT_AVOID = 1, 634 635 /** 636 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 637 * optimize the pipe utilization when using a single display; if the 638 * user connects to a second display, DC will avoid pipe split. 639 */ 640 MPC_SPLIT_AVOID_MULT_DISP = 2, 641 }; 642 643 enum wm_report_mode { 644 WM_REPORT_DEFAULT = 0, 645 WM_REPORT_OVERRIDE = 1, 646 }; 647 enum dtm_pstate{ 648 dtm_level_p0 = 0,/*highest voltage*/ 649 dtm_level_p1, 650 dtm_level_p2, 651 dtm_level_p3, 652 dtm_level_p4,/*when active_display_count = 0*/ 653 }; 654 655 enum dcn_pwr_state { 656 DCN_PWR_STATE_UNKNOWN = -1, 657 DCN_PWR_STATE_MISSION_MODE = 0, 658 DCN_PWR_STATE_LOW_POWER = 3, 659 }; 660 661 enum dcn_zstate_support_state { 662 DCN_ZSTATE_SUPPORT_UNKNOWN, 663 DCN_ZSTATE_SUPPORT_ALLOW, 664 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 665 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 666 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 667 DCN_ZSTATE_SUPPORT_DISALLOW, 668 }; 669 670 /* 671 * struct dc_clocks - DC pipe clocks 672 * 673 * For any clocks that may differ per pipe only the max is stored in this 674 * structure 675 */ 676 struct dc_clocks { 677 int dispclk_khz; 678 int actual_dispclk_khz; 679 int dppclk_khz; 680 int actual_dppclk_khz; 681 int disp_dpp_voltage_level_khz; 682 int dcfclk_khz; 683 int socclk_khz; 684 int dcfclk_deep_sleep_khz; 685 int fclk_khz; 686 int phyclk_khz; 687 int dramclk_khz; 688 bool p_state_change_support; 689 enum dcn_zstate_support_state zstate_support; 690 bool dtbclk_en; 691 int ref_dtbclk_khz; 692 bool fclk_p_state_change_support; 693 enum dcn_pwr_state pwr_state; 694 /* 695 * Elements below are not compared for the purposes of 696 * optimization required 697 */ 698 bool prev_p_state_change_support; 699 bool fclk_prev_p_state_change_support; 700 int num_ways; 701 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 702 703 /* 704 * @fw_based_mclk_switching 705 * 706 * DC has a mechanism that leverage the variable refresh rate to switch 707 * memory clock in cases that we have a large latency to achieve the 708 * memory clock change and a short vblank window. DC has some 709 * requirements to enable this feature, and this field describes if the 710 * system support or not such a feature. 711 */ 712 bool fw_based_mclk_switching; 713 bool fw_based_mclk_switching_shut_down; 714 int prev_num_ways; 715 enum dtm_pstate dtm_level; 716 int max_supported_dppclk_khz; 717 int max_supported_dispclk_khz; 718 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 719 int bw_dispclk_khz; 720 int idle_dramclk_khz; 721 int idle_fclk_khz; 722 int subvp_prefetch_dramclk_khz; 723 int subvp_prefetch_fclk_khz; 724 725 /* Stutter efficiency is technically not clock values 726 * but stored here so the values are part of the update_clocks call similar to num_ways 727 * Efficiencies are stored as percentage (0-100) 728 */ 729 struct { 730 uint8_t base_efficiency; //LP1 731 uint8_t low_power_efficiency; //LP2 732 } stutter_efficiency; 733 }; 734 735 struct dc_bw_validation_profile { 736 bool enable; 737 738 unsigned long long total_ticks; 739 unsigned long long voltage_level_ticks; 740 unsigned long long watermark_ticks; 741 unsigned long long rq_dlg_ticks; 742 743 unsigned long long total_count; 744 unsigned long long skip_fast_count; 745 unsigned long long skip_pass_count; 746 unsigned long long skip_fail_count; 747 }; 748 749 #define BW_VAL_TRACE_SETUP() \ 750 unsigned long long end_tick = 0; \ 751 unsigned long long voltage_level_tick = 0; \ 752 unsigned long long watermark_tick = 0; \ 753 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 754 dm_get_timestamp(dc->ctx) : 0 755 756 #define BW_VAL_TRACE_COUNT() \ 757 if (dc->debug.bw_val_profile.enable) \ 758 dc->debug.bw_val_profile.total_count++ 759 760 #define BW_VAL_TRACE_SKIP(status) \ 761 if (dc->debug.bw_val_profile.enable) { \ 762 if (!voltage_level_tick) \ 763 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 764 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 765 } 766 767 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 768 if (dc->debug.bw_val_profile.enable) \ 769 voltage_level_tick = dm_get_timestamp(dc->ctx) 770 771 #define BW_VAL_TRACE_END_WATERMARKS() \ 772 if (dc->debug.bw_val_profile.enable) \ 773 watermark_tick = dm_get_timestamp(dc->ctx) 774 775 #define BW_VAL_TRACE_FINISH() \ 776 if (dc->debug.bw_val_profile.enable) { \ 777 end_tick = dm_get_timestamp(dc->ctx); \ 778 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 779 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 780 if (watermark_tick) { \ 781 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 782 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 783 } \ 784 } 785 786 union mem_low_power_enable_options { 787 struct { 788 bool vga: 1; 789 bool i2c: 1; 790 bool dmcu: 1; 791 bool dscl: 1; 792 bool cm: 1; 793 bool mpc: 1; 794 bool optc: 1; 795 bool vpg: 1; 796 bool afmt: 1; 797 } bits; 798 uint32_t u32All; 799 }; 800 801 union root_clock_optimization_options { 802 struct { 803 bool dpp: 1; 804 bool dsc: 1; 805 bool hdmistream: 1; 806 bool hdmichar: 1; 807 bool dpstream: 1; 808 bool symclk32_se: 1; 809 bool symclk32_le: 1; 810 bool symclk_fe: 1; 811 bool physymclk: 1; 812 bool dpiasymclk: 1; 813 uint32_t reserved: 22; 814 } bits; 815 uint32_t u32All; 816 }; 817 818 union fine_grain_clock_gating_enable_options { 819 struct { 820 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 821 bool dchub : 1; /* Display controller hub */ 822 bool dchubbub : 1; 823 bool dpp : 1; /* Display pipes and planes */ 824 bool opp : 1; /* Output pixel processing */ 825 bool optc : 1; /* Output pipe timing combiner */ 826 bool dio : 1; /* Display output */ 827 bool dwb : 1; /* Display writeback */ 828 bool mmhubbub : 1; /* Multimedia hub */ 829 bool dmu : 1; /* Display core management unit */ 830 bool az : 1; /* Azalia */ 831 bool dchvm : 1; 832 bool dsc : 1; /* Display stream compression */ 833 834 uint32_t reserved : 19; 835 } bits; 836 uint32_t u32All; 837 }; 838 839 enum pg_hw_pipe_resources { 840 PG_HUBP = 0, 841 PG_DPP, 842 PG_DSC, 843 PG_MPCC, 844 PG_OPP, 845 PG_OPTC, 846 PG_DPSTREAM, 847 PG_HDMISTREAM, 848 PG_PHYSYMCLK, 849 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 850 }; 851 852 enum pg_hw_resources { 853 PG_DCCG = 0, 854 PG_DCIO, 855 PG_DIO, 856 PG_DCHUBBUB, 857 PG_DCHVM, 858 PG_DWB, 859 PG_HPO, 860 PG_DCOH, 861 PG_HW_RESOURCES_NUM_ELEMENT 862 }; 863 864 struct pg_block_update { 865 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 866 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 867 }; 868 869 union dpia_debug_options { 870 struct { 871 uint32_t disable_dpia:1; /* bit 0 */ 872 uint32_t force_non_lttpr:1; /* bit 1 */ 873 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 874 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 875 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 876 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 877 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 878 uint32_t reserved:25; 879 } bits; 880 uint32_t raw; 881 }; 882 883 /* AUX wake work around options 884 * 0: enable/disable work around 885 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 886 * 15-2: reserved 887 * 31-16: timeout in ms 888 */ 889 union aux_wake_wa_options { 890 struct { 891 uint32_t enable_wa : 1; 892 uint32_t use_default_timeout : 1; 893 uint32_t rsvd: 14; 894 uint32_t timeout_ms : 16; 895 } bits; 896 uint32_t raw; 897 }; 898 899 struct dc_debug_data { 900 uint32_t ltFailCount; 901 uint32_t i2cErrorCount; 902 uint32_t auxErrorCount; 903 }; 904 905 struct dc_phy_addr_space_config { 906 struct { 907 uint64_t start_addr; 908 uint64_t end_addr; 909 uint64_t fb_top; 910 uint64_t fb_offset; 911 uint64_t fb_base; 912 uint64_t agp_top; 913 uint64_t agp_bot; 914 uint64_t agp_base; 915 } system_aperture; 916 917 struct { 918 uint64_t page_table_start_addr; 919 uint64_t page_table_end_addr; 920 uint64_t page_table_base_addr; 921 bool base_addr_is_mc_addr; 922 } gart_config; 923 924 bool valid; 925 bool is_hvm_enabled; 926 uint64_t page_table_default_page_addr; 927 }; 928 929 struct dc_virtual_addr_space_config { 930 uint64_t page_table_base_addr; 931 uint64_t page_table_start_addr; 932 uint64_t page_table_end_addr; 933 uint32_t page_table_block_size_in_bytes; 934 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 935 }; 936 937 struct dc_bounding_box_overrides { 938 int sr_exit_time_ns; 939 int sr_enter_plus_exit_time_ns; 940 int sr_exit_z8_time_ns; 941 int sr_enter_plus_exit_z8_time_ns; 942 int urgent_latency_ns; 943 int percent_of_ideal_drambw; 944 int dram_clock_change_latency_ns; 945 int dummy_clock_change_latency_ns; 946 int fclk_clock_change_latency_ns; 947 /* This forces a hard min on the DCFCLK we use 948 * for DML. Unlike the debug option for forcing 949 * DCFCLK, this override affects watermark calculations 950 */ 951 int min_dcfclk_mhz; 952 }; 953 954 struct dc_state; 955 struct resource_pool; 956 struct dce_hwseq; 957 struct link_service; 958 959 /* 960 * struct dc_debug_options - DC debug struct 961 * 962 * This struct provides a simple mechanism for developers to change some 963 * configurations, enable/disable features, and activate extra debug options. 964 * This can be very handy to narrow down whether some specific feature is 965 * causing an issue or not. 966 */ 967 struct dc_debug_options { 968 bool native422_support; 969 bool disable_dsc; 970 enum visual_confirm visual_confirm; 971 int visual_confirm_rect_height; 972 973 bool sanity_checks; 974 bool max_disp_clk; 975 bool surface_trace; 976 bool clock_trace; 977 bool validation_trace; 978 bool bandwidth_calcs_trace; 979 int max_downscale_src_width; 980 981 /* stutter efficiency related */ 982 bool disable_stutter; 983 bool use_max_lb; 984 enum dcc_option disable_dcc; 985 986 /* 987 * @pipe_split_policy: Define which pipe split policy is used by the 988 * display core. 989 */ 990 enum pipe_split_policy pipe_split_policy; 991 bool force_single_disp_pipe_split; 992 bool voltage_align_fclk; 993 bool disable_min_fclk; 994 995 bool hdcp_lc_force_fw_enable; 996 bool hdcp_lc_enable_sw_fallback; 997 998 bool disable_dfs_bypass; 999 bool disable_dpp_power_gate; 1000 bool disable_hubp_power_gate; 1001 bool disable_dsc_power_gate; 1002 bool disable_optc_power_gate; 1003 bool disable_hpo_power_gate; 1004 bool disable_io_clk_power_gate; 1005 bool disable_mem_power_gate; 1006 bool disable_dio_power_gate; 1007 int dsc_min_slice_height_override; 1008 int dsc_bpp_increment_div; 1009 bool disable_pplib_wm_range; 1010 enum wm_report_mode pplib_wm_report_mode; 1011 unsigned int min_disp_clk_khz; 1012 unsigned int min_dpp_clk_khz; 1013 unsigned int min_dram_clk_khz; 1014 int sr_exit_time_dpm0_ns; 1015 int sr_enter_plus_exit_time_dpm0_ns; 1016 int sr_exit_time_ns; 1017 int sr_enter_plus_exit_time_ns; 1018 int sr_exit_z8_time_ns; 1019 int sr_enter_plus_exit_z8_time_ns; 1020 int urgent_latency_ns; 1021 uint32_t underflow_assert_delay_us; 1022 int percent_of_ideal_drambw; 1023 int dram_clock_change_latency_ns; 1024 bool optimized_watermark; 1025 int always_scale; 1026 bool disable_pplib_clock_request; 1027 bool disable_clock_gate; 1028 bool disable_mem_low_power; 1029 bool pstate_enabled; 1030 bool disable_dmcu; 1031 bool force_abm_enable; 1032 bool disable_stereo_support; 1033 bool vsr_support; 1034 bool performance_trace; 1035 bool az_endpoint_mute_only; 1036 bool always_use_regamma; 1037 bool recovery_enabled; 1038 bool avoid_vbios_exec_table; 1039 bool scl_reset_length10; 1040 bool hdmi20_disable; 1041 bool skip_detection_link_training; 1042 uint32_t edid_read_retry_times; 1043 unsigned int force_odm_combine; //bit vector based on otg inst 1044 unsigned int seamless_boot_odm_combine; 1045 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 1046 int minimum_z8_residency_time; 1047 int minimum_z10_residency_time; 1048 bool disable_z9_mpc; 1049 unsigned int force_fclk_khz; 1050 bool enable_tri_buf; 1051 bool ips_disallow_entry; 1052 bool dmub_offload_enabled; 1053 bool dmcub_emulation; 1054 bool disable_idle_power_optimizations; 1055 unsigned int mall_size_override; 1056 unsigned int mall_additional_timer_percent; 1057 bool mall_error_as_fatal; 1058 bool dmub_command_table; /* for testing only */ 1059 struct dc_bw_validation_profile bw_val_profile; 1060 bool disable_fec; 1061 bool disable_48mhz_pwrdwn; 1062 /* This forces a hard min on the DCFCLK requested to SMU/PP 1063 * watermarks are not affected. 1064 */ 1065 unsigned int force_min_dcfclk_mhz; 1066 int dwb_fi_phase; 1067 bool disable_timing_sync; 1068 bool cm_in_bypass; 1069 int force_clock_mode;/*every mode change.*/ 1070 1071 bool disable_dram_clock_change_vactive_support; 1072 bool validate_dml_output; 1073 bool enable_dmcub_surface_flip; 1074 bool usbc_combo_phy_reset_wa; 1075 bool enable_dram_clock_change_one_display_vactive; 1076 /* TODO - remove once tested */ 1077 bool legacy_dp2_lt; 1078 bool set_mst_en_for_sst; 1079 bool disable_uhbr; 1080 bool force_dp2_lt_fallback_method; 1081 bool ignore_cable_id; 1082 union mem_low_power_enable_options enable_mem_low_power; 1083 union root_clock_optimization_options root_clock_optimization; 1084 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1085 bool hpo_optimization; 1086 bool force_vblank_alignment; 1087 1088 /* Enable dmub aux for legacy ddc */ 1089 bool enable_dmub_aux_for_legacy_ddc; 1090 bool disable_fams; 1091 enum in_game_fams_config disable_fams_gaming; 1092 /* FEC/PSR1 sequence enable delay in 100us */ 1093 uint8_t fec_enable_delay_in100us; 1094 bool enable_driver_sequence_debug; 1095 enum det_size crb_alloc_policy; 1096 int crb_alloc_policy_min_disp_count; 1097 bool disable_z10; 1098 bool enable_z9_disable_interface; 1099 bool psr_skip_crtc_disable; 1100 uint32_t ips_skip_crtc_disable_mask; 1101 union dpia_debug_options dpia_debug; 1102 bool disable_fixed_vs_aux_timeout_wa; 1103 uint32_t fixed_vs_aux_delay_config_wa; 1104 bool force_disable_subvp; 1105 bool force_subvp_mclk_switch; 1106 bool allow_sw_cursor_fallback; 1107 unsigned int force_subvp_num_ways; 1108 unsigned int force_mall_ss_num_ways; 1109 bool alloc_extra_way_for_cursor; 1110 uint32_t subvp_extra_lines; 1111 bool disable_force_pstate_allow_on_hw_release; 1112 bool force_usr_allow; 1113 /* uses value at boot and disables switch */ 1114 bool disable_dtb_ref_clk_switch; 1115 bool extended_blank_optimization; 1116 union aux_wake_wa_options aux_wake_wa; 1117 uint32_t mst_start_top_delay; 1118 uint8_t psr_power_use_phy_fsm; 1119 enum dml_hostvm_override_opts dml_hostvm_override; 1120 bool dml_disallow_alternate_prefetch_modes; 1121 bool use_legacy_soc_bb_mechanism; 1122 bool exit_idle_opt_for_cursor_updates; 1123 bool using_dml2; 1124 bool enable_single_display_2to1_odm_policy; 1125 bool enable_double_buffered_dsc_pg_support; 1126 bool enable_dp_dig_pixel_rate_div_policy; 1127 bool using_dml21; 1128 enum lttpr_mode lttpr_mode_override; 1129 unsigned int dsc_delay_factor_wa_x1000; 1130 unsigned int min_prefetch_in_strobe_ns; 1131 bool disable_unbounded_requesting; 1132 bool dig_fifo_off_in_blank; 1133 bool override_dispclk_programming; 1134 bool otg_crc_db; 1135 bool disallow_dispclk_dppclk_ds; 1136 bool disable_fpo_optimizations; 1137 bool support_eDP1_5; 1138 uint32_t fpo_vactive_margin_us; 1139 bool disable_fpo_vactive; 1140 bool disable_boot_optimizations; 1141 bool override_odm_optimization; 1142 bool minimize_dispclk_using_odm; 1143 bool disable_subvp_high_refresh; 1144 bool disable_dp_plus_plus_wa; 1145 uint32_t fpo_vactive_min_active_margin_us; 1146 uint32_t fpo_vactive_max_blank_us; 1147 bool enable_hpo_pg_support; 1148 bool disable_dc_mode_overwrite; 1149 bool replay_skip_crtc_disabled; 1150 bool ignore_pg;/*do nothing, let pmfw control it*/ 1151 bool psp_disabled_wa; 1152 unsigned int ips2_eval_delay_us; 1153 unsigned int ips2_entry_delay_us; 1154 bool optimize_ips_handshake; 1155 bool disable_dmub_reallow_idle; 1156 bool disable_timeout; 1157 bool disable_extblankadj; 1158 bool enable_idle_reg_checks; 1159 unsigned int static_screen_wait_frames; 1160 uint32_t pwm_freq; 1161 bool force_chroma_subsampling_1tap; 1162 unsigned int dcc_meta_propagation_delay_us; 1163 bool disable_422_left_edge_pixel; 1164 bool dml21_force_pstate_method; 1165 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1166 uint32_t dml21_disable_pstate_method_mask; 1167 union fw_assisted_mclk_switch_version fams_version; 1168 union dmub_fams2_global_feature_config fams2_config; 1169 unsigned int force_cositing; 1170 unsigned int disable_spl; 1171 unsigned int force_easf; 1172 unsigned int force_sharpness; 1173 unsigned int force_sharpness_level; 1174 unsigned int force_lls; 1175 bool notify_dpia_hr_bw; 1176 bool enable_ips_visual_confirm; 1177 unsigned int sharpen_policy; 1178 unsigned int scale_to_sharpness_policy; 1179 unsigned int enable_oled_edp_power_up_opt; 1180 bool enable_hblank_borrow; 1181 bool force_subvp_df_throttle; 1182 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1183 bool enable_pg_cntl_debug_logs; 1184 unsigned int auxless_alpm_lfps_setup_ns; 1185 unsigned int auxless_alpm_lfps_period_ns; 1186 unsigned int auxless_alpm_lfps_silence_ns; 1187 unsigned int auxless_alpm_lfps_t1t2_us; 1188 short auxless_alpm_lfps_t1t2_offset_us; 1189 bool disable_stutter_for_wm_program; 1190 bool enable_block_sequence_programming; 1191 }; 1192 1193 1194 /* Generic structure that can be used to query properties of DC. More fields 1195 * can be added as required. 1196 */ 1197 struct dc_current_properties { 1198 unsigned int cursor_size_limit; 1199 }; 1200 1201 enum frame_buffer_mode { 1202 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1203 FRAME_BUFFER_MODE_ZFB_ONLY, 1204 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1205 } ; 1206 1207 struct dchub_init_data { 1208 int64_t zfb_phys_addr_base; 1209 int64_t zfb_mc_base_addr; 1210 uint64_t zfb_size_in_byte; 1211 enum frame_buffer_mode fb_mode; 1212 bool dchub_initialzied; 1213 bool dchub_info_valid; 1214 }; 1215 1216 struct dml2_soc_bb; 1217 1218 struct dc_init_data { 1219 struct hw_asic_id asic_id; 1220 void *driver; /* ctx */ 1221 struct cgs_device *cgs_device; 1222 struct dc_bounding_box_overrides bb_overrides; 1223 1224 int num_virtual_links; 1225 /* 1226 * If 'vbios_override' not NULL, it will be called instead 1227 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1228 */ 1229 struct dc_bios *vbios_override; 1230 enum dce_environment dce_environment; 1231 1232 struct dmub_offload_funcs *dmub_if; 1233 struct dc_reg_helper_state *dmub_offload; 1234 1235 struct dc_config flags; 1236 uint64_t log_mask; 1237 1238 struct dpcd_vendor_signature vendor_signature; 1239 bool force_smu_not_present; 1240 /* 1241 * IP offset for run time initializaion of register addresses 1242 * 1243 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1244 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1245 * before them. 1246 */ 1247 uint32_t *dcn_reg_offsets; 1248 uint32_t *nbio_reg_offsets; 1249 uint32_t *clk_reg_offsets; 1250 void *bb_from_dmub; 1251 }; 1252 1253 struct dc_callback_init { 1254 struct cp_psp cp_psp; 1255 }; 1256 1257 struct dc *dc_create(const struct dc_init_data *init_params); 1258 void dc_hardware_init(struct dc *dc); 1259 1260 int dc_get_vmid_use_vector(struct dc *dc); 1261 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1262 /* Returns the number of vmids supported */ 1263 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1264 void dc_init_callbacks(struct dc *dc, 1265 const struct dc_callback_init *init_params); 1266 void dc_deinit_callbacks(struct dc *dc); 1267 void dc_destroy(struct dc **dc); 1268 1269 /* Surface Interfaces */ 1270 1271 enum { 1272 TRANSFER_FUNC_POINTS = 1025 1273 }; 1274 1275 struct dc_hdr_static_metadata { 1276 /* display chromaticities and white point in units of 0.00001 */ 1277 unsigned int chromaticity_green_x; 1278 unsigned int chromaticity_green_y; 1279 unsigned int chromaticity_blue_x; 1280 unsigned int chromaticity_blue_y; 1281 unsigned int chromaticity_red_x; 1282 unsigned int chromaticity_red_y; 1283 unsigned int chromaticity_white_point_x; 1284 unsigned int chromaticity_white_point_y; 1285 1286 uint32_t min_luminance; 1287 uint32_t max_luminance; 1288 uint32_t maximum_content_light_level; 1289 uint32_t maximum_frame_average_light_level; 1290 }; 1291 1292 enum dc_transfer_func_type { 1293 TF_TYPE_PREDEFINED, 1294 TF_TYPE_DISTRIBUTED_POINTS, 1295 TF_TYPE_BYPASS, 1296 TF_TYPE_HWPWL 1297 }; 1298 1299 struct dc_transfer_func_distributed_points { 1300 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1301 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1302 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1303 1304 uint16_t end_exponent; 1305 uint16_t x_point_at_y1_red; 1306 uint16_t x_point_at_y1_green; 1307 uint16_t x_point_at_y1_blue; 1308 }; 1309 1310 enum dc_transfer_func_predefined { 1311 TRANSFER_FUNCTION_SRGB, 1312 TRANSFER_FUNCTION_BT709, 1313 TRANSFER_FUNCTION_PQ, 1314 TRANSFER_FUNCTION_LINEAR, 1315 TRANSFER_FUNCTION_UNITY, 1316 TRANSFER_FUNCTION_HLG, 1317 TRANSFER_FUNCTION_HLG12, 1318 TRANSFER_FUNCTION_GAMMA22, 1319 TRANSFER_FUNCTION_GAMMA24, 1320 TRANSFER_FUNCTION_GAMMA26 1321 }; 1322 1323 1324 struct dc_transfer_func { 1325 struct kref refcount; 1326 enum dc_transfer_func_type type; 1327 enum dc_transfer_func_predefined tf; 1328 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1329 uint32_t sdr_ref_white_level; 1330 union { 1331 struct pwl_params pwl; 1332 struct dc_transfer_func_distributed_points tf_pts; 1333 }; 1334 }; 1335 1336 1337 union dc_3dlut_state { 1338 struct { 1339 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1340 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1341 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1342 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1343 uint32_t mpc_rmu1_mux:4; 1344 uint32_t mpc_rmu2_mux:4; 1345 uint32_t reserved:15; 1346 } bits; 1347 uint32_t raw; 1348 }; 1349 1350 1351 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1352 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1353 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1354 1355 struct lut_rgb { 1356 uint16_t b; 1357 uint16_t g; 1358 uint16_t r; 1359 uint16_t padding; 1360 }; 1361 1362 //this structure maps directly to how the lut will read it from memory 1363 struct lut_mem_mapping { 1364 union { 1365 //NATIVE MODE 1, 2 1366 //RGB layout [b][g][r] //red is 128 byte aligned 1367 //BGR layout [r][g][b] //blue is 128 byte aligned 1368 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1369 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1370 1371 //TRANSFORMED 1372 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1373 }; 1374 uint16_t size; 1375 }; 1376 1377 struct dc_rmcm_3dlut { 1378 bool isInUse; 1379 const struct dc_stream_state *stream; 1380 uint8_t protection_bits; 1381 }; 1382 1383 struct dc_3dlut { 1384 struct kref refcount; 1385 struct tetrahedral_params lut_3d; 1386 struct fixed31_32 hdr_multiplier; 1387 union dc_3dlut_state state; 1388 }; 1389 /* 1390 * This structure is filled in by dc_surface_get_status and contains 1391 * the last requested address and the currently active address so the called 1392 * can determine if there are any outstanding flips 1393 */ 1394 struct dc_plane_status { 1395 struct dc_plane_address requested_address; 1396 struct dc_plane_address current_address; 1397 bool is_flip_pending; 1398 bool is_right_eye; 1399 }; 1400 1401 union surface_update_flags { 1402 1403 struct { 1404 uint32_t addr_update:1; 1405 /* Medium updates */ 1406 uint32_t dcc_change:1; 1407 uint32_t color_space_change:1; 1408 uint32_t horizontal_mirror_change:1; 1409 uint32_t per_pixel_alpha_change:1; 1410 uint32_t global_alpha_change:1; 1411 uint32_t hdr_mult:1; 1412 uint32_t rotation_change:1; 1413 uint32_t swizzle_change:1; 1414 uint32_t scaling_change:1; 1415 uint32_t position_change:1; 1416 uint32_t in_transfer_func_change:1; 1417 uint32_t input_csc_change:1; 1418 uint32_t coeff_reduction_change:1; 1419 uint32_t pixel_format_change:1; 1420 uint32_t plane_size_change:1; 1421 uint32_t gamut_remap_change:1; 1422 1423 /* Full updates */ 1424 uint32_t new_plane:1; 1425 uint32_t bpp_change:1; 1426 uint32_t gamma_change:1; 1427 uint32_t bandwidth_change:1; 1428 uint32_t clock_change:1; 1429 uint32_t stereo_format_change:1; 1430 uint32_t lut_3d:1; 1431 uint32_t tmz_changed:1; 1432 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1433 uint32_t full_update:1; 1434 uint32_t sdr_white_level_nits:1; 1435 } bits; 1436 1437 uint32_t raw; 1438 }; 1439 1440 #define DC_REMOVE_PLANE_POINTERS 1 1441 1442 struct dc_plane_state { 1443 struct dc_plane_address address; 1444 struct dc_plane_flip_time time; 1445 bool triplebuffer_flips; 1446 struct scaling_taps scaling_quality; 1447 struct rect src_rect; 1448 struct rect dst_rect; 1449 struct rect clip_rect; 1450 1451 struct plane_size plane_size; 1452 struct dc_tiling_info tiling_info; 1453 1454 struct dc_plane_dcc_param dcc; 1455 1456 struct dc_gamma gamma_correction; 1457 struct dc_transfer_func in_transfer_func; 1458 struct dc_bias_and_scale bias_and_scale; 1459 struct dc_csc_transform input_csc_color_matrix; 1460 struct fixed31_32 coeff_reduction_factor; 1461 struct fixed31_32 hdr_mult; 1462 struct colorspace_transform gamut_remap_matrix; 1463 1464 // TODO: No longer used, remove 1465 struct dc_hdr_static_metadata hdr_static_ctx; 1466 1467 enum dc_color_space color_space; 1468 1469 struct dc_3dlut lut3d_func; 1470 struct dc_transfer_func in_shaper_func; 1471 struct dc_transfer_func blend_tf; 1472 1473 struct dc_transfer_func *gamcor_tf; 1474 enum surface_pixel_format format; 1475 enum dc_rotation_angle rotation; 1476 enum plane_stereo_format stereo_format; 1477 1478 bool is_tiling_rotated; 1479 bool per_pixel_alpha; 1480 bool pre_multiplied_alpha; 1481 bool global_alpha; 1482 int global_alpha_value; 1483 bool visible; 1484 bool flip_immediate; 1485 bool horizontal_mirror; 1486 int layer_index; 1487 1488 union surface_update_flags update_flags; 1489 bool flip_int_enabled; 1490 bool skip_manual_trigger; 1491 1492 /* private to DC core */ 1493 struct dc_plane_status status; 1494 struct dc_context *ctx; 1495 1496 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1497 bool force_full_update; 1498 1499 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1500 1501 /* private to dc_surface.c */ 1502 enum dc_irq_source irq_source; 1503 struct kref refcount; 1504 struct tg_color visual_confirm_color; 1505 1506 bool is_statically_allocated; 1507 enum chroma_cositing cositing; 1508 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1509 bool mcm_lut1d_enable; 1510 struct dc_cm2_func_luts mcm_luts; 1511 bool lut_bank_a; 1512 enum mpcc_movable_cm_location mcm_location; 1513 struct dc_csc_transform cursor_csc_color_matrix; 1514 bool adaptive_sharpness_en; 1515 int adaptive_sharpness_policy; 1516 int sharpness_level; 1517 enum linear_light_scaling linear_light_scaling; 1518 unsigned int sdr_white_level_nits; 1519 struct spl_sharpness_range sharpness_range; 1520 enum sharpness_range_source sharpness_source; 1521 }; 1522 1523 struct dc_plane_info { 1524 struct plane_size plane_size; 1525 struct dc_tiling_info tiling_info; 1526 struct dc_plane_dcc_param dcc; 1527 enum surface_pixel_format format; 1528 enum dc_rotation_angle rotation; 1529 enum plane_stereo_format stereo_format; 1530 enum dc_color_space color_space; 1531 bool horizontal_mirror; 1532 bool visible; 1533 bool per_pixel_alpha; 1534 bool pre_multiplied_alpha; 1535 bool global_alpha; 1536 int global_alpha_value; 1537 bool input_csc_enabled; 1538 int layer_index; 1539 enum chroma_cositing cositing; 1540 }; 1541 1542 #include "dc_stream.h" 1543 1544 struct dc_scratch_space { 1545 /* used to temporarily backup plane states of a stream during 1546 * dc update. The reason is that plane states are overwritten 1547 * with surface updates in dc update. Once they are overwritten 1548 * current state is no longer valid. We want to temporarily 1549 * store current value in plane states so we can still recover 1550 * a valid current state during dc update. 1551 */ 1552 struct dc_plane_state plane_states[MAX_SURFACES]; 1553 1554 struct dc_stream_state stream_state; 1555 }; 1556 1557 /* 1558 * A link contains one or more sinks and their connected status. 1559 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1560 */ 1561 struct dc_link { 1562 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1563 unsigned int sink_count; 1564 struct dc_sink *local_sink; 1565 unsigned int link_index; 1566 enum dc_connection_type type; 1567 enum signal_type connector_signal; 1568 enum dc_irq_source irq_source_hpd; 1569 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1570 enum dc_irq_source irq_source_read_request;/* Read Request */ 1571 1572 bool is_hpd_filter_disabled; 1573 bool dp_ss_off; 1574 1575 /** 1576 * @link_state_valid: 1577 * 1578 * If there is no link and local sink, this variable should be set to 1579 * false. Otherwise, it should be set to true; usually, the function 1580 * core_link_enable_stream sets this field to true. 1581 */ 1582 bool link_state_valid; 1583 bool aux_access_disabled; 1584 bool sync_lt_in_progress; 1585 bool skip_stream_reenable; 1586 bool is_internal_display; 1587 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1588 bool is_dig_mapping_flexible; 1589 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1590 bool is_hpd_pending; /* Indicates a new received hpd */ 1591 1592 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1593 * for every link training. This is incompatible with DP LL compliance automation, 1594 * which expects the same link settings to be used every retry on a link loss. 1595 * This flag is used to skip the fallback when link loss occurs during automation. 1596 */ 1597 bool skip_fallback_on_link_loss; 1598 1599 bool edp_sink_present; 1600 1601 struct dp_trace dp_trace; 1602 1603 /* caps is the same as reported_link_cap. link_traing use 1604 * reported_link_cap. Will clean up. TODO 1605 */ 1606 struct dc_link_settings reported_link_cap; 1607 struct dc_link_settings verified_link_cap; 1608 struct dc_link_settings cur_link_settings; 1609 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1610 struct dc_link_settings preferred_link_setting; 1611 /* preferred_training_settings are override values that 1612 * come from DM. DM is responsible for the memory 1613 * management of the override pointers. 1614 */ 1615 struct dc_link_training_overrides preferred_training_settings; 1616 struct dp_audio_test_data audio_test_data; 1617 1618 uint8_t ddc_hw_inst; 1619 1620 uint8_t hpd_src; 1621 1622 uint8_t link_enc_hw_inst; 1623 /* DIG link encoder ID. Used as index in link encoder resource pool. 1624 * For links with fixed mapping to DIG, this is not changed after dc_link 1625 * object creation. 1626 */ 1627 enum engine_id eng_id; 1628 enum engine_id dpia_preferred_eng_id; 1629 1630 bool test_pattern_enabled; 1631 /* Pending/Current test pattern are only used to perform and track 1632 * FIXED_VS retimer test pattern/lane adjustment override state. 1633 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1634 * to perform specific lane adjust overrides before setting certain 1635 * PHY test patterns. In cases when lane adjust and set test pattern 1636 * calls are not performed atomically (i.e. performing link training), 1637 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1638 * and current_test_pattern will contain required context for any future 1639 * set pattern/set lane adjust to transition between override state(s). 1640 * */ 1641 enum dp_test_pattern current_test_pattern; 1642 enum dp_test_pattern pending_test_pattern; 1643 1644 union compliance_test_state compliance_test_state; 1645 1646 void *priv; 1647 1648 struct ddc_service *ddc; 1649 1650 enum dp_panel_mode panel_mode; 1651 bool aux_mode; 1652 1653 /* Private to DC core */ 1654 1655 const struct dc *dc; 1656 1657 struct dc_context *ctx; 1658 1659 struct panel_cntl *panel_cntl; 1660 struct link_encoder *link_enc; 1661 struct graphics_object_id link_id; 1662 /* Endpoint type distinguishes display endpoints which do not have entries 1663 * in the BIOS connector table from those that do. Helps when tracking link 1664 * encoder to display endpoint assignments. 1665 */ 1666 enum display_endpoint_type ep_type; 1667 union ddi_channel_mapping ddi_channel_mapping; 1668 struct connector_device_tag_info device_tag; 1669 struct dpcd_caps dpcd_caps; 1670 uint32_t dongle_max_pix_clk; 1671 unsigned short chip_caps; 1672 unsigned int dpcd_sink_count; 1673 struct hdcp_caps hdcp_caps; 1674 enum edp_revision edp_revision; 1675 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1676 1677 struct psr_settings psr_settings; 1678 struct replay_settings replay_settings; 1679 1680 /* Drive settings read from integrated info table */ 1681 struct dc_lane_settings bios_forced_drive_settings; 1682 1683 /* Vendor specific LTTPR workaround variables */ 1684 uint8_t vendor_specific_lttpr_link_rate_wa; 1685 bool apply_vendor_specific_lttpr_link_rate_wa; 1686 1687 /* MST record stream using this link */ 1688 struct link_flags { 1689 bool dp_keep_receiver_powered; 1690 bool dp_skip_DID2; 1691 bool dp_skip_reset_segment; 1692 bool dp_skip_fs_144hz; 1693 bool dp_mot_reset_segment; 1694 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1695 bool dpia_mst_dsc_always_on; 1696 /* Forced DPIA into TBT3 compatibility mode. */ 1697 bool dpia_forced_tbt3_mode; 1698 bool dongle_mode_timing_override; 1699 bool blank_stream_on_ocs_change; 1700 bool read_dpcd204h_on_irq_hpd; 1701 bool force_dp_ffe_preset; 1702 bool skip_phy_ssc_reduction; 1703 } wa_flags; 1704 union dc_dp_ffe_preset forced_dp_ffe_preset; 1705 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1706 1707 struct dc_link_status link_status; 1708 struct dprx_states dprx_states; 1709 1710 struct gpio *hpd_gpio; 1711 enum dc_link_fec_state fec_state; 1712 bool is_dds; 1713 bool is_display_mux_present; 1714 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1715 1716 struct dc_panel_config panel_config; 1717 struct phy_state phy_state; 1718 uint32_t phy_transition_bitmask; 1719 // BW ALLOCATON USB4 ONLY 1720 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1721 bool skip_implict_edp_power_control; 1722 enum backlight_control_type backlight_control_type; 1723 }; 1724 1725 struct dc { 1726 struct dc_debug_options debug; 1727 struct dc_versions versions; 1728 struct dc_caps caps; 1729 struct dc_check_config check_config; 1730 struct dc_cap_funcs cap_funcs; 1731 struct dc_config config; 1732 struct dc_bounding_box_overrides bb_overrides; 1733 struct dc_bug_wa work_arounds; 1734 struct dc_context *ctx; 1735 struct dc_phy_addr_space_config vm_pa_config; 1736 1737 uint8_t link_count; 1738 struct dc_link *links[MAX_LINKS]; 1739 uint8_t lowest_dpia_link_index; 1740 struct link_service *link_srv; 1741 1742 struct dc_state *current_state; 1743 struct resource_pool *res_pool; 1744 1745 struct clk_mgr *clk_mgr; 1746 1747 /* Display Engine Clock levels */ 1748 struct dm_pp_clock_levels sclk_lvls; 1749 1750 /* Inputs into BW and WM calculations. */ 1751 struct bw_calcs_dceip *bw_dceip; 1752 struct bw_calcs_vbios *bw_vbios; 1753 struct dcn_soc_bounding_box *dcn_soc; 1754 struct dcn_ip_params *dcn_ip; 1755 struct display_mode_lib dml; 1756 1757 /* HW functions */ 1758 struct hw_sequencer_funcs hwss; 1759 struct dce_hwseq *hwseq; 1760 1761 /* Require to optimize clocks and bandwidth for added/removed planes */ 1762 bool optimized_required; 1763 bool idle_optimizations_allowed; 1764 bool enable_c20_dtm_b0; 1765 1766 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1767 1768 /* For eDP to know the switching state of SmartMux */ 1769 bool is_switch_in_progress_orig; 1770 bool is_switch_in_progress_dest; 1771 1772 /* FBC compressor */ 1773 struct compressor *fbc_compressor; 1774 1775 struct dc_debug_data debug_data; 1776 struct dpcd_vendor_signature vendor_signature; 1777 1778 const char *build_id; 1779 struct vm_helper *vm_helper; 1780 1781 uint32_t *dcn_reg_offsets; 1782 uint32_t *nbio_reg_offsets; 1783 uint32_t *clk_reg_offsets; 1784 1785 /* Scratch memory */ 1786 struct { 1787 struct { 1788 /* 1789 * For matching clock_limits table in driver with table 1790 * from PMFW. 1791 */ 1792 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1793 } update_bw_bounding_box; 1794 struct dc_scratch_space current_state; 1795 struct dc_scratch_space new_state; 1796 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1797 struct dc_link temp_link; 1798 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1799 } scratch; 1800 1801 struct dml2_configuration_options dml2_options; 1802 struct dml2_configuration_options dml2_dc_power_options; 1803 enum dc_acpi_cm_power_state power_state; 1804 struct soc_and_ip_translator *soc_and_ip_translator; 1805 }; 1806 1807 struct dc_scaling_info { 1808 struct rect src_rect; 1809 struct rect dst_rect; 1810 struct rect clip_rect; 1811 struct scaling_taps scaling_quality; 1812 }; 1813 1814 struct dc_fast_update { 1815 const struct dc_flip_addrs *flip_addr; 1816 const struct dc_gamma *gamma; 1817 const struct colorspace_transform *gamut_remap_matrix; 1818 const struct dc_csc_transform *input_csc_color_matrix; 1819 const struct fixed31_32 *coeff_reduction_factor; 1820 struct dc_transfer_func *out_transfer_func; 1821 struct dc_csc_transform *output_csc_transform; 1822 const struct dc_csc_transform *cursor_csc_color_matrix; 1823 }; 1824 1825 struct dc_surface_update { 1826 struct dc_plane_state *surface; 1827 1828 /* isr safe update parameters. null means no updates */ 1829 const struct dc_flip_addrs *flip_addr; 1830 const struct dc_plane_info *plane_info; 1831 const struct dc_scaling_info *scaling_info; 1832 struct fixed31_32 hdr_mult; 1833 /* following updates require alloc/sleep/spin that is not isr safe, 1834 * null means no updates 1835 */ 1836 const struct dc_gamma *gamma; 1837 const struct dc_transfer_func *in_transfer_func; 1838 1839 const struct dc_csc_transform *input_csc_color_matrix; 1840 const struct fixed31_32 *coeff_reduction_factor; 1841 const struct dc_transfer_func *func_shaper; 1842 const struct dc_3dlut *lut3d_func; 1843 const struct dc_transfer_func *blend_tf; 1844 const struct colorspace_transform *gamut_remap_matrix; 1845 /* 1846 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1847 * 1848 * change cm2_params.component_settings: Full update 1849 * change cm2_params.cm2_luts: Fast update 1850 */ 1851 const struct dc_cm2_parameters *cm2_params; 1852 const struct dc_csc_transform *cursor_csc_color_matrix; 1853 unsigned int sdr_white_level_nits; 1854 struct dc_bias_and_scale bias_and_scale; 1855 }; 1856 1857 struct dc_underflow_debug_data { 1858 struct dcn_hubbub_reg_state *hubbub_reg_state; 1859 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 1860 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 1861 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 1862 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 1863 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 1864 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 1865 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 1866 }; 1867 1868 /* 1869 * Create a new surface with default parameters; 1870 */ 1871 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1872 void dc_gamma_release(struct dc_gamma **dc_gamma); 1873 struct dc_gamma *dc_create_gamma(void); 1874 1875 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1876 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1877 struct dc_transfer_func *dc_create_transfer_func(void); 1878 1879 struct dc_3dlut *dc_create_3dlut_func(void); 1880 void dc_3dlut_func_release(struct dc_3dlut *lut); 1881 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1882 1883 void dc_post_update_surfaces_to_stream( 1884 struct dc *dc); 1885 1886 /** 1887 * struct dc_validation_set - Struct to store surface/stream associations for validation 1888 */ 1889 struct dc_validation_set { 1890 /** 1891 * @stream: Stream state properties 1892 */ 1893 struct dc_stream_state *stream; 1894 1895 /** 1896 * @plane_states: Surface state 1897 */ 1898 struct dc_plane_state *plane_states[MAX_SURFACES]; 1899 1900 /** 1901 * @plane_count: Total of active planes 1902 */ 1903 uint8_t plane_count; 1904 }; 1905 1906 bool dc_validate_boot_timing(const struct dc *dc, 1907 const struct dc_sink *sink, 1908 struct dc_crtc_timing *crtc_timing); 1909 1910 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1911 1912 enum dc_status dc_validate_with_context(struct dc *dc, 1913 const struct dc_validation_set set[], 1914 int set_count, 1915 struct dc_state *context, 1916 enum dc_validate_mode validate_mode); 1917 1918 bool dc_set_generic_gpio_for_stereo(bool enable, 1919 struct gpio_service *gpio_service); 1920 1921 enum dc_status dc_validate_global_state( 1922 struct dc *dc, 1923 struct dc_state *new_ctx, 1924 enum dc_validate_mode validate_mode); 1925 1926 bool dc_acquire_release_mpc_3dlut( 1927 struct dc *dc, bool acquire, 1928 struct dc_stream_state *stream, 1929 struct dc_3dlut **lut, 1930 struct dc_transfer_func **shaper); 1931 1932 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1933 void get_audio_check(struct audio_info *aud_modes, 1934 struct audio_check *aud_chk); 1935 1936 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1937 void populate_fast_updates(struct dc_fast_update *fast_update, 1938 struct dc_surface_update *srf_updates, 1939 int surface_count, 1940 struct dc_stream_update *stream_update); 1941 /* 1942 * Set up streams and links associated to drive sinks 1943 * The streams parameter is an absolute set of all active streams. 1944 * 1945 * After this call: 1946 * Phy, Encoder, Timing Generator are programmed and enabled. 1947 * New streams are enabled with blank stream; no memory read. 1948 */ 1949 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1950 1951 1952 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1953 struct dc_stream_state *stream, 1954 int mpcc_inst); 1955 1956 1957 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1958 1959 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1960 1961 /* The function returns minimum bandwidth required to drive a given timing 1962 * return - minimum required timing bandwidth in kbps. 1963 */ 1964 uint32_t dc_bandwidth_in_kbps_from_timing( 1965 const struct dc_crtc_timing *timing, 1966 const enum dc_link_encoding_format link_encoding); 1967 1968 /* Link Interfaces */ 1969 /* Return an enumerated dc_link. 1970 * dc_link order is constant and determined at 1971 * boot time. They cannot be created or destroyed. 1972 * Use dc_get_caps() to get number of links. 1973 */ 1974 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1975 1976 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1977 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1978 const struct dc_link *link, 1979 unsigned int *inst_out); 1980 1981 /* Return an array of link pointers to edp links. */ 1982 void dc_get_edp_links(const struct dc *dc, 1983 struct dc_link **edp_links, 1984 int *edp_num); 1985 1986 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1987 bool powerOn); 1988 1989 /* The function initiates detection handshake over the given link. It first 1990 * determines if there are display connections over the link. If so it initiates 1991 * detection protocols supported by the connected receiver device. The function 1992 * contains protocol specific handshake sequences which are sometimes mandatory 1993 * to establish a proper connection between TX and RX. So it is always 1994 * recommended to call this function as the first link operation upon HPD event 1995 * or power up event. Upon completion, the function will update link structure 1996 * in place based on latest RX capabilities. The function may also cause dpms 1997 * to be reset to off for all currently enabled streams to the link. It is DM's 1998 * responsibility to serialize detection and DPMS updates. 1999 * 2000 * @reason - Indicate which event triggers this detection. dc may customize 2001 * detection flow depending on the triggering events. 2002 * return false - if detection is not fully completed. This could happen when 2003 * there is an unrecoverable error during detection or detection is partially 2004 * completed (detection has been delegated to dm mst manager ie. 2005 * link->connection_type == dc_connection_mst_branch when returning false). 2006 * return true - detection is completed, link has been fully updated with latest 2007 * detection result. 2008 */ 2009 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2010 2011 struct dc_sink_init_data; 2012 2013 /* When link connection type is dc_connection_mst_branch, remote sink can be 2014 * added to the link. The interface creates a remote sink and associates it with 2015 * current link. The sink will be retained by link until remove remote sink is 2016 * called. 2017 * 2018 * @dc_link - link the remote sink will be added to. 2019 * @edid - byte array of EDID raw data. 2020 * @len - size of the edid in byte 2021 * @init_data - 2022 */ 2023 struct dc_sink *dc_link_add_remote_sink( 2024 struct dc_link *dc_link, 2025 const uint8_t *edid, 2026 int len, 2027 struct dc_sink_init_data *init_data); 2028 2029 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2030 * @link - link the sink should be removed from 2031 * @sink - sink to be removed. 2032 */ 2033 void dc_link_remove_remote_sink( 2034 struct dc_link *link, 2035 struct dc_sink *sink); 2036 2037 /* Enable HPD interrupt handler for a given link */ 2038 void dc_link_enable_hpd(const struct dc_link *link); 2039 2040 /* Disable HPD interrupt handler for a given link */ 2041 void dc_link_disable_hpd(const struct dc_link *link); 2042 2043 /* determine if there is a sink connected to the link 2044 * 2045 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2046 * return - false if an unexpected error occurs, true otherwise. 2047 * 2048 * NOTE: This function doesn't detect downstream sink connections i.e 2049 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2050 * return dc_connection_single if the branch device is connected despite of 2051 * downstream sink's connection status. 2052 */ 2053 bool dc_link_detect_connection_type(struct dc_link *link, 2054 enum dc_connection_type *type); 2055 2056 /* query current hpd pin value 2057 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2058 * 2059 */ 2060 bool dc_link_get_hpd_state(struct dc_link *link); 2061 2062 /* Getter for cached link status from given link */ 2063 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2064 2065 /* enable/disable hardware HPD filter. 2066 * 2067 * @link - The link the HPD pin is associated with. 2068 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2069 * handler once after no HPD change has been detected within dc default HPD 2070 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2071 * pulses within default HPD interval, no HPD event will be received until HPD 2072 * toggles have stopped. Then HPD event will be queued to irq handler once after 2073 * dc default HPD filtering interval since last HPD event. 2074 * 2075 * @enable = false - disable hardware HPD filter. HPD event will be queued 2076 * immediately to irq handler after no HPD change has been detected within 2077 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2078 */ 2079 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2080 2081 /* submit i2c read/write payloads through ddc channel 2082 * @link_index - index to a link with ddc in i2c mode 2083 * @cmd - i2c command structure 2084 * return - true if success, false otherwise. 2085 */ 2086 bool dc_submit_i2c( 2087 struct dc *dc, 2088 uint32_t link_index, 2089 struct i2c_command *cmd); 2090 2091 /* submit i2c read/write payloads through oem channel 2092 * @link_index - index to a link with ddc in i2c mode 2093 * @cmd - i2c command structure 2094 * return - true if success, false otherwise. 2095 */ 2096 bool dc_submit_i2c_oem( 2097 struct dc *dc, 2098 struct i2c_command *cmd); 2099 2100 enum aux_return_code_type; 2101 /* Attempt to transfer the given aux payload. This function does not perform 2102 * retries or handle error states. The reply is returned in the payload->reply 2103 * and the result through operation_result. Returns the number of bytes 2104 * transferred,or -1 on a failure. 2105 */ 2106 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2107 struct aux_payload *payload, 2108 enum aux_return_code_type *operation_result); 2109 2110 struct ddc_service * 2111 dc_get_oem_i2c_device(struct dc *dc); 2112 2113 bool dc_is_oem_i2c_device_present( 2114 struct dc *dc, 2115 size_t slave_address 2116 ); 2117 2118 /* return true if the connected receiver supports the hdcp version */ 2119 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2120 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2121 2122 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2123 * 2124 * TODO - When defer_handling is true the function will have a different purpose. 2125 * It no longer does complete hpd rx irq handling. We should create a separate 2126 * interface specifically for this case. 2127 * 2128 * Return: 2129 * true - Downstream port status changed. DM should call DC to do the 2130 * detection. 2131 * false - no change in Downstream port status. No further action required 2132 * from DM. 2133 */ 2134 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2135 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2136 bool defer_handling, bool *has_left_work); 2137 /* handle DP specs define test automation sequence*/ 2138 void dc_link_dp_handle_automated_test(struct dc_link *link); 2139 2140 /* handle DP Link loss sequence and try to recover RX link loss with best 2141 * effort 2142 */ 2143 void dc_link_dp_handle_link_loss(struct dc_link *link); 2144 2145 /* Determine if hpd rx irq should be handled or ignored 2146 * return true - hpd rx irq should be handled. 2147 * return false - it is safe to ignore hpd rx irq event 2148 */ 2149 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2150 2151 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2152 * @link - link the hpd irq data associated with 2153 * @hpd_irq_dpcd_data - input hpd irq data 2154 * return - true if hpd irq data indicates a link lost 2155 */ 2156 bool dc_link_check_link_loss_status(struct dc_link *link, 2157 union hpd_irq_data *hpd_irq_dpcd_data); 2158 2159 /* Read hpd rx irq data from a given link 2160 * @link - link where the hpd irq data should be read from 2161 * @irq_data - output hpd irq data 2162 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2163 * read has failed. 2164 */ 2165 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2166 struct dc_link *link, 2167 union hpd_irq_data *irq_data); 2168 2169 /* The function clears recorded DP RX states in the link. DM should call this 2170 * function when it is resuming from S3 power state to previously connected links. 2171 * 2172 * TODO - in the future we should consider to expand link resume interface to 2173 * support clearing previous rx states. So we don't have to rely on dm to call 2174 * this interface explicitly. 2175 */ 2176 void dc_link_clear_dprx_states(struct dc_link *link); 2177 2178 /* Destruct the mst topology of the link and reset the allocated payload table 2179 * 2180 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2181 * still wants to reset MST topology on an unplug event */ 2182 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2183 2184 /* The function calculates effective DP link bandwidth when a given link is 2185 * using the given link settings. 2186 * 2187 * return - total effective link bandwidth in kbps. 2188 */ 2189 uint32_t dc_link_bandwidth_kbps( 2190 const struct dc_link *link, 2191 const struct dc_link_settings *link_setting); 2192 2193 struct dp_audio_bandwidth_params { 2194 const struct dc_crtc_timing *crtc_timing; 2195 enum dp_link_encoding link_encoding; 2196 uint32_t channel_count; 2197 uint32_t sample_rate_hz; 2198 }; 2199 2200 /* The function calculates the minimum size of hblank (in bytes) needed to 2201 * support the specified channel count and sample rate combination, given the 2202 * link encoding and timing to be used. This calculation is not supported 2203 * for 8b/10b SST. 2204 * 2205 * return - min hblank size in bytes, 0 if 8b/10b SST. 2206 */ 2207 uint32_t dc_link_required_hblank_size_bytes( 2208 const struct dc_link *link, 2209 struct dp_audio_bandwidth_params *audio_params); 2210 2211 /* The function takes a snapshot of current link resource allocation state 2212 * @dc: pointer to dc of the dm calling this 2213 * @map: a dc link resource snapshot defined internally to dc. 2214 * 2215 * DM needs to capture a snapshot of current link resource allocation mapping 2216 * and store it in its persistent storage. 2217 * 2218 * Some of the link resource is using first come first serve policy. 2219 * The allocation mapping depends on original hotplug order. This information 2220 * is lost after driver is loaded next time. The snapshot is used in order to 2221 * restore link resource to its previous state so user will get consistent 2222 * link capability allocation across reboot. 2223 * 2224 */ 2225 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2226 2227 /* This function restores link resource allocation state from a snapshot 2228 * @dc: pointer to dc of the dm calling this 2229 * @map: a dc link resource snapshot defined internally to dc. 2230 * 2231 * DM needs to call this function after initial link detection on boot and 2232 * before first commit streams to restore link resource allocation state 2233 * from previous boot session. 2234 * 2235 * Some of the link resource is using first come first serve policy. 2236 * The allocation mapping depends on original hotplug order. This information 2237 * is lost after driver is loaded next time. The snapshot is used in order to 2238 * restore link resource to its previous state so user will get consistent 2239 * link capability allocation across reboot. 2240 * 2241 */ 2242 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2243 2244 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2245 * interface i.e stream_update->dsc_config 2246 */ 2247 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2248 2249 /* translate a raw link rate data to bandwidth in kbps */ 2250 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2251 2252 /* determine the optimal bandwidth given link and required bw. 2253 * @link - current detected link 2254 * @req_bw - requested bandwidth in kbps 2255 * @link_settings - returned most optimal link settings that can fit the 2256 * requested bandwidth 2257 * return - false if link can't support requested bandwidth, true if link 2258 * settings is found. 2259 */ 2260 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2261 struct dc_link_settings *link_settings, 2262 uint32_t req_bw); 2263 2264 /* return the max dp link settings can be driven by the link without considering 2265 * connected RX device and its capability 2266 */ 2267 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2268 struct dc_link_settings *max_link_enc_cap); 2269 2270 /* determine when the link is driving MST mode, what DP link channel coding 2271 * format will be used. The decision will remain unchanged until next HPD event. 2272 * 2273 * @link - a link with DP RX connection 2274 * return - if stream is committed to this link with MST signal type, type of 2275 * channel coding format dc will choose. 2276 */ 2277 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2278 const struct dc_link *link); 2279 2280 /* get max dp link settings the link can enable with all things considered. (i.e 2281 * TX/RX/Cable capabilities and dp override policies. 2282 * 2283 * @link - a link with DP RX connection 2284 * return - max dp link settings the link can enable. 2285 * 2286 */ 2287 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2288 2289 /* Get the highest encoding format that the link supports; highest meaning the 2290 * encoding format which supports the maximum bandwidth. 2291 * 2292 * @link - a link with DP RX connection 2293 * return - highest encoding format link supports. 2294 */ 2295 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2296 2297 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2298 * to a link with dp connector signal type. 2299 * @link - a link with dp connector signal type 2300 * return - true if connected, false otherwise 2301 */ 2302 bool dc_link_is_dp_sink_present(struct dc_link *link); 2303 2304 /* Force DP lane settings update to main-link video signal and notify the change 2305 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2306 * tuning purpose. The interface assumes link has already been enabled with DP 2307 * signal. 2308 * 2309 * @lt_settings - a container structure with desired hw_lane_settings 2310 */ 2311 void dc_link_set_drive_settings(struct dc *dc, 2312 struct link_training_settings *lt_settings, 2313 struct dc_link *link); 2314 2315 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2316 * test or debugging purpose. The test pattern will remain until next un-plug. 2317 * 2318 * @link - active link with DP signal output enabled. 2319 * @test_pattern - desired test pattern to output. 2320 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2321 * @test_pattern_color_space - for video test pattern choose a desired color 2322 * space. 2323 * @p_link_settings - For PHY pattern choose a desired link settings 2324 * @p_custom_pattern - some test pattern will require a custom input to 2325 * customize some pattern details. Otherwise keep it to NULL. 2326 * @cust_pattern_size - size of the custom pattern input. 2327 * 2328 */ 2329 bool dc_link_dp_set_test_pattern( 2330 struct dc_link *link, 2331 enum dp_test_pattern test_pattern, 2332 enum dp_test_pattern_color_space test_pattern_color_space, 2333 const struct link_training_settings *p_link_settings, 2334 const unsigned char *p_custom_pattern, 2335 unsigned int cust_pattern_size); 2336 2337 /* Force DP link settings to always use a specific value until reboot to a 2338 * specific link. If link has already been enabled, the interface will also 2339 * switch to desired link settings immediately. This is a debug interface to 2340 * generic dp issue trouble shooting. 2341 */ 2342 void dc_link_set_preferred_link_settings(struct dc *dc, 2343 struct dc_link_settings *link_setting, 2344 struct dc_link *link); 2345 2346 /* Force DP link to customize a specific link training behavior by overriding to 2347 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2348 * display specific link training issues or apply some display specific 2349 * workaround in link training. 2350 * 2351 * @link_settings - if not NULL, force preferred link settings to the link. 2352 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2353 * will apply this particular override in future link training. If NULL is 2354 * passed in, dc resets previous overrides. 2355 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2356 * training settings. 2357 */ 2358 void dc_link_set_preferred_training_settings(struct dc *dc, 2359 struct dc_link_settings *link_setting, 2360 struct dc_link_training_overrides *lt_overrides, 2361 struct dc_link *link, 2362 bool skip_immediate_retrain); 2363 2364 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2365 bool dc_link_is_fec_supported(const struct dc_link *link); 2366 2367 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2368 * link enablement. 2369 * return - true if FEC should be enabled, false otherwise. 2370 */ 2371 bool dc_link_should_enable_fec(const struct dc_link *link); 2372 2373 /* determine lttpr mode the current link should be enabled with a specific link 2374 * settings. 2375 */ 2376 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2377 struct dc_link_settings *link_setting); 2378 2379 /* Force DP RX to update its power state. 2380 * NOTE: this interface doesn't update dp main-link. Calling this function will 2381 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2382 * RX power state back upon finish DM specific execution requiring DP RX in a 2383 * specific power state. 2384 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2385 * state. 2386 */ 2387 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2388 2389 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2390 * current value read from extended receiver cap from 02200h - 0220Fh. 2391 * Some DP RX has problems of providing accurate DP receiver caps from extended 2392 * field, this interface is a workaround to revert link back to use base caps. 2393 */ 2394 void dc_link_overwrite_extended_receiver_cap( 2395 struct dc_link *link); 2396 2397 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2398 bool wait_for_hpd); 2399 2400 /* Set backlight level of an embedded panel (eDP, LVDS). 2401 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2402 * and 16 bit fractional, where 1.0 is max backlight value. 2403 */ 2404 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2405 struct set_backlight_level_params *backlight_level_params); 2406 2407 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2408 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2409 bool isHDR, 2410 uint32_t backlight_millinits, 2411 uint32_t transition_time_in_ms); 2412 2413 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2414 uint32_t *backlight_millinits, 2415 uint32_t *backlight_millinits_peak); 2416 2417 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2418 2419 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2420 2421 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2422 bool wait, bool force_static, const unsigned int *power_opts); 2423 2424 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2425 2426 bool dc_link_setup_psr(struct dc_link *dc_link, 2427 const struct dc_stream_state *stream, struct psr_config *psr_config, 2428 struct psr_context *psr_context); 2429 2430 /* 2431 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2432 * 2433 * @link: pointer to the dc_link struct instance 2434 * @enable: enable(active) or disable(inactive) replay 2435 * @wait: state transition need to wait the active set completed. 2436 * @force_static: force disable(inactive) the replay 2437 * @power_opts: set power optimazation parameters to DMUB. 2438 * 2439 * return: allow Replay active will return true, else will return false. 2440 */ 2441 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2442 bool wait, bool force_static, const unsigned int *power_opts); 2443 2444 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2445 2446 /* On eDP links this function call will stall until T12 has elapsed. 2447 * If the panel is not in power off state, this function will return 2448 * immediately. 2449 */ 2450 bool dc_link_wait_for_t12(struct dc_link *link); 2451 2452 /* Determine if dp trace has been initialized to reflect upto date result * 2453 * return - true if trace is initialized and has valid data. False dp trace 2454 * doesn't have valid result. 2455 */ 2456 bool dc_dp_trace_is_initialized(struct dc_link *link); 2457 2458 /* Query a dp trace flag to indicate if the current dp trace data has been 2459 * logged before 2460 */ 2461 bool dc_dp_trace_is_logged(struct dc_link *link, 2462 bool in_detection); 2463 2464 /* Set dp trace flag to indicate whether DM has already logged the current dp 2465 * trace data. DM can set is_logged to true upon logging and check 2466 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2467 */ 2468 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2469 bool in_detection, 2470 bool is_logged); 2471 2472 /* Obtain driver time stamp for last dp link training end. The time stamp is 2473 * formatted based on dm_get_timestamp DM function. 2474 * @in_detection - true to get link training end time stamp of last link 2475 * training in detection sequence. false to get link training end time stamp 2476 * of last link training in commit (dpms) sequence 2477 */ 2478 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2479 bool in_detection); 2480 2481 /* Get how many link training attempts dc has done with latest sequence. 2482 * @in_detection - true to get link training count of last link 2483 * training in detection sequence. false to get link training count of last link 2484 * training in commit (dpms) sequence 2485 */ 2486 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2487 bool in_detection); 2488 2489 /* Get how many link loss has happened since last link training attempts */ 2490 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2491 2492 /* 2493 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2494 */ 2495 /* 2496 * Send a request from DP-Tx requesting to allocate BW remotely after 2497 * allocating it locally. This will get processed by CM and a CB function 2498 * will be called. 2499 * 2500 * @link: pointer to the dc_link struct instance 2501 * @req_bw: The requested bw in Kbyte to allocated 2502 * 2503 * return: none 2504 */ 2505 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2506 2507 /* 2508 * Handle the USB4 BW Allocation related functionality here: 2509 * Plug => Try to allocate max bw from timing parameters supported by the sink 2510 * Unplug => de-allocate bw 2511 * 2512 * @link: pointer to the dc_link struct instance 2513 * @peak_bw: Peak bw used by the link/sink 2514 * 2515 */ 2516 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2517 struct dc_link *link, int peak_bw); 2518 2519 /* 2520 * Calculates the DP tunneling bandwidth required for the stream timing 2521 * and aggregates the stream bandwidth for the respective DP tunneling link 2522 * 2523 * return: dc_status 2524 */ 2525 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2526 2527 /* 2528 * Get if ALPM is supported by the link 2529 */ 2530 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 2531 bool *auxwake_support); 2532 2533 /* Sink Interfaces - A sink corresponds to a display output device */ 2534 2535 struct dc_container_id { 2536 // 128bit GUID in binary form 2537 unsigned char guid[16]; 2538 // 8 byte port ID -> ELD.PortID 2539 unsigned int portId[2]; 2540 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2541 unsigned short manufacturerName; 2542 // 2 byte product code -> ELD.ProductCode 2543 unsigned short productCode; 2544 }; 2545 2546 2547 struct dc_sink_dsc_caps { 2548 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2549 // 'false' if they are sink's DSC caps 2550 bool is_virtual_dpcd_dsc; 2551 // 'true' if MST topology supports DSC passthrough for sink 2552 // 'false' if MST topology does not support DSC passthrough 2553 bool is_dsc_passthrough_supported; 2554 struct dsc_dec_dpcd_caps dsc_dec_caps; 2555 }; 2556 2557 struct dc_sink_hblank_expansion_caps { 2558 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2559 // 'false' if they are sink's HBlank expansion caps 2560 bool is_virtual_dpcd_hblank_expansion; 2561 struct hblank_expansion_dpcd_caps dpcd_caps; 2562 }; 2563 2564 struct dc_sink_fec_caps { 2565 bool is_rx_fec_supported; 2566 bool is_topology_fec_supported; 2567 }; 2568 2569 struct scdc_caps { 2570 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2571 union hdmi_scdc_device_id_data device_id; 2572 }; 2573 2574 /* 2575 * The sink structure contains EDID and other display device properties 2576 */ 2577 struct dc_sink { 2578 enum signal_type sink_signal; 2579 struct dc_edid dc_edid; /* raw edid */ 2580 struct dc_edid_caps edid_caps; /* parse display caps */ 2581 struct dc_container_id *dc_container_id; 2582 uint32_t dongle_max_pix_clk; 2583 void *priv; 2584 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2585 bool converter_disable_audio; 2586 2587 struct scdc_caps scdc_caps; 2588 struct dc_sink_dsc_caps dsc_caps; 2589 struct dc_sink_fec_caps fec_caps; 2590 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2591 2592 bool is_vsc_sdp_colorimetry_supported; 2593 2594 /* private to DC core */ 2595 struct dc_link *link; 2596 struct dc_context *ctx; 2597 2598 uint32_t sink_id; 2599 2600 /* private to dc_sink.c */ 2601 // refcount must be the last member in dc_sink, since we want the 2602 // sink structure to be logically cloneable up to (but not including) 2603 // refcount 2604 struct kref refcount; 2605 }; 2606 2607 void dc_sink_retain(struct dc_sink *sink); 2608 void dc_sink_release(struct dc_sink *sink); 2609 2610 struct dc_sink_init_data { 2611 enum signal_type sink_signal; 2612 struct dc_link *link; 2613 uint32_t dongle_max_pix_clk; 2614 bool converter_disable_audio; 2615 }; 2616 2617 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2618 2619 /* Newer interfaces */ 2620 struct dc_cursor { 2621 struct dc_plane_address address; 2622 struct dc_cursor_attributes attributes; 2623 }; 2624 2625 2626 /* Interrupt interfaces */ 2627 enum dc_irq_source dc_interrupt_to_irq_source( 2628 struct dc *dc, 2629 uint32_t src_id, 2630 uint32_t ext_id); 2631 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2632 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2633 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2634 struct dc *dc, uint32_t link_index); 2635 2636 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2637 2638 /* Power Interfaces */ 2639 2640 void dc_set_power_state( 2641 struct dc *dc, 2642 enum dc_acpi_cm_power_state power_state); 2643 void dc_resume(struct dc *dc); 2644 2645 void dc_power_down_on_boot(struct dc *dc); 2646 2647 /* 2648 * HDCP Interfaces 2649 */ 2650 enum hdcp_message_status dc_process_hdcp_msg( 2651 enum signal_type signal, 2652 struct dc_link *link, 2653 struct hdcp_protection_message *message_info); 2654 bool dc_is_dmcu_initialized(struct dc *dc); 2655 2656 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2657 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2658 2659 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2660 unsigned int pitch, 2661 unsigned int height, 2662 enum surface_pixel_format format, 2663 struct dc_cursor_attributes *cursor_attr); 2664 2665 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2666 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2667 2668 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2669 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2670 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2671 2672 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2673 void dc_unlock_memory_clock_frequency(struct dc *dc); 2674 2675 /* set min memory clock to the min required for current mode, max to maxDPM */ 2676 void dc_lock_memory_clock_frequency(struct dc *dc); 2677 2678 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2679 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2680 2681 /* cleanup on driver unload */ 2682 void dc_hardware_release(struct dc *dc); 2683 2684 /* disables fw based mclk switch */ 2685 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2686 2687 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2688 2689 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2690 2691 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2692 2693 void dc_z10_restore(const struct dc *dc); 2694 void dc_z10_save_init(struct dc *dc); 2695 2696 bool dc_is_dmub_outbox_supported(struct dc *dc); 2697 bool dc_enable_dmub_notifications(struct dc *dc); 2698 2699 bool dc_abm_save_restore( 2700 struct dc *dc, 2701 struct dc_stream_state *stream, 2702 struct abm_save_restore *pData); 2703 2704 void dc_enable_dmub_outbox(struct dc *dc); 2705 2706 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2707 uint32_t link_index, 2708 struct aux_payload *payload); 2709 2710 /* Get dc link index from dpia port index */ 2711 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2712 uint8_t dpia_port_index); 2713 2714 bool dc_process_dmub_set_config_async(struct dc *dc, 2715 uint32_t link_index, 2716 struct set_config_cmd_payload *payload, 2717 struct dmub_notification *notify); 2718 2719 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2720 uint32_t link_index, 2721 uint8_t mst_alloc_slots, 2722 uint8_t *mst_slots_in_use); 2723 2724 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2725 2726 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2727 uint32_t hpd_int_enable); 2728 2729 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2730 2731 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2732 2733 struct dc_power_profile { 2734 int power_level; /* Lower is better */ 2735 }; 2736 2737 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2738 2739 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2740 2741 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2742 2743 void dc_log_preos_dmcub_info(const struct dc *dc); 2744 2745 /* DSC Interfaces */ 2746 #include "dc_dsc.h" 2747 2748 void dc_get_visual_confirm_for_stream( 2749 struct dc *dc, 2750 struct dc_stream_state *stream_state, 2751 struct tg_color *color); 2752 2753 /* Disable acc mode Interfaces */ 2754 void dc_disable_accelerated_mode(struct dc *dc); 2755 2756 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2757 struct dc_stream_state *new_stream); 2758 2759 bool dc_is_cursor_limit_pending(struct dc *dc); 2760 bool dc_can_clear_cursor_limit(const struct dc *dc); 2761 2762 /** 2763 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 2764 * 2765 * @dc: Pointer to the display core context. 2766 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 2767 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 2768 * 2769 * This function collects and logs underflow-related HW states when underflow happens, 2770 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 2771 * The results are stored in the provided out_data structure for further analysis or logging. 2772 */ 2773 void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); 2774 2775 #endif /* DC_INTERFACE_H_ */ 2776