1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "dc_probe.h" 33 #include "grph_object_defs.h" 34 #include "logger_types.h" 35 #include "hdcp_msg_types.h" 36 #include "gpio_types.h" 37 #include "link_service_types.h" 38 #include "grph_object_ctrl_defs.h" 39 #include <inc/hw/opp.h> 40 41 #include "hwss/hw_sequencer.h" 42 #include "inc/compressor.h" 43 #include "inc/hw/dmcu.h" 44 #include "dml/display_mode_lib.h" 45 46 #include "dml2_0/dml2_wrapper.h" 47 48 #include "dmub/inc/dmub_cmd.h" 49 50 #include "dml/dml1_frl_cap_chk.h" 51 52 #include "sspl/dc_spl_types.h" 53 54 struct abm_save_restore; 55 56 /* forward declaration */ 57 struct aux_payload; 58 struct set_config_cmd_payload; 59 struct dmub_notification; 60 struct dcn_hubbub_reg_state; 61 struct dcn_hubp_reg_state; 62 struct dcn_dpp_reg_state; 63 struct dcn_mpc_reg_state; 64 struct dcn_opp_reg_state; 65 struct dcn_dsc_reg_state; 66 struct dcn_optc_reg_state; 67 struct dcn_dccg_reg_state; 68 69 #define DC_VER "3.2.390" 70 71 /** 72 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 73 */ 74 #define MAX_SURFACES 4 75 /** 76 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 77 */ 78 #define MAX_PLANES 6 79 #define MAX_STREAMS 6 80 #define MIN_VIEWPORT_SIZE 12 81 #define MAX_NUM_EDP 2 82 #define MAX_SUPPORTED_FORMATS 7 83 84 #define MAX_HOST_ROUTERS_NUM 3 85 #define MAX_DPIA_PER_HOST_ROUTER 3 86 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 87 88 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 89 90 struct frl_cap_chk_intermediates_fixed31_32 { 91 int c_frl_sb; 92 struct fixed31_32 overhead_sb; 93 struct fixed31_32 overhead_rs; 94 struct fixed31_32 overhead_map; 95 struct fixed31_32 overhead_min; 96 struct fixed31_32 overhead_max; 97 struct fixed31_32 f_pixel_clock_max; 98 struct fixed31_32 t_line; 99 struct fixed31_32 r_bit_min; 100 struct fixed31_32 r_frl_char_min; 101 struct fixed31_32 c_frl_line; 102 struct fixed31_32 ap; 103 struct fixed31_32 r_ap; 104 struct fixed31_32 avg_audio_packets_line; 105 struct fixed31_32 margin; 106 int audio_packets_line; 107 int blank_audio_min; 108 }; 109 110 struct frl_cap_chk_params_fixed31_32 { 111 int lanes; 112 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 113 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ 114 int audio_packet_type; 115 struct fixed31_32 f_audio; /* Audio rate (Hz) */ 116 int h_active; /* Active pixels per line */ 117 int h_blank; /* Blanking pixels per line */ 118 int bpc; /* Bits per component */ 119 int vic; /* Video Identification Code */ 120 121 enum hdmi_frl_pixel_encoding pixel_encoding; 122 123 bool compressed; /* set to true if DSC is enabled */ 124 bool bypass_hc_target_calc; /* debug only */ 125 bool allow_all_bpp; /* dsc_all_bpp */ 126 127 /* DSC parameters */ 128 int slices; 129 int slice_width; 130 struct fixed31_32 bpp_target; 131 int layout; 132 int acat; /* not supported */ 133 134 /* outputs */ 135 struct frl_dml_borrow_params borrow_params; 136 int average_tribyte_rate; 137 }; 138 139 /* Display Core Interfaces */ 140 struct dc_versions { 141 const char *dc_ver; 142 struct dmcu_version dmcu_version; 143 }; 144 145 enum dp_protocol_version { 146 DP_VERSION_1_4 = 0, 147 DP_VERSION_2_1, 148 DP_VERSION_UNKNOWN, 149 }; 150 151 enum dc_plane_type { 152 DC_PLANE_TYPE_INVALID, 153 DC_PLANE_TYPE_DCE_RGB, 154 DC_PLANE_TYPE_DCE_UNDERLAY, 155 DC_PLANE_TYPE_DCN_UNIVERSAL, 156 }; 157 158 // Sizes defined as multiples of 64KB 159 enum det_size { 160 DET_SIZE_DEFAULT = 0, 161 DET_SIZE_192KB = 3, 162 DET_SIZE_256KB = 4, 163 DET_SIZE_320KB = 5, 164 DET_SIZE_384KB = 6 165 }; 166 167 168 struct dc_plane_cap { 169 enum dc_plane_type type; 170 uint32_t per_pixel_alpha : 1; 171 struct { 172 uint32_t argb8888 : 1; 173 uint32_t nv12 : 1; 174 uint32_t fp16 : 1; 175 uint32_t p010 : 1; 176 uint32_t ayuv : 1; 177 } pixel_format_support; 178 // max upscaling factor x1000 179 // upscaling factors are always >= 1 180 // for example, 1080p -> 8K is 4.0, or 4000 raw value 181 struct { 182 uint32_t argb8888; 183 uint32_t nv12; 184 uint32_t fp16; 185 } max_upscale_factor; 186 // max downscale factor x1000 187 // downscale factors are always <= 1 188 // for example, 8K -> 1080p is 0.25, or 250 raw value 189 struct { 190 uint32_t argb8888; 191 uint32_t nv12; 192 uint32_t fp16; 193 } max_downscale_factor; 194 // minimal width/height 195 uint32_t min_width; 196 uint32_t min_height; 197 }; 198 199 /** 200 * DOC: color-management-caps 201 * 202 * **Color management caps (DPP and MPC)** 203 * 204 * Modules/color calculates various color operations which are translated to 205 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 206 * DCN1, every new generation comes with fairly major differences in color 207 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 208 * decide mapping to HW block based on logical capabilities. 209 */ 210 211 /** 212 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 213 * @srgb: RGB color space transfer func 214 * @bt2020: BT.2020 transfer func 215 * @gamma2_2: standard gamma 216 * @pq: perceptual quantizer transfer function 217 * @hlg: hybrid log–gamma transfer function 218 */ 219 struct rom_curve_caps { 220 uint16_t srgb : 1; 221 uint16_t bt2020 : 1; 222 uint16_t gamma2_2 : 1; 223 uint16_t pq : 1; 224 uint16_t hlg : 1; 225 }; 226 227 /** 228 * struct dpp_color_caps - color pipeline capabilities for display pipe and 229 * plane blocks 230 * 231 * @dcn_arch: all DCE generations treated the same 232 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 233 * just plain 256-entry lookup 234 * @icsc: input color space conversion 235 * @dgam_ram: programmable degamma LUT 236 * @post_csc: post color space conversion, before gamut remap 237 * @gamma_corr: degamma correction 238 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 239 * with MPC by setting mpc:shared_3d_lut flag 240 * @ogam_ram: programmable out/blend gamma LUT 241 * @ocsc: output color space conversion 242 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 243 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 244 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 245 * 246 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 247 */ 248 struct dpp_color_caps { 249 uint16_t dcn_arch : 1; 250 uint16_t input_lut_shared : 1; 251 uint16_t icsc : 1; 252 uint16_t dgam_ram : 1; 253 uint16_t post_csc : 1; 254 uint16_t gamma_corr : 1; 255 uint16_t hw_3d_lut : 1; 256 uint16_t ogam_ram : 1; 257 uint16_t ocsc : 1; 258 uint16_t dgam_rom_for_yuv : 1; 259 struct rom_curve_caps dgam_rom_caps; 260 struct rom_curve_caps ogam_rom_caps; 261 }; 262 263 /* Below structure is to describe the HW support for mem layout, extend support 264 range to match what OS could handle in the roadmap */ 265 struct lut3d_caps { 266 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 267 struct { 268 uint32_t swizzle_3d_rgb : 1; 269 uint32_t swizzle_3d_bgr : 1; 270 uint32_t linear_1d : 1; 271 } mem_layout_support; 272 struct { 273 uint32_t unorm_12msb : 1; 274 uint32_t unorm_12lsb : 1; 275 uint32_t float_fp1_5_10 : 1; 276 } mem_format_support; 277 struct { 278 uint32_t order_rgba : 1; 279 uint32_t order_bgra : 1; 280 } mem_pixel_order_support; 281 /*< size options are 9, 17, 33, 45, 65 */ 282 struct { 283 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 284 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 285 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 286 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 287 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 288 } lut_dim_caps; 289 }; 290 291 /** 292 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 293 * plane combined blocks 294 * 295 * @gamut_remap: color transformation matrix 296 * @ogam_ram: programmable out gamma LUT 297 * @ocsc: output color space conversion matrix 298 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 299 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 300 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 301 * instance 302 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 303 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 304 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 305 * @preblend: whether color manager supports preblend with MPC 306 */ 307 struct mpc_color_caps { 308 uint16_t gamut_remap : 1; 309 uint16_t ogam_ram : 1; 310 uint16_t ocsc : 1; 311 uint16_t num_3dluts : 3; 312 uint16_t num_rmcm_3dluts : 3; 313 uint16_t shared_3d_lut:1; 314 struct rom_curve_caps ogam_rom_caps; 315 struct lut3d_caps mcm_3d_lut_caps; 316 struct lut3d_caps rmcm_3d_lut_caps; 317 bool preblend; 318 }; 319 320 /** 321 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 322 * @dpp: color pipes caps for DPP 323 * @mpc: color pipes caps for MPC 324 */ 325 struct dc_color_caps { 326 struct dpp_color_caps dpp; 327 struct mpc_color_caps mpc; 328 }; 329 330 struct dc_dmub_caps { 331 bool psr; 332 bool mclk_sw; 333 bool subvp_psr; 334 bool gecc_enable; 335 uint8_t fams_ver; 336 bool aux_backlight_support; 337 }; 338 339 struct dc_scl_caps { 340 bool sharpener_support; 341 }; 342 343 struct dc_check_config { 344 /** 345 * max video plane width that can be safely assumed to be always 346 * supported by single DPP pipe. 347 */ 348 unsigned int max_optimizable_video_width; 349 bool enable_legacy_fast_update; 350 351 bool deferred_transition_state; 352 unsigned int transition_countdown_to_steady_state; 353 }; 354 355 struct dc_caps { 356 uint32_t max_streams; 357 uint32_t max_links; 358 uint32_t max_audios; 359 uint32_t max_slave_planes; 360 uint32_t max_slave_yuv_planes; 361 uint32_t max_slave_rgb_planes; 362 uint32_t max_planes; 363 uint32_t max_downscale_ratio; 364 uint32_t i2c_speed_in_khz; 365 uint32_t i2c_speed_in_khz_hdcp; 366 uint32_t dmdata_alloc_size; 367 unsigned int max_cursor_size; 368 unsigned int max_buffered_cursor_size; 369 unsigned int max_video_width; 370 unsigned int min_horizontal_blanking_period; 371 int linear_pitch_alignment; 372 bool dcc_const_color; 373 bool dynamic_audio; 374 bool is_apu; 375 bool dual_link_dvi; 376 bool post_blend_color_processing; 377 bool force_dp_tps4_for_cp2520; 378 bool disable_dp_clk_share; 379 bool psp_setup_panel_mode; 380 bool extended_aux_timeout_support; 381 bool dmcub_support; 382 bool zstate_support; 383 bool ips_support; 384 bool ips_v2_support; 385 uint32_t num_of_internal_disp; 386 enum dp_protocol_version max_dp_protocol_version; 387 bool hdmi_hpo; 388 unsigned int mall_size_per_mem_channel; 389 unsigned int mall_size_total; 390 unsigned int cursor_cache_size; 391 struct dc_plane_cap planes[MAX_PLANES]; 392 struct dc_color_caps color; 393 struct dc_dmub_caps dmub_caps; 394 bool dp_hpo; 395 bool dp_hdmi21_pcon_support; 396 bool edp_dsc_support; 397 bool vbios_lttpr_aware; 398 bool vbios_lttpr_enable; 399 bool fused_io_supported; 400 uint32_t max_otg_num; 401 uint32_t max_cab_allocation_bytes; 402 uint32_t cache_line_size; 403 uint32_t cache_num_ways; 404 uint16_t subvp_fw_processing_delay_us; 405 uint8_t subvp_drr_max_vblank_margin_us; 406 uint16_t subvp_prefetch_end_to_mall_start_us; 407 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 408 uint16_t subvp_pstate_allow_width_us; 409 uint16_t subvp_vertical_int_margin_us; 410 bool seamless_odm; 411 uint32_t max_v_total; 412 bool vtotal_limited_by_fp2; 413 uint32_t max_disp_clock_khz_at_vmin; 414 uint8_t subvp_drr_vblank_start_margin_us; 415 bool cursor_not_scaled; 416 bool dcmode_power_limits_present; 417 bool sequential_ono; 418 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 419 uint32_t dcc_plane_width_limit; 420 struct dc_scl_caps scl_caps; 421 uint8_t num_of_host_routers; 422 uint8_t num_of_dpias_per_host_router; 423 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 424 uint8_t max_odm_combine_factor; 425 }; 426 427 struct dc_bug_wa { 428 bool no_connect_phy_config; 429 bool dedcn20_305_wa; 430 bool skip_clock_update; 431 bool lt_early_cr_pattern; 432 struct { 433 uint8_t uclk : 1; 434 uint8_t fclk : 1; 435 uint8_t dcfclk : 1; 436 uint8_t dcfclk_ds: 1; 437 } clock_update_disable_mask; 438 bool skip_psr_ips_crtc_disable; 439 }; 440 struct dc_dcc_surface_param { 441 struct dc_size surface_size; 442 enum surface_pixel_format format; 443 unsigned int plane0_pitch; 444 struct dc_size plane1_size; 445 unsigned int plane1_pitch; 446 union { 447 enum swizzle_mode_values swizzle_mode; 448 enum swizzle_mode_addr3_values swizzle_mode_addr3; 449 }; 450 enum dc_scan_direction scan; 451 }; 452 453 struct dc_dcc_setting { 454 unsigned int max_compressed_blk_size; 455 unsigned int max_uncompressed_blk_size; 456 bool independent_64b_blks; 457 //These bitfields to be used starting with DCN 3.0 458 struct { 459 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 460 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 461 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 462 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 463 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 464 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 465 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 466 } dcc_controls; 467 }; 468 469 struct dc_surface_dcc_cap { 470 union { 471 struct { 472 struct dc_dcc_setting rgb; 473 } grph; 474 475 struct { 476 struct dc_dcc_setting luma; 477 struct dc_dcc_setting chroma; 478 } video; 479 }; 480 481 bool capable; 482 bool const_color_support; 483 }; 484 485 struct dc_static_screen_params { 486 struct { 487 bool force_trigger; 488 bool cursor_update; 489 bool surface_update; 490 bool overlay_update; 491 } triggers; 492 unsigned int num_frames; 493 }; 494 495 496 /* Surface update type is used by dc_update_surfaces_and_stream 497 * The update type is determined at the very beginning of the function based 498 * on parameters passed in and decides how much programming (or updating) is 499 * going to be done during the call. 500 * 501 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 502 * logical calculations or hardware register programming. This update MUST be 503 * ISR safe on windows. Currently fast update will only be used to flip surface 504 * address. 505 * 506 * UPDATE_TYPE_MED is used for slower updates which require significant hw 507 * re-programming however do not affect bandwidth consumption or clock 508 * requirements. At present, this is the level at which front end updates 509 * that do not require us to run bw_calcs happen. These are in/out transfer func 510 * updates, viewport offset changes, recout size changes and pixel depth changes. 511 * This update can be done at ISR, but we want to minimize how often this happens. 512 * 513 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 514 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 515 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 516 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 517 * a full update. This cannot be done at ISR level and should be a rare event. 518 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 519 * underscan we don't expect to see this call at all. 520 */ 521 522 enum dc_update_type { 523 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 524 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 525 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 526 }; 527 528 enum dc_lock_descriptor { 529 LOCK_DESCRIPTOR_NONE = 0x0, 530 LOCK_DESCRIPTOR_STREAM = 0x1, 531 LOCK_DESCRIPTOR_LINK = 0x2, 532 LOCK_DESCRIPTOR_GLOBAL = 0x4, 533 LOCK_DESCRIPTOR_PROBE = 0x8, 534 }; 535 536 struct dc_update_descriptor { 537 enum dc_update_type update_type; 538 enum dc_lock_descriptor lock_descriptor; 539 }; 540 541 /* Forward declaration*/ 542 struct dc; 543 struct dc_plane_state; 544 struct dc_state; 545 546 struct dc_cap_funcs { 547 bool (*get_dcc_compression_cap)(const struct dc *dc, 548 const struct dc_dcc_surface_param *input, 549 struct dc_surface_dcc_cap *output); 550 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 551 }; 552 553 struct link_training_settings; 554 555 union allow_lttpr_non_transparent_mode { 556 struct { 557 bool DP1_4A : 1; 558 bool DP2_0 : 1; 559 } bits; 560 unsigned char raw; 561 }; 562 /* Structure to hold configuration flags set by dm at dc creation. */ 563 struct dc_config { 564 bool gpu_vm_support; 565 bool disable_disp_pll_sharing; 566 bool fbc_support; 567 bool disable_fractional_pwm; 568 bool allow_seamless_boot_optimization; 569 bool seamless_boot_edp_requested; 570 bool edp_not_connected; 571 bool edp_no_power_sequencing; 572 bool force_enum_edp; 573 bool forced_clocks; 574 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 575 bool multi_mon_pp_mclk_switch; 576 bool disable_dmcu; 577 bool allow_4to1MPC; 578 bool enable_windowed_mpo_odm; 579 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 580 uint32_t allow_edp_hotplug_detection; 581 bool skip_riommu_prefetch_wa; 582 bool clamp_min_dcfclk; 583 uint64_t vblank_alignment_dto_params; 584 uint8_t vblank_alignment_max_frame_time_diff; 585 bool is_asymmetric_memory; 586 bool is_single_rank_dimm; 587 bool is_vmin_only_asic; 588 bool use_spl; 589 bool prefer_easf; 590 bool use_pipe_ctx_sync_logic; 591 int smart_mux_version; 592 bool ignore_dpref_ss; 593 bool enable_mipi_converter_optimization; 594 bool enable_frl; 595 bool force_hdmi21_frl_enc_enable; 596 bool use_default_clock_table; 597 bool force_bios_enable_lttpr; 598 uint8_t force_bios_fixed_vs; 599 unsigned int sdpif_request_limit_words_per_umc; 600 bool dc_mode_clk_limit_support; 601 bool EnableMinDispClkODM; 602 bool enable_auto_dpm_test_logs; 603 unsigned int disable_ips; 604 unsigned int disable_ips_rcg; 605 unsigned int disable_ips_in_vpb; 606 bool disable_ips_in_dpms_off; 607 bool usb4_bw_alloc_support; 608 bool allow_0_dtb_clk; 609 bool use_assr_psp_message; 610 bool support_edp0_on_dp1; 611 unsigned int enable_fpo_flicker_detection; 612 bool disable_hbr_audio_dp2; 613 bool consolidated_dpia_dp_lt; 614 bool set_pipe_unlock_order; 615 bool enable_dpia_pre_training; 616 bool unify_link_enc_assignment; 617 bool enable_cursor_offload; 618 bool dp_connector_no_native_i2c; 619 bool frame_update_cmd_version2; 620 struct spl_sharpness_range dcn_sharpness_range; 621 struct spl_sharpness_range dcn_override_sharpness_range; 622 bool no_native422_support; 623 }; 624 625 enum visual_confirm { 626 VISUAL_CONFIRM_DISABLE = 0, 627 VISUAL_CONFIRM_SURFACE = 1, 628 VISUAL_CONFIRM_HDR = 2, 629 VISUAL_CONFIRM_MPCTREE = 4, 630 VISUAL_CONFIRM_PSR = 5, 631 VISUAL_CONFIRM_SWAPCHAIN = 6, 632 VISUAL_CONFIRM_FAMS = 7, 633 VISUAL_CONFIRM_SWIZZLE = 9, 634 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 635 VISUAL_CONFIRM_REPLAY = 12, 636 VISUAL_CONFIRM_SUBVP = 14, 637 VISUAL_CONFIRM_ABM = 15, 638 VISUAL_CONFIRM_MCLK_SWITCH = 16, 639 VISUAL_CONFIRM_FAMS2 = 19, 640 VISUAL_CONFIRM_HW_CURSOR = 20, 641 VISUAL_CONFIRM_VABC = 21, 642 VISUAL_CONFIRM_DCC = 22, 643 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, 644 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 645 }; 646 647 enum dc_psr_power_opts { 648 psr_power_opt_invalid = 0x0, 649 psr_power_opt_smu_opt_static_screen = 0x1, 650 psr_power_opt_z10_static_screen = 0x10, 651 psr_power_opt_ds_disable_allow = 0x100, 652 }; 653 654 enum dml_hostvm_override_opts { 655 DML_HOSTVM_NO_OVERRIDE = 0x0, 656 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 657 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 658 }; 659 660 enum dc_replay_power_opts { 661 replay_power_opt_invalid = 0x0, 662 replay_power_opt_smu_opt_static_screen = 0x1, 663 replay_power_opt_z10_static_screen = 0x10, 664 }; 665 666 enum dcc_option { 667 DCC_ENABLE = 0, 668 DCC_DISABLE = 1, 669 DCC_HALF_REQ_DISALBE = 2, 670 }; 671 672 enum in_game_fams_config { 673 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 674 INGAME_FAMS_DISABLE, // disable in-game fams 675 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 676 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 677 }; 678 679 /** 680 * enum pipe_split_policy - Pipe split strategy supported by DCN 681 * 682 * This enum is used to define the pipe split policy supported by DCN. By 683 * default, DC favors MPC_SPLIT_DYNAMIC. 684 */ 685 enum pipe_split_policy { 686 /** 687 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 688 * pipe in order to bring the best trade-off between performance and 689 * power consumption. This is the recommended option. 690 */ 691 MPC_SPLIT_DYNAMIC = 0, 692 693 /** 694 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 695 * try any sort of split optimization. 696 */ 697 MPC_SPLIT_AVOID = 1, 698 699 /** 700 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 701 * optimize the pipe utilization when using a single display; if the 702 * user connects to a second display, DC will avoid pipe split. 703 */ 704 MPC_SPLIT_AVOID_MULT_DISP = 2, 705 }; 706 707 enum wm_report_mode { 708 WM_REPORT_DEFAULT = 0, 709 WM_REPORT_OVERRIDE = 1, 710 }; 711 enum dtm_pstate{ 712 dtm_level_p0 = 0,/*highest voltage*/ 713 dtm_level_p1, 714 dtm_level_p2, 715 dtm_level_p3, 716 dtm_level_p4,/*when active_display_count = 0*/ 717 }; 718 719 enum dcn_pwr_state { 720 DCN_PWR_STATE_UNKNOWN = -1, 721 DCN_PWR_STATE_MISSION_MODE = 0, 722 DCN_PWR_STATE_LOW_POWER = 3, 723 }; 724 725 enum dcn_zstate_support_state { 726 DCN_ZSTATE_SUPPORT_UNKNOWN, 727 DCN_ZSTATE_SUPPORT_ALLOW, 728 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 729 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 730 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 731 DCN_ZSTATE_SUPPORT_DISALLOW, 732 }; 733 734 /* 735 * struct dc_clocks - DC pipe clocks 736 * 737 * For any clocks that may differ per pipe only the max is stored in this 738 * structure 739 */ 740 struct dc_clocks { 741 int dispclk_khz; 742 int actual_dispclk_khz; 743 int dppclk_khz; 744 int actual_dppclk_khz; 745 int disp_dpp_voltage_level_khz; 746 int dcfclk_khz; 747 int socclk_khz; 748 int dcfclk_deep_sleep_khz; 749 int fclk_khz; 750 int phyclk_khz; 751 int dramclk_khz; 752 bool p_state_change_support; 753 enum dcn_zstate_support_state zstate_support; 754 bool dtbclk_en; 755 int ref_dtbclk_khz; 756 bool fclk_p_state_change_support; 757 enum dcn_pwr_state pwr_state; 758 /* 759 * Elements below are not compared for the purposes of 760 * optimization required 761 */ 762 763 /* 764 * @cstate_allow 765 * 766 * DCN's DF C-state vote as last successfully acknowledged by PMFW. 767 * false = DCN does NOT permit DF C-state; 768 * true = DCN permits DF C-state; 769 */ 770 bool cstate_allow; 771 bool prev_p_state_change_support; 772 bool fclk_prev_p_state_change_support; 773 int num_ways; 774 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 775 776 /* 777 * @fw_based_mclk_switching 778 * 779 * DC has a mechanism that leverage the variable refresh rate to switch 780 * memory clock in cases that we have a large latency to achieve the 781 * memory clock change and a short vblank window. DC has some 782 * requirements to enable this feature, and this field describes if the 783 * system support or not such a feature. 784 */ 785 bool fw_based_mclk_switching; 786 bool fw_based_mclk_switching_shut_down; 787 int prev_num_ways; 788 enum dtm_pstate dtm_level; 789 int max_supported_dppclk_khz; 790 int max_supported_dispclk_khz; 791 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 792 int bw_dispclk_khz; 793 int idle_dramclk_khz; 794 int idle_fclk_khz; 795 int subvp_prefetch_dramclk_khz; 796 int subvp_prefetch_fclk_khz; 797 798 /* Stutter efficiency is technically not clock values 799 * but stored here so the values are part of the update_clocks call similar to num_ways 800 * Efficiencies are stored as percentage (0-100) 801 */ 802 struct { 803 uint8_t base_efficiency; //LP1 804 uint8_t low_power_efficiency; //LP2 805 uint8_t z8_stutter_efficiency; 806 int z8_stutter_period; 807 } stutter_efficiency; 808 }; 809 810 struct dc_bw_validation_profile { 811 bool enable; 812 813 unsigned long long total_ticks; 814 unsigned long long voltage_level_ticks; 815 unsigned long long watermark_ticks; 816 unsigned long long rq_dlg_ticks; 817 818 unsigned long long total_count; 819 unsigned long long skip_fast_count; 820 unsigned long long skip_pass_count; 821 unsigned long long skip_fail_count; 822 }; 823 824 #define BW_VAL_TRACE_SETUP() \ 825 unsigned long long end_tick = 0; \ 826 unsigned long long voltage_level_tick = 0; \ 827 unsigned long long watermark_tick = 0; \ 828 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 829 dm_get_timestamp(dc->ctx) : 0 830 831 #define BW_VAL_TRACE_COUNT() \ 832 if (dc->debug.bw_val_profile.enable) \ 833 dc->debug.bw_val_profile.total_count++ 834 835 #define BW_VAL_TRACE_SKIP(status) \ 836 if (dc->debug.bw_val_profile.enable) { \ 837 if (!voltage_level_tick) \ 838 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 839 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 840 } 841 842 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 843 if (dc->debug.bw_val_profile.enable) \ 844 voltage_level_tick = dm_get_timestamp(dc->ctx) 845 846 #define BW_VAL_TRACE_END_WATERMARKS() \ 847 if (dc->debug.bw_val_profile.enable) \ 848 watermark_tick = dm_get_timestamp(dc->ctx) 849 850 #define BW_VAL_TRACE_FINISH() \ 851 if (dc->debug.bw_val_profile.enable) { \ 852 end_tick = dm_get_timestamp(dc->ctx); \ 853 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 854 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 855 if (watermark_tick) { \ 856 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 857 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 858 } \ 859 } 860 861 union mem_low_power_enable_options { 862 struct { 863 bool vga: 1; 864 bool i2c: 1; 865 bool dmcu: 1; 866 bool dscl: 1; 867 bool cm: 1; 868 bool mpc: 1; 869 bool optc: 1; 870 bool vpg: 1; 871 bool afmt: 1; 872 } bits; 873 uint32_t u32All; 874 }; 875 876 union root_clock_optimization_options { 877 struct { 878 bool dpp: 1; 879 bool dsc: 1; 880 bool hdmistream: 1; 881 bool hdmichar: 1; 882 bool dpstream: 1; 883 bool symclk32_se: 1; 884 bool symclk32_le: 1; 885 bool symclk_fe: 1; 886 bool physymclk: 1; 887 bool dpiasymclk: 1; 888 uint32_t reserved: 22; 889 } bits; 890 uint32_t u32All; 891 }; 892 893 union fine_grain_clock_gating_enable_options { 894 struct { 895 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 896 bool dchub : 1; /* Display controller hub */ 897 bool dchubbub : 1; 898 bool dpp : 1; /* Display pipes and planes */ 899 bool opp : 1; /* Output pixel processing */ 900 bool optc : 1; /* Output pipe timing combiner */ 901 bool dio : 1; /* Display output */ 902 bool dwb : 1; /* Display writeback */ 903 bool mmhubbub : 1; /* Multimedia hub */ 904 bool dmu : 1; /* Display core management unit */ 905 bool az : 1; /* Azalia */ 906 bool dchvm : 1; 907 bool dsc : 1; /* Display stream compression */ 908 909 uint32_t reserved : 19; 910 } bits; 911 uint32_t u32All; 912 }; 913 914 enum pg_hw_pipe_resources { 915 PG_HUBP = 0, 916 PG_DPP, 917 PG_DSC, 918 PG_MPCC, 919 PG_OPP, 920 PG_OPTC, 921 PG_DPSTREAM, 922 PG_HDMISTREAM, 923 PG_PHYSYMCLK, 924 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 925 }; 926 927 enum pg_hw_resources { 928 PG_DCCG = 0, 929 PG_DCIO, 930 PG_DIO, 931 PG_DCHUBBUB, 932 PG_DCHVM, 933 PG_DWB, 934 PG_HPO, 935 PG_DCOH, 936 PG_HW_RESOURCES_NUM_ELEMENT 937 }; 938 939 struct pg_block_update { 940 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 941 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 942 }; 943 944 union dpia_debug_options { 945 struct { 946 uint32_t disable_dpia:1; /* bit 0 */ 947 uint32_t force_non_lttpr:1; /* bit 1 */ 948 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 949 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 950 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 951 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 952 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 953 uint32_t reserved:25; 954 } bits; 955 uint32_t raw; 956 }; 957 958 /* AUX wake work around options 959 * 0: enable/disable work around 960 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 961 * 15-2: reserved 962 * 31-16: timeout in ms 963 */ 964 union aux_wake_wa_options { 965 struct { 966 uint32_t enable_wa : 1; 967 uint32_t use_default_timeout : 1; 968 uint32_t rsvd: 14; 969 uint32_t timeout_ms : 16; 970 } bits; 971 uint32_t raw; 972 }; 973 974 struct dc_debug_data { 975 uint32_t ltFailCount; 976 uint32_t i2cErrorCount; 977 uint32_t auxErrorCount; 978 struct pipe_topology_history topology_history; 979 }; 980 981 struct dc_phy_addr_space_config { 982 struct { 983 uint64_t start_addr; 984 uint64_t end_addr; 985 uint64_t fb_top; 986 uint64_t fb_offset; 987 uint64_t fb_base; 988 uint64_t agp_top; 989 uint64_t agp_bot; 990 uint64_t agp_base; 991 } system_aperture; 992 993 struct { 994 uint64_t page_table_start_addr; 995 uint64_t page_table_end_addr; 996 uint64_t page_table_base_addr; 997 bool base_addr_is_mc_addr; 998 } gart_config; 999 1000 bool valid; 1001 bool is_hvm_enabled; 1002 uint64_t page_table_default_page_addr; 1003 }; 1004 1005 struct dc_virtual_addr_space_config { 1006 uint64_t page_table_base_addr; 1007 uint64_t page_table_start_addr; 1008 uint64_t page_table_end_addr; 1009 uint32_t page_table_block_size_in_bytes; 1010 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 1011 }; 1012 1013 struct dc_bounding_box_overrides { 1014 unsigned int sr_exit_time_ns; 1015 unsigned int sr_enter_plus_exit_time_ns; 1016 unsigned int sr_exit_z8_time_ns; 1017 unsigned int sr_enter_plus_exit_z8_time_ns; 1018 unsigned int urgent_latency_ns; 1019 unsigned int percent_of_ideal_drambw; 1020 unsigned int dram_clock_change_latency_ns; 1021 unsigned int dummy_clock_change_latency_ns; 1022 unsigned int fclk_clock_change_latency_ns; 1023 /* This forces a hard min on the DCFCLK we use 1024 * for DML. Unlike the debug option for forcing 1025 * DCFCLK, this override affects watermark calculations 1026 */ 1027 unsigned int min_dcfclk_mhz; 1028 }; 1029 1030 struct dc_qos_info { 1031 uint32_t qos_bandwidth_lb_in_mbps; 1032 uint32_t calculated_avg_bw_in_mbps; 1033 uint32_t qos_max_latency_ub_in_ns; 1034 uint32_t qos_avg_latency_ub_in_ns; 1035 uint32_t dcn_bandwidth_ub_in_mbps; 1036 uint32_t qos_max_bw_budget_in_mbps; 1037 }; 1038 1039 struct dc_state; 1040 struct resource_pool; 1041 struct dce_hwseq; 1042 struct link_service; 1043 1044 /* 1045 * struct dc_debug_options - DC debug struct 1046 * 1047 * This struct provides a simple mechanism for developers to change some 1048 * configurations, enable/disable features, and activate extra debug options. 1049 * This can be very handy to narrow down whether some specific feature is 1050 * causing an issue or not. 1051 */ 1052 struct dc_debug_options { 1053 bool disable_dsc; 1054 enum visual_confirm visual_confirm; 1055 unsigned int visual_confirm_rect_height; 1056 1057 bool sanity_checks; 1058 bool max_disp_clk; 1059 bool surface_trace; 1060 bool clock_trace; 1061 bool validation_trace; 1062 bool bandwidth_calcs_trace; 1063 int max_downscale_src_width; 1064 1065 /* stutter efficiency related */ 1066 bool disable_stutter; 1067 bool use_max_lb; 1068 enum dcc_option disable_dcc; 1069 1070 /* 1071 * @pipe_split_policy: Define which pipe split policy is used by the 1072 * display core. 1073 */ 1074 enum pipe_split_policy pipe_split_policy; 1075 bool force_single_disp_pipe_split; 1076 bool voltage_align_fclk; 1077 bool disable_min_fclk; 1078 1079 bool hdcp_lc_force_fw_enable; 1080 bool hdcp_lc_enable_sw_fallback; 1081 1082 bool disable_dfs_bypass; 1083 bool disable_dpp_power_gate; 1084 bool disable_hubp_power_gate; 1085 bool disable_dsc_power_gate; 1086 bool disable_optc_power_gate; 1087 bool disable_hpo_power_gate; 1088 bool disable_io_clk_power_gate; 1089 bool disable_mem_power_gate; 1090 bool disable_dio_power_gate; 1091 unsigned int dsc_min_slice_height_override; 1092 unsigned int dsc_bpp_increment_div; 1093 bool disable_pplib_wm_range; 1094 enum wm_report_mode pplib_wm_report_mode; 1095 unsigned int min_disp_clk_khz; 1096 unsigned int min_dpp_clk_khz; 1097 unsigned int min_dram_clk_khz; 1098 unsigned int sr_exit_time_dpm0_ns; 1099 unsigned int sr_enter_plus_exit_time_dpm0_ns; 1100 unsigned int sr_exit_time_ns; 1101 unsigned int sr_enter_plus_exit_time_ns; 1102 unsigned int sr_exit_z8_time_ns; 1103 unsigned int sr_enter_plus_exit_z8_time_ns; 1104 unsigned int urgent_latency_ns; 1105 uint32_t underflow_assert_delay_us; 1106 unsigned int percent_of_ideal_drambw; 1107 unsigned int dram_clock_change_latency_ns; 1108 bool optimized_watermark; 1109 int always_scale; 1110 bool disable_pplib_clock_request; 1111 bool disable_clock_gate; 1112 bool disable_mem_low_power; 1113 bool pstate_enabled; 1114 bool disable_dmcu; 1115 bool force_abm_enable; 1116 bool disable_stereo_support; 1117 bool vsr_support; 1118 bool performance_trace; 1119 bool az_endpoint_mute_only; 1120 bool always_use_regamma; 1121 bool recovery_enabled; 1122 bool avoid_vbios_exec_table; 1123 bool scl_reset_length10; 1124 bool hdmi20_disable; 1125 bool skip_detection_link_training; 1126 uint32_t edid_read_retry_times; 1127 1128 uint8_t force_odm_combine; //bit vector based on otg inst 1129 uint8_t seamless_boot_odm_combine; 1130 uint8_t force_odm_combine_4to1; //bit vector based on otg inst 1131 1132 unsigned int minimum_z8_residency_time; 1133 unsigned int minimum_z10_residency_time; 1134 bool disable_z9_mpc; 1135 unsigned int force_fclk_khz; 1136 bool enable_tri_buf; 1137 bool ips_disallow_entry; 1138 bool disable_idle_power_optimizations; 1139 unsigned int mall_size_override; 1140 unsigned int mall_additional_timer_percent; 1141 bool mall_error_as_fatal; 1142 bool dmub_command_table; /* for testing only */ 1143 struct dc_bw_validation_profile bw_val_profile; 1144 bool disable_fec; 1145 bool disable_48mhz_pwrdwn; 1146 /* This forces a hard min on the DCFCLK requested to SMU/PP 1147 * watermarks are not affected. 1148 */ 1149 unsigned int force_min_dcfclk_mhz; 1150 int dwb_fi_phase; 1151 bool disable_timing_sync; 1152 bool cm_in_bypass; 1153 int force_clock_mode;/*every mode change.*/ 1154 1155 bool disable_dram_clock_change_vactive_support; 1156 bool validate_dml_output; 1157 bool enable_dmcub_surface_flip; 1158 bool usbc_combo_phy_reset_wa; 1159 bool force_fva; 1160 int max_frl_rate; 1161 unsigned int force_frl_rate; 1162 bool ignore_ffe; 1163 unsigned int select_ffe; 1164 unsigned int limit_ffe; 1165 bool force_frl_always; 1166 bool force_frl_dsc; 1167 bool force_frl_max; 1168 bool apply_vsdb_rcc_wa; 1169 bool enable_hdmi_idcc; 1170 1171 bool enable_dram_clock_change_one_display_vactive; 1172 /* TODO - remove once tested */ 1173 bool legacy_dp2_lt; 1174 bool set_mst_en_for_sst; 1175 bool disable_uhbr; 1176 bool force_dp2_lt_fallback_method; 1177 bool ignore_cable_id; 1178 union mem_low_power_enable_options enable_mem_low_power; 1179 union root_clock_optimization_options root_clock_optimization; 1180 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1181 bool hpo_optimization; 1182 bool force_vblank_alignment; 1183 1184 /* Enable dmub aux for legacy ddc */ 1185 bool enable_dmub_aux_for_legacy_ddc; 1186 bool disable_fams; 1187 enum in_game_fams_config disable_fams_gaming; 1188 /* FEC/PSR1 sequence enable delay in 100us */ 1189 uint8_t fec_enable_delay_in100us; 1190 bool enable_driver_sequence_debug; 1191 enum det_size crb_alloc_policy; 1192 unsigned int crb_alloc_policy_min_disp_count; 1193 bool disable_z10; 1194 bool enable_z9_disable_interface; 1195 bool psr_skip_crtc_disable; 1196 uint32_t ips_skip_crtc_disable_mask; 1197 union dpia_debug_options dpia_debug; 1198 bool disable_fixed_vs_aux_timeout_wa; 1199 uint32_t fixed_vs_aux_delay_config_wa; 1200 bool force_disable_subvp; 1201 bool force_subvp_mclk_switch; 1202 bool allow_sw_cursor_fallback; 1203 unsigned int force_subvp_num_ways; 1204 unsigned int force_mall_ss_num_ways; 1205 bool alloc_extra_way_for_cursor; 1206 uint32_t subvp_extra_lines; 1207 bool disable_force_pstate_allow_on_hw_release; 1208 bool force_usr_allow; 1209 /* uses value at boot and disables switch */ 1210 bool disable_dtb_ref_clk_switch; 1211 bool extended_blank_optimization; 1212 union aux_wake_wa_options aux_wake_wa; 1213 uint32_t mst_start_top_delay; 1214 uint8_t psr_power_use_phy_fsm; 1215 enum dml_hostvm_override_opts dml_hostvm_override; 1216 bool dml_disallow_alternate_prefetch_modes; 1217 bool use_legacy_soc_bb_mechanism; 1218 bool exit_idle_opt_for_cursor_updates; 1219 bool using_dml2; 1220 bool enable_single_display_2to1_odm_policy; 1221 bool enable_double_buffered_dsc_pg_support; 1222 bool enable_dp_dig_pixel_rate_div_policy; 1223 bool using_dml21; 1224 enum lttpr_mode lttpr_mode_override; 1225 unsigned int dsc_delay_factor_wa_x1000; 1226 unsigned int min_prefetch_in_strobe_ns; 1227 bool disable_unbounded_requesting; 1228 bool dig_fifo_off_in_blank; 1229 bool override_dispclk_programming; 1230 bool otg_crc_db; 1231 bool disallow_dispclk_dppclk_ds; 1232 bool disable_fpo_optimizations; 1233 bool support_eDP1_5; 1234 uint32_t fpo_vactive_margin_us; 1235 bool disable_fpo_vactive; 1236 bool disable_boot_optimizations; 1237 bool override_odm_optimization; 1238 bool minimize_dispclk_using_odm; 1239 bool disable_subvp_high_refresh; 1240 bool disable_dp_plus_plus_wa; 1241 uint32_t fpo_vactive_min_active_margin_us; 1242 uint32_t fpo_vactive_max_blank_us; 1243 bool enable_hpo_pg_support; 1244 bool disable_dc_mode_overwrite; 1245 bool replay_skip_crtc_disabled; 1246 bool ignore_pg;/*do nothing, let pmfw control it*/ 1247 bool psp_disabled_wa; 1248 unsigned int ips2_eval_delay_us; 1249 unsigned int ips2_entry_delay_us; 1250 bool optimize_ips_handshake; 1251 bool disable_dmub_reallow_idle; 1252 bool disable_timeout; 1253 bool disable_extblankadj; 1254 bool enable_idle_reg_checks; 1255 unsigned int static_screen_wait_frames; 1256 uint32_t pwm_freq; 1257 bool force_chroma_subsampling_1tap; 1258 unsigned int dcc_meta_propagation_delay_us; 1259 bool disable_422_left_edge_pixel; 1260 bool dml21_force_pstate_method; 1261 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1262 uint32_t dml21_disable_pstate_method_mask; 1263 union fw_assisted_mclk_switch_version fams_version; 1264 union dmub_fams2_global_feature_config fams2_config; 1265 unsigned int force_cositing; 1266 unsigned int disable_spl; 1267 unsigned int force_easf; 1268 unsigned int force_sharpness; 1269 unsigned int force_sharpness_level; 1270 unsigned int force_lls; 1271 bool notify_dpia_hr_bw; 1272 bool enable_ips_visual_confirm; 1273 unsigned int sharpen_policy; 1274 unsigned int scale_to_sharpness_policy; 1275 unsigned int enable_oled_edp_power_up_opt; 1276 bool enable_hblank_borrow; 1277 bool force_subvp_df_throttle; 1278 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1279 bool enable_pg_cntl_debug_logs; 1280 unsigned int auxless_alpm_lfps_setup_ns; 1281 unsigned int auxless_alpm_lfps_period_ns; 1282 unsigned int auxless_alpm_lfps_silence_ns; 1283 unsigned int auxless_alpm_lfps_t1t2_us; 1284 short auxless_alpm_lfps_t1t2_offset_us; 1285 bool disable_stutter_for_wm_program; 1286 bool enable_block_sequence_programming; 1287 uint32_t custom_psp_footer_size; 1288 bool disable_deferred_minimal_transitions; 1289 unsigned int num_fast_flips_to_steady_state_override; 1290 bool enable_dmu_recovery; 1291 unsigned int force_vmin_threshold; 1292 bool enable_otg_frame_sync_pwa; 1293 unsigned int min_deep_sleep_dcfclk_khz; 1294 unsigned int force_odm2to1_for_edp_pixclk_mhz; 1295 bool enable_replay_esd_recovery; 1296 uint8_t iommu_mismatch_temp_wka; 1297 bool disable_dynamic_expansion_for_test_pattern; 1298 uint32_t dml21_custom_derate_num_dpms; 1299 uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL]; 1300 }; 1301 1302 1303 /* Generic structure that can be used to query properties of DC. More fields 1304 * can be added as required. 1305 */ 1306 struct dc_current_properties { 1307 unsigned int cursor_size_limit; 1308 }; 1309 1310 enum frame_buffer_mode { 1311 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1312 FRAME_BUFFER_MODE_ZFB_ONLY, 1313 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1314 } ; 1315 1316 struct dchub_init_data { 1317 int64_t zfb_phys_addr_base; 1318 int64_t zfb_mc_base_addr; 1319 uint64_t zfb_size_in_byte; 1320 enum frame_buffer_mode fb_mode; 1321 bool dchub_initialzied; 1322 bool dchub_info_valid; 1323 }; 1324 1325 struct dml2_soc_bb; 1326 1327 struct dc_init_data { 1328 struct hw_asic_id asic_id; 1329 void *driver; /* ctx */ 1330 struct cgs_device *cgs_device; 1331 struct dc_bounding_box_overrides bb_overrides; 1332 1333 int num_virtual_links; 1334 /* 1335 * If 'vbios_override' not NULL, it will be called instead 1336 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1337 */ 1338 struct dc_bios *vbios_override; 1339 enum dce_environment dce_environment; 1340 1341 struct dmub_offload_funcs *dmub_if; 1342 1343 struct dc_config flags; 1344 uint64_t log_mask; 1345 1346 struct dpcd_vendor_signature vendor_signature; 1347 bool force_smu_not_present; 1348 /* 1349 * IP offset for run time initializaion of register addresses 1350 * 1351 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1352 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1353 * before them. 1354 */ 1355 uint32_t *dcn_reg_offsets; 1356 uint32_t *nbio_reg_offsets; 1357 uint32_t *clk_reg_offsets; 1358 void *bb_from_dmub; 1359 }; 1360 1361 struct dc_callback_init { 1362 struct cp_psp cp_psp; 1363 }; 1364 1365 struct dc *dc_create(const struct dc_init_data *init_params); 1366 void dc_hardware_init(struct dc *dc); 1367 1368 int dc_get_vmid_use_vector(struct dc *dc); 1369 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1370 /* Returns the number of vmids supported */ 1371 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1372 void dc_init_callbacks(struct dc *dc, 1373 const struct dc_callback_init *init_params); 1374 void dc_deinit_callbacks(struct dc *dc); 1375 void dc_destroy(struct dc **dc); 1376 1377 /* Surface Interfaces */ 1378 1379 enum { 1380 TRANSFER_FUNC_POINTS = 1025 1381 }; 1382 1383 struct dc_hdr_static_metadata { 1384 /* display chromaticities and white point in units of 0.00001 */ 1385 unsigned int chromaticity_green_x; 1386 unsigned int chromaticity_green_y; 1387 unsigned int chromaticity_blue_x; 1388 unsigned int chromaticity_blue_y; 1389 unsigned int chromaticity_red_x; 1390 unsigned int chromaticity_red_y; 1391 unsigned int chromaticity_white_point_x; 1392 unsigned int chromaticity_white_point_y; 1393 1394 uint32_t min_luminance; 1395 uint32_t max_luminance; 1396 uint32_t maximum_content_light_level; 1397 uint32_t maximum_frame_average_light_level; 1398 }; 1399 1400 enum dc_transfer_func_type { 1401 TF_TYPE_PREDEFINED, 1402 TF_TYPE_DISTRIBUTED_POINTS, 1403 TF_TYPE_BYPASS, 1404 TF_TYPE_HWPWL 1405 }; 1406 1407 struct dc_transfer_func_distributed_points { 1408 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1409 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1410 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1411 1412 uint16_t end_exponent; 1413 uint16_t x_point_at_y1_red; 1414 uint16_t x_point_at_y1_green; 1415 uint16_t x_point_at_y1_blue; 1416 }; 1417 1418 enum dc_transfer_func_predefined { 1419 TRANSFER_FUNCTION_SRGB, 1420 TRANSFER_FUNCTION_BT709, 1421 TRANSFER_FUNCTION_PQ, 1422 TRANSFER_FUNCTION_LINEAR, 1423 TRANSFER_FUNCTION_UNITY, 1424 TRANSFER_FUNCTION_HLG, 1425 TRANSFER_FUNCTION_HLG12, 1426 TRANSFER_FUNCTION_GAMMA22, 1427 TRANSFER_FUNCTION_GAMMA24, 1428 TRANSFER_FUNCTION_GAMMA26 1429 }; 1430 1431 1432 struct dc_transfer_func { 1433 struct kref refcount; 1434 enum dc_transfer_func_type type; 1435 enum dc_transfer_func_predefined tf; 1436 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1437 uint32_t sdr_ref_white_level; 1438 union { 1439 struct pwl_params pwl; 1440 struct dc_transfer_func_distributed_points tf_pts; 1441 }; 1442 }; 1443 1444 1445 union dc_3dlut_state { 1446 struct { 1447 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1448 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1449 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1450 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1451 uint32_t mpc_rmu1_mux:4; 1452 uint32_t mpc_rmu2_mux:4; 1453 uint32_t reserved:15; 1454 } bits; 1455 uint32_t raw; 1456 }; 1457 1458 1459 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1460 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1461 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1462 1463 struct lut_rgb { 1464 uint16_t b; 1465 uint16_t g; 1466 uint16_t r; 1467 uint16_t padding; 1468 }; 1469 1470 //this structure maps directly to how the lut will read it from memory 1471 struct lut_mem_mapping { 1472 union { 1473 //NATIVE MODE 1, 2 1474 //RGB layout [b][g][r] //red is 128 byte aligned 1475 //BGR layout [r][g][b] //blue is 128 byte aligned 1476 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1477 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1478 1479 //TRANSFORMED 1480 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1481 }; 1482 uint16_t size; 1483 }; 1484 1485 struct dc_rmcm_3dlut { 1486 bool isInUse; 1487 const struct dc_stream_state *stream; 1488 uint8_t protection_bits; 1489 }; 1490 1491 struct dc_3dlut { 1492 struct kref refcount; 1493 struct tetrahedral_params lut_3d; 1494 struct fixed31_32 hdr_multiplier; 1495 union dc_3dlut_state state; 1496 }; 1497 1498 /* 3DLUT DMA (Fast Load) params */ 1499 struct dc_3dlut_dma { 1500 struct dc_plane_address addr; 1501 enum dc_cm_lut_swizzle swizzle; 1502 enum dc_cm_lut_pixel_format format; 1503 uint16_t bias; /* FP1.5.10 */ 1504 uint16_t scale; /* FP1.5.10 */ 1505 enum dc_cm_lut_size size; 1506 }; 1507 1508 /* color manager */ 1509 union dc_plane_cm_flags { 1510 unsigned int all; 1511 struct { 1512 unsigned int shaper_enable : 1; 1513 unsigned int lut3d_enable : 1; 1514 unsigned int blend_enable : 1; 1515 /* whether legacy (lut3d_func) or DMA is valid */ 1516 unsigned int lut3d_dma_enable : 1; 1517 /* RMCM lut to be used instead of MCM */ 1518 unsigned int rmcm_enable : 1; 1519 unsigned int reserved: 27; 1520 } bits; 1521 }; 1522 1523 struct dc_plane_cm { 1524 struct kref refcount; 1525 struct dc_transfer_func shaper_func; 1526 union { 1527 struct dc_3dlut lut3d_func; 1528 struct dc_3dlut_dma lut3d_dma; 1529 }; 1530 struct dc_transfer_func blend_func; 1531 union dc_plane_cm_flags flags; 1532 }; 1533 1534 /* 1535 * This structure is filled in by dc_surface_get_status and contains 1536 * the last requested address and the currently active address so the called 1537 * can determine if there are any outstanding flips 1538 */ 1539 struct dc_plane_status { 1540 struct dc_plane_address requested_address; 1541 struct dc_plane_address current_address; 1542 bool is_flip_pending; 1543 bool is_right_eye; 1544 struct cm_hist cm_hist; 1545 }; 1546 1547 struct pipe_update_bits { 1548 uint32_t addr_update:1; 1549 uint32_t dcc_change:1; 1550 uint32_t color_space_change:1; 1551 uint32_t horizontal_mirror_change:1; 1552 uint32_t per_pixel_alpha_change:1; 1553 uint32_t global_alpha_change:1; 1554 uint32_t hdr_mult:1; 1555 uint32_t rotation_change:1; 1556 uint32_t swizzle_change:1; 1557 uint32_t scaling_change:1; 1558 uint32_t position_change:1; 1559 uint32_t in_transfer_func_change:1; 1560 uint32_t input_csc_change:1; 1561 uint32_t coeff_reduction_change:1; 1562 uint32_t pixel_format_change:1; 1563 uint32_t plane_size_change:1; 1564 uint32_t gamut_remap_change:1; 1565 uint32_t cursor_csc_color_matrix_change:1; 1566 uint32_t new_plane:1; 1567 uint32_t bpp_change:1; 1568 uint32_t gamma_change:1; 1569 uint32_t bandwidth_change:1; 1570 uint32_t clock_change:1; 1571 uint32_t stereo_format_change:1; 1572 uint32_t lut_3d:1; 1573 uint32_t tmz_changed:1; 1574 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1575 uint32_t full_update:1; 1576 uint32_t sdr_white_level_nits:1; 1577 uint32_t cm_hist_change:1; 1578 /* NOTE: When adding a new field, also update: 1579 * - dc_pipe_update_bits_set_full() 1580 * - dc_pipe_update_bits_is_any_set() 1581 */ 1582 }; 1583 1584 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags) 1585 { 1586 /* memset ensures padding bits are zeroed */ 1587 memset(flags, 0, sizeof(*flags)); 1588 } 1589 1590 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags) 1591 { 1592 dc_pipe_update_bits_clear(flags); 1593 flags->addr_update = 1; 1594 flags->dcc_change = 1; 1595 flags->color_space_change = 1; 1596 flags->horizontal_mirror_change = 1; 1597 flags->per_pixel_alpha_change = 1; 1598 flags->global_alpha_change = 1; 1599 flags->hdr_mult = 1; 1600 flags->rotation_change = 1; 1601 flags->swizzle_change = 1; 1602 flags->scaling_change = 1; 1603 flags->position_change = 1; 1604 flags->in_transfer_func_change = 1; 1605 flags->input_csc_change = 1; 1606 flags->coeff_reduction_change = 1; 1607 flags->pixel_format_change = 1; 1608 flags->plane_size_change = 1; 1609 flags->gamut_remap_change = 1; 1610 flags->cursor_csc_color_matrix_change = 1; 1611 flags->new_plane = 1; 1612 flags->bpp_change = 1; 1613 flags->gamma_change = 1; 1614 flags->bandwidth_change = 1; 1615 flags->clock_change = 1; 1616 flags->stereo_format_change = 1; 1617 flags->lut_3d = 1; 1618 flags->tmz_changed = 1; 1619 flags->mcm_transfer_function_enable_change = 1; 1620 flags->full_update = 1; 1621 flags->sdr_white_level_nits = 1; 1622 flags->cm_hist_change = 1; 1623 } 1624 1625 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags) 1626 { 1627 return flags->addr_update || 1628 flags->dcc_change || 1629 flags->color_space_change || 1630 flags->horizontal_mirror_change || 1631 flags->per_pixel_alpha_change || 1632 flags->global_alpha_change || 1633 flags->hdr_mult || 1634 flags->rotation_change || 1635 flags->swizzle_change || 1636 flags->scaling_change || 1637 flags->position_change || 1638 flags->in_transfer_func_change || 1639 flags->input_csc_change || 1640 flags->coeff_reduction_change || 1641 flags->pixel_format_change || 1642 flags->plane_size_change || 1643 flags->gamut_remap_change || 1644 flags->cursor_csc_color_matrix_change || 1645 flags->new_plane || 1646 flags->bpp_change || 1647 flags->gamma_change || 1648 flags->bandwidth_change || 1649 flags->clock_change || 1650 flags->stereo_format_change || 1651 flags->lut_3d || 1652 flags->tmz_changed || 1653 flags->mcm_transfer_function_enable_change || 1654 flags->full_update || 1655 flags->sdr_white_level_nits || 1656 flags->cm_hist_change; 1657 } 1658 1659 bool dc_check_address_only_update(struct pipe_update_bits update_bits); 1660 1661 #define DC_REMOVE_PLANE_POINTERS 1 1662 1663 struct dc_plane_state { 1664 struct dc_plane_address address; 1665 struct dc_plane_flip_time time; 1666 bool triplebuffer_flips; 1667 struct scaling_taps scaling_quality; 1668 struct rect src_rect; 1669 struct rect dst_rect; 1670 struct rect clip_rect; 1671 1672 struct plane_size plane_size; 1673 struct dc_tiling_info tiling_info; 1674 1675 struct dc_plane_dcc_param dcc; 1676 1677 struct dc_gamma gamma_correction; 1678 struct dc_transfer_func in_transfer_func; 1679 struct dc_bias_and_scale bias_and_scale; 1680 struct dc_csc_transform input_csc_color_matrix; 1681 struct fixed31_32 coeff_reduction_factor; 1682 struct fixed31_32 hdr_mult; 1683 struct colorspace_transform gamut_remap_matrix; 1684 1685 enum dc_color_space color_space; 1686 1687 #ifndef TRIM_CM2 1688 // TODO: No longer used, remove 1689 struct dc_hdr_static_metadata hdr_static_ctx; 1690 1691 struct dc_3dlut lut3d_func; 1692 struct dc_transfer_func in_shaper_func; 1693 struct dc_transfer_func blend_tf; 1694 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1695 bool mcm_lut1d_enable; 1696 struct dc_cm2_func_luts mcm_luts; 1697 #endif /* TRIM_CM2 */ 1698 bool lut_bank_a; 1699 enum mpcc_movable_cm_location mcm_location; 1700 struct dc_plane_cm cm; 1701 1702 struct dc_transfer_func *gamcor_tf; 1703 enum surface_pixel_format format; 1704 enum dc_rotation_angle rotation; 1705 enum plane_stereo_format stereo_format; 1706 1707 bool is_tiling_rotated; 1708 bool per_pixel_alpha; 1709 bool pre_multiplied_alpha; 1710 bool global_alpha; 1711 int global_alpha_value; 1712 bool visible; 1713 bool flip_immediate; 1714 bool horizontal_mirror; 1715 unsigned int layer_index; 1716 1717 struct pipe_update_bits update_bits; 1718 bool flip_int_enabled; 1719 bool skip_manual_trigger; 1720 1721 /* private to DC core */ 1722 struct dc_plane_status status; 1723 struct dc_context *ctx; 1724 1725 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1726 bool force_full_update; 1727 1728 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1729 1730 /* private to dc_surface.c */ 1731 enum dc_irq_source irq_source; 1732 struct kref refcount; 1733 struct tg_color visual_confirm_color; 1734 1735 bool is_statically_allocated; 1736 enum chroma_cositing cositing; 1737 struct dc_csc_transform cursor_csc_color_matrix; 1738 bool adaptive_sharpness_en; 1739 int adaptive_sharpness_policy; 1740 unsigned int sharpness_level; 1741 enum linear_light_scaling linear_light_scaling; 1742 unsigned int sdr_white_level_nits; 1743 struct cm_hist_control cm_hist_control; 1744 struct spl_sharpness_range sharpness_range; 1745 enum sharpness_range_source sharpness_source; 1746 }; 1747 1748 struct dc_plane_info { 1749 struct plane_size plane_size; 1750 struct dc_tiling_info tiling_info; 1751 struct dc_plane_dcc_param dcc; 1752 enum surface_pixel_format format; 1753 enum dc_rotation_angle rotation; 1754 enum plane_stereo_format stereo_format; 1755 enum dc_color_space color_space; 1756 bool horizontal_mirror; 1757 bool visible; 1758 bool per_pixel_alpha; 1759 bool pre_multiplied_alpha; 1760 bool global_alpha; 1761 int global_alpha_value; 1762 bool input_csc_enabled; 1763 unsigned int layer_index; 1764 enum chroma_cositing cositing; 1765 }; 1766 1767 #include "dc_stream.h" 1768 1769 struct dc_scratch_space { 1770 /* used to temporarily backup plane states of a stream during 1771 * dc update. The reason is that plane states are overwritten 1772 * with surface updates in dc update. Once they are overwritten 1773 * current state is no longer valid. We want to temporarily 1774 * store current value in plane states so we can still recover 1775 * a valid current state during dc update. 1776 */ 1777 struct dc_plane_state plane_states[MAX_SURFACES]; 1778 1779 struct dc_stream_state stream_state; 1780 }; 1781 1782 /* 1783 * A link contains one or more sinks and their connected status. 1784 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1785 */ 1786 struct dc_link { 1787 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1788 unsigned int sink_count; 1789 struct dc_sink *local_sink; 1790 unsigned int link_index; 1791 enum dc_connection_type type; 1792 enum signal_type connector_signal; 1793 enum dc_irq_source irq_source_hpd; 1794 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1795 enum dc_irq_source irq_source_read_request;/* Read Request */ 1796 1797 bool is_hpd_filter_disabled; 1798 bool dp_ss_off; 1799 1800 /** 1801 * @link_state_valid: 1802 * 1803 * If there is no link and local sink, this variable should be set to 1804 * false. Otherwise, it should be set to true; usually, the function 1805 * core_link_enable_stream sets this field to true. 1806 */ 1807 bool link_state_valid; 1808 bool aux_access_disabled; 1809 bool sync_lt_in_progress; 1810 bool skip_stream_reenable; 1811 bool is_internal_display; 1812 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1813 bool is_dig_mapping_flexible; 1814 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1815 bool is_hpd_pending; /* Indicates a new received hpd */ 1816 1817 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1818 * for every link training. This is incompatible with DP LL compliance automation, 1819 * which expects the same link settings to be used every retry on a link loss. 1820 * This flag is used to skip the fallback when link loss occurs during automation. 1821 */ 1822 bool skip_fallback_on_link_loss; 1823 1824 bool edp_sink_present; 1825 1826 struct dp_trace dp_trace; 1827 volatile bool is_link_locked; 1828 1829 /* caps is the same as reported_link_cap. link_traing use 1830 * reported_link_cap. Will clean up. TODO 1831 */ 1832 struct dc_link_settings reported_link_cap; 1833 struct dc_link_settings verified_link_cap; 1834 struct dc_link_settings cur_link_settings; 1835 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1836 struct dc_link_settings preferred_link_setting; 1837 /* preferred_training_settings are override values that 1838 * come from DM. DM is responsible for the memory 1839 * management of the override pointers. 1840 */ 1841 struct dc_link_training_overrides preferred_training_settings; 1842 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings; 1843 struct dp_audio_test_data audio_test_data; 1844 1845 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap 1846 * set by IFWI, link aux_hw_inst is used in aux layer functions instead 1847 * of ddc_pin to know which aux instance is associated with link. 1848 */ 1849 bool no_ddc_pin; 1850 /** When set, forces all native I2C communication on this DP connector 1851 * to use the I2C-over-AUX protocol instead of native I2C signaling. 1852 */ 1853 bool force_to_use_aux; 1854 enum gpio_ddc_line aux_hw_inst; 1855 1856 enum gpio_ddc_line ddc_hw_inst; 1857 1858 uint8_t hpd_src; 1859 1860 uint8_t link_enc_hw_inst; 1861 /* DIG link encoder ID. Used as index in link encoder resource pool. 1862 * For links with fixed mapping to DIG, this is not changed after dc_link 1863 * object creation. 1864 */ 1865 enum engine_id eng_id; 1866 enum engine_id dpia_preferred_eng_id; 1867 1868 bool test_pattern_enabled; 1869 /* Pending/Current test pattern are only used to perform and track 1870 * FIXED_VS retimer test pattern/lane adjustment override state. 1871 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1872 * to perform specific lane adjust overrides before setting certain 1873 * PHY test patterns. In cases when lane adjust and set test pattern 1874 * calls are not performed atomically (i.e. performing link training), 1875 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1876 * and current_test_pattern will contain required context for any future 1877 * set pattern/set lane adjust to transition between override state(s). 1878 * */ 1879 enum dp_test_pattern current_test_pattern; 1880 enum dp_test_pattern pending_test_pattern; 1881 1882 union compliance_test_state compliance_test_state; 1883 1884 void *priv; 1885 1886 struct ddc_service *ddc; 1887 1888 enum dp_panel_mode panel_mode; 1889 bool aux_mode; 1890 1891 /* Private to DC core */ 1892 1893 const struct dc *dc; 1894 1895 struct dc_context *ctx; 1896 1897 struct panel_cntl *panel_cntl; 1898 struct link_encoder *link_enc; 1899 struct hpo_frl_link_encoder *hpo_frl_link_enc; 1900 struct dc_hdmi_frl_link_settings frl_reported_link_cap; 1901 struct dc_hdmi_frl_link_settings frl_verified_link_cap; 1902 struct dc_hdmi_frl_link_settings frl_link_settings; 1903 struct dc_hdmi_frl_flags frl_flags; 1904 union hdmi_idcc_cable_id hdmi_cable_id; 1905 struct graphics_object_id link_id; 1906 1907 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1908 struct graphics_object_id ext_enc_id; 1909 1910 /* Endpoint type distinguishes display endpoints which do not have entries 1911 * in the BIOS connector table from those that do. Helps when tracking link 1912 * encoder to display endpoint assignments. 1913 */ 1914 enum display_endpoint_type ep_type; 1915 union ddi_channel_mapping ddi_channel_mapping; 1916 struct connector_device_tag_info device_tag; 1917 struct dpcd_caps dpcd_caps; 1918 uint32_t dongle_max_pix_clk; 1919 unsigned short chip_caps; 1920 unsigned int dpcd_sink_count; 1921 struct hdcp_caps hdcp_caps; 1922 enum edp_revision edp_revision; 1923 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1924 1925 struct psr_settings psr_settings; 1926 struct replay_settings replay_settings; 1927 1928 /* Drive settings read from integrated info table */ 1929 struct dc_lane_settings bios_forced_drive_settings; 1930 1931 /* Vendor specific LTTPR workaround variables */ 1932 uint8_t vendor_specific_lttpr_link_rate_wa; 1933 bool apply_vendor_specific_lttpr_link_rate_wa; 1934 1935 /* MST record stream using this link */ 1936 struct link_flags { 1937 bool dp_keep_receiver_powered; 1938 bool dp_skip_DID2; 1939 bool dp_skip_reset_segment; 1940 bool dp_skip_fs_144hz; 1941 /* Some DP bridges don't work with RBR and must use HBR. */ 1942 bool dp_skip_rbr; 1943 bool dp_mot_reset_segment; 1944 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1945 bool dpia_mst_dsc_always_on; 1946 /* Forced DPIA into TBT3 compatibility mode. */ 1947 bool dpia_forced_tbt3_mode; 1948 bool dongle_mode_timing_override; 1949 bool blank_stream_on_ocs_change; 1950 bool read_dpcd204h_on_irq_hpd; 1951 bool force_dp_ffe_preset; 1952 bool skip_phy_ssc_reduction; 1953 } wa_flags; 1954 union dc_dp_ffe_preset forced_dp_ffe_preset; 1955 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1956 1957 struct dc_link_status link_status; 1958 struct dprx_states dprx_states; 1959 1960 enum dc_link_fec_state fec_state; 1961 bool is_dds; 1962 bool is_display_mux_present; 1963 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1964 1965 struct dc_panel_config panel_config; 1966 enum dc_panel_type panel_type; 1967 struct phy_state phy_state; 1968 uint32_t phy_transition_bitmask; 1969 // BW ALLOCATON USB4 ONLY 1970 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1971 bool skip_implict_edp_power_control; 1972 enum backlight_control_type backlight_control_type; 1973 }; 1974 1975 struct dc { 1976 struct dc_debug_options debug; 1977 struct dc_versions versions; 1978 struct dc_caps caps; 1979 struct dc_check_config check_config; 1980 struct dc_cap_funcs cap_funcs; 1981 struct dc_config config; 1982 struct dc_bounding_box_overrides bb_overrides; 1983 struct dc_bug_wa work_arounds; 1984 struct dc_context *ctx; 1985 struct dc_phy_addr_space_config vm_pa_config; 1986 1987 uint8_t link_count; 1988 struct dc_link *links[MAX_LINKS]; 1989 uint8_t lowest_dpia_link_index; 1990 struct link_service *link_srv; 1991 1992 struct dc_state *current_state; 1993 struct resource_pool *res_pool; 1994 1995 /** 1996 * @update_scratch_pool: Per-commit scratch buffers for dc_update_state. 1997 */ 1998 struct dc_update_scratch_space *update_scratch_pool[MAX_STREAMS + 1]; 1999 bool update_scratch_in_use[MAX_STREAMS + 1]; 2000 2001 struct clk_mgr *clk_mgr; 2002 2003 /* Display Engine Clock levels */ 2004 struct dm_pp_clock_levels sclk_lvls; 2005 2006 /* Inputs into BW and WM calculations. */ 2007 struct bw_calcs_dceip *bw_dceip; 2008 struct bw_calcs_vbios *bw_vbios; 2009 struct dcn_soc_bounding_box *dcn_soc; 2010 struct dcn_ip_params *dcn_ip; 2011 struct display_mode_lib dml; 2012 2013 /* HW functions */ 2014 struct hw_sequencer_funcs hwss; 2015 struct dce_hwseq *hwseq; 2016 2017 /* Require to optimize clocks and bandwidth for added/removed planes */ 2018 bool optimized_required; 2019 bool idle_optimizations_allowed; 2020 bool enable_c20_dtm_b0; 2021 2022 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 2023 2024 /* For eDP to know the switching state of SmartMux */ 2025 bool is_switch_in_progress_orig; 2026 bool is_switch_in_progress_dest; 2027 2028 /* FBC compressor */ 2029 struct compressor *fbc_compressor; 2030 2031 struct dc_debug_data debug_data; 2032 struct dpcd_vendor_signature vendor_signature; 2033 2034 const char *build_id; 2035 struct vm_helper *vm_helper; 2036 2037 uint32_t *dcn_reg_offsets; 2038 uint32_t *nbio_reg_offsets; 2039 uint32_t *clk_reg_offsets; 2040 2041 /* Scratch memory */ 2042 struct { 2043 struct { 2044 /* 2045 * For matching clock_limits table in driver with table 2046 * from PMFW. 2047 */ 2048 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2049 } update_bw_bounding_box; 2050 struct dc_scratch_space current_state; 2051 struct dc_scratch_space new_state; 2052 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 2053 struct dc_link temp_link; 2054 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 2055 } scratch; 2056 2057 struct dml2_configuration_options dml2_options; 2058 struct dml2_configuration_options dml2_dc_power_options; 2059 enum dc_acpi_cm_power_state power_state; 2060 struct soc_and_ip_translator *soc_and_ip_translator; 2061 }; 2062 2063 struct dc_scaling_info { 2064 struct rect src_rect; 2065 struct rect dst_rect; 2066 struct rect clip_rect; 2067 struct scaling_taps scaling_quality; 2068 }; 2069 2070 struct dc_fast_update { 2071 const struct dc_flip_addrs *flip_addr; 2072 const struct dc_gamma *gamma; 2073 const struct colorspace_transform *gamut_remap_matrix; 2074 const struct dc_csc_transform *input_csc_color_matrix; 2075 const struct fixed31_32 *coeff_reduction_factor; 2076 struct dc_transfer_func *out_transfer_func; 2077 struct dc_csc_transform *output_csc_transform; 2078 const struct dc_csc_transform *cursor_csc_color_matrix; 2079 struct cm_hist_control *cm_hist_control; 2080 /* stream-level fast updates */ 2081 const struct colorspace_transform *gamut_remap; 2082 const struct dc_cursor_attributes *cursor_attributes; 2083 const struct dc_cursor_position *cursor_position; 2084 const struct periodic_interrupt_config *periodic_interrupt; 2085 const enum dc_dither_option *dither_option; 2086 struct dc_info_packet *vrr_infopacket; 2087 struct dc_info_packet *vsc_infopacket; 2088 struct dc_info_packet *vsp_infopacket; 2089 struct dc_info_packet *hfvsif_infopacket; 2090 struct dc_info_packet *vtem_infopacket; 2091 struct dc_info_packet *adaptive_sync_infopacket; 2092 struct dc_info_packet *avi_infopacket; 2093 struct dc_info_packet *hdr_static_metadata; 2094 }; 2095 2096 struct dc_surface_update { 2097 struct dc_plane_state *surface; 2098 2099 /* isr safe update parameters. null means no updates */ 2100 const struct dc_flip_addrs *flip_addr; 2101 const struct dc_plane_info *plane_info; 2102 const struct dc_scaling_info *scaling_info; 2103 struct fixed31_32 hdr_mult; 2104 /* following updates require alloc/sleep/spin that is not isr safe, 2105 * null means no updates 2106 */ 2107 const struct dc_gamma *gamma; 2108 const struct dc_transfer_func *in_transfer_func; 2109 2110 const struct dc_csc_transform *input_csc_color_matrix; 2111 const struct fixed31_32 *coeff_reduction_factor; 2112 const struct colorspace_transform *gamut_remap_matrix; 2113 const struct dc_plane_cm *cm; 2114 const struct dc_csc_transform *cursor_csc_color_matrix; 2115 unsigned int sdr_white_level_nits; 2116 struct dc_bias_and_scale bias_and_scale; 2117 struct cm_hist_control *cm_hist_control; 2118 }; 2119 2120 struct dc_state_update { 2121 struct dc_stream_state *stream; 2122 struct dc_stream_update *stream_update; 2123 struct dc_surface_update *surface_updates; 2124 int surface_count; 2125 const struct dc_probe_updates *probe_updates; 2126 }; 2127 2128 /** 2129 * dc_check_state_update() - Classify an update without committing it. 2130 * @check_config: DC check configuration 2131 * @updates: root update object to classify 2132 * 2133 * Return: descriptor indicating update type and required lock scope. 2134 */ 2135 struct dc_update_descriptor dc_check_state_update( 2136 const struct dc_check_config *check_config, 2137 const struct dc_state_update *updates); 2138 2139 /** 2140 * dc_update_state - Commit an absolute dc_state_update. 2141 * @dc: DC structure 2142 * @updates: root update object carrying stream, plane, and probe updates 2143 * 2144 * Return: true on success, false on failure. 2145 */ 2146 bool dc_update_state(struct dc *dc, const struct dc_state_update *updates); 2147 2148 struct dc_update_scratch_space; 2149 2150 /** 2151 * dc_update_state_init - Acquire and initialise a commit scratch buffer. 2152 * @dc: DC structure 2153 * @updates: update descriptor; validated before the slot is acquired 2154 * 2155 * Return: a scratch slot on success, NULL if validation fails or the pool 2156 * is exhausted. The slot must be released via dc_update_state_cleanup() on 2157 * success, or automatically by dc_update_state_prepare() on failure. 2158 */ 2159 struct dc_update_scratch_space *dc_update_state_init( 2160 struct dc *dc, 2161 const struct dc_state_update *updates 2162 ); 2163 2164 /** 2165 * dc_update_state_prepare - Prepare the commit under the global lock. 2166 * @scratch: commit scratch from dc_update_state_init() 2167 * 2168 * On failure the scratch slot is released and false is returned; the caller 2169 * must not call execute or cleanup. 2170 */ 2171 bool dc_update_state_prepare(struct dc_update_scratch_space *scratch); 2172 2173 /** 2174 * dc_update_state_execute - Program hardware; called without the global lock. 2175 * @scratch: commit scratch from dc_update_state_init() 2176 */ 2177 void dc_update_state_execute(const struct dc_update_scratch_space *scratch); 2178 2179 /** 2180 * dc_update_state_cleanup - Finalise the commit and release the scratch slot. 2181 * @scratch: commit scratch from dc_update_state_init() 2182 * 2183 * Must be called with the global lock held. Returns true if the caller must 2184 * loop back to prepare (SEAMLESS continuation). 2185 */ 2186 bool dc_update_state_cleanup(struct dc_update_scratch_space *scratch); 2187 2188 /** 2189 * struct dc_probe_latencies - min/max/avg memory latency in ns. 2190 * @max_latency_ns: maximum latency in nanoseconds 2191 * @avg_latency_ns: average latency in nanoseconds 2192 * @min_latency_ns: minimum latency in nanoseconds 2193 */ 2194 struct dc_probe_latencies { 2195 uint32_t max_latency_ns; 2196 uint32_t avg_latency_ns; 2197 uint32_t min_latency_ns; 2198 }; 2199 2200 /** 2201 * struct dc_probe_status - results for a probe. 2202 * @valid: true if a measurement was latched. 2203 * @type: type of the probe that produced this result. 2204 * @u.bandwidth_mbps: peak BW in Mbps (DC_PROBE_PEAK_MEM_BW). 2205 * @u.latency: min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), 2206 * stored as struct dc_probe_latencies. 2207 * @u.urgent_assertion_count: number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT). 2208 * @u.prefetch_data_size: total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE). 2209 */ 2210 struct dc_probe_status { 2211 bool valid; 2212 enum dc_probe_type type; 2213 union { 2214 uint32_t bandwidth_mbps; 2215 struct dc_probe_latencies latency; 2216 uint32_t urgent_assertion_count; 2217 uint32_t prefetch_data_size; 2218 } u; 2219 }; 2220 2221 /** 2222 * enum dc_get_status_type - Bitmask selecting which status classes to populate. 2223 * @DC_GET_STATUS_STREAM: populate stream_status fields in dc_state_status 2224 * @DC_GET_STATUS_PROBE: populate probe_status fields in dc_state_status 2225 */ 2226 enum dc_get_status_type { 2227 DC_GET_STATUS_STREAM = (1u << 0), 2228 DC_GET_STATUS_PROBE = (1u << 1), 2229 }; 2230 2231 /** 2232 * struct dc_get_status_options - Input selector for dc_state_get_status. 2233 * @state: source state to read status from 2234 * @types: OR of dc_get_status_type values selecting classes to populate 2235 * @stream: optional stream filter for DC_GET_STATUS_STREAM. NULL means 2236 * populate status for all streams in the state 2237 * @probe: optional probe filter for DC_GET_STATUS_PROBE. NULL means 2238 * populate status for all probes in the state 2239 */ 2240 struct dc_get_status_options { 2241 struct dc_state *state; 2242 uint32_t types; 2243 const struct dc_stream_state *stream; 2244 const struct dc_probe_state *probe; 2245 }; 2246 2247 /** 2248 * struct dc_state_status - Output-only status object from dc_state_get_status. 2249 * @stream_count: number of valid entries in stream_status (DC_GET_STATUS_STREAM) 2250 * @stream_status: pointers to live per-stream status entries 2251 * @probe_count: number of valid entries in probe_status (DC_GET_STATUS_PROBE) 2252 * @probe_status: pointers to live per-probe status entries 2253 */ 2254 struct dc_state_status { 2255 int stream_count; 2256 struct dc_stream_status *stream_status[MAX_STREAMS]; 2257 int probe_count; 2258 struct dc_probe_status *probe_status[MAX_PROBES]; 2259 }; 2260 2261 /** 2262 * dc_state_get_status - Unified status readback for dc_state. 2263 * @status: output object populated according to options->types 2264 * @options: selects the source state, status classes to fill, and filters 2265 * 2266 * Return: DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL. 2267 */ 2268 enum dc_status dc_state_get_status(struct dc_state_status *status, 2269 const struct dc_get_status_options *options); 2270 2271 struct dc_underflow_debug_data { 2272 struct dcn_hubbub_reg_state *hubbub_reg_state; 2273 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 2274 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 2275 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 2276 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 2277 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 2278 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 2279 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 2280 }; 2281 2282 struct power_features { 2283 bool ips; 2284 bool rcg; 2285 bool replay; 2286 bool dds; 2287 bool sprs; 2288 bool psr; 2289 bool fams; 2290 bool mpo; 2291 bool uclk_p_state; 2292 }; 2293 2294 /* 2295 * Create a new surface with default parameters; 2296 */ 2297 void dc_gamma_retain(struct dc_gamma *dc_gamma); 2298 void dc_gamma_release(struct dc_gamma **dc_gamma); 2299 struct dc_gamma *dc_create_gamma(void); 2300 2301 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 2302 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 2303 struct dc_transfer_func *dc_create_transfer_func(void); 2304 2305 struct dc_3dlut *dc_create_3dlut_func(void); 2306 void dc_3dlut_func_release(struct dc_3dlut *lut); 2307 void dc_3dlut_func_retain(struct dc_3dlut *lut); 2308 2309 struct dc_plane_cm *dc_plane_cm_create(void); 2310 void dc_plane_cm_release(struct dc_plane_cm *cm); 2311 void dc_plane_cm_retain(struct dc_plane_cm *cm); 2312 2313 void dc_post_update_surfaces_to_stream( 2314 struct dc *dc); 2315 2316 /* 2317 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling 2318 * description for (typically) linear surfaces. 2319 * 2320 * This is used by OS/DM paths that need a valid, fully-initialized tiling 2321 * description without hardcoding gfx-version specifics in the caller. 2322 */ 2323 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); 2324 2325 /** 2326 * struct dc_validation_stream - Per-stream surface/stream association for validation 2327 */ 2328 struct dc_validation_stream { 2329 /** 2330 * @stream: Stream state properties 2331 */ 2332 struct dc_stream_state *stream; 2333 2334 /** 2335 * @plane_states: Surface state 2336 */ 2337 struct dc_plane_state *plane_states[MAX_SURFACES]; 2338 2339 /** 2340 * @plane_count: Total of active planes 2341 */ 2342 uint8_t plane_count; 2343 }; 2344 2345 /** 2346 * struct dc_validation_set - Root validation input grouping all streams for a commit 2347 */ 2348 struct dc_validation_set { 2349 /** 2350 * @streams: Per-stream entries (stream + its planes) 2351 */ 2352 struct dc_validation_stream streams[MAX_STREAMS]; 2353 2354 /** 2355 * @stream_count: Number of active entries in @streams 2356 */ 2357 uint8_t stream_count; 2358 2359 /** 2360 * @probes: Global probe descriptors to validate alongside the streams 2361 */ 2362 struct dc_probe_state probes[MAX_PROBES]; 2363 2364 /** 2365 * @probe_count: Number of active entries in @probes 2366 */ 2367 uint8_t probe_count; 2368 }; 2369 2370 bool dc_validate_boot_timing(const struct dc *dc, 2371 const struct dc_sink *sink, 2372 struct dc_crtc_timing *crtc_timing); 2373 2374 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 2375 2376 enum dc_status dc_validate_with_context(struct dc *dc, 2377 const struct dc_validation_set *set, 2378 struct dc_state *context, 2379 enum dc_validate_mode validate_mode); 2380 2381 bool dc_set_generic_gpio_for_stereo(bool enable, 2382 struct gpio_service *gpio_service); 2383 2384 enum dc_status dc_validate_global_state( 2385 struct dc *dc, 2386 struct dc_state *new_ctx, 2387 enum dc_validate_mode validate_mode); 2388 2389 bool dc_acquire_release_mpc_3dlut( 2390 struct dc *dc, bool acquire, 2391 struct dc_stream_state *stream, 2392 struct dc_3dlut **lut, 2393 struct dc_transfer_func **shaper); 2394 2395 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 2396 void get_audio_check(struct audio_info *aud_modes, 2397 struct audio_check *aud_chk); 2398 2399 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 2400 void populate_fast_updates(struct dc_fast_update *fast_update, 2401 struct dc_surface_update *srf_updates, 2402 int surface_count, 2403 struct dc_stream_update *stream_update); 2404 /* 2405 * Set up streams and links associated to drive sinks 2406 * The streams parameter is an absolute set of all active streams. 2407 * 2408 * After this call: 2409 * Phy, Encoder, Timing Generator are programmed and enabled. 2410 * New streams are enabled with blank stream; no memory read. 2411 */ 2412 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 2413 2414 2415 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2416 struct dc_stream_state *stream, 2417 int mpcc_inst); 2418 2419 2420 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2421 bool dc_set_fva_vrr_adjust(struct dc *dc, 2422 struct dc_stream_state *stream, 2423 struct fva_adj *fva_adj, 2424 struct dc_crtc_timing_adjust *vrr_adj); 2425 2426 int dc_get_hw_max_fva_factor(struct dc *dc, 2427 struct dc_stream_state *stream, 2428 unsigned int max_pixel_clock); 2429 2430 void dc_set_vstartup_start(struct dc *dc, 2431 struct dc_stream_state *stream); 2432 2433 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2434 2435 /* The function returns minimum bandwidth required to drive a given timing 2436 * return - minimum required timing bandwidth in kbps. 2437 */ 2438 uint32_t dc_bandwidth_in_kbps_from_timing( 2439 const struct dc_crtc_timing *timing, 2440 const enum dc_link_encoding_format link_encoding); 2441 2442 /* Link Interfaces */ 2443 /* Return an enumerated dc_link. 2444 * dc_link order is constant and determined at 2445 * boot time. They cannot be created or destroyed. 2446 * Use dc_get_caps() to get number of links. 2447 */ 2448 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2449 2450 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2451 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2452 const struct dc_link *link, 2453 unsigned int *inst_out); 2454 2455 /* Return an array of link pointers to edp links. */ 2456 void dc_get_edp_links(const struct dc *dc, 2457 struct dc_link **edp_links, 2458 unsigned int *edp_num); 2459 2460 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2461 bool powerOn); 2462 2463 /* The function initiates detection handshake over the given link. It first 2464 * determines if there are display connections over the link. If so it initiates 2465 * detection protocols supported by the connected receiver device. The function 2466 * contains protocol specific handshake sequences which are sometimes mandatory 2467 * to establish a proper connection between TX and RX. So it is always 2468 * recommended to call this function as the first link operation upon HPD event 2469 * or power up event. Upon completion, the function will update link structure 2470 * in place based on latest RX capabilities. The function may also cause dpms 2471 * to be reset to off for all currently enabled streams to the link. It is DM's 2472 * responsibility to serialize detection and DPMS updates. 2473 * 2474 * @reason - Indicate which event triggers this detection. dc may customize 2475 * detection flow depending on the triggering events. 2476 * return false - if detection is not fully completed. This could happen when 2477 * there is an unrecoverable error during detection or detection is partially 2478 * completed (detection has been delegated to dm mst manager ie. 2479 * link->connection_type == dc_connection_mst_branch when returning false). 2480 * return true - detection is completed, link has been fully updated with latest 2481 * detection result. 2482 */ 2483 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2484 2485 struct dc_sink_init_data; 2486 2487 /* When link connection type is dc_connection_mst_branch, remote sink can be 2488 * added to the link. The interface creates a remote sink and associates it with 2489 * current link. The sink will be retained by link until remove remote sink is 2490 * called. 2491 * 2492 * @dc_link - link the remote sink will be added to. 2493 * @edid - byte array of EDID raw data. 2494 * @len - size of the edid in byte 2495 * @init_data - 2496 */ 2497 struct dc_sink *dc_link_add_remote_sink( 2498 struct dc_link *dc_link, 2499 const uint8_t *edid, 2500 unsigned int len, 2501 struct dc_sink_init_data *init_data); 2502 2503 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2504 * @link - link the sink should be removed from 2505 * @sink - sink to be removed. 2506 */ 2507 void dc_link_remove_remote_sink( 2508 struct dc_link *link, 2509 struct dc_sink *sink); 2510 2511 /* Enable HPD interrupt handler for a given link */ 2512 void dc_link_enable_hpd(const struct dc_link *link); 2513 2514 /* Disable HPD interrupt handler for a given link */ 2515 void dc_link_disable_hpd(const struct dc_link *link); 2516 2517 /* determine if there is a sink connected to the link 2518 * 2519 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2520 * return - false if an unexpected error occurs, true otherwise. 2521 * 2522 * NOTE: This function doesn't detect downstream sink connections i.e 2523 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2524 * return dc_connection_single if the branch device is connected despite of 2525 * downstream sink's connection status. 2526 */ 2527 bool dc_link_detect_connection_type(struct dc_link *link, 2528 enum dc_connection_type *type); 2529 2530 /* query current hpd pin value 2531 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2532 * 2533 */ 2534 bool dc_link_get_hpd_state(struct dc_link *link); 2535 2536 /* Getter for cached link status from given link */ 2537 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2538 2539 /* enable/disable hardware HPD filter. 2540 * 2541 * @link - The link the HPD pin is associated with. 2542 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2543 * handler once after no HPD change has been detected within dc default HPD 2544 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2545 * pulses within default HPD interval, no HPD event will be received until HPD 2546 * toggles have stopped. Then HPD event will be queued to irq handler once after 2547 * dc default HPD filtering interval since last HPD event. 2548 * 2549 * @enable = false - disable hardware HPD filter. HPD event will be queued 2550 * immediately to irq handler after no HPD change has been detected within 2551 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2552 */ 2553 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2554 2555 /* submit i2c read/write payloads through ddc channel 2556 * @link_index - index to a link with ddc in i2c mode 2557 * @cmd - i2c command structure 2558 * return - true if success, false otherwise. 2559 */ 2560 bool dc_submit_i2c( 2561 struct dc *dc, 2562 uint32_t link_index, 2563 struct i2c_command *cmd); 2564 2565 /* submit i2c read/write payloads through oem channel 2566 * @link_index - index to a link with ddc in i2c mode 2567 * @cmd - i2c command structure 2568 * return - true if success, false otherwise. 2569 */ 2570 bool dc_submit_i2c_oem( 2571 struct dc *dc, 2572 struct i2c_command *cmd); 2573 2574 enum aux_return_code_type; 2575 /* Attempt to transfer the given aux payload. This function does not perform 2576 * retries or handle error states. The reply is returned in the payload->reply 2577 * and the result through operation_result. Returns the number of bytes 2578 * transferred,or -1 on a failure. 2579 */ 2580 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2581 struct aux_payload *payload, 2582 enum aux_return_code_type *operation_result); 2583 2584 struct ddc_service * 2585 dc_get_oem_i2c_device(struct dc *dc); 2586 2587 bool dc_is_oem_i2c_device_present( 2588 struct dc *dc, 2589 size_t slave_address 2590 ); 2591 2592 /* return true if the connected receiver supports the hdcp version */ 2593 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2594 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2595 2596 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2597 * 2598 * TODO - When defer_handling is true the function will have a different purpose. 2599 * It no longer does complete hpd rx irq handling. We should create a separate 2600 * interface specifically for this case. 2601 * 2602 * Return: 2603 * true - Downstream port status changed. DM should call DC to do the 2604 * detection. 2605 * false - no change in Downstream port status. No further action required 2606 * from DM. 2607 */ 2608 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2609 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2610 bool defer_handling, bool *has_left_work); 2611 /* handle DP specs define test automation sequence*/ 2612 void dc_link_dp_handle_automated_test(struct dc_link *link); 2613 2614 /* handle DP Link loss sequence and try to recover RX link loss with best 2615 * effort 2616 */ 2617 void dc_link_dp_handle_link_loss(struct dc_link *link); 2618 2619 /* Determine if hpd rx irq should be handled or ignored 2620 * return true - hpd rx irq should be handled. 2621 * return false - it is safe to ignore hpd rx irq event 2622 */ 2623 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2624 2625 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2626 * @link - link the hpd irq data associated with 2627 * @hpd_irq_dpcd_data - input hpd irq data 2628 * return - true if hpd irq data indicates a link lost 2629 */ 2630 bool dc_link_check_link_loss_status(struct dc_link *link, 2631 union hpd_irq_data *hpd_irq_dpcd_data); 2632 2633 /* Read hpd rx irq data from a given link 2634 * @link - link where the hpd irq data should be read from 2635 * @irq_data - output hpd irq data 2636 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2637 * read has failed. 2638 */ 2639 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2640 struct dc_link *link, 2641 union hpd_irq_data *irq_data); 2642 2643 bool dc_link_frl_poll_status_flag(struct dc_link *link); 2644 bool dc_link_frl_margin_check_uncompressed_video( 2645 const struct dc_link *link, 2646 struct frl_cap_chk_params_fixed31_32 *params, 2647 struct frl_cap_chk_intermediates_fixed31_32 *inter); 2648 2649 /* The function clears recorded DP RX states in the link. DM should call this 2650 * function when it is resuming from S3 power state to previously connected links. 2651 * 2652 * TODO - in the future we should consider to expand link resume interface to 2653 * support clearing previous rx states. So we don't have to rely on dm to call 2654 * this interface explicitly. 2655 */ 2656 void dc_link_clear_dprx_states(struct dc_link *link); 2657 2658 /* Destruct the mst topology of the link and reset the allocated payload table 2659 * 2660 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2661 * still wants to reset MST topology on an unplug event */ 2662 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2663 2664 /* The function calculates effective DP link bandwidth when a given link is 2665 * using the given link settings. 2666 * 2667 * return - total effective link bandwidth in kbps. 2668 */ 2669 uint32_t dc_link_bandwidth_kbps( 2670 const struct dc_link *link, 2671 const struct dc_link_settings *link_setting); 2672 2673 /* The function returns effective HDMI FRL bandwidth given link rate. 2674 * return - total effective link bandwidth in kbps. 2675 */ 2676 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link, 2677 enum hdmi_frl_link_rate link_rate); 2678 2679 struct dp_audio_bandwidth_params { 2680 const struct dc_crtc_timing *crtc_timing; 2681 enum dp_link_encoding link_encoding; 2682 uint32_t channel_count; 2683 uint32_t sample_rate_hz; 2684 }; 2685 2686 /* The function calculates the minimum size of hblank (in bytes) needed to 2687 * support the specified channel count and sample rate combination, given the 2688 * link encoding and timing to be used. This calculation is not supported 2689 * for 8b/10b SST. 2690 * 2691 * return - min hblank size in bytes, 0 if 8b/10b SST. 2692 */ 2693 uint32_t dc_link_required_hblank_size_bytes( 2694 const struct dc_link *link, 2695 struct dp_audio_bandwidth_params *audio_params); 2696 2697 /* The function takes a snapshot of current link resource allocation state 2698 * @dc: pointer to dc of the dm calling this 2699 * @map: a dc link resource snapshot defined internally to dc. 2700 * 2701 * DM needs to capture a snapshot of current link resource allocation mapping 2702 * and store it in its persistent storage. 2703 * 2704 * Some of the link resource is using first come first serve policy. 2705 * The allocation mapping depends on original hotplug order. This information 2706 * is lost after driver is loaded next time. The snapshot is used in order to 2707 * restore link resource to its previous state so user will get consistent 2708 * link capability allocation across reboot. 2709 * 2710 */ 2711 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2712 2713 /* This function restores link resource allocation state from a snapshot 2714 * @dc: pointer to dc of the dm calling this 2715 * @map: a dc link resource snapshot defined internally to dc. 2716 * 2717 * DM needs to call this function after initial link detection on boot and 2718 * before first commit streams to restore link resource allocation state 2719 * from previous boot session. 2720 * 2721 * Some of the link resource is using first come first serve policy. 2722 * The allocation mapping depends on original hotplug order. This information 2723 * is lost after driver is loaded next time. The snapshot is used in order to 2724 * restore link resource to its previous state so user will get consistent 2725 * link capability allocation across reboot. 2726 * 2727 */ 2728 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2729 2730 void dc_link_wait_for_unlocked(struct dc_link *link); 2731 2732 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2733 * interface i.e stream_update->dsc_config 2734 */ 2735 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2736 2737 /* translate a raw link rate data to bandwidth in kbps */ 2738 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2739 2740 /* determine the optimal bandwidth given link and required bw. 2741 * @link - current detected link 2742 * @req_bw - requested bandwidth in kbps 2743 * @link_settings - returned most optimal link settings that can fit the 2744 * requested bandwidth 2745 * return - false if link can't support requested bandwidth, true if link 2746 * settings is found. 2747 */ 2748 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2749 struct dc_link_settings *link_settings, 2750 uint32_t req_bw); 2751 2752 /* return the max dp link settings can be driven by the link without considering 2753 * connected RX device and its capability 2754 */ 2755 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2756 struct dc_link_settings *max_link_enc_cap); 2757 2758 /* determine when the link is driving MST mode, what DP link channel coding 2759 * format will be used. The decision will remain unchanged until next HPD event. 2760 * 2761 * @link - a link with DP RX connection 2762 * return - if stream is committed to this link with MST signal type, type of 2763 * channel coding format dc will choose. 2764 */ 2765 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2766 const struct dc_link *link); 2767 2768 /* get max dp link settings the link can enable with all things considered. (i.e 2769 * TX/RX/Cable capabilities and dp override policies. 2770 * 2771 * @link - a link with DP RX connection 2772 * return - max dp link settings the link can enable. 2773 * 2774 */ 2775 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2776 2777 /* Get the highest encoding format that the link supports; highest meaning the 2778 * encoding format which supports the maximum bandwidth. 2779 * 2780 * @link - a link with DP RX connection 2781 * return - highest encoding format link supports. 2782 */ 2783 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2784 2785 /* get max frl link settings the link can enable with all things considered. 2786 * (i.e TX/RX capabilities and link verification result. 2787 * 2788 * @link - a link with FRL RX connection 2789 * return - max frl link settings the link can enable. 2790 * 2791 */ 2792 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap( 2793 struct dc_link *link); 2794 2795 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2796 * to a link with dp connector signal type. 2797 * @link - a link with dp connector signal type 2798 * return - true if connected, false otherwise 2799 */ 2800 bool dc_link_is_dp_sink_present(struct dc_link *link); 2801 2802 /* Force DP lane settings update to main-link video signal and notify the change 2803 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2804 * tuning purpose. The interface assumes link has already been enabled with DP 2805 * signal. 2806 * 2807 * @lt_settings - a container structure with desired hw_lane_settings 2808 */ 2809 void dc_link_set_drive_settings(struct dc *dc, 2810 struct link_training_settings *lt_settings, 2811 struct dc_link *link); 2812 2813 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2814 * test or debugging purpose. The test pattern will remain until next un-plug. 2815 * 2816 * @link - active link with DP signal output enabled. 2817 * @test_pattern - desired test pattern to output. 2818 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2819 * @test_pattern_color_space - for video test pattern choose a desired color 2820 * space. 2821 * @p_link_settings - For PHY pattern choose a desired link settings 2822 * @p_custom_pattern - some test pattern will require a custom input to 2823 * customize some pattern details. Otherwise keep it to NULL. 2824 * @cust_pattern_size - size of the custom pattern input. 2825 * 2826 */ 2827 bool dc_link_dp_set_test_pattern( 2828 struct dc_link *link, 2829 enum dp_test_pattern test_pattern, 2830 enum dp_test_pattern_color_space test_pattern_color_space, 2831 const struct link_training_settings *p_link_settings, 2832 const unsigned char *p_custom_pattern, 2833 unsigned int cust_pattern_size); 2834 2835 /* Force DP link settings to always use a specific value until reboot to a 2836 * specific link. If link has already been enabled, the interface will also 2837 * switch to desired link settings immediately. This is a debug interface to 2838 * generic dp issue trouble shooting. 2839 */ 2840 void dc_link_set_preferred_link_settings(struct dc *dc, 2841 struct dc_link_settings *link_setting, 2842 struct dc_link *link); 2843 2844 /* Force FRL link settings to always use a specific value until reboot to a 2845 * specific link. If link has already been enabled, the interface will also 2846 * switch to desired link settings immediately. This is a debug interface to 2847 * generic FRL issue trouble shooting. 2848 */ 2849 void dc_link_set_preferred_frl_link_settings(struct dc *dc, 2850 struct dc_hdmi_frl_link_settings *link_setting, 2851 struct dc_hdmi_frl_link_training_overrides *lt_overrides, 2852 struct dc_link *link); 2853 2854 /* Force DP link to customize a specific link training behavior by overriding to 2855 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2856 * display specific link training issues or apply some display specific 2857 * workaround in link training. 2858 * 2859 * @link_settings - if not NULL, force preferred link settings to the link. 2860 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2861 * will apply this particular override in future link training. If NULL is 2862 * passed in, dc resets previous overrides. 2863 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2864 * training settings. 2865 */ 2866 void dc_link_set_preferred_training_settings(struct dc *dc, 2867 struct dc_link_settings *link_setting, 2868 struct dc_link_training_overrides *lt_overrides, 2869 struct dc_link *link, 2870 bool skip_immediate_retrain); 2871 2872 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2873 bool dc_link_is_fec_supported(const struct dc_link *link); 2874 2875 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2876 * link enablement. 2877 * return - true if FEC should be enabled, false otherwise. 2878 */ 2879 bool dc_link_should_enable_fec(const struct dc_link *link); 2880 2881 /* determine lttpr mode the current link should be enabled with a specific link 2882 * settings. 2883 */ 2884 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2885 struct dc_link_settings *link_setting); 2886 2887 /* Force DP RX to update its power state. 2888 * NOTE: this interface doesn't update dp main-link. Calling this function will 2889 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2890 * RX power state back upon finish DM specific execution requiring DP RX in a 2891 * specific power state. 2892 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2893 * state. 2894 */ 2895 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2896 2897 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2898 * current value read from extended receiver cap from 02200h - 0220Fh. 2899 * Some DP RX has problems of providing accurate DP receiver caps from extended 2900 * field, this interface is a workaround to revert link back to use base caps. 2901 */ 2902 void dc_link_overwrite_extended_receiver_cap( 2903 struct dc_link *link); 2904 2905 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2906 bool wait_for_hpd); 2907 2908 /* Set backlight level of an embedded panel (eDP, LVDS). 2909 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2910 * and 16 bit fractional, where 1.0 is max backlight value. 2911 */ 2912 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2913 struct set_backlight_level_params *backlight_level_params); 2914 2915 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2916 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2917 bool isHDR, 2918 uint32_t backlight_millinits, 2919 uint32_t transition_time_in_ms); 2920 2921 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2922 uint32_t *backlight_millinits, 2923 uint32_t *backlight_millinits_peak); 2924 2925 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2926 2927 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2928 2929 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2930 bool wait, bool force_static, const unsigned int *power_opts); 2931 2932 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2933 2934 bool dc_link_setup_psr(struct dc_link *dc_link, 2935 const struct dc_stream_state *stream, struct psr_config *psr_config, 2936 struct psr_context *psr_context); 2937 2938 /* 2939 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2940 * 2941 * @link: pointer to the dc_link struct instance 2942 * @enable: enable(active) or disable(inactive) replay 2943 * @wait: state transition need to wait the active set completed. 2944 * @force_static: force disable(inactive) the replay 2945 * @power_opts: set power optimazation parameters to DMUB. 2946 * 2947 * return: allow Replay active will return true, else will return false. 2948 */ 2949 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2950 bool wait, bool force_static, const unsigned int *power_opts); 2951 2952 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2953 2954 /* 2955 * Enable or disable Panel Replay on the specified link: 2956 * 2957 * @link: pointer to the dc_link struct instance 2958 * @enable: enable or disable Panel Replay 2959 * 2960 * return: true if successful, false otherwise 2961 */ 2962 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2963 2964 /* 2965 * Update Panel Replay state parameters: 2966 * 2967 * @link: pointer to the dc_link struct instance 2968 * @update_state_data: pointer to state update data structure 2969 * 2970 * return: true if successful, false otherwise 2971 */ 2972 bool dc_link_update_pr_state(struct dc_link *link, 2973 struct dmub_cmd_pr_update_state_data *update_state_data); 2974 2975 /* 2976 * Send general command to Panel Replay firmware: 2977 * 2978 * @link: pointer to the dc_link struct instance 2979 * @general_cmd_data: pointer to general command data structure 2980 * 2981 * return: true if successful, false otherwise 2982 */ 2983 bool dc_link_set_pr_general_cmd(struct dc_link *link, 2984 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 2985 2986 /* 2987 * Get Panel Replay state: 2988 * 2989 * @link: pointer to the dc_link struct instance 2990 * @state: pointer to store the Panel Replay state 2991 * 2992 * return: true if successful, false otherwise 2993 */ 2994 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 2995 2996 /* On eDP links this function call will stall until T12 has elapsed. 2997 * If the panel is not in power off state, this function will return 2998 * immediately. 2999 */ 3000 bool dc_link_wait_for_t12(struct dc_link *link); 3001 3002 /* Determine if dp trace has been initialized to reflect upto date result * 3003 * return - true if trace is initialized and has valid data. False dp trace 3004 * doesn't have valid result. 3005 */ 3006 bool dc_dp_trace_is_initialized(struct dc_link *link); 3007 3008 /* Query a dp trace flag to indicate if the current dp trace data has been 3009 * logged before 3010 */ 3011 bool dc_dp_trace_is_logged(struct dc_link *link, 3012 bool in_detection); 3013 3014 /* Set dp trace flag to indicate whether DM has already logged the current dp 3015 * trace data. DM can set is_logged to true upon logging and check 3016 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 3017 */ 3018 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 3019 bool in_detection, 3020 bool is_logged); 3021 3022 /* Obtain driver time stamp for last dp link training end. The time stamp is 3023 * formatted based on dm_get_timestamp DM function. 3024 * @in_detection - true to get link training end time stamp of last link 3025 * training in detection sequence. false to get link training end time stamp 3026 * of last link training in commit (dpms) sequence 3027 */ 3028 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 3029 bool in_detection); 3030 3031 /* Get how many link training attempts dc has done with latest sequence. 3032 * @in_detection - true to get link training count of last link 3033 * training in detection sequence. false to get link training count of last link 3034 * training in commit (dpms) sequence 3035 */ 3036 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 3037 bool in_detection); 3038 3039 /* Get how many link loss has happened since last link training attempts */ 3040 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 3041 3042 /* 3043 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 3044 */ 3045 /* 3046 * Send a request from DP-Tx requesting to allocate BW remotely after 3047 * allocating it locally. This will get processed by CM and a CB function 3048 * will be called. 3049 * 3050 * @link: pointer to the dc_link struct instance 3051 * @req_bw: The requested bw in Kbyte to allocated 3052 * 3053 * return: none 3054 */ 3055 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 3056 3057 /* 3058 * Handle the USB4 BW Allocation related functionality here: 3059 * Plug => Try to allocate max bw from timing parameters supported by the sink 3060 * Unplug => de-allocate bw 3061 * 3062 * @link: pointer to the dc_link struct instance 3063 * @peak_bw: Peak bw used by the link/sink 3064 * 3065 */ 3066 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 3067 struct dc_link *link, int peak_bw); 3068 3069 /* 3070 * Calculates the DP tunneling bandwidth required for the stream timing 3071 * and aggregates the stream bandwidth for the respective DP tunneling link 3072 * 3073 * return: dc_status 3074 */ 3075 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 3076 3077 /* 3078 * Get if ALPM is supported by the link 3079 */ 3080 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 3081 bool *auxwake_support); 3082 3083 /* Sink Interfaces - A sink corresponds to a display output device */ 3084 3085 struct dc_container_id { 3086 // 128bit GUID in binary form 3087 unsigned char guid[16]; 3088 // 8 byte port ID -> ELD.PortID 3089 unsigned int portId[2]; 3090 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 3091 unsigned short manufacturerName; 3092 // 2 byte product code -> ELD.ProductCode 3093 unsigned short productCode; 3094 }; 3095 3096 3097 struct dc_sink_dsc_caps { 3098 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 3099 // 'false' if they are sink's DSC caps 3100 bool is_virtual_dpcd_dsc; 3101 // 'true' if MST topology supports DSC passthrough for sink 3102 // 'false' if MST topology does not support DSC passthrough 3103 bool is_dsc_passthrough_supported; 3104 struct dsc_dec_dpcd_caps dsc_dec_caps; 3105 }; 3106 3107 struct dc_sink_hblank_expansion_caps { 3108 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 3109 // 'false' if they are sink's HBlank expansion caps 3110 bool is_virtual_dpcd_hblank_expansion; 3111 struct hblank_expansion_dpcd_caps dpcd_caps; 3112 }; 3113 3114 struct dc_sink_fec_caps { 3115 bool is_rx_fec_supported; 3116 bool is_topology_fec_supported; 3117 }; 3118 3119 struct scdc_caps { 3120 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 3121 union hdmi_scdc_device_id_data device_id; 3122 }; 3123 3124 /* 3125 * The sink structure contains EDID and other display device properties 3126 */ 3127 struct dc_sink { 3128 enum signal_type sink_signal; 3129 struct dc_edid dc_edid; /* raw edid */ 3130 struct dc_edid_caps edid_caps; /* parse display caps */ 3131 struct dc_container_id *dc_container_id; 3132 uint32_t dongle_max_pix_clk; 3133 void *priv; 3134 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 3135 bool converter_disable_audio; 3136 3137 struct mccs_caps mccs_caps; 3138 struct scdc_caps scdc_caps; 3139 struct dc_sink_dsc_caps dsc_caps; 3140 struct dc_sink_fec_caps fec_caps; 3141 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 3142 3143 bool is_vsc_sdp_colorimetry_supported; 3144 3145 /* private to DC core */ 3146 struct dc_link *link; 3147 struct dc_context *ctx; 3148 3149 uint32_t sink_id; 3150 3151 /* private to dc_sink.c */ 3152 // refcount must be the last member in dc_sink, since we want the 3153 // sink structure to be logically cloneable up to (but not including) 3154 // refcount 3155 struct kref refcount; 3156 }; 3157 3158 void dc_sink_retain(struct dc_sink *sink); 3159 void dc_sink_release(struct dc_sink *sink); 3160 3161 struct dc_sink_init_data { 3162 enum signal_type sink_signal; 3163 struct dc_link *link; 3164 uint32_t dongle_max_pix_clk; 3165 bool converter_disable_audio; 3166 }; 3167 3168 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 3169 3170 /* Newer interfaces */ 3171 struct dc_cursor { 3172 struct dc_plane_address address; 3173 struct dc_cursor_attributes attributes; 3174 }; 3175 3176 3177 /* Interrupt interfaces */ 3178 enum dc_irq_source dc_interrupt_to_irq_source( 3179 struct dc *dc, 3180 uint32_t src_id, 3181 uint32_t ext_id); 3182 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 3183 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 3184 bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst); 3185 enum dc_irq_source dc_get_hpd_irq_source_at_index( 3186 struct dc *dc, uint32_t link_index); 3187 3188 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 3189 3190 /* Power Interfaces */ 3191 3192 void dc_set_power_state( 3193 struct dc *dc, 3194 enum dc_acpi_cm_power_state power_state); 3195 void dc_resume(struct dc *dc); 3196 3197 void dc_power_down_on_boot(struct dc *dc); 3198 3199 void dc_disable_dangling_timing_generators(struct dc *dc); 3200 3201 /* 3202 * HDCP Interfaces 3203 */ 3204 enum hdcp_message_status dc_process_hdcp_msg( 3205 enum signal_type signal, 3206 struct dc_link *link, 3207 struct hdcp_protection_message *message_info); 3208 bool dc_is_dmcu_initialized(struct dc *dc); 3209 3210 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 3211 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 3212 3213 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 3214 unsigned int pitch, 3215 unsigned int height, 3216 enum surface_pixel_format format, 3217 struct dc_cursor_attributes *cursor_attr); 3218 3219 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 3220 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 3221 3222 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 3223 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 3224 bool dc_dmub_is_ips_idle_state(struct dc *dc); 3225 3226 /* set min and max memory clock to lowest and highest DPM level, respectively */ 3227 void dc_unlock_memory_clock_frequency(struct dc *dc); 3228 3229 /* set min memory clock to the min required for current mode, max to maxDPM */ 3230 void dc_lock_memory_clock_frequency(struct dc *dc); 3231 3232 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 3233 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 3234 3235 /* cleanup on driver unload */ 3236 void dc_hardware_release(struct dc *dc); 3237 3238 /* disables fw based mclk switch */ 3239 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 3240 3241 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 3242 3243 bool dc_set_replay_allow_active(struct dc *dc, bool active); 3244 3245 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 3246 3247 void dc_z10_restore(const struct dc *dc); 3248 void dc_z10_save_init(struct dc *dc); 3249 3250 bool dc_is_dmub_outbox_supported(struct dc *dc); 3251 bool dc_enable_dmub_notifications(struct dc *dc); 3252 3253 bool dc_abm_save_restore( 3254 struct dc *dc, 3255 struct dc_stream_state *stream, 3256 struct abm_save_restore *pData); 3257 3258 void dc_enable_dmub_outbox(struct dc *dc); 3259 3260 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 3261 uint32_t link_index, 3262 struct aux_payload *payload); 3263 3264 /* 3265 * smart power OLED Interfaces 3266 */ 3267 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 3268 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 3269 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 3270 3271 /* Get dc link index from dpia port index */ 3272 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 3273 uint8_t dpia_port_index); 3274 3275 bool dc_process_dmub_set_config_async(struct dc *dc, 3276 uint32_t link_index, 3277 struct set_config_cmd_payload *payload, 3278 struct dmub_notification *notify); 3279 3280 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 3281 uint32_t link_index, 3282 uint8_t mst_alloc_slots, 3283 uint8_t *mst_slots_in_use); 3284 3285 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 3286 3287 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 3288 uint32_t hpd_int_enable); 3289 3290 void dc_print_dmub_diagnostic_data(const struct dc *dc); 3291 3292 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 3293 3294 struct dc_power_profile { 3295 int power_level; /* Lower is better */ 3296 }; 3297 3298 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 3299 3300 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 3301 3302 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 3303 3304 void dc_log_preos_dmcub_info(const struct dc *dc); 3305 3306 /* DSC Interfaces */ 3307 #include "dc_dsc.h" 3308 3309 void dc_get_visual_confirm_for_stream( 3310 struct dc *dc, 3311 struct dc_stream_state *stream_state, 3312 struct tg_color *color); 3313 3314 /* Disable acc mode Interfaces */ 3315 void dc_disable_accelerated_mode(struct dc *dc); 3316 3317 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 3318 struct dc_stream_state *new_stream); 3319 3320 bool dc_is_cursor_limit_pending(struct dc *dc); 3321 bool dc_can_clear_cursor_limit(const struct dc *dc); 3322 3323 /** 3324 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 3325 * 3326 * @dc: Pointer to the display core context. 3327 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 3328 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 3329 * 3330 * This function collects and logs underflow-related HW states when underflow happens, 3331 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 3332 * The results are stored in the provided out_data structure for further analysis or logging. 3333 */ 3334 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); 3335 3336 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); 3337 3338 /* 3339 * Software state variables used to program register fields across the display pipeline 3340 */ 3341 struct dc_register_software_state { 3342 /* HUBP register programming variables for each pipe */ 3343 struct { 3344 bool valid_plane_state; 3345 bool valid_stream; 3346 bool min_dc_gfx_version9; 3347 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 3348 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 3349 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 3350 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 3351 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 3352 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 3353 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 3354 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 3355 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 3356 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 3357 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 3358 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 3359 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 3360 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 3361 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 3362 3363 /* Additional DCC configuration */ 3364 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 3365 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 3366 3367 /* Surface pitch configuration */ 3368 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 3369 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 3370 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 3371 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 3372 3373 /* Surface addresses */ 3374 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 3375 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 3376 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 3377 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 3378 3379 /* TMZ configuration */ 3380 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 3381 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 3382 3383 /* Tiling configuration */ 3384 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 3385 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 3386 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 3387 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 3388 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 3389 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 3390 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 3391 3392 /* DML Request Size Configuration - Luma */ 3393 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 3394 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 3395 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 3396 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 3397 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 3398 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 3399 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 3400 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 3401 3402 /* DML Request Size Configuration - Chroma */ 3403 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 3404 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 3405 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 3406 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 3407 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 3408 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 3409 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 3410 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 3411 3412 /* DML Expansion Modes */ 3413 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 3414 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 3415 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 3416 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 3417 3418 /* DML DLG parameters - nominal */ 3419 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 3420 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 3421 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 3422 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 3423 3424 /* DML prefetch settings */ 3425 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 3426 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 3427 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 3428 3429 /* TTU parameters */ 3430 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 3431 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 3432 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 3433 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 3434 } hubp[MAX_PIPES]; 3435 3436 /* HUBBUB register programming variables */ 3437 struct { 3438 /* Individual DET buffer control per pipe - software state that programs DET registers */ 3439 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 3440 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 3441 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 3442 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 3443 3444 /* Compression buffer control - software state that programs COMPBUF registers */ 3445 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 3446 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 3447 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 3448 } hubbub; 3449 3450 /* DPP register programming variables for each pipe (simplified for available fields) */ 3451 struct { 3452 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 3453 3454 /* Recout (Rectangle of Interest) configuration */ 3455 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 3456 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 3457 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 3458 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 3459 3460 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 3461 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 3462 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 3463 3464 /* DSCL mode configuration */ 3465 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3466 3467 /* Scaler ratios (simplified to integer parts) */ 3468 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3469 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3470 3471 /* Basic scaler taps */ 3472 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3473 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3474 } dpp[MAX_PIPES]; 3475 3476 /* DCCG register programming variables */ 3477 struct { 3478 /* Core Display Clock Control */ 3479 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3480 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3481 3482 /* DPP Clock Control - 4 fields per pipe */ 3483 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3484 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3485 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3486 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3487 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3488 3489 /* DSC Clock Control - 4 fields per DSC resource */ 3490 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3491 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3492 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3493 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3494 3495 /* Pixel Clock Control - per pipe */ 3496 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3497 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3498 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3499 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3500 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3501 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3502 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3503 3504 /* DTBCLK DTO Control - 4 DTOs */ 3505 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3506 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3507 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3508 3509 /* DP Stream Clock Control - 4 pipes */ 3510 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3511 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3512 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3513 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3514 3515 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3516 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3517 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3518 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3519 3520 /* SYMCLK32 SE Control - 4 instances */ 3521 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3522 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3523 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3524 3525 /* SYMCLK32 LE Control - 2 instances */ 3526 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3527 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3528 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3529 3530 /* HDMI Clock Control */ 3531 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */ 3532 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */ 3533 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */ 3534 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */ 3535 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */ 3536 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */ 3537 3538 /* DPIA Clock Control */ 3539 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3540 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3541 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3542 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3543 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3544 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3545 3546 /* Clock Gating Control */ 3547 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3548 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3549 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3550 3551 /* VSync Control */ 3552 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3553 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3554 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3555 3556 /* Time Base Control */ 3557 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3558 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3559 } dccg; 3560 3561 /* DSC essential configuration for underflow analysis */ 3562 struct { 3563 /* DSC active state - critical for bandwidth analysis */ 3564 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3565 3566 /* DSC configuration affecting bandwidth and timing */ 3567 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3568 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3569 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3570 3571 /* OPP integration - affects pipeline flow */ 3572 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3573 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3574 } dsc[MAX_PIPES]; 3575 3576 /* MPC register programming variables */ 3577 struct { 3578 /* MPCC blending tree and mode control */ 3579 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3580 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3581 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3582 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3583 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3584 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3585 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3586 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3587 3588 /* MPCC blending tree connections */ 3589 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3590 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3591 3592 /* MPCC output gamma control */ 3593 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3594 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3595 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3596 3597 /* MPCC pipe assignment and status */ 3598 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3599 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3600 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3601 3602 /* MPC output processing */ 3603 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3604 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3605 } mpc; 3606 3607 /* OPP register programming variables for each pipe */ 3608 struct { 3609 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3610 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3611 3612 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3613 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3614 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3615 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3616 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3617 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3618 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3619 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3620 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3621 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3622 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3623 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3624 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3625 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3626 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3627 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3628 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3629 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3630 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3631 3632 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3633 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3634 3635 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3636 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3637 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3638 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3639 3640 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3641 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3642 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3643 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3644 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3645 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3646 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3647 3648 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3649 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3650 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3651 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3652 } opp[MAX_PIPES]; 3653 3654 /* OPTC register programming variables for each pipe */ 3655 struct { 3656 uint32_t otg_master_inst; 3657 3658 /* OTG_CONTROL register - 5 fields for OTG control */ 3659 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3660 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3661 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3662 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3663 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3664 3665 /* OTG Horizontal Timing - 7 fields */ 3666 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3667 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3668 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3669 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3670 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3671 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3672 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3673 3674 /* OTG Vertical Timing - 7 fields */ 3675 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3676 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3677 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3678 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3679 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3680 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3681 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3682 3683 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3684 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3685 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3686 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3687 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3688 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3689 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3690 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3691 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3692 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3693 3694 /* OPTC Data Source and ODM - 6 fields */ 3695 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3696 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3697 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3698 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3699 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3700 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3701 3702 /* OPTC Data Format and DSC - 4 fields */ 3703 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3704 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3705 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3706 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3707 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3708 3709 /* OPTC Clock and Underflow Control - 4 fields */ 3710 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3711 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3712 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3713 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3714 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3715 3716 /* OTG Stereo and 3D Control - 6 fields */ 3717 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3718 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3719 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3720 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3721 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3722 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3723 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3724 3725 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3726 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3727 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3728 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3729 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3730 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3731 3732 /* OTG DRR Advanced Control - 4 fields */ 3733 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3734 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3735 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3736 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3737 3738 /* OTG DSC Position Control - 2 fields */ 3739 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3740 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3741 3742 /* OTG Double Buffer Control - 2 fields */ 3743 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3744 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3745 3746 /* OTG Vertical Interrupts - 6 fields */ 3747 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3748 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3749 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3750 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3751 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3752 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3753 3754 /* OTG Global Sync Parameters - 6 fields */ 3755 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3756 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3757 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3758 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3759 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3760 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3761 3762 /* OTG Manual Trigger Control - 11 fields */ 3763 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3764 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3765 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3766 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3767 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3768 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3769 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3770 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3771 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3772 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3773 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3774 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3775 3776 /* OTG Static Screen and Update Control - 6 fields */ 3777 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3778 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3779 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3780 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3781 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3782 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3783 3784 /* VTG Control - 3 fields */ 3785 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3786 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3787 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3788 3789 /* OTG Status (Read-Only) - 12 fields */ 3790 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3791 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3792 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3793 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3794 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3795 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3796 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3797 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3798 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3799 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3800 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3801 } optc[MAX_PIPES]; 3802 3803 /* Metadata */ 3804 uint32_t active_pipe_count; 3805 uint32_t active_stream_count; 3806 bool state_valid; 3807 }; 3808 3809 /** 3810 * dc_capture_register_software_state() - Capture software state for register programming 3811 * @dc: DC context containing current display configuration 3812 * @state: Pointer to dc_register_software_state structure to populate 3813 * 3814 * Extracts all software state variables that are used to program hardware register 3815 * fields across the display driver pipeline. This provides a complete snapshot 3816 * of the software configuration that drives hardware register programming. 3817 * 3818 * The function traverses the DC context and extracts values from: 3819 * - Stream configurations (timing, format, DSC settings) 3820 * - Plane states (surface format, rotation, scaling, cursor) 3821 * - Pipe contexts (resource allocation, blending, viewport) 3822 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3823 * - Resource context (DET buffer allocation, ODM configuration) 3824 * 3825 * This is essential for underflow debugging as it captures the exact software 3826 * state that determines how registers are programmed, allowing analysis of 3827 * whether underflow is caused by incorrect register programming or timing issues. 3828 * 3829 * Return: true if state was successfully captured, false on error 3830 */ 3831 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3832 3833 /** 3834 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3835 * @dc: DC context containing current display configuration 3836 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3837 * 3838 * This function retrieves QoS metrics from the display core that can be used by 3839 * benchmark tools to analyze display system performance. The function may take 3840 * several milliseconds to execute due to hardware measurement requirements. 3841 * 3842 * QoS information includes: 3843 * - Bandwidth bounds (lower limits in Mbps) 3844 * - Latency bounds (upper limits in nanoseconds) 3845 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3846 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3847 * 3848 * The function will populate the provided dc_qos_info structure with current 3849 * QoS measurements. If hardware measurement functions are not available for 3850 * the current DCN version, the function returns false with zero'd info structure. 3851 * 3852 * Return: true if QoS information was successfully retrieved, false if measurement 3853 * functions are unavailable or hardware measurements cannot be performed 3854 */ 3855 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3856 3857 /** 3858 * dc_override_memory_bandwidth_request - Override the DCN nominal memory 3859 * bandwidth request sent to PMFW, independent of the current display mode. 3860 * For debug use only. 3861 * @dc: DC instance 3862 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override 3863 * 3864 * Return: capped bandwidth value actually applied (MB/s) 3865 */ 3866 unsigned int dc_override_memory_bandwidth_request( 3867 struct dc *dc, 3868 unsigned int bw_mbps); 3869 3870 #endif /* DC_INTERFACE_H_ */ 3871