1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "dc_probe.h" 33 #include "grph_object_defs.h" 34 #include "logger_types.h" 35 #include "hdcp_msg_types.h" 36 #include "gpio_types.h" 37 #include "link_service_types.h" 38 #include "grph_object_ctrl_defs.h" 39 #include <inc/hw/opp.h> 40 41 #include "hwss/hw_sequencer.h" 42 #include "inc/compressor.h" 43 #include "inc/hw/dmcu.h" 44 #include "dml/display_mode_lib.h" 45 46 #include "dml2_0/dml2_wrapper.h" 47 48 #include "dmub/inc/dmub_cmd.h" 49 50 #include "dml/dml1_frl_cap_chk.h" 51 52 #include "sspl/dc_spl_types.h" 53 54 struct abm_save_restore; 55 56 /* forward declaration */ 57 struct aux_payload; 58 struct set_config_cmd_payload; 59 struct dmub_notification; 60 struct dcn_hubbub_reg_state; 61 struct dcn_hubp_reg_state; 62 struct dcn_dpp_reg_state; 63 struct dcn_mpc_reg_state; 64 struct dcn_opp_reg_state; 65 struct dcn_dsc_reg_state; 66 struct dcn_optc_reg_state; 67 struct dcn_dccg_reg_state; 68 69 #define DC_VER "3.2.391" 70 71 /** 72 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 73 */ 74 #define MAX_SURFACES 4 75 /** 76 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 77 */ 78 #define MAX_PLANES 6 79 #define MAX_STREAMS 6 80 #define MIN_VIEWPORT_SIZE 12 81 #define MAX_NUM_EDP 2 82 #define MAX_SUPPORTED_FORMATS 7 83 84 #define MAX_HOST_ROUTERS_NUM 3 85 #define MAX_DPIA_PER_HOST_ROUTER 3 86 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 87 88 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 89 90 struct frl_cap_chk_intermediates_fixed31_32 { 91 int c_frl_sb; 92 struct fixed31_32 overhead_sb; 93 struct fixed31_32 overhead_rs; 94 struct fixed31_32 overhead_map; 95 struct fixed31_32 overhead_min; 96 struct fixed31_32 overhead_max; 97 struct fixed31_32 f_pixel_clock_max; 98 struct fixed31_32 t_line; 99 struct fixed31_32 r_bit_min; 100 struct fixed31_32 r_frl_char_min; 101 struct fixed31_32 c_frl_line; 102 struct fixed31_32 ap; 103 struct fixed31_32 r_ap; 104 struct fixed31_32 avg_audio_packets_line; 105 struct fixed31_32 margin; 106 int audio_packets_line; 107 int blank_audio_min; 108 }; 109 110 struct frl_cap_chk_params_fixed31_32 { 111 int lanes; 112 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 113 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ 114 int audio_packet_type; 115 struct fixed31_32 f_audio; /* Audio rate (Hz) */ 116 int h_active; /* Active pixels per line */ 117 int h_blank; /* Blanking pixels per line */ 118 int bpc; /* Bits per component */ 119 int vic; /* Video Identification Code */ 120 121 enum hdmi_frl_pixel_encoding pixel_encoding; 122 123 bool compressed; /* set to true if DSC is enabled */ 124 bool bypass_hc_target_calc; /* debug only */ 125 bool allow_all_bpp; /* dsc_all_bpp */ 126 127 /* DSC parameters */ 128 int slices; 129 int slice_width; 130 struct fixed31_32 bpp_target; 131 int layout; 132 int acat; /* not supported */ 133 134 /* outputs */ 135 struct frl_dml_borrow_params borrow_params; 136 int average_tribyte_rate; 137 }; 138 139 /* Display Core Interfaces */ 140 struct dc_versions { 141 const char *dc_ver; 142 struct dmcu_version dmcu_version; 143 }; 144 145 enum dp_protocol_version { 146 DP_VERSION_1_4 = 0, 147 DP_VERSION_2_1, 148 DP_VERSION_UNKNOWN, 149 }; 150 151 enum dc_plane_type { 152 DC_PLANE_TYPE_INVALID, 153 DC_PLANE_TYPE_DCE_RGB, 154 DC_PLANE_TYPE_DCE_UNDERLAY, 155 DC_PLANE_TYPE_DCN_UNIVERSAL, 156 }; 157 158 // Sizes defined as multiples of 64KB 159 enum det_size { 160 DET_SIZE_DEFAULT = 0, 161 DET_SIZE_192KB = 3, 162 DET_SIZE_256KB = 4, 163 DET_SIZE_320KB = 5, 164 DET_SIZE_384KB = 6 165 }; 166 167 168 struct dc_plane_cap { 169 enum dc_plane_type type; 170 uint32_t per_pixel_alpha : 1; 171 struct { 172 uint32_t argb8888 : 1; 173 uint32_t nv12 : 1; 174 uint32_t fp16 : 1; 175 uint32_t p010 : 1; 176 uint32_t ayuv : 1; 177 uint32_t yuy2 : 1; // Packed 422 8bpc 178 uint32_t y210 : 1; // Packed 422 10bpc 179 uint32_t y212 : 1; // Packed 422 12bpc 180 uint32_t p208 : 1; // Planar 422 8bpc 181 uint32_t p210 : 1; // Planar 422 10bpc 182 uint32_t p212 : 1; // Planar 422 12bpc 183 /* Not all caps will be used/supported */ 184 } pixel_format_support; 185 // max upscaling factor x1000 186 // upscaling factors are always >= 1 187 // for example, 1080p -> 8K is 4.0, or 4000 raw value 188 struct { 189 uint32_t argb8888; 190 uint32_t nv12; 191 uint32_t fp16; 192 } max_upscale_factor; 193 // max downscale factor x1000 194 // downscale factors are always <= 1 195 // for example, 8K -> 1080p is 0.25, or 250 raw value 196 struct { 197 uint32_t argb8888; 198 uint32_t nv12; 199 uint32_t fp16; 200 } max_downscale_factor; 201 // minimal width/height 202 uint32_t min_width; 203 uint32_t min_height; 204 }; 205 206 /** 207 * DOC: color-management-caps 208 * 209 * **Color management caps (DPP and MPC)** 210 * 211 * Modules/color calculates various color operations which are translated to 212 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 213 * DCN1, every new generation comes with fairly major differences in color 214 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 215 * decide mapping to HW block based on logical capabilities. 216 */ 217 218 /** 219 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 220 * @srgb: RGB color space transfer func 221 * @bt2020: BT.2020 transfer func 222 * @gamma2_2: standard gamma 223 * @pq: perceptual quantizer transfer function 224 * @hlg: hybrid log–gamma transfer function 225 */ 226 struct rom_curve_caps { 227 uint16_t srgb : 1; 228 uint16_t bt2020 : 1; 229 uint16_t gamma2_2 : 1; 230 uint16_t pq : 1; 231 uint16_t hlg : 1; 232 }; 233 234 /** 235 * struct dpp_color_caps - color pipeline capabilities for display pipe and 236 * plane blocks 237 * 238 * @dcn_arch: all DCE generations treated the same 239 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 240 * just plain 256-entry lookup 241 * @icsc: input color space conversion 242 * @dgam_ram: programmable degamma LUT 243 * @post_csc: post color space conversion, before gamut remap 244 * @gamma_corr: degamma correction 245 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 246 * with MPC by setting mpc:shared_3d_lut flag 247 * @ogam_ram: programmable out/blend gamma LUT 248 * @ocsc: output color space conversion 249 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 250 * @upsp_pre_scaler: Ability to upsample 420/422 before scaling 251 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 252 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 253 * 254 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 255 */ 256 struct dpp_color_caps { 257 uint16_t dcn_arch : 1; 258 uint16_t input_lut_shared : 1; 259 uint16_t icsc : 1; 260 uint16_t dgam_ram : 1; 261 uint16_t post_csc : 1; 262 uint16_t gamma_corr : 1; 263 uint16_t hw_3d_lut : 1; 264 uint16_t ogam_ram : 1; 265 uint16_t ocsc : 1; 266 uint16_t dgam_rom_for_yuv : 1; 267 uint16_t upsp_pre_scaler : 1; 268 struct rom_curve_caps dgam_rom_caps; 269 struct rom_curve_caps ogam_rom_caps; 270 }; 271 272 /* Below structure is to describe the HW support for mem layout, extend support 273 range to match what OS could handle in the roadmap */ 274 struct lut3d_caps { 275 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 276 struct { 277 uint32_t swizzle_3d_rgb : 1; 278 uint32_t swizzle_3d_bgr : 1; 279 uint32_t linear_1d : 1; 280 } mem_layout_support; 281 struct { 282 uint32_t unorm_12msb : 1; 283 uint32_t unorm_12lsb : 1; 284 uint32_t float_fp1_5_10 : 1; 285 } mem_format_support; 286 struct { 287 uint32_t order_rgba : 1; 288 uint32_t order_bgra : 1; 289 } mem_pixel_order_support; 290 /*< size options are 9, 17, 33, 45, 65 */ 291 struct { 292 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 293 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 294 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 295 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 296 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 297 } lut_dim_caps; 298 }; 299 300 /** 301 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 302 * plane combined blocks 303 * 304 * @gamut_remap: color transformation matrix 305 * @ogam_ram: programmable out gamma LUT 306 * @ocsc: output color space conversion matrix 307 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 308 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 309 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 310 * instance 311 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 312 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 313 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 314 * @preblend: whether color manager supports preblend with MPC 315 */ 316 struct mpc_color_caps { 317 uint16_t gamut_remap : 1; 318 uint16_t ogam_ram : 1; 319 uint16_t ocsc : 1; 320 uint16_t num_3dluts : 3; 321 uint16_t num_rmcm_3dluts : 3; 322 uint16_t shared_3d_lut:1; 323 struct rom_curve_caps ogam_rom_caps; 324 struct lut3d_caps mcm_3d_lut_caps; 325 struct lut3d_caps rmcm_3d_lut_caps; 326 bool preblend; 327 struct fixed31_32 max_gamut_remap_coeff; 328 }; 329 330 /** 331 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 332 * @dpp: color pipes caps for DPP 333 * @mpc: color pipes caps for MPC 334 */ 335 struct dc_color_caps { 336 struct dpp_color_caps dpp; 337 struct mpc_color_caps mpc; 338 }; 339 340 struct dc_dmub_caps { 341 bool psr; 342 bool mclk_sw; 343 bool subvp_psr; 344 bool gecc_enable; 345 uint8_t fams_ver; 346 bool aux_backlight_support; 347 }; 348 349 struct dc_scl_caps { 350 bool sharpener_support; 351 }; 352 353 struct dc_check_config { 354 /** 355 * max video plane width that can be safely assumed to be always 356 * supported by single DPP pipe. 357 */ 358 unsigned int max_optimizable_video_width; 359 bool enable_legacy_fast_update; 360 361 bool deferred_transition_state; 362 unsigned int transition_countdown_to_steady_state; 363 }; 364 365 struct dc_caps { 366 uint32_t max_streams; 367 uint32_t max_links; 368 uint32_t max_audios; 369 uint32_t max_slave_planes; 370 uint32_t max_slave_yuv_planes; 371 uint32_t max_slave_rgb_planes; 372 uint32_t max_planes; 373 uint32_t max_downscale_ratio; 374 uint32_t i2c_speed_in_khz; 375 uint32_t i2c_speed_in_khz_hdcp; 376 uint32_t dmdata_alloc_size; 377 unsigned int max_cursor_size; 378 unsigned int max_buffered_cursor_size; 379 unsigned int max_video_width; 380 unsigned int min_horizontal_blanking_period; 381 int linear_pitch_alignment; 382 bool dcc_const_color; 383 bool dynamic_audio; 384 bool is_apu; 385 bool dual_link_dvi; 386 bool post_blend_color_processing; 387 bool force_dp_tps4_for_cp2520; 388 bool disable_dp_clk_share; 389 bool psp_setup_panel_mode; 390 bool extended_aux_timeout_support; 391 bool dmcub_support; 392 bool zstate_support; 393 bool ips_support; 394 bool ips_v2_support; 395 uint32_t num_of_internal_disp; 396 enum dp_protocol_version max_dp_protocol_version; 397 bool hdmi_hpo; 398 unsigned int mall_size_per_mem_channel; 399 unsigned int mall_size_total; 400 unsigned int cursor_cache_size; 401 struct dc_plane_cap planes[MAX_PLANES]; 402 struct dc_color_caps color; 403 struct dc_dmub_caps dmub_caps; 404 bool dp_hpo; 405 bool dp_hdmi21_pcon_support; 406 bool edp_dsc_support; 407 bool vbios_lttpr_aware; 408 bool vbios_lttpr_enable; 409 bool fused_io_supported; 410 uint32_t max_otg_num; 411 uint32_t max_cab_allocation_bytes; 412 uint32_t cache_line_size; 413 uint32_t cache_num_ways; 414 uint16_t subvp_fw_processing_delay_us; 415 uint8_t subvp_drr_max_vblank_margin_us; 416 uint16_t subvp_prefetch_end_to_mall_start_us; 417 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 418 uint16_t subvp_pstate_allow_width_us; 419 uint16_t subvp_vertical_int_margin_us; 420 bool seamless_odm; 421 uint32_t max_v_total; 422 bool vtotal_limited_by_fp2; 423 uint32_t max_disp_clock_khz_at_vmin; 424 uint8_t subvp_drr_vblank_start_margin_us; 425 bool cursor_not_scaled; 426 bool dcmode_power_limits_present; 427 bool sequential_ono; 428 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 429 uint32_t dcc_plane_width_limit; 430 struct dc_scl_caps scl_caps; 431 uint8_t num_of_host_routers; 432 uint8_t num_of_dpias_per_host_router; 433 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 434 uint8_t max_odm_combine_factor; 435 }; 436 437 struct dc_bug_wa { 438 bool no_connect_phy_config; 439 bool dedcn20_305_wa; 440 bool skip_clock_update; 441 bool lt_early_cr_pattern; 442 struct { 443 uint8_t uclk : 1; 444 uint8_t fclk : 1; 445 uint8_t dcfclk : 1; 446 uint8_t dcfclk_ds: 1; 447 } clock_update_disable_mask; 448 bool skip_psr_ips_crtc_disable; 449 }; 450 struct dc_dcc_surface_param { 451 struct dc_size surface_size; 452 enum surface_pixel_format format; 453 unsigned int plane0_pitch; 454 struct dc_size plane1_size; 455 unsigned int plane1_pitch; 456 union { 457 enum swizzle_mode_values swizzle_mode; 458 enum swizzle_mode_addr3_values swizzle_mode_addr3; 459 }; 460 enum dc_scan_direction scan; 461 }; 462 463 struct dc_dcc_setting { 464 unsigned int max_compressed_blk_size; 465 unsigned int max_uncompressed_blk_size; 466 bool independent_64b_blks; 467 //These bitfields to be used starting with DCN 3.0 468 struct { 469 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 470 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 471 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 472 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 473 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 474 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 475 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 476 } dcc_controls; 477 }; 478 479 struct dc_surface_dcc_cap { 480 union { 481 struct { 482 struct dc_dcc_setting rgb; 483 } grph; 484 485 struct { 486 struct dc_dcc_setting luma; 487 struct dc_dcc_setting chroma; 488 } video; 489 }; 490 491 bool capable; 492 bool const_color_support; 493 }; 494 495 struct dc_static_screen_params { 496 struct { 497 bool force_trigger; 498 bool cursor_update; 499 bool surface_update; 500 bool overlay_update; 501 } triggers; 502 unsigned int num_frames; 503 }; 504 505 506 /* Surface update type is used by dc_update_surfaces_and_stream 507 * The update type is determined at the very beginning of the function based 508 * on parameters passed in and decides how much programming (or updating) is 509 * going to be done during the call. 510 * 511 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 512 * logical calculations or hardware register programming. This update MUST be 513 * ISR safe on windows. Currently fast update will only be used to flip surface 514 * address. 515 * 516 * UPDATE_TYPE_MED is used for slower updates which require significant hw 517 * re-programming however do not affect bandwidth consumption or clock 518 * requirements. At present, this is the level at which front end updates 519 * that do not require us to run bw_calcs happen. These are in/out transfer func 520 * updates, viewport offset changes, recout size changes and pixel depth changes. 521 * This update can be done at ISR, but we want to minimize how often this happens. 522 * 523 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 524 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 525 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 526 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 527 * a full update. This cannot be done at ISR level and should be a rare event. 528 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 529 * underscan we don't expect to see this call at all. 530 */ 531 532 enum dc_update_type { 533 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 534 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 535 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 536 }; 537 538 enum dc_lock_descriptor { 539 LOCK_DESCRIPTOR_NONE = 0x0, 540 LOCK_DESCRIPTOR_STREAM = 0x1, 541 LOCK_DESCRIPTOR_LINK = 0x2, 542 LOCK_DESCRIPTOR_GLOBAL = 0x4, 543 LOCK_DESCRIPTOR_PROBE = 0x8, 544 }; 545 546 struct dc_update_descriptor { 547 enum dc_update_type update_type; 548 enum dc_lock_descriptor lock_descriptor; 549 }; 550 551 /* Forward declaration*/ 552 struct dc; 553 struct dc_plane_state; 554 struct dc_state; 555 556 struct dc_cap_funcs { 557 bool (*get_dcc_compression_cap)(const struct dc *dc, 558 const struct dc_dcc_surface_param *input, 559 struct dc_surface_dcc_cap *output); 560 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 561 }; 562 563 struct link_training_settings; 564 565 union allow_lttpr_non_transparent_mode { 566 struct { 567 bool DP1_4A : 1; 568 bool DP2_0 : 1; 569 } bits; 570 unsigned char raw; 571 }; 572 /* Structure to hold configuration flags set by dm at dc creation. */ 573 struct dc_config { 574 bool gpu_vm_support; 575 bool disable_disp_pll_sharing; 576 bool fbc_support; 577 bool disable_fractional_pwm; 578 bool allow_seamless_boot_optimization; 579 bool seamless_boot_edp_requested; 580 bool edp_not_connected; 581 bool edp_no_power_sequencing; 582 bool force_enum_edp; 583 bool forced_clocks; 584 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 585 bool multi_mon_pp_mclk_switch; 586 bool disable_dmcu; 587 bool allow_4to1MPC; 588 bool enable_windowed_mpo_odm; 589 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 590 uint32_t allow_edp_hotplug_detection; 591 bool skip_riommu_prefetch_wa; 592 bool clamp_min_dcfclk; 593 uint64_t vblank_alignment_dto_params; 594 uint8_t vblank_alignment_max_frame_time_diff; 595 bool is_asymmetric_memory; 596 bool is_single_rank_dimm; 597 bool is_vmin_only_asic; 598 bool use_spl; 599 bool prefer_easf; 600 bool use_pipe_ctx_sync_logic; 601 int smart_mux_version; 602 bool ignore_dpref_ss; 603 bool enable_mipi_converter_optimization; 604 bool enable_frl; 605 bool force_hdmi21_frl_enc_enable; 606 bool use_default_clock_table; 607 bool force_bios_enable_lttpr; 608 uint8_t force_bios_fixed_vs; 609 unsigned int sdpif_request_limit_words_per_umc; 610 bool dc_mode_clk_limit_support; 611 bool EnableMinDispClkODM; 612 bool enable_auto_dpm_test_logs; 613 unsigned int disable_ips; 614 unsigned int disable_ips_rcg; 615 unsigned int disable_ips_in_vpb; 616 bool disable_ips_in_dpms_off; 617 bool usb4_bw_alloc_support; 618 bool allow_0_dtb_clk; 619 bool use_assr_psp_message; 620 bool support_edp0_on_dp1; 621 unsigned int enable_fpo_flicker_detection; 622 bool disable_hbr_audio_dp2; 623 bool consolidated_dpia_dp_lt; 624 bool set_pipe_unlock_order; 625 bool enable_dpia_pre_training; 626 bool unify_link_enc_assignment; 627 bool enable_cursor_offload; 628 bool dp_connector_no_native_i2c; 629 unsigned int link_index_with_no_ddc; 630 bool frame_update_cmd_version2; 631 struct spl_sharpness_range dcn_sharpness_range; 632 struct spl_sharpness_range dcn_override_sharpness_range; 633 bool no_native422_support; 634 }; 635 636 enum visual_confirm { 637 VISUAL_CONFIRM_DISABLE = 0, 638 VISUAL_CONFIRM_SURFACE = 1, 639 VISUAL_CONFIRM_HDR = 2, 640 VISUAL_CONFIRM_MPCTREE = 4, 641 VISUAL_CONFIRM_PSR = 5, 642 VISUAL_CONFIRM_SWAPCHAIN = 6, 643 VISUAL_CONFIRM_FAMS = 7, 644 VISUAL_CONFIRM_SWIZZLE = 9, 645 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 646 VISUAL_CONFIRM_REPLAY = 12, 647 VISUAL_CONFIRM_SUBVP = 14, 648 VISUAL_CONFIRM_ABM = 15, 649 VISUAL_CONFIRM_MCLK_SWITCH = 16, 650 VISUAL_CONFIRM_FAMS2 = 19, 651 VISUAL_CONFIRM_HW_CURSOR = 20, 652 VISUAL_CONFIRM_VABC = 21, 653 VISUAL_CONFIRM_DCC = 22, 654 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, 655 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 656 }; 657 658 enum dc_psr_power_opts { 659 psr_power_opt_invalid = 0x0, 660 psr_power_opt_smu_opt_static_screen = 0x1, 661 psr_power_opt_z10_static_screen = 0x10, 662 psr_power_opt_ds_disable_allow = 0x100, 663 }; 664 665 enum dml_hostvm_override_opts { 666 DML_HOSTVM_NO_OVERRIDE = 0x0, 667 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 668 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 669 }; 670 671 enum dc_replay_power_opts { 672 replay_power_opt_invalid = 0x0, 673 replay_power_opt_smu_opt_static_screen = 0x1, 674 replay_power_opt_z10_static_screen = 0x10, 675 }; 676 677 enum dcc_option { 678 DCC_ENABLE = 0, 679 DCC_DISABLE = 1, 680 DCC_HALF_REQ_DISALBE = 2, 681 }; 682 683 enum in_game_fams_config { 684 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 685 INGAME_FAMS_DISABLE, // disable in-game fams 686 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 687 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 688 }; 689 690 /** 691 * enum pipe_split_policy - Pipe split strategy supported by DCN 692 * 693 * This enum is used to define the pipe split policy supported by DCN. By 694 * default, DC favors MPC_SPLIT_DYNAMIC. 695 */ 696 enum pipe_split_policy { 697 /** 698 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 699 * pipe in order to bring the best trade-off between performance and 700 * power consumption. This is the recommended option. 701 */ 702 MPC_SPLIT_DYNAMIC = 0, 703 704 /** 705 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 706 * try any sort of split optimization. 707 */ 708 MPC_SPLIT_AVOID = 1, 709 710 /** 711 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 712 * optimize the pipe utilization when using a single display; if the 713 * user connects to a second display, DC will avoid pipe split. 714 */ 715 MPC_SPLIT_AVOID_MULT_DISP = 2, 716 }; 717 718 enum wm_report_mode { 719 WM_REPORT_DEFAULT = 0, 720 WM_REPORT_OVERRIDE = 1, 721 }; 722 enum dtm_pstate{ 723 dtm_level_p0 = 0,/*highest voltage*/ 724 dtm_level_p1, 725 dtm_level_p2, 726 dtm_level_p3, 727 dtm_level_p4,/*when active_display_count = 0*/ 728 }; 729 730 enum dcn_pwr_state { 731 DCN_PWR_STATE_UNKNOWN = -1, 732 DCN_PWR_STATE_MISSION_MODE = 0, 733 DCN_PWR_STATE_LOW_POWER = 3, 734 }; 735 736 enum dcn_zstate_support_state { 737 DCN_ZSTATE_SUPPORT_UNKNOWN, 738 DCN_ZSTATE_SUPPORT_ALLOW, 739 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 740 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 741 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 742 DCN_ZSTATE_SUPPORT_DISALLOW, 743 }; 744 745 /* 746 * struct dc_clocks - DC pipe clocks 747 * 748 * For any clocks that may differ per pipe only the max is stored in this 749 * structure 750 */ 751 struct dc_clocks { 752 int dispclk_khz; 753 int actual_dispclk_khz; 754 int dppclk_khz; 755 int actual_dppclk_khz; 756 int disp_dpp_voltage_level_khz; 757 int dcfclk_khz; 758 int socclk_khz; 759 int dcfclk_deep_sleep_khz; 760 int fclk_khz; 761 int phyclk_khz; 762 int dramclk_khz; 763 bool p_state_change_support; 764 enum dcn_zstate_support_state zstate_support; 765 bool dtbclk_en; 766 int ref_dtbclk_khz; 767 bool fclk_p_state_change_support; 768 enum dcn_pwr_state pwr_state; 769 /* 770 * Elements below are not compared for the purposes of 771 * optimization required 772 */ 773 774 /* 775 * @cstate_allow 776 * 777 * DCN's DF C-state vote as last successfully acknowledged by PMFW. 778 * false = DCN does NOT permit DF C-state; 779 * true = DCN permits DF C-state; 780 */ 781 bool cstate_allow; 782 bool prev_p_state_change_support; 783 bool fclk_prev_p_state_change_support; 784 int num_ways; 785 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 786 787 /* 788 * @fw_based_mclk_switching 789 * 790 * DC has a mechanism that leverage the variable refresh rate to switch 791 * memory clock in cases that we have a large latency to achieve the 792 * memory clock change and a short vblank window. DC has some 793 * requirements to enable this feature, and this field describes if the 794 * system support or not such a feature. 795 */ 796 bool fw_based_mclk_switching; 797 bool fw_based_mclk_switching_shut_down; 798 bool alt_ch_pstate_switch; 799 int prev_num_ways; 800 enum dtm_pstate dtm_level; 801 int max_supported_dppclk_khz; 802 int max_supported_dispclk_khz; 803 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 804 int bw_dispclk_khz; 805 int idle_dramclk_khz; 806 int idle_fclk_khz; 807 int subvp_prefetch_dramclk_khz; 808 int subvp_prefetch_fclk_khz; 809 /* deprecated: use _KBps variants — will be removed after DML update */ 810 unsigned int utm_urgent_bandwidth_lb_Kbps; 811 unsigned int utm_nominal_bandwidth_lb_Kbps; 812 unsigned int utm_urgent_bandwidth_lb_KBps; 813 unsigned int utm_nominal_bandwidth_lb_KBps; 814 unsigned int utm_latency_ub_index; 815 unsigned int utm_lsdma_bandwidth_lb_KBps; 816 unsigned int utm_nominal_max_latency_ub_ns; 817 unsigned int utm_nominal_avg_latency_ub_ns; 818 /* deprecated: use _KBps variant — will be removed after DML update */ 819 unsigned int required_avg_active_bandwidth_Kbps; 820 unsigned int required_avg_active_bandwidth_KBps; 821 822 /* Stutter efficiency is technically not clock values 823 * but stored here so the values are part of the update_clocks call similar to num_ways 824 * Efficiencies are stored as percentage (0-100) 825 */ 826 struct { 827 uint8_t base_efficiency; //LP1 828 uint8_t low_power_efficiency; //LP2 829 uint8_t z8_stutter_efficiency; 830 int z8_stutter_period; 831 } stutter_efficiency; 832 }; 833 834 struct dc_bw_validation_profile { 835 bool enable; 836 837 unsigned long long total_ticks; 838 unsigned long long voltage_level_ticks; 839 unsigned long long watermark_ticks; 840 unsigned long long rq_dlg_ticks; 841 842 unsigned long long total_count; 843 unsigned long long skip_fast_count; 844 unsigned long long skip_pass_count; 845 unsigned long long skip_fail_count; 846 }; 847 848 #define BW_VAL_TRACE_SETUP() \ 849 unsigned long long end_tick = 0; \ 850 unsigned long long voltage_level_tick = 0; \ 851 unsigned long long watermark_tick = 0; \ 852 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 853 dm_get_timestamp(dc->ctx) : 0 854 855 #define BW_VAL_TRACE_COUNT() \ 856 if (dc->debug.bw_val_profile.enable) \ 857 dc->debug.bw_val_profile.total_count++ 858 859 #define BW_VAL_TRACE_SKIP(status) \ 860 if (dc->debug.bw_val_profile.enable) { \ 861 if (!voltage_level_tick) \ 862 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 863 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 864 } 865 866 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 867 if (dc->debug.bw_val_profile.enable) \ 868 voltage_level_tick = dm_get_timestamp(dc->ctx) 869 870 #define BW_VAL_TRACE_END_WATERMARKS() \ 871 if (dc->debug.bw_val_profile.enable) \ 872 watermark_tick = dm_get_timestamp(dc->ctx) 873 874 #define BW_VAL_TRACE_FINISH() \ 875 if (dc->debug.bw_val_profile.enable) { \ 876 end_tick = dm_get_timestamp(dc->ctx); \ 877 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 878 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 879 if (watermark_tick) { \ 880 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 881 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 882 } \ 883 } 884 885 union mem_low_power_enable_options { 886 struct { 887 bool vga: 1; 888 bool i2c: 1; 889 bool dmcu: 1; 890 bool dscl: 1; 891 bool cm: 1; 892 bool mpc: 1; 893 bool optc: 1; 894 bool vpg: 1; 895 bool afmt: 1; 896 } bits; 897 uint32_t u32All; 898 }; 899 900 union root_clock_optimization_options { 901 struct { 902 bool dpp: 1; 903 bool dsc: 1; 904 bool hdmistream: 1; 905 bool hdmichar: 1; 906 bool dpstream: 1; 907 bool symclk32_se: 1; 908 bool symclk32_le: 1; 909 bool symclk_fe: 1; 910 bool physymclk: 1; 911 bool dpiasymclk: 1; 912 uint32_t reserved: 22; 913 } bits; 914 uint32_t u32All; 915 }; 916 917 union fine_grain_clock_gating_enable_options { 918 struct { 919 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 920 bool dchub : 1; /* Display controller hub */ 921 bool dchubbub : 1; 922 bool dpp : 1; /* Display pipes and planes */ 923 bool opp : 1; /* Output pixel processing */ 924 bool optc : 1; /* Output pipe timing combiner */ 925 bool dio : 1; /* Display output */ 926 bool dwb : 1; /* Display writeback */ 927 bool mmhubbub : 1; /* Multimedia hub */ 928 bool dmu : 1; /* Display core management unit */ 929 bool az : 1; /* Azalia */ 930 bool dchvm : 1; 931 bool dsc : 1; /* Display stream compression */ 932 933 uint32_t reserved : 19; 934 } bits; 935 uint32_t u32All; 936 }; 937 938 enum pg_hw_pipe_resources { 939 PG_HUBP = 0, 940 PG_DPP, 941 PG_DSC, 942 PG_MPCC, 943 PG_OPP, 944 PG_OPTC, 945 PG_DPSTREAM, 946 PG_HDMISTREAM, 947 PG_PHYSYMCLK, 948 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 949 }; 950 951 enum pg_hw_resources { 952 PG_DCCG = 0, 953 PG_DCIO, 954 PG_DIO, 955 PG_DCHUBBUB, 956 PG_DCHVM, 957 PG_DWB, 958 PG_HPO, 959 PG_DCOH, 960 PG_HW_RESOURCES_NUM_ELEMENT 961 }; 962 963 struct pg_block_update { 964 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 965 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 966 }; 967 968 union dpia_debug_options { 969 struct { 970 uint32_t disable_dpia:1; /* bit 0 */ 971 uint32_t force_non_lttpr:1; /* bit 1 */ 972 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 973 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 974 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 975 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 976 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 977 uint32_t reserved:25; 978 } bits; 979 uint32_t raw; 980 }; 981 982 /* AUX wake work around options 983 * 0: enable/disable work around 984 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 985 * 15-2: reserved 986 * 31-16: timeout in ms 987 */ 988 union aux_wake_wa_options { 989 struct { 990 uint32_t enable_wa : 1; 991 uint32_t use_default_timeout : 1; 992 uint32_t rsvd: 14; 993 uint32_t timeout_ms : 16; 994 } bits; 995 uint32_t raw; 996 }; 997 998 struct dc_debug_data { 999 uint32_t ltFailCount; 1000 uint32_t i2cErrorCount; 1001 uint32_t auxErrorCount; 1002 struct pipe_topology_history topology_history; 1003 }; 1004 1005 struct dc_phy_addr_space_config { 1006 struct { 1007 uint64_t start_addr; 1008 uint64_t end_addr; 1009 uint64_t fb_top; 1010 uint64_t fb_offset; 1011 uint64_t fb_base; 1012 uint64_t agp_top; 1013 uint64_t agp_bot; 1014 uint64_t agp_base; 1015 } system_aperture; 1016 1017 struct { 1018 uint64_t page_table_start_addr; 1019 uint64_t page_table_end_addr; 1020 uint64_t page_table_base_addr; 1021 bool base_addr_is_mc_addr; 1022 } gart_config; 1023 1024 bool valid; 1025 bool is_hvm_enabled; 1026 uint64_t page_table_default_page_addr; 1027 }; 1028 1029 struct dc_virtual_addr_space_config { 1030 uint64_t page_table_base_addr; 1031 uint64_t page_table_start_addr; 1032 uint64_t page_table_end_addr; 1033 uint32_t page_table_block_size_in_bytes; 1034 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 1035 }; 1036 1037 struct dc_bounding_box_overrides { 1038 unsigned int sr_exit_time_ns; 1039 unsigned int sr_enter_plus_exit_time_ns; 1040 unsigned int sr_exit_z8_time_ns; 1041 unsigned int sr_enter_plus_exit_z8_time_ns; 1042 unsigned int urgent_latency_ns; 1043 unsigned int percent_of_ideal_drambw; 1044 unsigned int dram_clock_change_latency_ns; 1045 unsigned int dummy_clock_change_latency_ns; 1046 unsigned int fclk_clock_change_latency_ns; 1047 /* This forces a hard min on the DCFCLK we use 1048 * for DML. Unlike the debug option for forcing 1049 * DCFCLK, this override affects watermark calculations 1050 */ 1051 unsigned int min_dcfclk_mhz; 1052 }; 1053 1054 struct dc_qos_info { 1055 uint32_t qos_bandwidth_lb_in_mbps; 1056 uint32_t calculated_avg_bw_in_mbps; 1057 uint32_t qos_max_latency_ub_in_ns; 1058 uint32_t qos_avg_latency_ub_in_ns; 1059 uint32_t dcn_bandwidth_ub_in_mbps; 1060 uint32_t qos_max_bw_budget_in_mbps; 1061 }; 1062 1063 struct dc_state; 1064 struct resource_pool; 1065 struct dce_hwseq; 1066 struct link_service; 1067 1068 /* 1069 * struct dc_debug_options - DC debug struct 1070 * 1071 * This struct provides a simple mechanism for developers to change some 1072 * configurations, enable/disable features, and activate extra debug options. 1073 * This can be very handy to narrow down whether some specific feature is 1074 * causing an issue or not. 1075 */ 1076 struct dc_debug_options { 1077 bool disable_dsc; 1078 enum visual_confirm visual_confirm; 1079 unsigned int visual_confirm_rect_height; 1080 1081 bool sanity_checks; 1082 bool max_disp_clk; 1083 bool surface_trace; 1084 bool clock_trace; 1085 bool validation_trace; 1086 bool bandwidth_calcs_trace; 1087 int max_downscale_src_width; 1088 1089 /* stutter efficiency related */ 1090 bool disable_stutter; 1091 bool use_max_lb; 1092 enum dcc_option disable_dcc; 1093 1094 /* 1095 * @pipe_split_policy: Define which pipe split policy is used by the 1096 * display core. 1097 */ 1098 enum pipe_split_policy pipe_split_policy; 1099 bool force_single_disp_pipe_split; 1100 bool voltage_align_fclk; 1101 bool disable_min_fclk; 1102 1103 bool hdcp_lc_force_fw_enable; 1104 bool hdcp_lc_enable_sw_fallback; 1105 1106 bool disable_dfs_bypass; 1107 bool disable_dpp_power_gate; 1108 bool disable_hubp_power_gate; 1109 bool disable_dsc_power_gate; 1110 bool disable_optc_power_gate; 1111 bool disable_hpo_power_gate; 1112 bool disable_io_clk_power_gate; 1113 bool disable_mem_power_gate; 1114 bool disable_dio_power_gate; 1115 unsigned int dsc_min_slice_height_override; 1116 unsigned int dsc_bpp_increment_div; 1117 bool disable_pplib_wm_range; 1118 enum wm_report_mode pplib_wm_report_mode; 1119 unsigned int min_disp_clk_khz; 1120 unsigned int min_dpp_clk_khz; 1121 unsigned int min_dram_clk_khz; 1122 unsigned int sr_exit_time_dpm0_ns; 1123 unsigned int sr_enter_plus_exit_time_dpm0_ns; 1124 unsigned int sr_exit_time_ns; 1125 unsigned int sr_enter_plus_exit_time_ns; 1126 unsigned int sr_exit_z8_time_ns; 1127 unsigned int sr_enter_plus_exit_z8_time_ns; 1128 unsigned int urgent_latency_ns; 1129 uint32_t underflow_assert_delay_us; 1130 unsigned int percent_of_ideal_drambw; 1131 unsigned int dram_clock_change_latency_ns; 1132 bool optimized_watermark; 1133 int always_scale; 1134 bool disable_pplib_clock_request; 1135 bool disable_clock_gate; 1136 bool disable_mem_low_power; 1137 bool pstate_enabled; 1138 bool disable_dmcu; 1139 bool force_abm_enable; 1140 bool disable_stereo_support; 1141 bool vsr_support; 1142 bool performance_trace; 1143 bool az_endpoint_mute_only; 1144 bool always_use_regamma; 1145 bool recovery_enabled; 1146 bool avoid_vbios_exec_table; 1147 bool scl_reset_length10; 1148 bool hdmi20_disable; 1149 bool skip_detection_link_training; 1150 uint32_t edid_read_retry_times; 1151 1152 uint8_t force_odm_combine; //bit vector based on otg inst 1153 uint8_t seamless_boot_odm_combine; 1154 uint8_t force_odm_combine_4to1; //bit vector based on otg inst 1155 1156 unsigned int minimum_z8_residency_time; 1157 unsigned int minimum_z10_residency_time; 1158 bool disable_z9_mpc; 1159 unsigned int force_fclk_khz; 1160 bool enable_tri_buf; 1161 bool ips_disallow_entry; 1162 bool disable_idle_power_optimizations; 1163 unsigned int mall_size_override; 1164 unsigned int mall_additional_timer_percent; 1165 bool mall_error_as_fatal; 1166 bool dmub_command_table; /* for testing only */ 1167 struct dc_bw_validation_profile bw_val_profile; 1168 bool disable_fec; 1169 bool disable_48mhz_pwrdwn; 1170 /* This forces a hard min on the DCFCLK requested to SMU/PP 1171 * watermarks are not affected. 1172 */ 1173 unsigned int force_min_dcfclk_mhz; 1174 int dwb_fi_phase; 1175 bool disable_timing_sync; 1176 bool cm_in_bypass; 1177 int force_clock_mode;/*every mode change.*/ 1178 1179 bool disable_dram_clock_change_vactive_support; 1180 bool validate_dml_output; 1181 bool enable_dmcub_surface_flip; 1182 bool usbc_combo_phy_reset_wa; 1183 bool force_fva; 1184 int max_frl_rate; 1185 unsigned int force_frl_rate; 1186 bool ignore_ffe; 1187 unsigned int select_ffe; 1188 unsigned int limit_ffe; 1189 bool force_frl_always; 1190 bool force_frl_dsc; 1191 bool force_frl_max; 1192 bool apply_vsdb_rcc_wa; 1193 bool enable_hdmi_idcc; 1194 1195 bool enable_dram_clock_change_one_display_vactive; 1196 /* TODO - remove once tested */ 1197 bool legacy_dp2_lt; 1198 bool set_mst_en_for_sst; 1199 bool disable_uhbr; 1200 bool force_dp2_lt_fallback_method; 1201 bool ignore_cable_id; 1202 union mem_low_power_enable_options enable_mem_low_power; 1203 union root_clock_optimization_options root_clock_optimization; 1204 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1205 bool hpo_optimization; 1206 bool force_vblank_alignment; 1207 1208 /* Enable dmub aux for legacy ddc */ 1209 bool enable_dmub_aux_for_legacy_ddc; 1210 bool disable_fams; 1211 enum in_game_fams_config disable_fams_gaming; 1212 /* FEC/PSR1 sequence enable delay in 100us */ 1213 uint8_t fec_enable_delay_in100us; 1214 bool enable_driver_sequence_debug; 1215 enum det_size crb_alloc_policy; 1216 unsigned int crb_alloc_policy_min_disp_count; 1217 bool disable_z10; 1218 bool enable_z9_disable_interface; 1219 bool psr_skip_crtc_disable; 1220 uint32_t ips_skip_crtc_disable_mask; 1221 union dpia_debug_options dpia_debug; 1222 bool disable_fixed_vs_aux_timeout_wa; 1223 uint32_t fixed_vs_aux_delay_config_wa; 1224 bool force_disable_subvp; 1225 bool force_subvp_mclk_switch; 1226 bool allow_sw_cursor_fallback; 1227 unsigned int force_subvp_num_ways; 1228 unsigned int force_mall_ss_num_ways; 1229 bool alloc_extra_way_for_cursor; 1230 uint32_t subvp_extra_lines; 1231 bool disable_force_pstate_allow_on_hw_release; 1232 bool force_usr_allow; 1233 /* uses value at boot and disables switch */ 1234 bool disable_dtb_ref_clk_switch; 1235 bool extended_blank_optimization; 1236 union aux_wake_wa_options aux_wake_wa; 1237 uint32_t mst_start_top_delay; 1238 uint8_t psr_power_use_phy_fsm; 1239 enum dml_hostvm_override_opts dml_hostvm_override; 1240 bool dml_disallow_alternate_prefetch_modes; 1241 bool use_legacy_soc_bb_mechanism; 1242 bool exit_idle_opt_for_cursor_updates; 1243 bool using_dml2; 1244 bool enable_single_display_2to1_odm_policy; 1245 bool enable_double_buffered_dsc_pg_support; 1246 bool enable_dp_dig_pixel_rate_div_policy; 1247 bool using_dml21; 1248 enum lttpr_mode lttpr_mode_override; 1249 unsigned int dsc_delay_factor_wa_x1000; 1250 unsigned int min_prefetch_in_strobe_ns; 1251 bool disable_unbounded_requesting; 1252 bool dig_fifo_off_in_blank; 1253 bool override_dispclk_programming; 1254 bool otg_crc_db; 1255 bool disallow_dispclk_dppclk_ds; 1256 bool disable_fpo_optimizations; 1257 bool support_eDP1_5; 1258 uint32_t fpo_vactive_margin_us; 1259 bool disable_fpo_vactive; 1260 bool disable_boot_optimizations; 1261 bool override_odm_optimization; 1262 bool minimize_dispclk_using_odm; 1263 bool disable_subvp_high_refresh; 1264 bool disable_dp_plus_plus_wa; 1265 uint32_t fpo_vactive_min_active_margin_us; 1266 uint32_t fpo_vactive_max_blank_us; 1267 bool enable_hpo_pg_support; 1268 bool disable_dc_mode_overwrite; 1269 bool replay_skip_crtc_disabled; 1270 bool ignore_pg;/*do nothing, let pmfw control it*/ 1271 bool psp_disabled_wa; 1272 unsigned int ips2_eval_delay_us; 1273 unsigned int ips2_entry_delay_us; 1274 bool optimize_ips_handshake; 1275 bool disable_dmub_reallow_idle; 1276 bool disable_timeout; 1277 bool disable_extblankadj; 1278 bool enable_idle_reg_checks; 1279 unsigned int static_screen_wait_frames; 1280 uint32_t pwm_freq; 1281 bool force_chroma_subsampling_1tap; 1282 unsigned int dcc_meta_propagation_delay_us; 1283 bool disable_422_left_edge_pixel; 1284 bool dml21_force_pstate_method; 1285 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1286 uint32_t dml21_disable_pstate_method_mask; 1287 union fw_assisted_mclk_switch_version fams_version; 1288 union dmub_fams2_global_feature_config fams2_config; 1289 unsigned int force_cositing; 1290 unsigned int disable_spl; 1291 unsigned int force_easf; 1292 unsigned int force_sharpness; 1293 unsigned int force_sharpness_level; 1294 unsigned int force_lls; 1295 bool notify_dpia_hr_bw; 1296 bool enable_ips_visual_confirm; 1297 unsigned int sharpen_policy; 1298 unsigned int scale_to_sharpness_policy; 1299 unsigned int enable_oled_edp_power_up_opt; 1300 bool enable_hblank_borrow; 1301 bool force_subvp_df_throttle; 1302 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1303 bool enable_pg_cntl_debug_logs; 1304 unsigned int auxless_alpm_lfps_setup_ns; 1305 unsigned int auxless_alpm_lfps_period_ns; 1306 unsigned int auxless_alpm_lfps_silence_ns; 1307 unsigned int auxless_alpm_lfps_t1t2_us; 1308 short auxless_alpm_lfps_t1t2_offset_us; 1309 bool disable_stutter_for_wm_program; 1310 bool enable_block_sequence_programming; 1311 uint32_t custom_psp_footer_size; 1312 bool disable_deferred_minimal_transitions; 1313 unsigned int num_fast_flips_to_steady_state_override; 1314 bool enable_dmu_recovery; 1315 unsigned int force_vmin_threshold; 1316 bool enable_otg_frame_sync_pwa; 1317 unsigned int min_deep_sleep_dcfclk_khz; 1318 unsigned int force_odm2to1_for_edp_pixclk_mhz; 1319 bool enable_replay_esd_recovery; 1320 uint8_t iommu_mismatch_temp_wka; 1321 bool disable_dynamic_expansion_for_test_pattern; 1322 uint32_t dml21_custom_derate_num_dpms; 1323 uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL]; 1324 }; 1325 1326 1327 /* Generic structure that can be used to query properties of DC. More fields 1328 * can be added as required. 1329 */ 1330 struct dc_current_properties { 1331 unsigned int cursor_size_limit; 1332 }; 1333 1334 enum frame_buffer_mode { 1335 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1336 FRAME_BUFFER_MODE_ZFB_ONLY, 1337 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1338 } ; 1339 1340 struct dchub_init_data { 1341 int64_t zfb_phys_addr_base; 1342 int64_t zfb_mc_base_addr; 1343 uint64_t zfb_size_in_byte; 1344 enum frame_buffer_mode fb_mode; 1345 bool dchub_initialzied; 1346 bool dchub_info_valid; 1347 }; 1348 1349 struct dml2_soc_bb; 1350 1351 struct dc_init_data { 1352 struct hw_asic_id asic_id; 1353 void *driver; /* ctx */ 1354 struct cgs_device *cgs_device; 1355 struct dc_bounding_box_overrides bb_overrides; 1356 1357 int num_virtual_links; 1358 /* 1359 * If 'vbios_override' not NULL, it will be called instead 1360 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1361 */ 1362 struct dc_bios *vbios_override; 1363 enum dce_environment dce_environment; 1364 1365 struct dmub_offload_funcs *dmub_if; 1366 1367 struct dc_config flags; 1368 uint64_t log_mask; 1369 1370 struct dpcd_vendor_signature vendor_signature; 1371 bool force_smu_not_present; 1372 /* 1373 * IP offset for run time initializaion of register addresses 1374 * 1375 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1376 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1377 * before them. 1378 */ 1379 uint32_t *dcn_reg_offsets; 1380 uint32_t *nbio_reg_offsets; 1381 uint32_t *clk_reg_offsets; 1382 void *bb_from_dmub; 1383 }; 1384 1385 struct dc_callback_init { 1386 struct cp_psp cp_psp; 1387 }; 1388 1389 struct dc *dc_create(const struct dc_init_data *init_params); 1390 void dc_hardware_init(struct dc *dc); 1391 1392 int dc_get_vmid_use_vector(struct dc *dc); 1393 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1394 /* Returns the number of vmids supported */ 1395 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1396 void dc_init_callbacks(struct dc *dc, 1397 const struct dc_callback_init *init_params); 1398 void dc_deinit_callbacks(struct dc *dc); 1399 void dc_destroy(struct dc **dc); 1400 1401 /* Surface Interfaces */ 1402 1403 enum { 1404 TRANSFER_FUNC_POINTS = 1025 1405 }; 1406 1407 struct dc_hdr_static_metadata { 1408 /* display chromaticities and white point in units of 0.00001 */ 1409 unsigned int chromaticity_green_x; 1410 unsigned int chromaticity_green_y; 1411 unsigned int chromaticity_blue_x; 1412 unsigned int chromaticity_blue_y; 1413 unsigned int chromaticity_red_x; 1414 unsigned int chromaticity_red_y; 1415 unsigned int chromaticity_white_point_x; 1416 unsigned int chromaticity_white_point_y; 1417 1418 uint32_t min_luminance; 1419 uint32_t max_luminance; 1420 uint32_t maximum_content_light_level; 1421 uint32_t maximum_frame_average_light_level; 1422 }; 1423 1424 enum dc_transfer_func_type { 1425 TF_TYPE_PREDEFINED, 1426 TF_TYPE_DISTRIBUTED_POINTS, 1427 TF_TYPE_BYPASS, 1428 TF_TYPE_HWPWL 1429 }; 1430 1431 struct dc_transfer_func_distributed_points { 1432 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1433 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1434 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1435 1436 uint16_t end_exponent; 1437 uint16_t x_point_at_y1_red; 1438 uint16_t x_point_at_y1_green; 1439 uint16_t x_point_at_y1_blue; 1440 }; 1441 1442 enum dc_transfer_func_predefined { 1443 TRANSFER_FUNCTION_SRGB, 1444 TRANSFER_FUNCTION_BT709, 1445 TRANSFER_FUNCTION_PQ, 1446 TRANSFER_FUNCTION_LINEAR, 1447 TRANSFER_FUNCTION_UNITY, 1448 TRANSFER_FUNCTION_HLG, 1449 TRANSFER_FUNCTION_HLG12, 1450 TRANSFER_FUNCTION_GAMMA22, 1451 TRANSFER_FUNCTION_GAMMA24, 1452 TRANSFER_FUNCTION_GAMMA26 1453 }; 1454 1455 1456 struct dc_transfer_func { 1457 struct kref refcount; 1458 enum dc_transfer_func_type type; 1459 enum dc_transfer_func_predefined tf; 1460 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1461 uint32_t sdr_ref_white_level; 1462 union { 1463 struct pwl_params pwl; 1464 struct dc_transfer_func_distributed_points tf_pts; 1465 }; 1466 }; 1467 1468 1469 union dc_3dlut_state { 1470 struct { 1471 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1472 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1473 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1474 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1475 uint32_t mpc_rmu1_mux:4; 1476 uint32_t mpc_rmu2_mux:4; 1477 uint32_t reserved:15; 1478 } bits; 1479 uint32_t raw; 1480 }; 1481 1482 1483 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1484 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1485 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1486 1487 struct lut_rgb { 1488 uint16_t b; 1489 uint16_t g; 1490 uint16_t r; 1491 uint16_t padding; 1492 }; 1493 1494 //this structure maps directly to how the lut will read it from memory 1495 struct lut_mem_mapping { 1496 union { 1497 //NATIVE MODE 1, 2 1498 //RGB layout [b][g][r] //red is 128 byte aligned 1499 //BGR layout [r][g][b] //blue is 128 byte aligned 1500 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1501 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1502 1503 //TRANSFORMED 1504 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1505 }; 1506 uint16_t size; 1507 }; 1508 1509 struct dc_rmcm_3dlut { 1510 bool isInUse; 1511 const struct dc_stream_state *stream; 1512 uint8_t protection_bits; 1513 }; 1514 1515 struct dc_3dlut { 1516 struct kref refcount; 1517 struct tetrahedral_params lut_3d; 1518 struct fixed31_32 hdr_multiplier; 1519 union dc_3dlut_state state; 1520 }; 1521 1522 /* 3DLUT DMA (Fast Load) params */ 1523 struct dc_3dlut_dma { 1524 struct dc_plane_address addr; 1525 enum dc_cm_lut_swizzle swizzle; 1526 enum dc_cm_lut_pixel_format format; 1527 uint16_t bias; /* FP1.5.10 */ 1528 uint16_t scale; /* FP1.5.10 */ 1529 enum dc_cm_lut_size size; 1530 }; 1531 1532 /* color manager */ 1533 union dc_plane_cm_flags { 1534 unsigned int all; 1535 struct { 1536 unsigned int shaper_enable : 1; 1537 unsigned int lut3d_enable : 1; 1538 unsigned int blend_enable : 1; 1539 /* whether legacy (lut3d_func) or DMA is valid */ 1540 unsigned int lut3d_dma_enable : 1; 1541 /* RMCM lut to be used instead of MCM */ 1542 unsigned int rmcm_enable : 1; 1543 unsigned int reserved: 27; 1544 } bits; 1545 }; 1546 1547 struct dc_plane_cm { 1548 struct kref refcount; 1549 struct dc_transfer_func shaper_func; 1550 union { 1551 struct dc_3dlut lut3d_func; 1552 struct dc_3dlut_dma lut3d_dma; 1553 }; 1554 struct dc_transfer_func blend_func; 1555 union dc_plane_cm_flags flags; 1556 }; 1557 1558 /* 1559 * This structure is filled in by dc_surface_get_status and contains 1560 * the last requested address and the currently active address so the called 1561 * can determine if there are any outstanding flips 1562 */ 1563 struct dc_plane_status { 1564 struct dc_plane_address requested_address; 1565 struct dc_plane_address current_address; 1566 bool is_flip_pending; 1567 bool is_right_eye; 1568 struct cm_hist cm_hist; 1569 }; 1570 1571 struct pipe_update_bits { 1572 uint32_t addr_update:1; 1573 uint32_t dcc_change:1; 1574 uint32_t color_space_change:1; 1575 uint32_t horizontal_mirror_change:1; 1576 uint32_t per_pixel_alpha_change:1; 1577 uint32_t global_alpha_change:1; 1578 uint32_t hdr_mult:1; 1579 uint32_t rotation_change:1; 1580 uint32_t swizzle_change:1; 1581 uint32_t scaling_change:1; 1582 uint32_t position_change:1; 1583 uint32_t in_transfer_func_change:1; 1584 uint32_t input_csc_change:1; 1585 uint32_t coeff_reduction_change:1; 1586 uint32_t pixel_format_change:1; 1587 uint32_t plane_size_change:1; 1588 uint32_t gamut_remap_change:1; 1589 uint32_t cursor_csc_color_matrix_change:1; 1590 uint32_t new_plane:1; 1591 uint32_t bpp_change:1; 1592 uint32_t gamma_change:1; 1593 uint32_t bandwidth_change:1; 1594 uint32_t clock_change:1; 1595 uint32_t stereo_format_change:1; 1596 uint32_t lut_3d:1; 1597 uint32_t tmz_changed:1; 1598 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1599 uint32_t full_update:1; 1600 uint32_t sdr_white_level_nits:1; 1601 uint32_t cm_hist_change:1; 1602 /* NOTE: When adding a new field, also update: 1603 * - dc_pipe_update_bits_set_full() 1604 * - dc_pipe_update_bits_is_any_set() 1605 */ 1606 }; 1607 1608 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags) 1609 { 1610 /* memset ensures padding bits are zeroed */ 1611 memset(flags, 0, sizeof(*flags)); 1612 } 1613 1614 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags) 1615 { 1616 dc_pipe_update_bits_clear(flags); 1617 flags->addr_update = 1; 1618 flags->dcc_change = 1; 1619 flags->color_space_change = 1; 1620 flags->horizontal_mirror_change = 1; 1621 flags->per_pixel_alpha_change = 1; 1622 flags->global_alpha_change = 1; 1623 flags->hdr_mult = 1; 1624 flags->rotation_change = 1; 1625 flags->swizzle_change = 1; 1626 flags->scaling_change = 1; 1627 flags->position_change = 1; 1628 flags->in_transfer_func_change = 1; 1629 flags->input_csc_change = 1; 1630 flags->coeff_reduction_change = 1; 1631 flags->pixel_format_change = 1; 1632 flags->plane_size_change = 1; 1633 flags->gamut_remap_change = 1; 1634 flags->cursor_csc_color_matrix_change = 1; 1635 flags->new_plane = 1; 1636 flags->bpp_change = 1; 1637 flags->gamma_change = 1; 1638 flags->bandwidth_change = 1; 1639 flags->clock_change = 1; 1640 flags->stereo_format_change = 1; 1641 flags->lut_3d = 1; 1642 flags->tmz_changed = 1; 1643 flags->mcm_transfer_function_enable_change = 1; 1644 flags->full_update = 1; 1645 flags->sdr_white_level_nits = 1; 1646 flags->cm_hist_change = 1; 1647 } 1648 1649 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags) 1650 { 1651 return flags->addr_update || 1652 flags->dcc_change || 1653 flags->color_space_change || 1654 flags->horizontal_mirror_change || 1655 flags->per_pixel_alpha_change || 1656 flags->global_alpha_change || 1657 flags->hdr_mult || 1658 flags->rotation_change || 1659 flags->swizzle_change || 1660 flags->scaling_change || 1661 flags->position_change || 1662 flags->in_transfer_func_change || 1663 flags->input_csc_change || 1664 flags->coeff_reduction_change || 1665 flags->pixel_format_change || 1666 flags->plane_size_change || 1667 flags->gamut_remap_change || 1668 flags->cursor_csc_color_matrix_change || 1669 flags->new_plane || 1670 flags->bpp_change || 1671 flags->gamma_change || 1672 flags->bandwidth_change || 1673 flags->clock_change || 1674 flags->stereo_format_change || 1675 flags->lut_3d || 1676 flags->tmz_changed || 1677 flags->mcm_transfer_function_enable_change || 1678 flags->full_update || 1679 flags->sdr_white_level_nits || 1680 flags->cm_hist_change; 1681 } 1682 1683 bool dc_check_address_only_update(struct pipe_update_bits update_bits); 1684 1685 #define DC_REMOVE_PLANE_POINTERS 1 1686 1687 struct dc_plane_state { 1688 struct dc_plane_address address; 1689 struct dc_plane_flip_time time; 1690 bool triplebuffer_flips; 1691 struct scaling_taps scaling_quality; 1692 struct rect src_rect; 1693 struct rect dst_rect; 1694 struct rect clip_rect; 1695 1696 struct plane_size plane_size; 1697 struct dc_tiling_info tiling_info; 1698 1699 struct dc_plane_dcc_param dcc; 1700 1701 struct dc_gamma gamma_correction; 1702 struct dc_transfer_func in_transfer_func; 1703 struct dc_bias_and_scale bias_and_scale; 1704 struct dc_csc_transform input_csc_color_matrix; 1705 struct fixed31_32 coeff_reduction_factor; 1706 struct fixed31_32 hdr_mult; 1707 struct colorspace_transform gamut_remap_matrix; 1708 1709 enum dc_color_space color_space; 1710 1711 #ifndef TRIM_CM2 1712 // TODO: No longer used, remove 1713 struct dc_hdr_static_metadata hdr_static_ctx; 1714 1715 struct dc_3dlut lut3d_func; 1716 struct dc_transfer_func in_shaper_func; 1717 struct dc_transfer_func blend_tf; 1718 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1719 bool mcm_lut1d_enable; 1720 struct dc_cm2_func_luts mcm_luts; 1721 #endif /* TRIM_CM2 */ 1722 bool lut_bank_a; 1723 enum mpcc_movable_cm_location mcm_location; 1724 struct dc_plane_cm cm; 1725 1726 struct dc_transfer_func *gamcor_tf; 1727 enum surface_pixel_format format; 1728 enum dc_rotation_angle rotation; 1729 enum plane_stereo_format stereo_format; 1730 1731 bool is_tiling_rotated; 1732 bool per_pixel_alpha; 1733 bool pre_multiplied_alpha; 1734 bool global_alpha; 1735 int global_alpha_value; 1736 bool visible; 1737 bool flip_immediate; 1738 bool horizontal_mirror; 1739 unsigned int layer_index; 1740 1741 struct pipe_update_bits update_bits; 1742 bool flip_int_enabled; 1743 bool skip_manual_trigger; 1744 1745 /* private to DC core */ 1746 struct dc_plane_status status; 1747 struct dc_context *ctx; 1748 1749 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1750 bool force_full_update; 1751 1752 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1753 1754 /* private to dc_surface.c */ 1755 enum dc_irq_source irq_source; 1756 struct kref refcount; 1757 struct tg_color visual_confirm_color; 1758 1759 bool is_statically_allocated; 1760 enum chroma_cositing cositing; 1761 struct dc_csc_transform cursor_csc_color_matrix; 1762 bool adaptive_sharpness_en; 1763 int adaptive_sharpness_policy; 1764 unsigned int sharpness_level; 1765 enum dc_scaling_linearity scaling_linearity; 1766 unsigned int sdr_white_level_nits; 1767 struct cm_hist_control cm_hist_control; 1768 struct spl_sharpness_range sharpness_range; 1769 enum sharpness_range_source sharpness_source; 1770 }; 1771 1772 struct dc_plane_info { 1773 struct plane_size plane_size; 1774 struct dc_tiling_info tiling_info; 1775 struct dc_plane_dcc_param dcc; 1776 enum surface_pixel_format format; 1777 enum dc_rotation_angle rotation; 1778 enum plane_stereo_format stereo_format; 1779 enum dc_color_space color_space; 1780 bool horizontal_mirror; 1781 bool visible; 1782 bool per_pixel_alpha; 1783 bool pre_multiplied_alpha; 1784 bool global_alpha; 1785 int global_alpha_value; 1786 bool input_csc_enabled; 1787 unsigned int layer_index; 1788 enum chroma_cositing cositing; 1789 enum dc_scaling_linearity scaling_linearity; 1790 }; 1791 1792 #include "dc_stream.h" 1793 1794 struct dc_scratch_space { 1795 /* used to temporarily backup plane states of a stream during 1796 * dc update. The reason is that plane states are overwritten 1797 * with surface updates in dc update. Once they are overwritten 1798 * current state is no longer valid. We want to temporarily 1799 * store current value in plane states so we can still recover 1800 * a valid current state during dc update. 1801 */ 1802 struct dc_plane_state plane_states[MAX_SURFACES]; 1803 1804 struct dc_stream_state stream_state; 1805 }; 1806 1807 /* 1808 * A link contains one or more sinks and their connected status. 1809 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1810 */ 1811 struct dc_link { 1812 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1813 unsigned int sink_count; 1814 struct dc_sink *local_sink; 1815 unsigned int link_index; 1816 enum dc_connection_type type; 1817 enum signal_type connector_signal; 1818 enum dc_irq_source irq_source_hpd; 1819 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1820 enum dc_irq_source irq_source_read_request;/* Read Request */ 1821 1822 bool is_hpd_filter_disabled; 1823 bool dp_ss_off; 1824 1825 /** 1826 * @link_state_valid: 1827 * 1828 * If there is no link and local sink, this variable should be set to 1829 * false. Otherwise, it should be set to true; usually, the function 1830 * core_link_enable_stream sets this field to true. 1831 */ 1832 bool link_state_valid; 1833 bool aux_access_disabled; 1834 bool sync_lt_in_progress; 1835 bool skip_stream_reenable; 1836 bool is_internal_display; 1837 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1838 bool is_dig_mapping_flexible; 1839 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1840 bool is_hpd_pending; /* Indicates a new received hpd */ 1841 1842 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1843 * for every link training. This is incompatible with DP LL compliance automation, 1844 * which expects the same link settings to be used every retry on a link loss. 1845 * This flag is used to skip the fallback when link loss occurs during automation. 1846 */ 1847 bool skip_fallback_on_link_loss; 1848 1849 bool edp_sink_present; 1850 1851 struct dp_trace dp_trace; 1852 volatile bool is_link_locked; 1853 1854 /* caps is the same as reported_link_cap. link_traing use 1855 * reported_link_cap. Will clean up. TODO 1856 */ 1857 struct dc_link_settings reported_link_cap; 1858 struct dc_link_settings verified_link_cap; 1859 struct dc_link_settings cur_link_settings; 1860 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1861 struct dc_link_settings preferred_link_setting; 1862 /* preferred_training_settings are override values that 1863 * come from DM. DM is responsible for the memory 1864 * management of the override pointers. 1865 */ 1866 struct dc_link_training_overrides preferred_training_settings; 1867 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings; 1868 struct dp_audio_test_data audio_test_data; 1869 1870 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap 1871 * set by IFWI, link aux_hw_inst is used in aux layer functions instead 1872 * of ddc_pin to know which aux instance is associated with link. 1873 */ 1874 bool no_ddc_pin; 1875 /** When set, forces all native I2C communication on this DP connector 1876 * to use the I2C-over-AUX protocol instead of native I2C signaling. 1877 */ 1878 bool force_to_use_aux; 1879 enum gpio_ddc_line aux_hw_inst; 1880 1881 enum gpio_ddc_line ddc_hw_inst; 1882 1883 uint8_t hpd_src; 1884 1885 uint8_t link_enc_hw_inst; 1886 /* DIG link encoder ID. Used as index in link encoder resource pool. 1887 * For links with fixed mapping to DIG, this is not changed after dc_link 1888 * object creation. 1889 */ 1890 enum engine_id eng_id; 1891 enum engine_id dpia_preferred_eng_id; 1892 1893 bool test_pattern_enabled; 1894 /* Pending/Current test pattern are only used to perform and track 1895 * FIXED_VS retimer test pattern/lane adjustment override state. 1896 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1897 * to perform specific lane adjust overrides before setting certain 1898 * PHY test patterns. In cases when lane adjust and set test pattern 1899 * calls are not performed atomically (i.e. performing link training), 1900 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1901 * and current_test_pattern will contain required context for any future 1902 * set pattern/set lane adjust to transition between override state(s). 1903 * */ 1904 enum dp_test_pattern current_test_pattern; 1905 enum dp_test_pattern pending_test_pattern; 1906 1907 union compliance_test_state compliance_test_state; 1908 1909 void *priv; 1910 1911 struct ddc_service *ddc; 1912 1913 enum dp_panel_mode panel_mode; 1914 bool aux_mode; 1915 1916 /* Private to DC core */ 1917 1918 const struct dc *dc; 1919 1920 struct dc_context *ctx; 1921 1922 struct panel_cntl *panel_cntl; 1923 struct link_encoder *link_enc; 1924 struct hpo_frl_link_encoder *hpo_frl_link_enc; 1925 struct dc_hdmi_frl_link_settings frl_reported_link_cap; 1926 struct dc_hdmi_frl_link_settings frl_verified_link_cap; 1927 struct dc_hdmi_frl_link_settings frl_link_settings; 1928 struct dc_hdmi_frl_flags frl_flags; 1929 union hdmi_idcc_cable_id hdmi_cable_id; 1930 struct graphics_object_id link_id; 1931 1932 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1933 struct graphics_object_id ext_enc_id; 1934 1935 /* Endpoint type distinguishes display endpoints which do not have entries 1936 * in the BIOS connector table from those that do. Helps when tracking link 1937 * encoder to display endpoint assignments. 1938 */ 1939 enum display_endpoint_type ep_type; 1940 union ddi_channel_mapping ddi_channel_mapping; 1941 struct connector_device_tag_info device_tag; 1942 struct dpcd_caps dpcd_caps; 1943 uint32_t dongle_max_pix_clk; 1944 unsigned short chip_caps; 1945 unsigned int dpcd_sink_count; 1946 struct hdcp_caps hdcp_caps; 1947 enum edp_revision edp_revision; 1948 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1949 1950 struct psr_settings psr_settings; 1951 struct replay_settings replay_settings; 1952 1953 /* Drive settings read from integrated info table */ 1954 struct dc_lane_settings bios_forced_drive_settings; 1955 1956 /* Vendor specific LTTPR workaround variables */ 1957 uint8_t vendor_specific_lttpr_link_rate_wa; 1958 bool apply_vendor_specific_lttpr_link_rate_wa; 1959 1960 /* MST record stream using this link */ 1961 struct link_flags { 1962 bool dp_keep_receiver_powered; 1963 bool dp_skip_DID2; 1964 bool dp_skip_reset_segment; 1965 bool dp_skip_fs_144hz; 1966 /* Some DP bridges don't work with RBR and must use HBR. */ 1967 bool dp_skip_rbr; 1968 bool dp_mot_reset_segment; 1969 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1970 bool dpia_mst_dsc_always_on; 1971 /* Forced DPIA into TBT3 compatibility mode. */ 1972 bool dpia_forced_tbt3_mode; 1973 bool dongle_mode_timing_override; 1974 bool blank_stream_on_ocs_change; 1975 bool read_dpcd204h_on_irq_hpd; 1976 bool force_dp_ffe_preset; 1977 bool skip_phy_ssc_reduction; 1978 } wa_flags; 1979 union dc_dp_ffe_preset forced_dp_ffe_preset; 1980 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1981 1982 struct dc_link_status link_status; 1983 struct dprx_states dprx_states; 1984 1985 enum dc_link_fec_state fec_state; 1986 bool is_dds; 1987 bool is_display_mux_present; 1988 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1989 1990 struct dc_panel_config panel_config; 1991 enum dc_panel_type panel_type; 1992 struct phy_state phy_state; 1993 uint32_t phy_transition_bitmask; 1994 // BW ALLOCATON USB4 ONLY 1995 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1996 bool skip_implict_edp_power_control; 1997 bool forced_psr_active; 1998 enum backlight_control_type backlight_control_type; 1999 }; 2000 2001 struct dc { 2002 struct dc_debug_options debug; 2003 struct dc_versions versions; 2004 struct dc_caps caps; 2005 struct dc_check_config check_config; 2006 struct dc_cap_funcs cap_funcs; 2007 struct dc_config config; 2008 struct dc_bounding_box_overrides bb_overrides; 2009 struct dc_bug_wa work_arounds; 2010 struct dc_context *ctx; 2011 struct dc_phy_addr_space_config vm_pa_config; 2012 2013 uint8_t link_count; 2014 struct dc_link *links[MAX_LINKS]; 2015 uint8_t lowest_dpia_link_index; 2016 struct link_service *link_srv; 2017 2018 struct dc_state *current_state; 2019 struct resource_pool *res_pool; 2020 2021 /** 2022 * @update_scratch_pool: Per-commit scratch buffers for dc_update_state. 2023 */ 2024 struct dc_update_scratch_space *update_scratch_pool[MAX_STREAMS + 1]; 2025 bool update_scratch_in_use[MAX_STREAMS + 1]; 2026 2027 struct clk_mgr *clk_mgr; 2028 2029 /* Display Engine Clock levels */ 2030 struct dm_pp_clock_levels sclk_lvls; 2031 2032 /* Inputs into BW and WM calculations. */ 2033 struct bw_calcs_dceip *bw_dceip; 2034 struct bw_calcs_vbios *bw_vbios; 2035 struct dcn_soc_bounding_box *dcn_soc; 2036 struct dcn_ip_params *dcn_ip; 2037 struct display_mode_lib dml; 2038 2039 /* HW functions */ 2040 struct hw_sequencer_funcs hwss; 2041 struct dce_hwseq *hwseq; 2042 2043 /* Require to optimize clocks and bandwidth for added/removed planes */ 2044 bool optimized_required; 2045 bool idle_optimizations_allowed; 2046 bool enable_c20_dtm_b0; 2047 2048 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 2049 2050 /* For eDP to know the switching state of SmartMux */ 2051 bool is_switch_in_progress_orig; 2052 bool is_switch_in_progress_dest; 2053 2054 /* FBC compressor */ 2055 struct compressor *fbc_compressor; 2056 2057 struct dc_debug_data debug_data; 2058 struct dpcd_vendor_signature vendor_signature; 2059 2060 const char *build_id; 2061 struct vm_helper *vm_helper; 2062 2063 uint32_t *dcn_reg_offsets; 2064 uint32_t *nbio_reg_offsets; 2065 uint32_t *clk_reg_offsets; 2066 2067 /* Scratch memory */ 2068 struct { 2069 struct { 2070 /* 2071 * For matching clock_limits table in driver with table 2072 * from PMFW. 2073 */ 2074 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2075 } update_bw_bounding_box; 2076 struct dc_scratch_space current_state; 2077 struct dc_scratch_space new_state; 2078 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 2079 struct dc_link temp_link; 2080 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 2081 } scratch; 2082 2083 struct dml2_configuration_options dml2_options; 2084 struct dml2_configuration_options dml2_dc_power_options; 2085 enum dc_acpi_cm_power_state power_state; 2086 struct soc_and_ip_translator *soc_and_ip_translator; 2087 }; 2088 2089 struct dc_scaling_info { 2090 struct rect src_rect; 2091 struct rect dst_rect; 2092 struct rect clip_rect; 2093 struct scaling_taps scaling_quality; 2094 }; 2095 2096 struct dc_fast_update { 2097 const struct dc_flip_addrs *flip_addr; 2098 const struct dc_gamma *gamma; 2099 const struct colorspace_transform *gamut_remap_matrix; 2100 const struct dc_csc_transform *input_csc_color_matrix; 2101 const struct fixed31_32 *coeff_reduction_factor; 2102 struct dc_transfer_func *out_transfer_func; 2103 struct dc_csc_transform *output_csc_transform; 2104 const struct dc_csc_transform *cursor_csc_color_matrix; 2105 struct cm_hist_control *cm_hist_control; 2106 /* stream-level fast updates */ 2107 const struct colorspace_transform *gamut_remap; 2108 const struct dc_cursor_attributes *cursor_attributes; 2109 const struct dc_cursor_position *cursor_position; 2110 const struct periodic_interrupt_config *periodic_interrupt; 2111 const enum dc_dither_option *dither_option; 2112 struct dc_info_packet *vrr_infopacket; 2113 struct dc_info_packet *vsc_infopacket; 2114 struct dc_info_packet *vsp_infopacket; 2115 struct dc_info_packet *hfvsif_infopacket; 2116 struct dc_info_packet *vtem_infopacket; 2117 struct dc_info_packet *adaptive_sync_infopacket; 2118 struct dc_info_packet *avi_infopacket; 2119 struct dc_info_packet *hdr_static_metadata; 2120 }; 2121 2122 struct dc_surface_update { 2123 struct dc_plane_state *surface; 2124 2125 /* isr safe update parameters. null means no updates */ 2126 const struct dc_flip_addrs *flip_addr; 2127 const struct dc_plane_info *plane_info; 2128 const struct dc_scaling_info *scaling_info; 2129 struct fixed31_32 hdr_mult; 2130 /* following updates require alloc/sleep/spin that is not isr safe, 2131 * null means no updates 2132 */ 2133 const struct dc_gamma *gamma; 2134 const struct dc_transfer_func *in_transfer_func; 2135 2136 const struct dc_csc_transform *input_csc_color_matrix; 2137 const struct fixed31_32 *coeff_reduction_factor; 2138 const struct colorspace_transform *gamut_remap_matrix; 2139 const struct dc_plane_cm *cm; 2140 const struct dc_csc_transform *cursor_csc_color_matrix; 2141 unsigned int sdr_white_level_nits; 2142 struct dc_bias_and_scale bias_and_scale; 2143 struct cm_hist_control *cm_hist_control; 2144 }; 2145 2146 struct dc_state_update { 2147 struct dc_stream_state *stream; 2148 struct dc_stream_update *stream_update; 2149 struct dc_surface_update *surface_updates; 2150 int surface_count; 2151 const struct dc_probe_updates *probe_updates; 2152 }; 2153 2154 /** 2155 * dc_check_state_update() - Classify an update without committing it. 2156 * @check_config: DC check configuration 2157 * @updates: root update object to classify 2158 * 2159 * Return: descriptor indicating update type and required lock scope. 2160 */ 2161 struct dc_update_descriptor dc_check_state_update( 2162 const struct dc_check_config *check_config, 2163 const struct dc_state_update *updates); 2164 2165 /** 2166 * dc_update_state - Commit an absolute dc_state_update. 2167 * @dc: DC structure 2168 * @updates: root update object carrying stream, plane, and probe updates 2169 * 2170 * Return: true on success, false on failure. 2171 */ 2172 bool dc_update_state(struct dc *dc, const struct dc_state_update *updates); 2173 2174 struct dc_update_scratch_space; 2175 2176 /** 2177 * dc_update_state_init - Acquire and initialise a commit scratch buffer. 2178 * @dc: DC structure 2179 * @updates: update descriptor; validated before the slot is acquired 2180 * 2181 * Return: a scratch slot on success, NULL if validation fails or the pool 2182 * is exhausted. The slot must be released via dc_update_state_cleanup() on 2183 * success, or automatically by dc_update_state_prepare() on failure. 2184 */ 2185 struct dc_update_scratch_space *dc_update_state_init( 2186 struct dc *dc, 2187 const struct dc_state_update *updates 2188 ); 2189 2190 /** 2191 * dc_update_state_prepare - Prepare the commit under the global lock. 2192 * @scratch: commit scratch from dc_update_state_init() 2193 * 2194 * On failure the scratch slot is released and false is returned; the caller 2195 * must not call execute or cleanup. 2196 */ 2197 bool dc_update_state_prepare(struct dc_update_scratch_space *scratch); 2198 2199 /** 2200 * dc_update_state_execute - Program hardware; called without the global lock. 2201 * @scratch: commit scratch from dc_update_state_init() 2202 */ 2203 void dc_update_state_execute(const struct dc_update_scratch_space *scratch); 2204 2205 /** 2206 * dc_update_state_cleanup - Finalise the commit and release the scratch slot. 2207 * @scratch: commit scratch from dc_update_state_init() 2208 * 2209 * Must be called with the global lock held. Returns true if the caller must 2210 * loop back to prepare (SEAMLESS continuation). 2211 */ 2212 bool dc_update_state_cleanup(struct dc_update_scratch_space *scratch); 2213 2214 /** 2215 * struct dc_probe_latencies - min/max/avg memory latency in ns. 2216 * @max_latency_ns: maximum latency in nanoseconds 2217 * @avg_latency_ns: average latency in nanoseconds 2218 * @min_latency_ns: minimum latency in nanoseconds 2219 */ 2220 struct dc_probe_latencies { 2221 uint32_t max_latency_ns; 2222 uint32_t avg_latency_ns; 2223 uint32_t min_latency_ns; 2224 }; 2225 2226 /** 2227 * struct dc_probe_status - results for a probe. 2228 * @valid: true if a measurement was latched. 2229 * @type: type of the probe that produced this result. 2230 * @u.bandwidth_mbps: peak BW in Mbps (DC_PROBE_PEAK_MEM_BW). 2231 * @u.latency: min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), 2232 * stored as struct dc_probe_latencies. 2233 * @u.urgent_assertion_count: number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT). 2234 * @u.prefetch_data_size: total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE). 2235 */ 2236 struct dc_probe_status { 2237 bool valid; 2238 enum dc_probe_type type; 2239 union { 2240 uint32_t bandwidth_mbps; 2241 struct dc_probe_latencies latency; 2242 uint32_t urgent_assertion_count; 2243 uint32_t prefetch_data_size; 2244 } u; 2245 }; 2246 2247 /** 2248 * enum dc_get_status_type - Bitmask selecting which status classes to populate. 2249 * @DC_GET_STATUS_STREAM: populate stream_status fields in dc_state_status 2250 * @DC_GET_STATUS_PROBE: populate probe_status fields in dc_state_status 2251 */ 2252 enum dc_get_status_type { 2253 DC_GET_STATUS_STREAM = (1u << 0), 2254 DC_GET_STATUS_PROBE = (1u << 1), 2255 }; 2256 2257 /** 2258 * struct dc_get_status_options - Input selector for dc_state_get_status. 2259 * @state: source state to read status from 2260 * @types: OR of dc_get_status_type values selecting classes to populate 2261 * @stream: optional stream filter for DC_GET_STATUS_STREAM. NULL means 2262 * populate status for all streams in the state 2263 * @probe: optional probe filter for DC_GET_STATUS_PROBE. NULL means 2264 * populate status for all probes in the state 2265 */ 2266 struct dc_get_status_options { 2267 struct dc_state *state; 2268 uint32_t types; 2269 const struct dc_stream_state *stream; 2270 const struct dc_probe_state *probe; 2271 }; 2272 2273 /** 2274 * struct dc_state_status - Output-only status object from dc_state_get_status. 2275 * @stream_count: number of valid entries in stream_status (DC_GET_STATUS_STREAM) 2276 * @stream_status: pointers to live per-stream status entries 2277 * @probe_count: number of valid entries in probe_status (DC_GET_STATUS_PROBE) 2278 * @probe_status: pointers to live per-probe status entries 2279 */ 2280 struct dc_state_status { 2281 int stream_count; 2282 struct dc_stream_status *stream_status[MAX_STREAMS]; 2283 int probe_count; 2284 struct dc_probe_status *probe_status[MAX_PROBES]; 2285 }; 2286 2287 /** 2288 * dc_state_get_status - Unified status readback for dc_state. 2289 * @status: output object populated according to options->types 2290 * @options: selects the source state, status classes to fill, and filters 2291 * 2292 * Return: DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL. 2293 */ 2294 enum dc_status dc_state_get_status(struct dc_state_status *status, 2295 const struct dc_get_status_options *options); 2296 2297 struct dc_underflow_debug_data { 2298 struct dcn_hubbub_reg_state *hubbub_reg_state; 2299 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 2300 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 2301 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 2302 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 2303 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 2304 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 2305 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 2306 }; 2307 2308 struct power_features { 2309 bool ips; 2310 bool rcg; 2311 bool replay; 2312 bool dds; 2313 bool sprs; 2314 bool psr; 2315 bool fams; 2316 bool mpo; 2317 bool uclk_p_state; 2318 }; 2319 2320 /* 2321 * Create a new surface with default parameters; 2322 */ 2323 void dc_gamma_retain(struct dc_gamma *dc_gamma); 2324 void dc_gamma_release(struct dc_gamma **dc_gamma); 2325 struct dc_gamma *dc_create_gamma(void); 2326 2327 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 2328 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 2329 struct dc_transfer_func *dc_create_transfer_func(void); 2330 2331 struct dc_3dlut *dc_create_3dlut_func(void); 2332 void dc_3dlut_func_release(struct dc_3dlut *lut); 2333 void dc_3dlut_func_retain(struct dc_3dlut *lut); 2334 2335 struct dc_plane_cm *dc_plane_cm_create(void); 2336 void dc_plane_cm_release(struct dc_plane_cm *cm); 2337 void dc_plane_cm_retain(struct dc_plane_cm *cm); 2338 2339 void dc_post_update_surfaces_to_stream( 2340 struct dc *dc); 2341 2342 /* 2343 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling 2344 * description for (typically) linear surfaces. 2345 * 2346 * This is used by OS/DM paths that need a valid, fully-initialized tiling 2347 * description without hardcoding gfx-version specifics in the caller. 2348 */ 2349 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); 2350 2351 /** 2352 * struct dc_validation_stream - Per-stream surface/stream association for validation 2353 */ 2354 struct dc_validation_stream { 2355 /** 2356 * @stream: Stream state properties 2357 */ 2358 struct dc_stream_state *stream; 2359 2360 /** 2361 * @plane_states: Surface state 2362 */ 2363 struct dc_plane_state *plane_states[MAX_SURFACES]; 2364 2365 /** 2366 * @plane_count: Total of active planes 2367 */ 2368 uint8_t plane_count; 2369 }; 2370 2371 /** 2372 * struct dc_validation_set - Root validation input grouping all streams for a commit 2373 */ 2374 struct dc_validation_set { 2375 /** 2376 * @streams: Per-stream entries (stream + its planes) 2377 */ 2378 struct dc_validation_stream streams[MAX_STREAMS]; 2379 2380 /** 2381 * @stream_count: Number of active entries in @streams 2382 */ 2383 uint8_t stream_count; 2384 2385 /** 2386 * @probes: Global probe descriptors to validate alongside the streams 2387 */ 2388 struct dc_probe_state probes[MAX_PROBES]; 2389 2390 /** 2391 * @probe_count: Number of active entries in @probes 2392 */ 2393 uint8_t probe_count; 2394 }; 2395 2396 bool dc_validate_boot_timing(const struct dc *dc, 2397 const struct dc_sink *sink, 2398 struct dc_crtc_timing *crtc_timing); 2399 2400 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 2401 2402 enum dc_status dc_validate_with_context(struct dc *dc, 2403 const struct dc_validation_set *set, 2404 struct dc_state *context, 2405 enum dc_validate_mode validate_mode); 2406 2407 bool dc_set_generic_gpio_for_stereo(bool enable, 2408 struct gpio_service *gpio_service); 2409 2410 enum dc_status dc_validate_global_state( 2411 struct dc *dc, 2412 struct dc_state *new_ctx, 2413 enum dc_validate_mode validate_mode); 2414 2415 bool dc_acquire_release_mpc_3dlut( 2416 struct dc *dc, bool acquire, 2417 struct dc_stream_state *stream, 2418 struct dc_3dlut **lut, 2419 struct dc_transfer_func **shaper); 2420 2421 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 2422 void get_audio_check(struct audio_info *aud_modes, 2423 struct audio_check *aud_chk); 2424 2425 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 2426 void populate_fast_updates(struct dc_fast_update *fast_update, 2427 struct dc_surface_update *srf_updates, 2428 int surface_count, 2429 struct dc_stream_update *stream_update); 2430 /* 2431 * Set up streams and links associated to drive sinks 2432 * The streams parameter is an absolute set of all active streams. 2433 * 2434 * After this call: 2435 * Phy, Encoder, Timing Generator are programmed and enabled. 2436 * New streams are enabled with blank stream; no memory read. 2437 */ 2438 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 2439 2440 2441 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2442 struct dc_stream_state *stream, 2443 int mpcc_inst); 2444 2445 2446 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2447 bool dc_set_fva_vrr_adjust(struct dc *dc, 2448 struct dc_stream_state *stream, 2449 struct fva_adj *fva_adj, 2450 struct dc_crtc_timing_adjust *vrr_adj); 2451 2452 int dc_get_hw_max_fva_factor(struct dc *dc, 2453 struct dc_stream_state *stream, 2454 unsigned int max_pixel_clock); 2455 2456 void dc_set_vstartup_start(struct dc *dc, 2457 struct dc_stream_state *stream); 2458 2459 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2460 2461 /* The function returns minimum bandwidth required to drive a given timing 2462 * return - minimum required timing bandwidth in kbps. 2463 */ 2464 uint32_t dc_bandwidth_in_kbps_from_timing( 2465 const struct dc_crtc_timing *timing, 2466 const enum dc_link_encoding_format link_encoding); 2467 2468 /* Link Interfaces */ 2469 /* Return an enumerated dc_link. 2470 * dc_link order is constant and determined at 2471 * boot time. They cannot be created or destroyed. 2472 * Use dc_get_caps() to get number of links. 2473 */ 2474 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2475 2476 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2477 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2478 const struct dc_link *link, 2479 unsigned int *inst_out); 2480 2481 /* Return an array of link pointers to edp links. */ 2482 void dc_get_edp_links(const struct dc *dc, 2483 struct dc_link **edp_links, 2484 unsigned int *edp_num); 2485 2486 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2487 bool powerOn); 2488 2489 /* The function initiates detection handshake over the given link. It first 2490 * determines if there are display connections over the link. If so it initiates 2491 * detection protocols supported by the connected receiver device. The function 2492 * contains protocol specific handshake sequences which are sometimes mandatory 2493 * to establish a proper connection between TX and RX. So it is always 2494 * recommended to call this function as the first link operation upon HPD event 2495 * or power up event. Upon completion, the function will update link structure 2496 * in place based on latest RX capabilities. The function may also cause dpms 2497 * to be reset to off for all currently enabled streams to the link. It is DM's 2498 * responsibility to serialize detection and DPMS updates. 2499 * 2500 * @reason - Indicate which event triggers this detection. dc may customize 2501 * detection flow depending on the triggering events. 2502 * return false - if detection is not fully completed. This could happen when 2503 * there is an unrecoverable error during detection or detection is partially 2504 * completed (detection has been delegated to dm mst manager ie. 2505 * link->connection_type == dc_connection_mst_branch when returning false). 2506 * return true - detection is completed, link has been fully updated with latest 2507 * detection result. 2508 */ 2509 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2510 2511 struct dc_sink_init_data; 2512 2513 /* When link connection type is dc_connection_mst_branch, remote sink can be 2514 * added to the link. The interface creates a remote sink and associates it with 2515 * current link. The sink will be retained by link until remove remote sink is 2516 * called. 2517 * 2518 * @dc_link - link the remote sink will be added to. 2519 * @edid - byte array of EDID raw data. 2520 * @len - size of the edid in byte 2521 * @init_data - 2522 */ 2523 struct dc_sink *dc_link_add_remote_sink( 2524 struct dc_link *dc_link, 2525 const uint8_t *edid, 2526 unsigned int len, 2527 struct dc_sink_init_data *init_data); 2528 2529 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2530 * @link - link the sink should be removed from 2531 * @sink - sink to be removed. 2532 */ 2533 void dc_link_remove_remote_sink( 2534 struct dc_link *link, 2535 struct dc_sink *sink); 2536 2537 /* Enable HPD interrupt handler for a given link */ 2538 void dc_link_enable_hpd(const struct dc_link *link); 2539 2540 /* Disable HPD interrupt handler for a given link */ 2541 void dc_link_disable_hpd(const struct dc_link *link); 2542 2543 /* determine if there is a sink connected to the link 2544 * 2545 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2546 * return - false if an unexpected error occurs, true otherwise. 2547 * 2548 * NOTE: This function doesn't detect downstream sink connections i.e 2549 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2550 * return dc_connection_single if the branch device is connected despite of 2551 * downstream sink's connection status. 2552 */ 2553 bool dc_link_detect_connection_type(struct dc_link *link, 2554 enum dc_connection_type *type); 2555 2556 /* query current hpd pin value 2557 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2558 * 2559 */ 2560 bool dc_link_get_hpd_state(struct dc_link *link); 2561 2562 /* Getter for cached link status from given link */ 2563 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2564 2565 /* enable/disable hardware HPD filter. 2566 * 2567 * @link - The link the HPD pin is associated with. 2568 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2569 * handler once after no HPD change has been detected within dc default HPD 2570 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2571 * pulses within default HPD interval, no HPD event will be received until HPD 2572 * toggles have stopped. Then HPD event will be queued to irq handler once after 2573 * dc default HPD filtering interval since last HPD event. 2574 * 2575 * @enable = false - disable hardware HPD filter. HPD event will be queued 2576 * immediately to irq handler after no HPD change has been detected within 2577 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2578 */ 2579 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2580 2581 /* submit i2c read/write payloads through ddc channel 2582 * @link_index - index to a link with ddc in i2c mode 2583 * @cmd - i2c command structure 2584 * return - true if success, false otherwise. 2585 */ 2586 bool dc_submit_i2c( 2587 struct dc *dc, 2588 uint32_t link_index, 2589 struct i2c_command *cmd); 2590 2591 /* submit i2c read/write payloads through oem channel 2592 * @link_index - index to a link with ddc in i2c mode 2593 * @cmd - i2c command structure 2594 * return - true if success, false otherwise. 2595 */ 2596 bool dc_submit_i2c_oem( 2597 struct dc *dc, 2598 struct i2c_command *cmd); 2599 2600 enum aux_return_code_type; 2601 /* Attempt to transfer the given aux payload. This function does not perform 2602 * retries or handle error states. The reply is returned in the payload->reply 2603 * and the result through operation_result. Returns the number of bytes 2604 * transferred,or -1 on a failure. 2605 */ 2606 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2607 struct aux_payload *payload, 2608 enum aux_return_code_type *operation_result); 2609 2610 struct ddc_service * 2611 dc_get_oem_i2c_device(struct dc *dc); 2612 2613 bool dc_is_oem_i2c_device_present( 2614 struct dc *dc, 2615 size_t slave_address 2616 ); 2617 2618 /* return true if the connected receiver supports the hdcp version */ 2619 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2620 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2621 2622 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2623 * 2624 * TODO - When defer_handling is true the function will have a different purpose. 2625 * It no longer does complete hpd rx irq handling. We should create a separate 2626 * interface specifically for this case. 2627 * 2628 * Return: 2629 * true - Downstream port status changed. DM should call DC to do the 2630 * detection. 2631 * false - no change in Downstream port status. No further action required 2632 * from DM. 2633 */ 2634 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2635 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2636 bool defer_handling, bool *has_left_work); 2637 /* handle DP specs define test automation sequence*/ 2638 void dc_link_dp_handle_automated_test(struct dc_link *link); 2639 2640 /* handle DP Link loss sequence and try to recover RX link loss with best 2641 * effort 2642 */ 2643 void dc_link_dp_handle_link_loss(struct dc_link *link); 2644 2645 /* Determine if hpd rx irq should be handled or ignored 2646 * return true - hpd rx irq should be handled. 2647 * return false - it is safe to ignore hpd rx irq event 2648 */ 2649 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2650 2651 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2652 * @link - link the hpd irq data associated with 2653 * @hpd_irq_dpcd_data - input hpd irq data 2654 * return - true if hpd irq data indicates a link lost 2655 */ 2656 bool dc_link_check_link_loss_status(struct dc_link *link, 2657 union hpd_irq_data *hpd_irq_dpcd_data); 2658 2659 /* Read hpd rx irq data from a given link 2660 * @link - link where the hpd irq data should be read from 2661 * @irq_data - output hpd irq data 2662 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2663 * read has failed. 2664 */ 2665 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2666 struct dc_link *link, 2667 union hpd_irq_data *irq_data); 2668 2669 bool dc_link_frl_poll_status_flag(struct dc_link *link); 2670 bool dc_link_frl_margin_check_uncompressed_video( 2671 const struct dc_link *link, 2672 struct frl_cap_chk_params_fixed31_32 *params, 2673 struct frl_cap_chk_intermediates_fixed31_32 *inter); 2674 2675 /* The function clears recorded DP RX states in the link. DM should call this 2676 * function when it is resuming from S3 power state to previously connected links. 2677 * 2678 * TODO - in the future we should consider to expand link resume interface to 2679 * support clearing previous rx states. So we don't have to rely on dm to call 2680 * this interface explicitly. 2681 */ 2682 void dc_link_clear_dprx_states(struct dc_link *link); 2683 2684 /* Destruct the mst topology of the link and reset the allocated payload table 2685 * 2686 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2687 * still wants to reset MST topology on an unplug event */ 2688 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2689 2690 /* The function calculates effective DP link bandwidth when a given link is 2691 * using the given link settings. 2692 * 2693 * return - total effective link bandwidth in kbps. 2694 */ 2695 uint32_t dc_link_bandwidth_kbps( 2696 const struct dc_link *link, 2697 const struct dc_link_settings *link_setting); 2698 2699 /* The function returns effective HDMI FRL bandwidth given link rate. 2700 * return - total effective link bandwidth in kbps. 2701 */ 2702 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link, 2703 enum hdmi_frl_link_rate link_rate); 2704 2705 struct dp_audio_bandwidth_params { 2706 const struct dc_crtc_timing *crtc_timing; 2707 enum dp_link_encoding link_encoding; 2708 uint32_t channel_count; 2709 uint32_t sample_rate_hz; 2710 }; 2711 2712 /* The function calculates the minimum size of hblank (in bytes) needed to 2713 * support the specified channel count and sample rate combination, given the 2714 * link encoding and timing to be used. This calculation is not supported 2715 * for 8b/10b SST. 2716 * 2717 * return - min hblank size in bytes, 0 if 8b/10b SST. 2718 */ 2719 uint32_t dc_link_required_hblank_size_bytes( 2720 const struct dc_link *link, 2721 struct dp_audio_bandwidth_params *audio_params); 2722 2723 /* The function takes a snapshot of current link resource allocation state 2724 * @dc: pointer to dc of the dm calling this 2725 * @map: a dc link resource snapshot defined internally to dc. 2726 * 2727 * DM needs to capture a snapshot of current link resource allocation mapping 2728 * and store it in its persistent storage. 2729 * 2730 * Some of the link resource is using first come first serve policy. 2731 * The allocation mapping depends on original hotplug order. This information 2732 * is lost after driver is loaded next time. The snapshot is used in order to 2733 * restore link resource to its previous state so user will get consistent 2734 * link capability allocation across reboot. 2735 * 2736 */ 2737 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2738 2739 /* This function restores link resource allocation state from a snapshot 2740 * @dc: pointer to dc of the dm calling this 2741 * @map: a dc link resource snapshot defined internally to dc. 2742 * 2743 * DM needs to call this function after initial link detection on boot and 2744 * before first commit streams to restore link resource allocation state 2745 * from previous boot session. 2746 * 2747 * Some of the link resource is using first come first serve policy. 2748 * The allocation mapping depends on original hotplug order. This information 2749 * is lost after driver is loaded next time. The snapshot is used in order to 2750 * restore link resource to its previous state so user will get consistent 2751 * link capability allocation across reboot. 2752 * 2753 */ 2754 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2755 2756 void dc_link_wait_for_unlocked(struct dc_link *link); 2757 2758 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2759 * interface i.e stream_update->dsc_config 2760 */ 2761 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2762 2763 /* translate a raw link rate data to bandwidth in kbps */ 2764 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2765 2766 /* determine the optimal bandwidth given link and required bw. 2767 * @link - current detected link 2768 * @req_bw - requested bandwidth in kbps 2769 * @link_settings - returned most optimal link settings that can fit the 2770 * requested bandwidth 2771 * return - false if link can't support requested bandwidth, true if link 2772 * settings is found. 2773 */ 2774 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2775 struct dc_link_settings *link_settings, 2776 uint32_t req_bw); 2777 2778 /* return the max dp link settings can be driven by the link without considering 2779 * connected RX device and its capability 2780 */ 2781 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2782 struct dc_link_settings *max_link_enc_cap); 2783 2784 /* determine when the link is driving MST mode, what DP link channel coding 2785 * format will be used. The decision will remain unchanged until next HPD event. 2786 * 2787 * @link - a link with DP RX connection 2788 * return - if stream is committed to this link with MST signal type, type of 2789 * channel coding format dc will choose. 2790 */ 2791 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2792 const struct dc_link *link); 2793 2794 /* get max dp link settings the link can enable with all things considered. (i.e 2795 * TX/RX/Cable capabilities and dp override policies. 2796 * 2797 * @link - a link with DP RX connection 2798 * return - max dp link settings the link can enable. 2799 * 2800 */ 2801 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2802 2803 /* Get the highest encoding format that the link supports; highest meaning the 2804 * encoding format which supports the maximum bandwidth. 2805 * 2806 * @link - a link with DP RX connection 2807 * return - highest encoding format link supports. 2808 */ 2809 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2810 2811 /* get max frl link settings the link can enable with all things considered. 2812 * (i.e TX/RX capabilities and link verification result. 2813 * 2814 * @link - a link with FRL RX connection 2815 * return - max frl link settings the link can enable. 2816 * 2817 */ 2818 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap( 2819 struct dc_link *link); 2820 2821 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2822 * to a link with dp connector signal type. 2823 * @link - a link with dp connector signal type 2824 * return - true if connected, false otherwise 2825 */ 2826 bool dc_link_is_dp_sink_present(struct dc_link *link); 2827 2828 /* Force DP lane settings update to main-link video signal and notify the change 2829 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2830 * tuning purpose. The interface assumes link has already been enabled with DP 2831 * signal. 2832 * 2833 * @lt_settings - a container structure with desired hw_lane_settings 2834 */ 2835 void dc_link_set_drive_settings(struct dc *dc, 2836 struct link_training_settings *lt_settings, 2837 struct dc_link *link); 2838 2839 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2840 * test or debugging purpose. The test pattern will remain until next un-plug. 2841 * 2842 * @link - active link with DP signal output enabled. 2843 * @test_pattern - desired test pattern to output. 2844 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2845 * @test_pattern_color_space - for video test pattern choose a desired color 2846 * space. 2847 * @p_link_settings - For PHY pattern choose a desired link settings 2848 * @p_custom_pattern - some test pattern will require a custom input to 2849 * customize some pattern details. Otherwise keep it to NULL. 2850 * @cust_pattern_size - size of the custom pattern input. 2851 * 2852 */ 2853 bool dc_link_dp_set_test_pattern( 2854 struct dc_link *link, 2855 enum dp_test_pattern test_pattern, 2856 enum dp_test_pattern_color_space test_pattern_color_space, 2857 const struct link_training_settings *p_link_settings, 2858 const unsigned char *p_custom_pattern, 2859 unsigned int cust_pattern_size); 2860 2861 /* Force DP link settings to always use a specific value until reboot to a 2862 * specific link. If link has already been enabled, the interface will also 2863 * switch to desired link settings immediately. This is a debug interface to 2864 * generic dp issue trouble shooting. 2865 */ 2866 void dc_link_set_preferred_link_settings(struct dc *dc, 2867 struct dc_link_settings *link_setting, 2868 struct dc_link *link); 2869 2870 /* Force FRL link settings to always use a specific value until reboot to a 2871 * specific link. If link has already been enabled, the interface will also 2872 * switch to desired link settings immediately. This is a debug interface to 2873 * generic FRL issue trouble shooting. 2874 */ 2875 void dc_link_set_preferred_frl_link_settings(struct dc *dc, 2876 struct dc_hdmi_frl_link_settings *link_setting, 2877 struct dc_hdmi_frl_link_training_overrides *lt_overrides, 2878 struct dc_link *link); 2879 2880 /* Force DP link to customize a specific link training behavior by overriding to 2881 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2882 * display specific link training issues or apply some display specific 2883 * workaround in link training. 2884 * 2885 * @link_settings - if not NULL, force preferred link settings to the link. 2886 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2887 * will apply this particular override in future link training. If NULL is 2888 * passed in, dc resets previous overrides. 2889 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2890 * training settings. 2891 */ 2892 void dc_link_set_preferred_training_settings(struct dc *dc, 2893 struct dc_link_settings *link_setting, 2894 struct dc_link_training_overrides *lt_overrides, 2895 struct dc_link *link, 2896 bool skip_immediate_retrain); 2897 2898 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2899 bool dc_link_is_fec_supported(const struct dc_link *link); 2900 2901 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2902 * link enablement. 2903 * return - true if FEC should be enabled, false otherwise. 2904 */ 2905 bool dc_link_should_enable_fec(const struct dc_link *link); 2906 2907 /* determine lttpr mode the current link should be enabled with a specific link 2908 * settings. 2909 */ 2910 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2911 struct dc_link_settings *link_setting); 2912 2913 /* Force DP RX to update its power state. 2914 * NOTE: this interface doesn't update dp main-link. Calling this function will 2915 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2916 * RX power state back upon finish DM specific execution requiring DP RX in a 2917 * specific power state. 2918 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2919 * state. 2920 */ 2921 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2922 2923 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2924 * current value read from extended receiver cap from 02200h - 0220Fh. 2925 * Some DP RX has problems of providing accurate DP receiver caps from extended 2926 * field, this interface is a workaround to revert link back to use base caps. 2927 */ 2928 void dc_link_overwrite_extended_receiver_cap( 2929 struct dc_link *link); 2930 2931 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2932 bool wait_for_hpd); 2933 2934 /* Set backlight level of an embedded panel (eDP, LVDS). 2935 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2936 * and 16 bit fractional, where 1.0 is max backlight value. 2937 */ 2938 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2939 struct set_backlight_level_params *backlight_level_params); 2940 2941 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2942 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2943 bool isHDR, 2944 uint32_t backlight_millinits, 2945 uint32_t transition_time_in_ms); 2946 2947 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2948 uint32_t *backlight_millinits, 2949 uint32_t *backlight_millinits_peak); 2950 2951 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2952 2953 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2954 2955 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2956 bool wait, bool force_static, const unsigned int *power_opts); 2957 2958 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2959 2960 bool dc_link_setup_psr(struct dc_link *dc_link, 2961 const struct dc_stream_state *stream, struct psr_config *psr_config, 2962 struct psr_context *psr_context); 2963 2964 /* 2965 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2966 * 2967 * @link: pointer to the dc_link struct instance 2968 * @enable: enable(active) or disable(inactive) replay 2969 * @wait: state transition need to wait the active set completed. 2970 * @force_static: force disable(inactive) the replay 2971 * @power_opts: set power optimazation parameters to DMUB. 2972 * 2973 * return: allow Replay active will return true, else will return false. 2974 */ 2975 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2976 bool wait, bool force_static, const unsigned int *power_opts); 2977 2978 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2979 2980 /* 2981 * Enable or disable Panel Replay on the specified link: 2982 * 2983 * @link: pointer to the dc_link struct instance 2984 * @enable: enable or disable Panel Replay 2985 * 2986 * return: true if successful, false otherwise 2987 */ 2988 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2989 2990 /* 2991 * Update Panel Replay state parameters: 2992 * 2993 * @link: pointer to the dc_link struct instance 2994 * @update_state_data: pointer to state update data structure 2995 * 2996 * return: true if successful, false otherwise 2997 */ 2998 bool dc_link_update_pr_state(struct dc_link *link, 2999 struct dmub_cmd_pr_update_state_data *update_state_data); 3000 3001 /* 3002 * Send general command to Panel Replay firmware: 3003 * 3004 * @link: pointer to the dc_link struct instance 3005 * @general_cmd_data: pointer to general command data structure 3006 * 3007 * return: true if successful, false otherwise 3008 */ 3009 bool dc_link_set_pr_general_cmd(struct dc_link *link, 3010 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 3011 3012 /* 3013 * Measure Panel Replay residency for the given link. 3014 * mode: PR_RESIDENCY_MODE_PHY, PR_RESIDENCY_MODE_ALPM, or 3015 * PR_RESIDENCY_MODE_ENABLEMENT_PERIOD 3016 */ 3017 void dc_link_edp_replay_residency(const struct dc_link *link, 3018 unsigned int *residency, bool is_start, enum pr_residency_mode mode); 3019 3020 /* 3021 * Get Panel Replay state: 3022 * 3023 * @link: pointer to the dc_link struct instance 3024 * @state: pointer to store the Panel Replay state 3025 * 3026 * return: true if successful, false otherwise 3027 */ 3028 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 3029 3030 /* On eDP links this function call will stall until T12 has elapsed. 3031 * If the panel is not in power off state, this function will return 3032 * immediately. 3033 */ 3034 bool dc_link_wait_for_t12(struct dc_link *link); 3035 3036 /* Determine if dp trace has been initialized to reflect upto date result * 3037 * return - true if trace is initialized and has valid data. False dp trace 3038 * doesn't have valid result. 3039 */ 3040 bool dc_dp_trace_is_initialized(struct dc_link *link); 3041 3042 /* Query a dp trace flag to indicate if the current dp trace data has been 3043 * logged before 3044 */ 3045 bool dc_dp_trace_is_logged(struct dc_link *link, 3046 bool in_detection); 3047 3048 /* Set dp trace flag to indicate whether DM has already logged the current dp 3049 * trace data. DM can set is_logged to true upon logging and check 3050 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 3051 */ 3052 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 3053 bool in_detection, 3054 bool is_logged); 3055 3056 /* Obtain driver time stamp for last dp link training end. The time stamp is 3057 * formatted based on dm_get_timestamp DM function. 3058 * @in_detection - true to get link training end time stamp of last link 3059 * training in detection sequence. false to get link training end time stamp 3060 * of last link training in commit (dpms) sequence 3061 */ 3062 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 3063 bool in_detection); 3064 3065 /* Get how many link training attempts dc has done with latest sequence. 3066 * @in_detection - true to get link training count of last link 3067 * training in detection sequence. false to get link training count of last link 3068 * training in commit (dpms) sequence 3069 */ 3070 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 3071 bool in_detection); 3072 3073 /* Get how many link loss has happened since last link training attempts */ 3074 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 3075 3076 /* 3077 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 3078 */ 3079 /* 3080 * Send a request from DP-Tx requesting to allocate BW remotely after 3081 * allocating it locally. This will get processed by CM and a CB function 3082 * will be called. 3083 * 3084 * @link: pointer to the dc_link struct instance 3085 * @req_bw: The requested bw in Kbyte to allocated 3086 * 3087 * return: none 3088 */ 3089 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 3090 3091 /* 3092 * Handle the USB4 BW Allocation related functionality here: 3093 * Plug => Try to allocate max bw from timing parameters supported by the sink 3094 * Unplug => de-allocate bw 3095 * 3096 * @link: pointer to the dc_link struct instance 3097 * @peak_bw: Peak bw used by the link/sink 3098 * 3099 */ 3100 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 3101 struct dc_link *link, int peak_bw); 3102 3103 /* 3104 * Calculates the DP tunneling bandwidth required for the stream timing 3105 * and aggregates the stream bandwidth for the respective DP tunneling link 3106 * 3107 * return: dc_status 3108 */ 3109 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 3110 3111 /* 3112 * Get if ALPM is supported by the link 3113 */ 3114 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 3115 bool *auxwake_support); 3116 3117 /* Sink Interfaces - A sink corresponds to a display output device */ 3118 3119 struct dc_container_id { 3120 // 128bit GUID in binary form 3121 unsigned char guid[16]; 3122 // 8 byte port ID -> ELD.PortID 3123 unsigned int portId[2]; 3124 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 3125 unsigned short manufacturerName; 3126 // 2 byte product code -> ELD.ProductCode 3127 unsigned short productCode; 3128 }; 3129 3130 3131 struct dc_sink_dsc_caps { 3132 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 3133 // 'false' if they are sink's DSC caps 3134 bool is_virtual_dpcd_dsc; 3135 // 'true' if MST topology supports DSC passthrough for sink 3136 // 'false' if MST topology does not support DSC passthrough 3137 bool is_dsc_passthrough_supported; 3138 struct dsc_dec_dpcd_caps dsc_dec_caps; 3139 }; 3140 3141 struct dc_sink_hblank_expansion_caps { 3142 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 3143 // 'false' if they are sink's HBlank expansion caps 3144 bool is_virtual_dpcd_hblank_expansion; 3145 struct hblank_expansion_dpcd_caps dpcd_caps; 3146 }; 3147 3148 struct dc_sink_fec_caps { 3149 bool is_rx_fec_supported; 3150 bool is_topology_fec_supported; 3151 }; 3152 3153 struct scdc_caps { 3154 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 3155 union hdmi_scdc_device_id_data device_id; 3156 }; 3157 3158 /* 3159 * The sink structure contains EDID and other display device properties 3160 */ 3161 struct dc_sink { 3162 enum signal_type sink_signal; 3163 struct dc_edid dc_edid; /* raw edid */ 3164 struct dc_edid_caps edid_caps; /* parse display caps */ 3165 struct dc_container_id *dc_container_id; 3166 uint32_t dongle_max_pix_clk; 3167 void *priv; 3168 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 3169 bool converter_disable_audio; 3170 3171 struct mccs_caps mccs_caps; 3172 struct scdc_caps scdc_caps; 3173 struct dc_sink_dsc_caps dsc_caps; 3174 struct dc_sink_fec_caps fec_caps; 3175 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 3176 3177 bool is_vsc_sdp_colorimetry_supported; 3178 3179 /* private to DC core */ 3180 struct dc_link *link; 3181 struct dc_context *ctx; 3182 3183 uint32_t sink_id; 3184 3185 /* private to dc_sink.c */ 3186 // refcount must be the last member in dc_sink, since we want the 3187 // sink structure to be logically cloneable up to (but not including) 3188 // refcount 3189 struct kref refcount; 3190 }; 3191 3192 void dc_sink_retain(struct dc_sink *sink); 3193 void dc_sink_release(struct dc_sink *sink); 3194 3195 struct dc_sink_init_data { 3196 enum signal_type sink_signal; 3197 struct dc_link *link; 3198 uint32_t dongle_max_pix_clk; 3199 bool converter_disable_audio; 3200 }; 3201 3202 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 3203 3204 /* Newer interfaces */ 3205 struct dc_cursor { 3206 struct dc_plane_address address; 3207 struct dc_cursor_attributes attributes; 3208 }; 3209 3210 3211 /* Interrupt interfaces */ 3212 enum dc_irq_source dc_interrupt_to_irq_source( 3213 struct dc *dc, 3214 uint32_t src_id, 3215 uint32_t ext_id); 3216 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 3217 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 3218 bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst); 3219 enum dc_irq_source dc_get_hpd_irq_source_at_index( 3220 struct dc *dc, uint32_t link_index); 3221 3222 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 3223 3224 /* Power Interfaces */ 3225 3226 void dc_set_power_state( 3227 struct dc *dc, 3228 enum dc_acpi_cm_power_state power_state); 3229 void dc_resume(struct dc *dc); 3230 3231 void dc_power_down_on_boot(struct dc *dc); 3232 3233 void dc_disable_dangling_timing_generators(struct dc *dc); 3234 3235 /* 3236 * HDCP Interfaces 3237 */ 3238 enum hdcp_message_status dc_process_hdcp_msg( 3239 enum signal_type signal, 3240 struct dc_link *link, 3241 struct hdcp_protection_message *message_info); 3242 bool dc_is_dmcu_initialized(struct dc *dc); 3243 3244 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 3245 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 3246 3247 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 3248 unsigned int pitch, 3249 unsigned int height, 3250 enum surface_pixel_format format, 3251 struct dc_cursor_attributes *cursor_attr); 3252 3253 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 3254 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 3255 3256 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 3257 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 3258 bool dc_dmub_is_ips_idle_state(struct dc *dc); 3259 3260 /* set min and max memory clock to lowest and highest DPM level, respectively */ 3261 void dc_unlock_memory_clock_frequency(struct dc *dc); 3262 3263 /* set min memory clock to the min required for current mode, max to maxDPM */ 3264 void dc_lock_memory_clock_frequency(struct dc *dc); 3265 3266 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 3267 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 3268 3269 /* cleanup on driver unload */ 3270 void dc_hardware_release(struct dc *dc); 3271 3272 /* disables fw based mclk switch */ 3273 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 3274 3275 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 3276 3277 bool dc_set_replay_allow_active(struct dc *dc, bool active); 3278 3279 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 3280 3281 void dc_z10_restore(const struct dc *dc); 3282 void dc_z10_save_init(struct dc *dc); 3283 3284 bool dc_is_dmub_outbox_supported(struct dc *dc); 3285 bool dc_enable_dmub_notifications(struct dc *dc); 3286 3287 bool dc_abm_save_restore( 3288 struct dc *dc, 3289 struct dc_stream_state *stream, 3290 struct abm_save_restore *pData); 3291 3292 void dc_enable_dmub_outbox(struct dc *dc); 3293 3294 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 3295 uint32_t link_index, 3296 struct aux_payload *payload); 3297 3298 /* 3299 * smart power OLED Interfaces 3300 */ 3301 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 3302 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 3303 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 3304 3305 /* Get dc link index from dpia port index */ 3306 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 3307 uint8_t dpia_port_index); 3308 3309 bool dc_process_dmub_set_config_async(struct dc *dc, 3310 uint32_t link_index, 3311 struct set_config_cmd_payload *payload, 3312 struct dmub_notification *notify); 3313 3314 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 3315 uint32_t link_index, 3316 uint8_t mst_alloc_slots, 3317 uint8_t *mst_slots_in_use); 3318 3319 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 3320 3321 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 3322 uint32_t hpd_int_enable); 3323 3324 void dc_print_dmub_diagnostic_data(const struct dc *dc); 3325 3326 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 3327 3328 struct dc_power_profile { 3329 int power_level; /* Lower is better */ 3330 }; 3331 3332 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 3333 3334 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 3335 3336 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 3337 3338 void dc_log_preos_dmcub_info(const struct dc *dc); 3339 3340 /* DSC Interfaces */ 3341 #include "dc_dsc.h" 3342 3343 void dc_get_visual_confirm_for_stream( 3344 struct dc *dc, 3345 struct dc_stream_state *stream_state, 3346 struct tg_color *color); 3347 3348 /* Disable acc mode Interfaces */ 3349 void dc_disable_accelerated_mode(struct dc *dc); 3350 3351 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 3352 struct dc_stream_state *new_stream); 3353 3354 bool dc_is_cursor_limit_pending(struct dc *dc); 3355 bool dc_can_clear_cursor_limit(const struct dc *dc); 3356 3357 /** 3358 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 3359 * 3360 * @dc: Pointer to the display core context. 3361 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 3362 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 3363 * 3364 * This function collects and logs underflow-related HW states when underflow happens, 3365 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 3366 * The results are stored in the provided out_data structure for further analysis or logging. 3367 */ 3368 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); 3369 3370 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); 3371 3372 /* 3373 * Software state variables used to program register fields across the display pipeline 3374 */ 3375 struct dc_register_software_state { 3376 /* HUBP register programming variables for each pipe */ 3377 struct { 3378 bool valid_plane_state; 3379 bool valid_stream; 3380 bool min_dc_gfx_version9; 3381 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 3382 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 3383 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 3384 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 3385 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 3386 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 3387 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 3388 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 3389 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 3390 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 3391 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 3392 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 3393 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 3394 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 3395 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 3396 3397 /* Additional DCC configuration */ 3398 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 3399 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 3400 3401 /* Surface pitch configuration */ 3402 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 3403 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 3404 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 3405 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 3406 3407 /* Surface addresses */ 3408 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 3409 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 3410 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 3411 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 3412 3413 /* TMZ configuration */ 3414 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 3415 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 3416 3417 /* Tiling configuration */ 3418 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 3419 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 3420 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 3421 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 3422 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 3423 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 3424 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 3425 3426 /* DML Request Size Configuration - Luma */ 3427 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 3428 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 3429 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 3430 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 3431 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 3432 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 3433 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 3434 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 3435 3436 /* DML Request Size Configuration - Chroma */ 3437 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 3438 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 3439 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 3440 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 3441 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 3442 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 3443 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 3444 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 3445 3446 /* DML Expansion Modes */ 3447 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 3448 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 3449 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 3450 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 3451 3452 /* DML DLG parameters - nominal */ 3453 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 3454 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 3455 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 3456 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 3457 3458 /* DML prefetch settings */ 3459 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 3460 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 3461 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 3462 3463 /* TTU parameters */ 3464 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 3465 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 3466 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 3467 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 3468 } hubp[MAX_PIPES]; 3469 3470 /* HUBBUB register programming variables */ 3471 struct { 3472 /* Individual DET buffer control per pipe - software state that programs DET registers */ 3473 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 3474 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 3475 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 3476 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 3477 3478 /* Compression buffer control - software state that programs COMPBUF registers */ 3479 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 3480 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 3481 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 3482 } hubbub; 3483 3484 /* DPP register programming variables for each pipe (simplified for available fields) */ 3485 struct { 3486 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 3487 3488 /* Recout (Rectangle of Interest) configuration */ 3489 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 3490 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 3491 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 3492 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 3493 3494 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 3495 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 3496 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 3497 3498 /* DSCL mode configuration */ 3499 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3500 3501 /* Scaler ratios (simplified to integer parts) */ 3502 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3503 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3504 3505 /* Basic scaler taps */ 3506 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3507 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3508 } dpp[MAX_PIPES]; 3509 3510 /* DCCG register programming variables */ 3511 struct { 3512 /* Core Display Clock Control */ 3513 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3514 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3515 3516 /* DPP Clock Control - 4 fields per pipe */ 3517 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3518 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3519 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3520 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3521 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3522 3523 /* DSC Clock Control - 4 fields per DSC resource */ 3524 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3525 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3526 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3527 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3528 3529 /* Pixel Clock Control - per pipe */ 3530 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3531 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3532 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3533 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3534 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3535 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3536 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3537 3538 /* DTBCLK DTO Control - 4 DTOs */ 3539 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3540 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3541 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3542 3543 /* DP Stream Clock Control - 4 pipes */ 3544 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3545 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3546 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3547 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3548 3549 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3550 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3551 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3552 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3553 3554 /* SYMCLK32 SE Control - 4 instances */ 3555 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3556 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3557 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3558 3559 /* SYMCLK32 LE Control - 2 instances */ 3560 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3561 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3562 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3563 3564 /* HDMI Clock Control */ 3565 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */ 3566 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */ 3567 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */ 3568 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */ 3569 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */ 3570 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */ 3571 3572 /* DPIA Clock Control */ 3573 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3574 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3575 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3576 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3577 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3578 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3579 3580 /* Clock Gating Control */ 3581 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3582 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3583 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3584 3585 /* VSync Control */ 3586 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3587 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3588 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3589 3590 /* Time Base Control */ 3591 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3592 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3593 } dccg; 3594 3595 /* DSC essential configuration for underflow analysis */ 3596 struct { 3597 /* DSC active state - critical for bandwidth analysis */ 3598 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3599 3600 /* DSC configuration affecting bandwidth and timing */ 3601 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3602 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3603 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3604 3605 /* OPP integration - affects pipeline flow */ 3606 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3607 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3608 } dsc[MAX_PIPES]; 3609 3610 /* MPC register programming variables */ 3611 struct { 3612 /* MPCC blending tree and mode control */ 3613 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3614 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3615 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3616 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3617 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3618 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3619 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3620 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3621 3622 /* MPCC blending tree connections */ 3623 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3624 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3625 3626 /* MPCC output gamma control */ 3627 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3628 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3629 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3630 3631 /* MPCC pipe assignment and status */ 3632 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3633 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3634 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3635 3636 /* MPC output processing */ 3637 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3638 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3639 } mpc; 3640 3641 /* OPP register programming variables for each pipe */ 3642 struct { 3643 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3644 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3645 3646 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3647 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3648 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3649 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3650 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3651 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3652 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3653 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3654 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3655 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3656 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3657 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3658 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3659 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3660 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3661 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3662 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3663 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3664 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3665 3666 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3667 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3668 3669 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3670 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3671 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3672 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3673 3674 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3675 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3676 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3677 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3678 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3679 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3680 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3681 3682 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3683 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3684 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3685 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3686 } opp[MAX_PIPES]; 3687 3688 /* OPTC register programming variables for each pipe */ 3689 struct { 3690 uint32_t otg_master_inst; 3691 3692 /* OTG_CONTROL register - 5 fields for OTG control */ 3693 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3694 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3695 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3696 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3697 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3698 3699 /* OTG Horizontal Timing - 7 fields */ 3700 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3701 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3702 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3703 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3704 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3705 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3706 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3707 3708 /* OTG Vertical Timing - 7 fields */ 3709 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3710 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3711 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3712 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3713 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3714 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3715 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3716 3717 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3718 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3719 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3720 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3721 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3722 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3723 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3724 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3725 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3726 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3727 3728 /* OPTC Data Source and ODM - 6 fields */ 3729 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3730 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3731 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3732 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3733 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3734 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3735 3736 /* OPTC Data Format and DSC - 4 fields */ 3737 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3738 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3739 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3740 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3741 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3742 3743 /* OPTC Clock and Underflow Control - 4 fields */ 3744 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3745 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3746 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3747 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3748 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3749 3750 /* OTG Stereo and 3D Control - 6 fields */ 3751 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3752 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3753 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3754 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3755 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3756 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3757 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3758 3759 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3760 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3761 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3762 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3763 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3764 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3765 3766 /* OTG DRR Advanced Control - 4 fields */ 3767 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3768 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3769 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3770 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3771 3772 /* OTG DSC Position Control - 2 fields */ 3773 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3774 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3775 3776 /* OTG Double Buffer Control - 2 fields */ 3777 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3778 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3779 3780 /* OTG Vertical Interrupts - 6 fields */ 3781 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3782 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3783 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3784 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3785 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3786 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3787 3788 /* OTG Global Sync Parameters - 6 fields */ 3789 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3790 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3791 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3792 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3793 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3794 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3795 3796 /* OTG Manual Trigger Control - 11 fields */ 3797 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3798 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3799 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3800 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3801 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3802 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3803 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3804 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3805 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3806 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3807 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3808 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3809 3810 /* OTG Static Screen and Update Control - 6 fields */ 3811 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3812 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3813 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3814 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3815 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3816 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3817 3818 /* VTG Control - 3 fields */ 3819 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3820 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3821 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3822 3823 /* OTG Status (Read-Only) - 12 fields */ 3824 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3825 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3826 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3827 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3828 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3829 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3830 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3831 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3832 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3833 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3834 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3835 } optc[MAX_PIPES]; 3836 3837 /* Metadata */ 3838 uint32_t active_pipe_count; 3839 uint32_t active_stream_count; 3840 bool state_valid; 3841 }; 3842 3843 /** 3844 * dc_capture_register_software_state() - Capture software state for register programming 3845 * @dc: DC context containing current display configuration 3846 * @state: Pointer to dc_register_software_state structure to populate 3847 * 3848 * Extracts all software state variables that are used to program hardware register 3849 * fields across the display driver pipeline. This provides a complete snapshot 3850 * of the software configuration that drives hardware register programming. 3851 * 3852 * The function traverses the DC context and extracts values from: 3853 * - Stream configurations (timing, format, DSC settings) 3854 * - Plane states (surface format, rotation, scaling, cursor) 3855 * - Pipe contexts (resource allocation, blending, viewport) 3856 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3857 * - Resource context (DET buffer allocation, ODM configuration) 3858 * 3859 * This is essential for underflow debugging as it captures the exact software 3860 * state that determines how registers are programmed, allowing analysis of 3861 * whether underflow is caused by incorrect register programming or timing issues. 3862 * 3863 * Return: true if state was successfully captured, false on error 3864 */ 3865 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3866 3867 /** 3868 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3869 * @dc: DC context containing current display configuration 3870 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3871 * 3872 * This function retrieves QoS metrics from the display core that can be used by 3873 * benchmark tools to analyze display system performance. The function may take 3874 * several milliseconds to execute due to hardware measurement requirements. 3875 * 3876 * QoS information includes: 3877 * - Bandwidth bounds (lower limits in Mbps) 3878 * - Latency bounds (upper limits in nanoseconds) 3879 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3880 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3881 * 3882 * The function will populate the provided dc_qos_info structure with current 3883 * QoS measurements. If hardware measurement functions are not available for 3884 * the current DCN version, the function returns false with zero'd info structure. 3885 * 3886 * Return: true if QoS information was successfully retrieved, false if measurement 3887 * functions are unavailable or hardware measurements cannot be performed 3888 */ 3889 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3890 3891 /** 3892 * dc_override_memory_bandwidth_request - Override the DCN nominal memory 3893 * bandwidth request sent to PMFW, independent of the current display mode. 3894 * For debug use only. 3895 * @dc: DC instance 3896 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override 3897 * 3898 * Return: capped bandwidth value actually applied (MB/s) 3899 */ 3900 unsigned int dc_override_memory_bandwidth_request( 3901 struct dc *dc, 3902 unsigned int bw_mbps); 3903 3904 #endif /* DC_INTERFACE_H_ */ 3905