1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 struct abm_save_restore; 50 51 /* forward declaration */ 52 struct aux_payload; 53 struct set_config_cmd_payload; 54 struct dmub_notification; 55 56 #define DC_VER "3.2.327" 57 58 /** 59 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 60 */ 61 #define MAX_SURFACES 4 62 /** 63 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 64 */ 65 #define MAX_PLANES 6 66 #define MAX_STREAMS 6 67 #define MIN_VIEWPORT_SIZE 12 68 #define MAX_NUM_EDP 2 69 #define MAX_HOST_ROUTERS_NUM 2 70 71 /* Display Core Interfaces */ 72 struct dc_versions { 73 const char *dc_ver; 74 struct dmcu_version dmcu_version; 75 }; 76 77 enum dp_protocol_version { 78 DP_VERSION_1_4 = 0, 79 DP_VERSION_2_1, 80 DP_VERSION_UNKNOWN, 81 }; 82 83 enum dc_plane_type { 84 DC_PLANE_TYPE_INVALID, 85 DC_PLANE_TYPE_DCE_RGB, 86 DC_PLANE_TYPE_DCE_UNDERLAY, 87 DC_PLANE_TYPE_DCN_UNIVERSAL, 88 }; 89 90 // Sizes defined as multiples of 64KB 91 enum det_size { 92 DET_SIZE_DEFAULT = 0, 93 DET_SIZE_192KB = 3, 94 DET_SIZE_256KB = 4, 95 DET_SIZE_320KB = 5, 96 DET_SIZE_384KB = 6 97 }; 98 99 100 struct dc_plane_cap { 101 enum dc_plane_type type; 102 uint32_t per_pixel_alpha : 1; 103 struct { 104 uint32_t argb8888 : 1; 105 uint32_t nv12 : 1; 106 uint32_t fp16 : 1; 107 uint32_t p010 : 1; 108 uint32_t ayuv : 1; 109 } pixel_format_support; 110 // max upscaling factor x1000 111 // upscaling factors are always >= 1 112 // for example, 1080p -> 8K is 4.0, or 4000 raw value 113 struct { 114 uint32_t argb8888; 115 uint32_t nv12; 116 uint32_t fp16; 117 } max_upscale_factor; 118 // max downscale factor x1000 119 // downscale factors are always <= 1 120 // for example, 8K -> 1080p is 0.25, or 250 raw value 121 struct { 122 uint32_t argb8888; 123 uint32_t nv12; 124 uint32_t fp16; 125 } max_downscale_factor; 126 // minimal width/height 127 uint32_t min_width; 128 uint32_t min_height; 129 }; 130 131 /** 132 * DOC: color-management-caps 133 * 134 * **Color management caps (DPP and MPC)** 135 * 136 * Modules/color calculates various color operations which are translated to 137 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 138 * DCN1, every new generation comes with fairly major differences in color 139 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 140 * decide mapping to HW block based on logical capabilities. 141 */ 142 143 /** 144 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 145 * @srgb: RGB color space transfer func 146 * @bt2020: BT.2020 transfer func 147 * @gamma2_2: standard gamma 148 * @pq: perceptual quantizer transfer function 149 * @hlg: hybrid log–gamma transfer function 150 */ 151 struct rom_curve_caps { 152 uint16_t srgb : 1; 153 uint16_t bt2020 : 1; 154 uint16_t gamma2_2 : 1; 155 uint16_t pq : 1; 156 uint16_t hlg : 1; 157 }; 158 159 /** 160 * struct dpp_color_caps - color pipeline capabilities for display pipe and 161 * plane blocks 162 * 163 * @dcn_arch: all DCE generations treated the same 164 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 165 * just plain 256-entry lookup 166 * @icsc: input color space conversion 167 * @dgam_ram: programmable degamma LUT 168 * @post_csc: post color space conversion, before gamut remap 169 * @gamma_corr: degamma correction 170 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 171 * with MPC by setting mpc:shared_3d_lut flag 172 * @ogam_ram: programmable out/blend gamma LUT 173 * @ocsc: output color space conversion 174 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 175 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 176 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 177 * 178 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 179 */ 180 struct dpp_color_caps { 181 uint16_t dcn_arch : 1; 182 uint16_t input_lut_shared : 1; 183 uint16_t icsc : 1; 184 uint16_t dgam_ram : 1; 185 uint16_t post_csc : 1; 186 uint16_t gamma_corr : 1; 187 uint16_t hw_3d_lut : 1; 188 uint16_t ogam_ram : 1; 189 uint16_t ocsc : 1; 190 uint16_t dgam_rom_for_yuv : 1; 191 struct rom_curve_caps dgam_rom_caps; 192 struct rom_curve_caps ogam_rom_caps; 193 }; 194 195 /** 196 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 197 * plane combined blocks 198 * 199 * @gamut_remap: color transformation matrix 200 * @ogam_ram: programmable out gamma LUT 201 * @ocsc: output color space conversion matrix 202 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 203 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 204 * instance 205 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 206 */ 207 struct mpc_color_caps { 208 uint16_t gamut_remap : 1; 209 uint16_t ogam_ram : 1; 210 uint16_t ocsc : 1; 211 uint16_t num_3dluts : 3; 212 uint16_t shared_3d_lut:1; 213 struct rom_curve_caps ogam_rom_caps; 214 }; 215 216 /** 217 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 218 * @dpp: color pipes caps for DPP 219 * @mpc: color pipes caps for MPC 220 */ 221 struct dc_color_caps { 222 struct dpp_color_caps dpp; 223 struct mpc_color_caps mpc; 224 }; 225 226 struct dc_dmub_caps { 227 bool psr; 228 bool mclk_sw; 229 bool subvp_psr; 230 bool gecc_enable; 231 uint8_t fams_ver; 232 bool aux_backlight_support; 233 }; 234 235 struct dc_scl_caps { 236 bool sharpener_support; 237 }; 238 239 struct dc_caps { 240 uint32_t max_streams; 241 uint32_t max_links; 242 uint32_t max_audios; 243 uint32_t max_slave_planes; 244 uint32_t max_slave_yuv_planes; 245 uint32_t max_slave_rgb_planes; 246 uint32_t max_planes; 247 uint32_t max_downscale_ratio; 248 uint32_t i2c_speed_in_khz; 249 uint32_t i2c_speed_in_khz_hdcp; 250 uint32_t dmdata_alloc_size; 251 unsigned int max_cursor_size; 252 unsigned int max_video_width; 253 /* 254 * max video plane width that can be safely assumed to be always 255 * supported by single DPP pipe. 256 */ 257 unsigned int max_optimizable_video_width; 258 unsigned int min_horizontal_blanking_period; 259 int linear_pitch_alignment; 260 bool dcc_const_color; 261 bool dynamic_audio; 262 bool is_apu; 263 bool dual_link_dvi; 264 bool post_blend_color_processing; 265 bool force_dp_tps4_for_cp2520; 266 bool disable_dp_clk_share; 267 bool psp_setup_panel_mode; 268 bool extended_aux_timeout_support; 269 bool dmcub_support; 270 bool zstate_support; 271 bool ips_support; 272 uint32_t num_of_internal_disp; 273 enum dp_protocol_version max_dp_protocol_version; 274 unsigned int mall_size_per_mem_channel; 275 unsigned int mall_size_total; 276 unsigned int cursor_cache_size; 277 struct dc_plane_cap planes[MAX_PLANES]; 278 struct dc_color_caps color; 279 struct dc_dmub_caps dmub_caps; 280 bool dp_hpo; 281 bool dp_hdmi21_pcon_support; 282 bool edp_dsc_support; 283 bool vbios_lttpr_aware; 284 bool vbios_lttpr_enable; 285 bool fused_io_supported; 286 uint32_t max_otg_num; 287 uint32_t max_cab_allocation_bytes; 288 uint32_t cache_line_size; 289 uint32_t cache_num_ways; 290 uint16_t subvp_fw_processing_delay_us; 291 uint8_t subvp_drr_max_vblank_margin_us; 292 uint16_t subvp_prefetch_end_to_mall_start_us; 293 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 294 uint16_t subvp_pstate_allow_width_us; 295 uint16_t subvp_vertical_int_margin_us; 296 bool seamless_odm; 297 uint32_t max_v_total; 298 bool vtotal_limited_by_fp2; 299 uint32_t max_disp_clock_khz_at_vmin; 300 uint8_t subvp_drr_vblank_start_margin_us; 301 bool cursor_not_scaled; 302 bool dcmode_power_limits_present; 303 bool sequential_ono; 304 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 305 uint32_t dcc_plane_width_limit; 306 struct dc_scl_caps scl_caps; 307 }; 308 309 struct dc_bug_wa { 310 bool no_connect_phy_config; 311 bool dedcn20_305_wa; 312 bool skip_clock_update; 313 bool lt_early_cr_pattern; 314 struct { 315 uint8_t uclk : 1; 316 uint8_t fclk : 1; 317 uint8_t dcfclk : 1; 318 uint8_t dcfclk_ds: 1; 319 } clock_update_disable_mask; 320 bool skip_psr_ips_crtc_disable; 321 }; 322 struct dc_dcc_surface_param { 323 struct dc_size surface_size; 324 enum surface_pixel_format format; 325 unsigned int plane0_pitch; 326 struct dc_size plane1_size; 327 unsigned int plane1_pitch; 328 union { 329 enum swizzle_mode_values swizzle_mode; 330 enum swizzle_mode_addr3_values swizzle_mode_addr3; 331 }; 332 enum dc_scan_direction scan; 333 }; 334 335 struct dc_dcc_setting { 336 unsigned int max_compressed_blk_size; 337 unsigned int max_uncompressed_blk_size; 338 bool independent_64b_blks; 339 //These bitfields to be used starting with DCN 3.0 340 struct { 341 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 342 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 343 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 344 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 345 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 346 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 347 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 348 } dcc_controls; 349 }; 350 351 struct dc_surface_dcc_cap { 352 union { 353 struct { 354 struct dc_dcc_setting rgb; 355 } grph; 356 357 struct { 358 struct dc_dcc_setting luma; 359 struct dc_dcc_setting chroma; 360 } video; 361 }; 362 363 bool capable; 364 bool const_color_support; 365 }; 366 367 struct dc_static_screen_params { 368 struct { 369 bool force_trigger; 370 bool cursor_update; 371 bool surface_update; 372 bool overlay_update; 373 } triggers; 374 unsigned int num_frames; 375 }; 376 377 378 /* Surface update type is used by dc_update_surfaces_and_stream 379 * The update type is determined at the very beginning of the function based 380 * on parameters passed in and decides how much programming (or updating) is 381 * going to be done during the call. 382 * 383 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 384 * logical calculations or hardware register programming. This update MUST be 385 * ISR safe on windows. Currently fast update will only be used to flip surface 386 * address. 387 * 388 * UPDATE_TYPE_MED is used for slower updates which require significant hw 389 * re-programming however do not affect bandwidth consumption or clock 390 * requirements. At present, this is the level at which front end updates 391 * that do not require us to run bw_calcs happen. These are in/out transfer func 392 * updates, viewport offset changes, recout size changes and pixel depth changes. 393 * This update can be done at ISR, but we want to minimize how often this happens. 394 * 395 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 396 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 397 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 398 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 399 * a full update. This cannot be done at ISR level and should be a rare event. 400 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 401 * underscan we don't expect to see this call at all. 402 */ 403 404 enum surface_update_type { 405 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 406 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 407 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 408 }; 409 410 /* Forward declaration*/ 411 struct dc; 412 struct dc_plane_state; 413 struct dc_state; 414 415 struct dc_cap_funcs { 416 bool (*get_dcc_compression_cap)(const struct dc *dc, 417 const struct dc_dcc_surface_param *input, 418 struct dc_surface_dcc_cap *output); 419 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 420 }; 421 422 struct link_training_settings; 423 424 union allow_lttpr_non_transparent_mode { 425 struct { 426 bool DP1_4A : 1; 427 bool DP2_0 : 1; 428 } bits; 429 unsigned char raw; 430 }; 431 432 /* Structure to hold configuration flags set by dm at dc creation. */ 433 struct dc_config { 434 bool gpu_vm_support; 435 bool disable_disp_pll_sharing; 436 bool fbc_support; 437 bool disable_fractional_pwm; 438 bool allow_seamless_boot_optimization; 439 bool seamless_boot_edp_requested; 440 bool edp_not_connected; 441 bool edp_no_power_sequencing; 442 bool force_enum_edp; 443 bool forced_clocks; 444 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 445 bool multi_mon_pp_mclk_switch; 446 bool disable_dmcu; 447 bool enable_4to1MPC; 448 bool enable_windowed_mpo_odm; 449 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 450 uint32_t allow_edp_hotplug_detection; 451 bool clamp_min_dcfclk; 452 uint64_t vblank_alignment_dto_params; 453 uint8_t vblank_alignment_max_frame_time_diff; 454 bool is_asymmetric_memory; 455 bool is_single_rank_dimm; 456 bool is_vmin_only_asic; 457 bool use_spl; 458 bool prefer_easf; 459 bool use_pipe_ctx_sync_logic; 460 bool ignore_dpref_ss; 461 bool enable_mipi_converter_optimization; 462 bool use_default_clock_table; 463 bool force_bios_enable_lttpr; 464 uint8_t force_bios_fixed_vs; 465 int sdpif_request_limit_words_per_umc; 466 bool dc_mode_clk_limit_support; 467 bool EnableMinDispClkODM; 468 bool enable_auto_dpm_test_logs; 469 unsigned int disable_ips; 470 unsigned int disable_ips_in_vpb; 471 bool disable_ips_in_dpms_off; 472 bool usb4_bw_alloc_support; 473 bool allow_0_dtb_clk; 474 bool use_assr_psp_message; 475 bool support_edp0_on_dp1; 476 unsigned int enable_fpo_flicker_detection; 477 bool disable_hbr_audio_dp2; 478 bool consolidated_dpia_dp_lt; 479 bool set_pipe_unlock_order; 480 bool enable_dpia_pre_training; 481 bool unify_link_enc_assignment; 482 }; 483 484 enum visual_confirm { 485 VISUAL_CONFIRM_DISABLE = 0, 486 VISUAL_CONFIRM_SURFACE = 1, 487 VISUAL_CONFIRM_HDR = 2, 488 VISUAL_CONFIRM_MPCTREE = 4, 489 VISUAL_CONFIRM_PSR = 5, 490 VISUAL_CONFIRM_SWAPCHAIN = 6, 491 VISUAL_CONFIRM_FAMS = 7, 492 VISUAL_CONFIRM_SWIZZLE = 9, 493 VISUAL_CONFIRM_REPLAY = 12, 494 VISUAL_CONFIRM_SUBVP = 14, 495 VISUAL_CONFIRM_MCLK_SWITCH = 16, 496 VISUAL_CONFIRM_FAMS2 = 19, 497 VISUAL_CONFIRM_HW_CURSOR = 20, 498 VISUAL_CONFIRM_VABC = 21, 499 VISUAL_CONFIRM_DCC = 22, 500 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 501 }; 502 503 enum dc_psr_power_opts { 504 psr_power_opt_invalid = 0x0, 505 psr_power_opt_smu_opt_static_screen = 0x1, 506 psr_power_opt_z10_static_screen = 0x10, 507 psr_power_opt_ds_disable_allow = 0x100, 508 }; 509 510 enum dml_hostvm_override_opts { 511 DML_HOSTVM_NO_OVERRIDE = 0x0, 512 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 513 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 514 }; 515 516 enum dc_replay_power_opts { 517 replay_power_opt_invalid = 0x0, 518 replay_power_opt_smu_opt_static_screen = 0x1, 519 replay_power_opt_z10_static_screen = 0x10, 520 }; 521 522 enum dcc_option { 523 DCC_ENABLE = 0, 524 DCC_DISABLE = 1, 525 DCC_HALF_REQ_DISALBE = 2, 526 }; 527 528 enum in_game_fams_config { 529 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 530 INGAME_FAMS_DISABLE, // disable in-game fams 531 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 532 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 533 }; 534 535 /** 536 * enum pipe_split_policy - Pipe split strategy supported by DCN 537 * 538 * This enum is used to define the pipe split policy supported by DCN. By 539 * default, DC favors MPC_SPLIT_DYNAMIC. 540 */ 541 enum pipe_split_policy { 542 /** 543 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 544 * pipe in order to bring the best trade-off between performance and 545 * power consumption. This is the recommended option. 546 */ 547 MPC_SPLIT_DYNAMIC = 0, 548 549 /** 550 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 551 * try any sort of split optimization. 552 */ 553 MPC_SPLIT_AVOID = 1, 554 555 /** 556 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 557 * optimize the pipe utilization when using a single display; if the 558 * user connects to a second display, DC will avoid pipe split. 559 */ 560 MPC_SPLIT_AVOID_MULT_DISP = 2, 561 }; 562 563 enum wm_report_mode { 564 WM_REPORT_DEFAULT = 0, 565 WM_REPORT_OVERRIDE = 1, 566 }; 567 enum dtm_pstate{ 568 dtm_level_p0 = 0,/*highest voltage*/ 569 dtm_level_p1, 570 dtm_level_p2, 571 dtm_level_p3, 572 dtm_level_p4,/*when active_display_count = 0*/ 573 }; 574 575 enum dcn_pwr_state { 576 DCN_PWR_STATE_UNKNOWN = -1, 577 DCN_PWR_STATE_MISSION_MODE = 0, 578 DCN_PWR_STATE_LOW_POWER = 3, 579 }; 580 581 enum dcn_zstate_support_state { 582 DCN_ZSTATE_SUPPORT_UNKNOWN, 583 DCN_ZSTATE_SUPPORT_ALLOW, 584 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 585 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 586 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 587 DCN_ZSTATE_SUPPORT_DISALLOW, 588 }; 589 590 /* 591 * struct dc_clocks - DC pipe clocks 592 * 593 * For any clocks that may differ per pipe only the max is stored in this 594 * structure 595 */ 596 struct dc_clocks { 597 int dispclk_khz; 598 int actual_dispclk_khz; 599 int dppclk_khz; 600 int actual_dppclk_khz; 601 int disp_dpp_voltage_level_khz; 602 int dcfclk_khz; 603 int socclk_khz; 604 int dcfclk_deep_sleep_khz; 605 int fclk_khz; 606 int phyclk_khz; 607 int dramclk_khz; 608 bool p_state_change_support; 609 enum dcn_zstate_support_state zstate_support; 610 bool dtbclk_en; 611 int ref_dtbclk_khz; 612 bool fclk_p_state_change_support; 613 enum dcn_pwr_state pwr_state; 614 /* 615 * Elements below are not compared for the purposes of 616 * optimization required 617 */ 618 bool prev_p_state_change_support; 619 bool fclk_prev_p_state_change_support; 620 int num_ways; 621 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 622 623 /* 624 * @fw_based_mclk_switching 625 * 626 * DC has a mechanism that leverage the variable refresh rate to switch 627 * memory clock in cases that we have a large latency to achieve the 628 * memory clock change and a short vblank window. DC has some 629 * requirements to enable this feature, and this field describes if the 630 * system support or not such a feature. 631 */ 632 bool fw_based_mclk_switching; 633 bool fw_based_mclk_switching_shut_down; 634 int prev_num_ways; 635 enum dtm_pstate dtm_level; 636 int max_supported_dppclk_khz; 637 int max_supported_dispclk_khz; 638 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 639 int bw_dispclk_khz; 640 int idle_dramclk_khz; 641 int idle_fclk_khz; 642 int subvp_prefetch_dramclk_khz; 643 int subvp_prefetch_fclk_khz; 644 }; 645 646 struct dc_bw_validation_profile { 647 bool enable; 648 649 unsigned long long total_ticks; 650 unsigned long long voltage_level_ticks; 651 unsigned long long watermark_ticks; 652 unsigned long long rq_dlg_ticks; 653 654 unsigned long long total_count; 655 unsigned long long skip_fast_count; 656 unsigned long long skip_pass_count; 657 unsigned long long skip_fail_count; 658 }; 659 660 #define BW_VAL_TRACE_SETUP() \ 661 unsigned long long end_tick = 0; \ 662 unsigned long long voltage_level_tick = 0; \ 663 unsigned long long watermark_tick = 0; \ 664 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 665 dm_get_timestamp(dc->ctx) : 0 666 667 #define BW_VAL_TRACE_COUNT() \ 668 if (dc->debug.bw_val_profile.enable) \ 669 dc->debug.bw_val_profile.total_count++ 670 671 #define BW_VAL_TRACE_SKIP(status) \ 672 if (dc->debug.bw_val_profile.enable) { \ 673 if (!voltage_level_tick) \ 674 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 675 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 676 } 677 678 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 679 if (dc->debug.bw_val_profile.enable) \ 680 voltage_level_tick = dm_get_timestamp(dc->ctx) 681 682 #define BW_VAL_TRACE_END_WATERMARKS() \ 683 if (dc->debug.bw_val_profile.enable) \ 684 watermark_tick = dm_get_timestamp(dc->ctx) 685 686 #define BW_VAL_TRACE_FINISH() \ 687 if (dc->debug.bw_val_profile.enable) { \ 688 end_tick = dm_get_timestamp(dc->ctx); \ 689 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 690 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 691 if (watermark_tick) { \ 692 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 693 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 694 } \ 695 } 696 697 union mem_low_power_enable_options { 698 struct { 699 bool vga: 1; 700 bool i2c: 1; 701 bool dmcu: 1; 702 bool dscl: 1; 703 bool cm: 1; 704 bool mpc: 1; 705 bool optc: 1; 706 bool vpg: 1; 707 bool afmt: 1; 708 } bits; 709 uint32_t u32All; 710 }; 711 712 union root_clock_optimization_options { 713 struct { 714 bool dpp: 1; 715 bool dsc: 1; 716 bool hdmistream: 1; 717 bool hdmichar: 1; 718 bool dpstream: 1; 719 bool symclk32_se: 1; 720 bool symclk32_le: 1; 721 bool symclk_fe: 1; 722 bool physymclk: 1; 723 bool dpiasymclk: 1; 724 uint32_t reserved: 22; 725 } bits; 726 uint32_t u32All; 727 }; 728 729 union fine_grain_clock_gating_enable_options { 730 struct { 731 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 732 bool dchub : 1; /* Display controller hub */ 733 bool dchubbub : 1; 734 bool dpp : 1; /* Display pipes and planes */ 735 bool opp : 1; /* Output pixel processing */ 736 bool optc : 1; /* Output pipe timing combiner */ 737 bool dio : 1; /* Display output */ 738 bool dwb : 1; /* Display writeback */ 739 bool mmhubbub : 1; /* Multimedia hub */ 740 bool dmu : 1; /* Display core management unit */ 741 bool az : 1; /* Azalia */ 742 bool dchvm : 1; 743 bool dsc : 1; /* Display stream compression */ 744 745 uint32_t reserved : 19; 746 } bits; 747 uint32_t u32All; 748 }; 749 750 enum pg_hw_pipe_resources { 751 PG_HUBP = 0, 752 PG_DPP, 753 PG_DSC, 754 PG_MPCC, 755 PG_OPP, 756 PG_OPTC, 757 PG_DPSTREAM, 758 PG_HDMISTREAM, 759 PG_PHYSYMCLK, 760 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 761 }; 762 763 enum pg_hw_resources { 764 PG_DCCG = 0, 765 PG_DCIO, 766 PG_DIO, 767 PG_DCHUBBUB, 768 PG_DCHVM, 769 PG_DWB, 770 PG_HPO, 771 PG_HW_RESOURCES_NUM_ELEMENT 772 }; 773 774 struct pg_block_update { 775 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 776 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 777 }; 778 779 union dpia_debug_options { 780 struct { 781 uint32_t disable_dpia:1; /* bit 0 */ 782 uint32_t force_non_lttpr:1; /* bit 1 */ 783 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 784 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 785 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 786 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 787 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 788 uint32_t enable_dpia_pre_training:1; /* bit 7 */ 789 uint32_t unify_link_enc_assignment:1; /* bit 8 */ 790 uint32_t reserved:24; 791 } bits; 792 uint32_t raw; 793 }; 794 795 /* AUX wake work around options 796 * 0: enable/disable work around 797 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 798 * 15-2: reserved 799 * 31-16: timeout in ms 800 */ 801 union aux_wake_wa_options { 802 struct { 803 uint32_t enable_wa : 1; 804 uint32_t use_default_timeout : 1; 805 uint32_t rsvd: 14; 806 uint32_t timeout_ms : 16; 807 } bits; 808 uint32_t raw; 809 }; 810 811 struct dc_debug_data { 812 uint32_t ltFailCount; 813 uint32_t i2cErrorCount; 814 uint32_t auxErrorCount; 815 }; 816 817 struct dc_phy_addr_space_config { 818 struct { 819 uint64_t start_addr; 820 uint64_t end_addr; 821 uint64_t fb_top; 822 uint64_t fb_offset; 823 uint64_t fb_base; 824 uint64_t agp_top; 825 uint64_t agp_bot; 826 uint64_t agp_base; 827 } system_aperture; 828 829 struct { 830 uint64_t page_table_start_addr; 831 uint64_t page_table_end_addr; 832 uint64_t page_table_base_addr; 833 bool base_addr_is_mc_addr; 834 } gart_config; 835 836 bool valid; 837 bool is_hvm_enabled; 838 uint64_t page_table_default_page_addr; 839 }; 840 841 struct dc_virtual_addr_space_config { 842 uint64_t page_table_base_addr; 843 uint64_t page_table_start_addr; 844 uint64_t page_table_end_addr; 845 uint32_t page_table_block_size_in_bytes; 846 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 847 }; 848 849 struct dc_bounding_box_overrides { 850 int sr_exit_time_ns; 851 int sr_enter_plus_exit_time_ns; 852 int sr_exit_z8_time_ns; 853 int sr_enter_plus_exit_z8_time_ns; 854 int urgent_latency_ns; 855 int percent_of_ideal_drambw; 856 int dram_clock_change_latency_ns; 857 int dummy_clock_change_latency_ns; 858 int fclk_clock_change_latency_ns; 859 /* This forces a hard min on the DCFCLK we use 860 * for DML. Unlike the debug option for forcing 861 * DCFCLK, this override affects watermark calculations 862 */ 863 int min_dcfclk_mhz; 864 }; 865 866 struct dc_state; 867 struct resource_pool; 868 struct dce_hwseq; 869 struct link_service; 870 871 /* 872 * struct dc_debug_options - DC debug struct 873 * 874 * This struct provides a simple mechanism for developers to change some 875 * configurations, enable/disable features, and activate extra debug options. 876 * This can be very handy to narrow down whether some specific feature is 877 * causing an issue or not. 878 */ 879 struct dc_debug_options { 880 bool native422_support; 881 bool disable_dsc; 882 enum visual_confirm visual_confirm; 883 int visual_confirm_rect_height; 884 885 bool sanity_checks; 886 bool max_disp_clk; 887 bool surface_trace; 888 bool clock_trace; 889 bool validation_trace; 890 bool bandwidth_calcs_trace; 891 int max_downscale_src_width; 892 893 /* stutter efficiency related */ 894 bool disable_stutter; 895 bool use_max_lb; 896 enum dcc_option disable_dcc; 897 898 /* 899 * @pipe_split_policy: Define which pipe split policy is used by the 900 * display core. 901 */ 902 enum pipe_split_policy pipe_split_policy; 903 bool force_single_disp_pipe_split; 904 bool voltage_align_fclk; 905 bool disable_min_fclk; 906 907 bool hdcp_lc_force_fw_enable; 908 bool hdcp_lc_enable_sw_fallback; 909 910 bool disable_dfs_bypass; 911 bool disable_dpp_power_gate; 912 bool disable_hubp_power_gate; 913 bool disable_dsc_power_gate; 914 bool disable_optc_power_gate; 915 bool disable_hpo_power_gate; 916 int dsc_min_slice_height_override; 917 int dsc_bpp_increment_div; 918 bool disable_pplib_wm_range; 919 enum wm_report_mode pplib_wm_report_mode; 920 unsigned int min_disp_clk_khz; 921 unsigned int min_dpp_clk_khz; 922 unsigned int min_dram_clk_khz; 923 int sr_exit_time_dpm0_ns; 924 int sr_enter_plus_exit_time_dpm0_ns; 925 int sr_exit_time_ns; 926 int sr_enter_plus_exit_time_ns; 927 int sr_exit_z8_time_ns; 928 int sr_enter_plus_exit_z8_time_ns; 929 int urgent_latency_ns; 930 uint32_t underflow_assert_delay_us; 931 int percent_of_ideal_drambw; 932 int dram_clock_change_latency_ns; 933 bool optimized_watermark; 934 int always_scale; 935 bool disable_pplib_clock_request; 936 bool disable_clock_gate; 937 bool disable_mem_low_power; 938 bool pstate_enabled; 939 bool disable_dmcu; 940 bool force_abm_enable; 941 bool disable_stereo_support; 942 bool vsr_support; 943 bool performance_trace; 944 bool az_endpoint_mute_only; 945 bool always_use_regamma; 946 bool recovery_enabled; 947 bool avoid_vbios_exec_table; 948 bool scl_reset_length10; 949 bool hdmi20_disable; 950 bool skip_detection_link_training; 951 uint32_t edid_read_retry_times; 952 unsigned int force_odm_combine; //bit vector based on otg inst 953 unsigned int seamless_boot_odm_combine; 954 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 955 int minimum_z8_residency_time; 956 int minimum_z10_residency_time; 957 bool disable_z9_mpc; 958 unsigned int force_fclk_khz; 959 bool enable_tri_buf; 960 bool ips_disallow_entry; 961 bool dmub_offload_enabled; 962 bool dmcub_emulation; 963 bool disable_idle_power_optimizations; 964 unsigned int mall_size_override; 965 unsigned int mall_additional_timer_percent; 966 bool mall_error_as_fatal; 967 bool dmub_command_table; /* for testing only */ 968 struct dc_bw_validation_profile bw_val_profile; 969 bool disable_fec; 970 bool disable_48mhz_pwrdwn; 971 /* This forces a hard min on the DCFCLK requested to SMU/PP 972 * watermarks are not affected. 973 */ 974 unsigned int force_min_dcfclk_mhz; 975 int dwb_fi_phase; 976 bool disable_timing_sync; 977 bool cm_in_bypass; 978 int force_clock_mode;/*every mode change.*/ 979 980 bool disable_dram_clock_change_vactive_support; 981 bool validate_dml_output; 982 bool enable_dmcub_surface_flip; 983 bool usbc_combo_phy_reset_wa; 984 bool enable_dram_clock_change_one_display_vactive; 985 /* TODO - remove once tested */ 986 bool legacy_dp2_lt; 987 bool set_mst_en_for_sst; 988 bool disable_uhbr; 989 bool force_dp2_lt_fallback_method; 990 bool ignore_cable_id; 991 union mem_low_power_enable_options enable_mem_low_power; 992 union root_clock_optimization_options root_clock_optimization; 993 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 994 bool hpo_optimization; 995 bool force_vblank_alignment; 996 997 /* Enable dmub aux for legacy ddc */ 998 bool enable_dmub_aux_for_legacy_ddc; 999 bool disable_fams; 1000 enum in_game_fams_config disable_fams_gaming; 1001 /* FEC/PSR1 sequence enable delay in 100us */ 1002 uint8_t fec_enable_delay_in100us; 1003 bool enable_driver_sequence_debug; 1004 enum det_size crb_alloc_policy; 1005 int crb_alloc_policy_min_disp_count; 1006 bool disable_z10; 1007 bool enable_z9_disable_interface; 1008 bool psr_skip_crtc_disable; 1009 uint32_t ips_skip_crtc_disable_mask; 1010 union dpia_debug_options dpia_debug; 1011 bool disable_fixed_vs_aux_timeout_wa; 1012 uint32_t fixed_vs_aux_delay_config_wa; 1013 bool force_disable_subvp; 1014 bool force_subvp_mclk_switch; 1015 bool allow_sw_cursor_fallback; 1016 unsigned int force_subvp_num_ways; 1017 unsigned int force_mall_ss_num_ways; 1018 bool alloc_extra_way_for_cursor; 1019 uint32_t subvp_extra_lines; 1020 bool force_usr_allow; 1021 /* uses value at boot and disables switch */ 1022 bool disable_dtb_ref_clk_switch; 1023 bool extended_blank_optimization; 1024 union aux_wake_wa_options aux_wake_wa; 1025 uint32_t mst_start_top_delay; 1026 uint8_t psr_power_use_phy_fsm; 1027 enum dml_hostvm_override_opts dml_hostvm_override; 1028 bool dml_disallow_alternate_prefetch_modes; 1029 bool use_legacy_soc_bb_mechanism; 1030 bool exit_idle_opt_for_cursor_updates; 1031 bool using_dml2; 1032 bool enable_single_display_2to1_odm_policy; 1033 bool enable_double_buffered_dsc_pg_support; 1034 bool enable_dp_dig_pixel_rate_div_policy; 1035 bool using_dml21; 1036 enum lttpr_mode lttpr_mode_override; 1037 unsigned int dsc_delay_factor_wa_x1000; 1038 unsigned int min_prefetch_in_strobe_ns; 1039 bool disable_unbounded_requesting; 1040 bool dig_fifo_off_in_blank; 1041 bool override_dispclk_programming; 1042 bool otg_crc_db; 1043 bool disallow_dispclk_dppclk_ds; 1044 bool disable_fpo_optimizations; 1045 bool support_eDP1_5; 1046 uint32_t fpo_vactive_margin_us; 1047 bool disable_fpo_vactive; 1048 bool disable_boot_optimizations; 1049 bool override_odm_optimization; 1050 bool minimize_dispclk_using_odm; 1051 bool disable_subvp_high_refresh; 1052 bool disable_dp_plus_plus_wa; 1053 uint32_t fpo_vactive_min_active_margin_us; 1054 uint32_t fpo_vactive_max_blank_us; 1055 bool enable_hpo_pg_support; 1056 bool enable_legacy_fast_update; 1057 bool disable_dc_mode_overwrite; 1058 bool replay_skip_crtc_disabled; 1059 bool ignore_pg;/*do nothing, let pmfw control it*/ 1060 bool psp_disabled_wa; 1061 unsigned int ips2_eval_delay_us; 1062 unsigned int ips2_entry_delay_us; 1063 bool optimize_ips_handshake; 1064 bool disable_dmub_reallow_idle; 1065 bool disable_timeout; 1066 bool disable_extblankadj; 1067 bool enable_idle_reg_checks; 1068 unsigned int static_screen_wait_frames; 1069 uint32_t pwm_freq; 1070 bool force_chroma_subsampling_1tap; 1071 unsigned int dcc_meta_propagation_delay_us; 1072 bool disable_422_left_edge_pixel; 1073 bool dml21_force_pstate_method; 1074 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1075 uint32_t dml21_disable_pstate_method_mask; 1076 union fw_assisted_mclk_switch_version fams_version; 1077 union dmub_fams2_global_feature_config fams2_config; 1078 unsigned int force_cositing; 1079 unsigned int disable_spl; 1080 unsigned int force_easf; 1081 unsigned int force_sharpness; 1082 unsigned int force_sharpness_level; 1083 unsigned int force_lls; 1084 bool notify_dpia_hr_bw; 1085 bool enable_ips_visual_confirm; 1086 unsigned int sharpen_policy; 1087 unsigned int scale_to_sharpness_policy; 1088 bool skip_full_updated_if_possible; 1089 unsigned int enable_oled_edp_power_up_opt; 1090 bool enable_hblank_borrow; 1091 bool force_subvp_df_throttle; 1092 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1093 }; 1094 1095 1096 /* Generic structure that can be used to query properties of DC. More fields 1097 * can be added as required. 1098 */ 1099 struct dc_current_properties { 1100 unsigned int cursor_size_limit; 1101 }; 1102 1103 enum frame_buffer_mode { 1104 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1105 FRAME_BUFFER_MODE_ZFB_ONLY, 1106 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1107 } ; 1108 1109 struct dchub_init_data { 1110 int64_t zfb_phys_addr_base; 1111 int64_t zfb_mc_base_addr; 1112 uint64_t zfb_size_in_byte; 1113 enum frame_buffer_mode fb_mode; 1114 bool dchub_initialzied; 1115 bool dchub_info_valid; 1116 }; 1117 1118 struct dml2_soc_bb; 1119 1120 struct dc_init_data { 1121 struct hw_asic_id asic_id; 1122 void *driver; /* ctx */ 1123 struct cgs_device *cgs_device; 1124 struct dc_bounding_box_overrides bb_overrides; 1125 1126 int num_virtual_links; 1127 /* 1128 * If 'vbios_override' not NULL, it will be called instead 1129 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1130 */ 1131 struct dc_bios *vbios_override; 1132 enum dce_environment dce_environment; 1133 1134 struct dmub_offload_funcs *dmub_if; 1135 struct dc_reg_helper_state *dmub_offload; 1136 1137 struct dc_config flags; 1138 uint64_t log_mask; 1139 1140 struct dpcd_vendor_signature vendor_signature; 1141 bool force_smu_not_present; 1142 /* 1143 * IP offset for run time initializaion of register addresses 1144 * 1145 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1146 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1147 * before them. 1148 */ 1149 uint32_t *dcn_reg_offsets; 1150 uint32_t *nbio_reg_offsets; 1151 uint32_t *clk_reg_offsets; 1152 struct dml2_soc_bb *bb_from_dmub; 1153 }; 1154 1155 struct dc_callback_init { 1156 struct cp_psp cp_psp; 1157 }; 1158 1159 struct dc *dc_create(const struct dc_init_data *init_params); 1160 void dc_hardware_init(struct dc *dc); 1161 1162 int dc_get_vmid_use_vector(struct dc *dc); 1163 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1164 /* Returns the number of vmids supported */ 1165 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1166 void dc_init_callbacks(struct dc *dc, 1167 const struct dc_callback_init *init_params); 1168 void dc_deinit_callbacks(struct dc *dc); 1169 void dc_destroy(struct dc **dc); 1170 1171 /* Surface Interfaces */ 1172 1173 enum { 1174 TRANSFER_FUNC_POINTS = 1025 1175 }; 1176 1177 struct dc_hdr_static_metadata { 1178 /* display chromaticities and white point in units of 0.00001 */ 1179 unsigned int chromaticity_green_x; 1180 unsigned int chromaticity_green_y; 1181 unsigned int chromaticity_blue_x; 1182 unsigned int chromaticity_blue_y; 1183 unsigned int chromaticity_red_x; 1184 unsigned int chromaticity_red_y; 1185 unsigned int chromaticity_white_point_x; 1186 unsigned int chromaticity_white_point_y; 1187 1188 uint32_t min_luminance; 1189 uint32_t max_luminance; 1190 uint32_t maximum_content_light_level; 1191 uint32_t maximum_frame_average_light_level; 1192 }; 1193 1194 enum dc_transfer_func_type { 1195 TF_TYPE_PREDEFINED, 1196 TF_TYPE_DISTRIBUTED_POINTS, 1197 TF_TYPE_BYPASS, 1198 TF_TYPE_HWPWL 1199 }; 1200 1201 struct dc_transfer_func_distributed_points { 1202 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1203 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1204 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1205 1206 uint16_t end_exponent; 1207 uint16_t x_point_at_y1_red; 1208 uint16_t x_point_at_y1_green; 1209 uint16_t x_point_at_y1_blue; 1210 }; 1211 1212 enum dc_transfer_func_predefined { 1213 TRANSFER_FUNCTION_SRGB, 1214 TRANSFER_FUNCTION_BT709, 1215 TRANSFER_FUNCTION_PQ, 1216 TRANSFER_FUNCTION_LINEAR, 1217 TRANSFER_FUNCTION_UNITY, 1218 TRANSFER_FUNCTION_HLG, 1219 TRANSFER_FUNCTION_HLG12, 1220 TRANSFER_FUNCTION_GAMMA22, 1221 TRANSFER_FUNCTION_GAMMA24, 1222 TRANSFER_FUNCTION_GAMMA26 1223 }; 1224 1225 1226 struct dc_transfer_func { 1227 struct kref refcount; 1228 enum dc_transfer_func_type type; 1229 enum dc_transfer_func_predefined tf; 1230 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1231 uint32_t sdr_ref_white_level; 1232 union { 1233 struct pwl_params pwl; 1234 struct dc_transfer_func_distributed_points tf_pts; 1235 }; 1236 }; 1237 1238 1239 union dc_3dlut_state { 1240 struct { 1241 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1242 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1243 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1244 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1245 uint32_t mpc_rmu1_mux:4; 1246 uint32_t mpc_rmu2_mux:4; 1247 uint32_t reserved:15; 1248 } bits; 1249 uint32_t raw; 1250 }; 1251 1252 1253 struct dc_3dlut { 1254 struct kref refcount; 1255 struct tetrahedral_params lut_3d; 1256 struct fixed31_32 hdr_multiplier; 1257 union dc_3dlut_state state; 1258 }; 1259 /* 1260 * This structure is filled in by dc_surface_get_status and contains 1261 * the last requested address and the currently active address so the called 1262 * can determine if there are any outstanding flips 1263 */ 1264 struct dc_plane_status { 1265 struct dc_plane_address requested_address; 1266 struct dc_plane_address current_address; 1267 bool is_flip_pending; 1268 bool is_right_eye; 1269 }; 1270 1271 union surface_update_flags { 1272 1273 struct { 1274 uint32_t addr_update:1; 1275 /* Medium updates */ 1276 uint32_t dcc_change:1; 1277 uint32_t color_space_change:1; 1278 uint32_t horizontal_mirror_change:1; 1279 uint32_t per_pixel_alpha_change:1; 1280 uint32_t global_alpha_change:1; 1281 uint32_t hdr_mult:1; 1282 uint32_t rotation_change:1; 1283 uint32_t swizzle_change:1; 1284 uint32_t scaling_change:1; 1285 uint32_t position_change:1; 1286 uint32_t in_transfer_func_change:1; 1287 uint32_t input_csc_change:1; 1288 uint32_t coeff_reduction_change:1; 1289 uint32_t output_tf_change:1; 1290 uint32_t pixel_format_change:1; 1291 uint32_t plane_size_change:1; 1292 uint32_t gamut_remap_change:1; 1293 1294 /* Full updates */ 1295 uint32_t new_plane:1; 1296 uint32_t bpp_change:1; 1297 uint32_t gamma_change:1; 1298 uint32_t bandwidth_change:1; 1299 uint32_t clock_change:1; 1300 uint32_t stereo_format_change:1; 1301 uint32_t lut_3d:1; 1302 uint32_t tmz_changed:1; 1303 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1304 uint32_t full_update:1; 1305 uint32_t sdr_white_level_nits:1; 1306 } bits; 1307 1308 uint32_t raw; 1309 }; 1310 1311 #define DC_REMOVE_PLANE_POINTERS 1 1312 1313 struct dc_plane_state { 1314 struct dc_plane_address address; 1315 struct dc_plane_flip_time time; 1316 bool triplebuffer_flips; 1317 struct scaling_taps scaling_quality; 1318 struct rect src_rect; 1319 struct rect dst_rect; 1320 struct rect clip_rect; 1321 1322 struct plane_size plane_size; 1323 struct dc_tiling_info tiling_info; 1324 1325 struct dc_plane_dcc_param dcc; 1326 1327 struct dc_gamma gamma_correction; 1328 struct dc_transfer_func in_transfer_func; 1329 struct dc_bias_and_scale bias_and_scale; 1330 struct dc_csc_transform input_csc_color_matrix; 1331 struct fixed31_32 coeff_reduction_factor; 1332 struct fixed31_32 hdr_mult; 1333 struct colorspace_transform gamut_remap_matrix; 1334 1335 // TODO: No longer used, remove 1336 struct dc_hdr_static_metadata hdr_static_ctx; 1337 1338 enum dc_color_space color_space; 1339 1340 struct dc_3dlut lut3d_func; 1341 struct dc_transfer_func in_shaper_func; 1342 struct dc_transfer_func blend_tf; 1343 1344 struct dc_transfer_func *gamcor_tf; 1345 enum surface_pixel_format format; 1346 enum dc_rotation_angle rotation; 1347 enum plane_stereo_format stereo_format; 1348 1349 bool is_tiling_rotated; 1350 bool per_pixel_alpha; 1351 bool pre_multiplied_alpha; 1352 bool global_alpha; 1353 int global_alpha_value; 1354 bool visible; 1355 bool flip_immediate; 1356 bool horizontal_mirror; 1357 int layer_index; 1358 1359 union surface_update_flags update_flags; 1360 bool flip_int_enabled; 1361 bool skip_manual_trigger; 1362 1363 /* private to DC core */ 1364 struct dc_plane_status status; 1365 struct dc_context *ctx; 1366 1367 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1368 bool force_full_update; 1369 1370 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1371 1372 /* private to dc_surface.c */ 1373 enum dc_irq_source irq_source; 1374 struct kref refcount; 1375 struct tg_color visual_confirm_color; 1376 1377 bool is_statically_allocated; 1378 enum chroma_cositing cositing; 1379 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1380 bool mcm_lut1d_enable; 1381 struct dc_cm2_func_luts mcm_luts; 1382 bool lut_bank_a; 1383 enum mpcc_movable_cm_location mcm_location; 1384 struct dc_csc_transform cursor_csc_color_matrix; 1385 bool adaptive_sharpness_en; 1386 int adaptive_sharpness_policy; 1387 int sharpness_level; 1388 enum linear_light_scaling linear_light_scaling; 1389 unsigned int sdr_white_level_nits; 1390 }; 1391 1392 struct dc_plane_info { 1393 struct plane_size plane_size; 1394 struct dc_tiling_info tiling_info; 1395 struct dc_plane_dcc_param dcc; 1396 enum surface_pixel_format format; 1397 enum dc_rotation_angle rotation; 1398 enum plane_stereo_format stereo_format; 1399 enum dc_color_space color_space; 1400 bool horizontal_mirror; 1401 bool visible; 1402 bool per_pixel_alpha; 1403 bool pre_multiplied_alpha; 1404 bool global_alpha; 1405 int global_alpha_value; 1406 bool input_csc_enabled; 1407 int layer_index; 1408 enum chroma_cositing cositing; 1409 }; 1410 1411 #include "dc_stream.h" 1412 1413 struct dc_scratch_space { 1414 /* used to temporarily backup plane states of a stream during 1415 * dc update. The reason is that plane states are overwritten 1416 * with surface updates in dc update. Once they are overwritten 1417 * current state is no longer valid. We want to temporarily 1418 * store current value in plane states so we can still recover 1419 * a valid current state during dc update. 1420 */ 1421 struct dc_plane_state plane_states[MAX_SURFACES]; 1422 1423 struct dc_stream_state stream_state; 1424 }; 1425 1426 /* 1427 * A link contains one or more sinks and their connected status. 1428 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1429 */ 1430 struct dc_link { 1431 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1432 unsigned int sink_count; 1433 struct dc_sink *local_sink; 1434 unsigned int link_index; 1435 enum dc_connection_type type; 1436 enum signal_type connector_signal; 1437 enum dc_irq_source irq_source_hpd; 1438 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1439 1440 bool is_hpd_filter_disabled; 1441 bool dp_ss_off; 1442 1443 /** 1444 * @link_state_valid: 1445 * 1446 * If there is no link and local sink, this variable should be set to 1447 * false. Otherwise, it should be set to true; usually, the function 1448 * core_link_enable_stream sets this field to true. 1449 */ 1450 bool link_state_valid; 1451 bool aux_access_disabled; 1452 bool sync_lt_in_progress; 1453 bool skip_stream_reenable; 1454 bool is_internal_display; 1455 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1456 bool is_dig_mapping_flexible; 1457 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1458 bool is_hpd_pending; /* Indicates a new received hpd */ 1459 1460 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1461 * for every link training. This is incompatible with DP LL compliance automation, 1462 * which expects the same link settings to be used every retry on a link loss. 1463 * This flag is used to skip the fallback when link loss occurs during automation. 1464 */ 1465 bool skip_fallback_on_link_loss; 1466 1467 bool edp_sink_present; 1468 1469 struct dp_trace dp_trace; 1470 1471 /* caps is the same as reported_link_cap. link_traing use 1472 * reported_link_cap. Will clean up. TODO 1473 */ 1474 struct dc_link_settings reported_link_cap; 1475 struct dc_link_settings verified_link_cap; 1476 struct dc_link_settings cur_link_settings; 1477 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1478 struct dc_link_settings preferred_link_setting; 1479 /* preferred_training_settings are override values that 1480 * come from DM. DM is responsible for the memory 1481 * management of the override pointers. 1482 */ 1483 struct dc_link_training_overrides preferred_training_settings; 1484 struct dp_audio_test_data audio_test_data; 1485 1486 uint8_t ddc_hw_inst; 1487 1488 uint8_t hpd_src; 1489 1490 uint8_t link_enc_hw_inst; 1491 /* DIG link encoder ID. Used as index in link encoder resource pool. 1492 * For links with fixed mapping to DIG, this is not changed after dc_link 1493 * object creation. 1494 */ 1495 enum engine_id eng_id; 1496 enum engine_id dpia_preferred_eng_id; 1497 1498 bool test_pattern_enabled; 1499 /* Pending/Current test pattern are only used to perform and track 1500 * FIXED_VS retimer test pattern/lane adjustment override state. 1501 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1502 * to perform specific lane adjust overrides before setting certain 1503 * PHY test patterns. In cases when lane adjust and set test pattern 1504 * calls are not performed atomically (i.e. performing link training), 1505 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1506 * and current_test_pattern will contain required context for any future 1507 * set pattern/set lane adjust to transition between override state(s). 1508 * */ 1509 enum dp_test_pattern current_test_pattern; 1510 enum dp_test_pattern pending_test_pattern; 1511 1512 union compliance_test_state compliance_test_state; 1513 1514 void *priv; 1515 1516 struct ddc_service *ddc; 1517 1518 enum dp_panel_mode panel_mode; 1519 bool aux_mode; 1520 1521 /* Private to DC core */ 1522 1523 const struct dc *dc; 1524 1525 struct dc_context *ctx; 1526 1527 struct panel_cntl *panel_cntl; 1528 struct link_encoder *link_enc; 1529 struct graphics_object_id link_id; 1530 /* Endpoint type distinguishes display endpoints which do not have entries 1531 * in the BIOS connector table from those that do. Helps when tracking link 1532 * encoder to display endpoint assignments. 1533 */ 1534 enum display_endpoint_type ep_type; 1535 union ddi_channel_mapping ddi_channel_mapping; 1536 struct connector_device_tag_info device_tag; 1537 struct dpcd_caps dpcd_caps; 1538 uint32_t dongle_max_pix_clk; 1539 unsigned short chip_caps; 1540 unsigned int dpcd_sink_count; 1541 struct hdcp_caps hdcp_caps; 1542 enum edp_revision edp_revision; 1543 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1544 1545 struct psr_settings psr_settings; 1546 struct replay_settings replay_settings; 1547 1548 /* Drive settings read from integrated info table */ 1549 struct dc_lane_settings bios_forced_drive_settings; 1550 1551 /* Vendor specific LTTPR workaround variables */ 1552 uint8_t vendor_specific_lttpr_link_rate_wa; 1553 bool apply_vendor_specific_lttpr_link_rate_wa; 1554 1555 /* MST record stream using this link */ 1556 struct link_flags { 1557 bool dp_keep_receiver_powered; 1558 bool dp_skip_DID2; 1559 bool dp_skip_reset_segment; 1560 bool dp_skip_fs_144hz; 1561 bool dp_mot_reset_segment; 1562 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1563 bool dpia_mst_dsc_always_on; 1564 /* Forced DPIA into TBT3 compatibility mode. */ 1565 bool dpia_forced_tbt3_mode; 1566 bool dongle_mode_timing_override; 1567 bool blank_stream_on_ocs_change; 1568 bool read_dpcd204h_on_irq_hpd; 1569 bool force_dp_ffe_preset; 1570 } wa_flags; 1571 union dc_dp_ffe_preset forced_dp_ffe_preset; 1572 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1573 1574 struct dc_link_status link_status; 1575 struct dprx_states dprx_states; 1576 1577 struct gpio *hpd_gpio; 1578 enum dc_link_fec_state fec_state; 1579 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1580 1581 struct dc_panel_config panel_config; 1582 struct phy_state phy_state; 1583 uint32_t phy_transition_bitmask; 1584 // BW ALLOCATON USB4 ONLY 1585 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1586 bool skip_implict_edp_power_control; 1587 enum backlight_control_type backlight_control_type; 1588 }; 1589 1590 struct dc { 1591 struct dc_debug_options debug; 1592 struct dc_versions versions; 1593 struct dc_caps caps; 1594 struct dc_cap_funcs cap_funcs; 1595 struct dc_config config; 1596 struct dc_bounding_box_overrides bb_overrides; 1597 struct dc_bug_wa work_arounds; 1598 struct dc_context *ctx; 1599 struct dc_phy_addr_space_config vm_pa_config; 1600 1601 uint8_t link_count; 1602 struct dc_link *links[MAX_LINKS]; 1603 struct link_service *link_srv; 1604 1605 struct dc_state *current_state; 1606 struct resource_pool *res_pool; 1607 1608 struct clk_mgr *clk_mgr; 1609 1610 /* Display Engine Clock levels */ 1611 struct dm_pp_clock_levels sclk_lvls; 1612 1613 /* Inputs into BW and WM calculations. */ 1614 struct bw_calcs_dceip *bw_dceip; 1615 struct bw_calcs_vbios *bw_vbios; 1616 struct dcn_soc_bounding_box *dcn_soc; 1617 struct dcn_ip_params *dcn_ip; 1618 struct display_mode_lib dml; 1619 1620 /* HW functions */ 1621 struct hw_sequencer_funcs hwss; 1622 struct dce_hwseq *hwseq; 1623 1624 /* Require to optimize clocks and bandwidth for added/removed planes */ 1625 bool optimized_required; 1626 bool wm_optimized_required; 1627 bool idle_optimizations_allowed; 1628 bool enable_c20_dtm_b0; 1629 1630 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1631 1632 /* FBC compressor */ 1633 struct compressor *fbc_compressor; 1634 1635 struct dc_debug_data debug_data; 1636 struct dpcd_vendor_signature vendor_signature; 1637 1638 const char *build_id; 1639 struct vm_helper *vm_helper; 1640 1641 uint32_t *dcn_reg_offsets; 1642 uint32_t *nbio_reg_offsets; 1643 uint32_t *clk_reg_offsets; 1644 1645 /* Scratch memory */ 1646 struct { 1647 struct { 1648 /* 1649 * For matching clock_limits table in driver with table 1650 * from PMFW. 1651 */ 1652 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1653 } update_bw_bounding_box; 1654 struct dc_scratch_space current_state; 1655 struct dc_scratch_space new_state; 1656 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1657 struct dc_link temp_link; 1658 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1659 } scratch; 1660 1661 struct dml2_configuration_options dml2_options; 1662 struct dml2_configuration_options dml2_tmp; 1663 enum dc_acpi_cm_power_state power_state; 1664 1665 }; 1666 1667 struct dc_scaling_info { 1668 struct rect src_rect; 1669 struct rect dst_rect; 1670 struct rect clip_rect; 1671 struct scaling_taps scaling_quality; 1672 }; 1673 1674 struct dc_fast_update { 1675 const struct dc_flip_addrs *flip_addr; 1676 const struct dc_gamma *gamma; 1677 const struct colorspace_transform *gamut_remap_matrix; 1678 const struct dc_csc_transform *input_csc_color_matrix; 1679 const struct fixed31_32 *coeff_reduction_factor; 1680 struct dc_transfer_func *out_transfer_func; 1681 struct dc_csc_transform *output_csc_transform; 1682 const struct dc_csc_transform *cursor_csc_color_matrix; 1683 }; 1684 1685 struct dc_surface_update { 1686 struct dc_plane_state *surface; 1687 1688 /* isr safe update parameters. null means no updates */ 1689 const struct dc_flip_addrs *flip_addr; 1690 const struct dc_plane_info *plane_info; 1691 const struct dc_scaling_info *scaling_info; 1692 struct fixed31_32 hdr_mult; 1693 /* following updates require alloc/sleep/spin that is not isr safe, 1694 * null means no updates 1695 */ 1696 const struct dc_gamma *gamma; 1697 const struct dc_transfer_func *in_transfer_func; 1698 1699 const struct dc_csc_transform *input_csc_color_matrix; 1700 const struct fixed31_32 *coeff_reduction_factor; 1701 const struct dc_transfer_func *func_shaper; 1702 const struct dc_3dlut *lut3d_func; 1703 const struct dc_transfer_func *blend_tf; 1704 const struct colorspace_transform *gamut_remap_matrix; 1705 /* 1706 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1707 * 1708 * change cm2_params.component_settings: Full update 1709 * change cm2_params.cm2_luts: Fast update 1710 */ 1711 const struct dc_cm2_parameters *cm2_params; 1712 const struct dc_csc_transform *cursor_csc_color_matrix; 1713 unsigned int sdr_white_level_nits; 1714 struct dc_bias_and_scale bias_and_scale; 1715 }; 1716 1717 /* 1718 * Create a new surface with default parameters; 1719 */ 1720 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1721 void dc_gamma_release(struct dc_gamma **dc_gamma); 1722 struct dc_gamma *dc_create_gamma(void); 1723 1724 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1725 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1726 struct dc_transfer_func *dc_create_transfer_func(void); 1727 1728 struct dc_3dlut *dc_create_3dlut_func(void); 1729 void dc_3dlut_func_release(struct dc_3dlut *lut); 1730 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1731 1732 void dc_post_update_surfaces_to_stream( 1733 struct dc *dc); 1734 1735 #include "dc_stream.h" 1736 1737 /** 1738 * struct dc_validation_set - Struct to store surface/stream associations for validation 1739 */ 1740 struct dc_validation_set { 1741 /** 1742 * @stream: Stream state properties 1743 */ 1744 struct dc_stream_state *stream; 1745 1746 /** 1747 * @plane_states: Surface state 1748 */ 1749 struct dc_plane_state *plane_states[MAX_SURFACES]; 1750 1751 /** 1752 * @plane_count: Total of active planes 1753 */ 1754 uint8_t plane_count; 1755 }; 1756 1757 bool dc_validate_boot_timing(const struct dc *dc, 1758 const struct dc_sink *sink, 1759 struct dc_crtc_timing *crtc_timing); 1760 1761 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1762 1763 enum dc_status dc_validate_with_context(struct dc *dc, 1764 const struct dc_validation_set set[], 1765 int set_count, 1766 struct dc_state *context, 1767 bool fast_validate); 1768 1769 bool dc_set_generic_gpio_for_stereo(bool enable, 1770 struct gpio_service *gpio_service); 1771 1772 /* 1773 * fast_validate: we return after determining if we can support the new state, 1774 * but before we populate the programming info 1775 */ 1776 enum dc_status dc_validate_global_state( 1777 struct dc *dc, 1778 struct dc_state *new_ctx, 1779 bool fast_validate); 1780 1781 bool dc_acquire_release_mpc_3dlut( 1782 struct dc *dc, bool acquire, 1783 struct dc_stream_state *stream, 1784 struct dc_3dlut **lut, 1785 struct dc_transfer_func **shaper); 1786 1787 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1788 void get_audio_check(struct audio_info *aud_modes, 1789 struct audio_check *aud_chk); 1790 1791 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1792 void populate_fast_updates(struct dc_fast_update *fast_update, 1793 struct dc_surface_update *srf_updates, 1794 int surface_count, 1795 struct dc_stream_update *stream_update); 1796 /* 1797 * Set up streams and links associated to drive sinks 1798 * The streams parameter is an absolute set of all active streams. 1799 * 1800 * After this call: 1801 * Phy, Encoder, Timing Generator are programmed and enabled. 1802 * New streams are enabled with blank stream; no memory read. 1803 */ 1804 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1805 1806 1807 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1808 struct dc_stream_state *stream, 1809 int mpcc_inst); 1810 1811 1812 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1813 1814 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1815 1816 /* The function returns minimum bandwidth required to drive a given timing 1817 * return - minimum required timing bandwidth in kbps. 1818 */ 1819 uint32_t dc_bandwidth_in_kbps_from_timing( 1820 const struct dc_crtc_timing *timing, 1821 const enum dc_link_encoding_format link_encoding); 1822 1823 /* Link Interfaces */ 1824 /* Return an enumerated dc_link. 1825 * dc_link order is constant and determined at 1826 * boot time. They cannot be created or destroyed. 1827 * Use dc_get_caps() to get number of links. 1828 */ 1829 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1830 1831 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1832 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1833 const struct dc_link *link, 1834 unsigned int *inst_out); 1835 1836 /* Return an array of link pointers to edp links. */ 1837 void dc_get_edp_links(const struct dc *dc, 1838 struct dc_link **edp_links, 1839 int *edp_num); 1840 1841 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1842 bool powerOn); 1843 1844 /* The function initiates detection handshake over the given link. It first 1845 * determines if there are display connections over the link. If so it initiates 1846 * detection protocols supported by the connected receiver device. The function 1847 * contains protocol specific handshake sequences which are sometimes mandatory 1848 * to establish a proper connection between TX and RX. So it is always 1849 * recommended to call this function as the first link operation upon HPD event 1850 * or power up event. Upon completion, the function will update link structure 1851 * in place based on latest RX capabilities. The function may also cause dpms 1852 * to be reset to off for all currently enabled streams to the link. It is DM's 1853 * responsibility to serialize detection and DPMS updates. 1854 * 1855 * @reason - Indicate which event triggers this detection. dc may customize 1856 * detection flow depending on the triggering events. 1857 * return false - if detection is not fully completed. This could happen when 1858 * there is an unrecoverable error during detection or detection is partially 1859 * completed (detection has been delegated to dm mst manager ie. 1860 * link->connection_type == dc_connection_mst_branch when returning false). 1861 * return true - detection is completed, link has been fully updated with latest 1862 * detection result. 1863 */ 1864 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1865 1866 struct dc_sink_init_data; 1867 1868 /* When link connection type is dc_connection_mst_branch, remote sink can be 1869 * added to the link. The interface creates a remote sink and associates it with 1870 * current link. The sink will be retained by link until remove remote sink is 1871 * called. 1872 * 1873 * @dc_link - link the remote sink will be added to. 1874 * @edid - byte array of EDID raw data. 1875 * @len - size of the edid in byte 1876 * @init_data - 1877 */ 1878 struct dc_sink *dc_link_add_remote_sink( 1879 struct dc_link *dc_link, 1880 const uint8_t *edid, 1881 int len, 1882 struct dc_sink_init_data *init_data); 1883 1884 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1885 * @link - link the sink should be removed from 1886 * @sink - sink to be removed. 1887 */ 1888 void dc_link_remove_remote_sink( 1889 struct dc_link *link, 1890 struct dc_sink *sink); 1891 1892 /* Enable HPD interrupt handler for a given link */ 1893 void dc_link_enable_hpd(const struct dc_link *link); 1894 1895 /* Disable HPD interrupt handler for a given link */ 1896 void dc_link_disable_hpd(const struct dc_link *link); 1897 1898 /* determine if there is a sink connected to the link 1899 * 1900 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1901 * return - false if an unexpected error occurs, true otherwise. 1902 * 1903 * NOTE: This function doesn't detect downstream sink connections i.e 1904 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1905 * return dc_connection_single if the branch device is connected despite of 1906 * downstream sink's connection status. 1907 */ 1908 bool dc_link_detect_connection_type(struct dc_link *link, 1909 enum dc_connection_type *type); 1910 1911 /* query current hpd pin value 1912 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1913 * 1914 */ 1915 bool dc_link_get_hpd_state(struct dc_link *link); 1916 1917 /* Getter for cached link status from given link */ 1918 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1919 1920 /* enable/disable hardware HPD filter. 1921 * 1922 * @link - The link the HPD pin is associated with. 1923 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1924 * handler once after no HPD change has been detected within dc default HPD 1925 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1926 * pulses within default HPD interval, no HPD event will be received until HPD 1927 * toggles have stopped. Then HPD event will be queued to irq handler once after 1928 * dc default HPD filtering interval since last HPD event. 1929 * 1930 * @enable = false - disable hardware HPD filter. HPD event will be queued 1931 * immediately to irq handler after no HPD change has been detected within 1932 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1933 */ 1934 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1935 1936 /* submit i2c read/write payloads through ddc channel 1937 * @link_index - index to a link with ddc in i2c mode 1938 * @cmd - i2c command structure 1939 * return - true if success, false otherwise. 1940 */ 1941 bool dc_submit_i2c( 1942 struct dc *dc, 1943 uint32_t link_index, 1944 struct i2c_command *cmd); 1945 1946 /* submit i2c read/write payloads through oem channel 1947 * @link_index - index to a link with ddc in i2c mode 1948 * @cmd - i2c command structure 1949 * return - true if success, false otherwise. 1950 */ 1951 bool dc_submit_i2c_oem( 1952 struct dc *dc, 1953 struct i2c_command *cmd); 1954 1955 enum aux_return_code_type; 1956 /* Attempt to transfer the given aux payload. This function does not perform 1957 * retries or handle error states. The reply is returned in the payload->reply 1958 * and the result through operation_result. Returns the number of bytes 1959 * transferred,or -1 on a failure. 1960 */ 1961 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1962 struct aux_payload *payload, 1963 enum aux_return_code_type *operation_result); 1964 1965 struct ddc_service * 1966 dc_get_oem_i2c_device(struct dc *dc); 1967 1968 bool dc_is_oem_i2c_device_present( 1969 struct dc *dc, 1970 size_t slave_address 1971 ); 1972 1973 /* return true if the connected receiver supports the hdcp version */ 1974 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1975 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1976 1977 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1978 * 1979 * TODO - When defer_handling is true the function will have a different purpose. 1980 * It no longer does complete hpd rx irq handling. We should create a separate 1981 * interface specifically for this case. 1982 * 1983 * Return: 1984 * true - Downstream port status changed. DM should call DC to do the 1985 * detection. 1986 * false - no change in Downstream port status. No further action required 1987 * from DM. 1988 */ 1989 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1990 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1991 bool defer_handling, bool *has_left_work); 1992 /* handle DP specs define test automation sequence*/ 1993 void dc_link_dp_handle_automated_test(struct dc_link *link); 1994 1995 /* handle DP Link loss sequence and try to recover RX link loss with best 1996 * effort 1997 */ 1998 void dc_link_dp_handle_link_loss(struct dc_link *link); 1999 2000 /* Determine if hpd rx irq should be handled or ignored 2001 * return true - hpd rx irq should be handled. 2002 * return false - it is safe to ignore hpd rx irq event 2003 */ 2004 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2005 2006 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2007 * @link - link the hpd irq data associated with 2008 * @hpd_irq_dpcd_data - input hpd irq data 2009 * return - true if hpd irq data indicates a link lost 2010 */ 2011 bool dc_link_check_link_loss_status(struct dc_link *link, 2012 union hpd_irq_data *hpd_irq_dpcd_data); 2013 2014 /* Read hpd rx irq data from a given link 2015 * @link - link where the hpd irq data should be read from 2016 * @irq_data - output hpd irq data 2017 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2018 * read has failed. 2019 */ 2020 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2021 struct dc_link *link, 2022 union hpd_irq_data *irq_data); 2023 2024 /* The function clears recorded DP RX states in the link. DM should call this 2025 * function when it is resuming from S3 power state to previously connected links. 2026 * 2027 * TODO - in the future we should consider to expand link resume interface to 2028 * support clearing previous rx states. So we don't have to rely on dm to call 2029 * this interface explicitly. 2030 */ 2031 void dc_link_clear_dprx_states(struct dc_link *link); 2032 2033 /* Destruct the mst topology of the link and reset the allocated payload table 2034 * 2035 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2036 * still wants to reset MST topology on an unplug event */ 2037 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2038 2039 /* The function calculates effective DP link bandwidth when a given link is 2040 * using the given link settings. 2041 * 2042 * return - total effective link bandwidth in kbps. 2043 */ 2044 uint32_t dc_link_bandwidth_kbps( 2045 const struct dc_link *link, 2046 const struct dc_link_settings *link_setting); 2047 2048 struct dp_audio_bandwidth_params { 2049 const struct dc_crtc_timing *crtc_timing; 2050 enum dp_link_encoding link_encoding; 2051 uint32_t channel_count; 2052 uint32_t sample_rate_hz; 2053 }; 2054 2055 /* The function calculates the minimum size of hblank (in bytes) needed to 2056 * support the specified channel count and sample rate combination, given the 2057 * link encoding and timing to be used. This calculation is not supported 2058 * for 8b/10b SST. 2059 * 2060 * return - min hblank size in bytes, 0 if 8b/10b SST. 2061 */ 2062 uint32_t dc_link_required_hblank_size_bytes( 2063 const struct dc_link *link, 2064 struct dp_audio_bandwidth_params *audio_params); 2065 2066 /* The function takes a snapshot of current link resource allocation state 2067 * @dc: pointer to dc of the dm calling this 2068 * @map: a dc link resource snapshot defined internally to dc. 2069 * 2070 * DM needs to capture a snapshot of current link resource allocation mapping 2071 * and store it in its persistent storage. 2072 * 2073 * Some of the link resource is using first come first serve policy. 2074 * The allocation mapping depends on original hotplug order. This information 2075 * is lost after driver is loaded next time. The snapshot is used in order to 2076 * restore link resource to its previous state so user will get consistent 2077 * link capability allocation across reboot. 2078 * 2079 */ 2080 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2081 2082 /* This function restores link resource allocation state from a snapshot 2083 * @dc: pointer to dc of the dm calling this 2084 * @map: a dc link resource snapshot defined internally to dc. 2085 * 2086 * DM needs to call this function after initial link detection on boot and 2087 * before first commit streams to restore link resource allocation state 2088 * from previous boot session. 2089 * 2090 * Some of the link resource is using first come first serve policy. 2091 * The allocation mapping depends on original hotplug order. This information 2092 * is lost after driver is loaded next time. The snapshot is used in order to 2093 * restore link resource to its previous state so user will get consistent 2094 * link capability allocation across reboot. 2095 * 2096 */ 2097 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2098 2099 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2100 * interface i.e stream_update->dsc_config 2101 */ 2102 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2103 2104 /* translate a raw link rate data to bandwidth in kbps */ 2105 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2106 2107 /* determine the optimal bandwidth given link and required bw. 2108 * @link - current detected link 2109 * @req_bw - requested bandwidth in kbps 2110 * @link_settings - returned most optimal link settings that can fit the 2111 * requested bandwidth 2112 * return - false if link can't support requested bandwidth, true if link 2113 * settings is found. 2114 */ 2115 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2116 struct dc_link_settings *link_settings, 2117 uint32_t req_bw); 2118 2119 /* return the max dp link settings can be driven by the link without considering 2120 * connected RX device and its capability 2121 */ 2122 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2123 struct dc_link_settings *max_link_enc_cap); 2124 2125 /* determine when the link is driving MST mode, what DP link channel coding 2126 * format will be used. The decision will remain unchanged until next HPD event. 2127 * 2128 * @link - a link with DP RX connection 2129 * return - if stream is committed to this link with MST signal type, type of 2130 * channel coding format dc will choose. 2131 */ 2132 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2133 const struct dc_link *link); 2134 2135 /* get max dp link settings the link can enable with all things considered. (i.e 2136 * TX/RX/Cable capabilities and dp override policies. 2137 * 2138 * @link - a link with DP RX connection 2139 * return - max dp link settings the link can enable. 2140 * 2141 */ 2142 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2143 2144 /* Get the highest encoding format that the link supports; highest meaning the 2145 * encoding format which supports the maximum bandwidth. 2146 * 2147 * @link - a link with DP RX connection 2148 * return - highest encoding format link supports. 2149 */ 2150 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2151 2152 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2153 * to a link with dp connector signal type. 2154 * @link - a link with dp connector signal type 2155 * return - true if connected, false otherwise 2156 */ 2157 bool dc_link_is_dp_sink_present(struct dc_link *link); 2158 2159 /* Force DP lane settings update to main-link video signal and notify the change 2160 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2161 * tuning purpose. The interface assumes link has already been enabled with DP 2162 * signal. 2163 * 2164 * @lt_settings - a container structure with desired hw_lane_settings 2165 */ 2166 void dc_link_set_drive_settings(struct dc *dc, 2167 struct link_training_settings *lt_settings, 2168 struct dc_link *link); 2169 2170 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2171 * test or debugging purpose. The test pattern will remain until next un-plug. 2172 * 2173 * @link - active link with DP signal output enabled. 2174 * @test_pattern - desired test pattern to output. 2175 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2176 * @test_pattern_color_space - for video test pattern choose a desired color 2177 * space. 2178 * @p_link_settings - For PHY pattern choose a desired link settings 2179 * @p_custom_pattern - some test pattern will require a custom input to 2180 * customize some pattern details. Otherwise keep it to NULL. 2181 * @cust_pattern_size - size of the custom pattern input. 2182 * 2183 */ 2184 bool dc_link_dp_set_test_pattern( 2185 struct dc_link *link, 2186 enum dp_test_pattern test_pattern, 2187 enum dp_test_pattern_color_space test_pattern_color_space, 2188 const struct link_training_settings *p_link_settings, 2189 const unsigned char *p_custom_pattern, 2190 unsigned int cust_pattern_size); 2191 2192 /* Force DP link settings to always use a specific value until reboot to a 2193 * specific link. If link has already been enabled, the interface will also 2194 * switch to desired link settings immediately. This is a debug interface to 2195 * generic dp issue trouble shooting. 2196 */ 2197 void dc_link_set_preferred_link_settings(struct dc *dc, 2198 struct dc_link_settings *link_setting, 2199 struct dc_link *link); 2200 2201 /* Force DP link to customize a specific link training behavior by overriding to 2202 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2203 * display specific link training issues or apply some display specific 2204 * workaround in link training. 2205 * 2206 * @link_settings - if not NULL, force preferred link settings to the link. 2207 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2208 * will apply this particular override in future link training. If NULL is 2209 * passed in, dc resets previous overrides. 2210 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2211 * training settings. 2212 */ 2213 void dc_link_set_preferred_training_settings(struct dc *dc, 2214 struct dc_link_settings *link_setting, 2215 struct dc_link_training_overrides *lt_overrides, 2216 struct dc_link *link, 2217 bool skip_immediate_retrain); 2218 2219 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2220 bool dc_link_is_fec_supported(const struct dc_link *link); 2221 2222 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2223 * link enablement. 2224 * return - true if FEC should be enabled, false otherwise. 2225 */ 2226 bool dc_link_should_enable_fec(const struct dc_link *link); 2227 2228 /* determine lttpr mode the current link should be enabled with a specific link 2229 * settings. 2230 */ 2231 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2232 struct dc_link_settings *link_setting); 2233 2234 /* Force DP RX to update its power state. 2235 * NOTE: this interface doesn't update dp main-link. Calling this function will 2236 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2237 * RX power state back upon finish DM specific execution requiring DP RX in a 2238 * specific power state. 2239 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2240 * state. 2241 */ 2242 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2243 2244 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2245 * current value read from extended receiver cap from 02200h - 0220Fh. 2246 * Some DP RX has problems of providing accurate DP receiver caps from extended 2247 * field, this interface is a workaround to revert link back to use base caps. 2248 */ 2249 void dc_link_overwrite_extended_receiver_cap( 2250 struct dc_link *link); 2251 2252 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2253 bool wait_for_hpd); 2254 2255 /* Set backlight level of an embedded panel (eDP, LVDS). 2256 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2257 * and 16 bit fractional, where 1.0 is max backlight value. 2258 */ 2259 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2260 struct set_backlight_level_params *backlight_level_params); 2261 2262 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2263 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2264 bool isHDR, 2265 uint32_t backlight_millinits, 2266 uint32_t transition_time_in_ms); 2267 2268 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2269 uint32_t *backlight_millinits, 2270 uint32_t *backlight_millinits_peak); 2271 2272 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2273 2274 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2275 2276 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2277 bool wait, bool force_static, const unsigned int *power_opts); 2278 2279 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2280 2281 bool dc_link_setup_psr(struct dc_link *dc_link, 2282 const struct dc_stream_state *stream, struct psr_config *psr_config, 2283 struct psr_context *psr_context); 2284 2285 /* 2286 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2287 * 2288 * @link: pointer to the dc_link struct instance 2289 * @enable: enable(active) or disable(inactive) replay 2290 * @wait: state transition need to wait the active set completed. 2291 * @force_static: force disable(inactive) the replay 2292 * @power_opts: set power optimazation parameters to DMUB. 2293 * 2294 * return: allow Replay active will return true, else will return false. 2295 */ 2296 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2297 bool wait, bool force_static, const unsigned int *power_opts); 2298 2299 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2300 2301 /* On eDP links this function call will stall until T12 has elapsed. 2302 * If the panel is not in power off state, this function will return 2303 * immediately. 2304 */ 2305 bool dc_link_wait_for_t12(struct dc_link *link); 2306 2307 /* Determine if dp trace has been initialized to reflect upto date result * 2308 * return - true if trace is initialized and has valid data. False dp trace 2309 * doesn't have valid result. 2310 */ 2311 bool dc_dp_trace_is_initialized(struct dc_link *link); 2312 2313 /* Query a dp trace flag to indicate if the current dp trace data has been 2314 * logged before 2315 */ 2316 bool dc_dp_trace_is_logged(struct dc_link *link, 2317 bool in_detection); 2318 2319 /* Set dp trace flag to indicate whether DM has already logged the current dp 2320 * trace data. DM can set is_logged to true upon logging and check 2321 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2322 */ 2323 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2324 bool in_detection, 2325 bool is_logged); 2326 2327 /* Obtain driver time stamp for last dp link training end. The time stamp is 2328 * formatted based on dm_get_timestamp DM function. 2329 * @in_detection - true to get link training end time stamp of last link 2330 * training in detection sequence. false to get link training end time stamp 2331 * of last link training in commit (dpms) sequence 2332 */ 2333 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2334 bool in_detection); 2335 2336 /* Get how many link training attempts dc has done with latest sequence. 2337 * @in_detection - true to get link training count of last link 2338 * training in detection sequence. false to get link training count of last link 2339 * training in commit (dpms) sequence 2340 */ 2341 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2342 bool in_detection); 2343 2344 /* Get how many link loss has happened since last link training attempts */ 2345 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2346 2347 /* 2348 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2349 */ 2350 /* 2351 * Send a request from DP-Tx requesting to allocate BW remotely after 2352 * allocating it locally. This will get processed by CM and a CB function 2353 * will be called. 2354 * 2355 * @link: pointer to the dc_link struct instance 2356 * @req_bw: The requested bw in Kbyte to allocated 2357 * 2358 * return: none 2359 */ 2360 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2361 2362 /* 2363 * Handle the USB4 BW Allocation related functionality here: 2364 * Plug => Try to allocate max bw from timing parameters supported by the sink 2365 * Unplug => de-allocate bw 2366 * 2367 * @link: pointer to the dc_link struct instance 2368 * @peak_bw: Peak bw used by the link/sink 2369 * 2370 */ 2371 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2372 struct dc_link *link, int peak_bw); 2373 2374 /* 2375 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2376 * available BW for each host router 2377 * 2378 * @dc: pointer to dc struct 2379 * @stream: pointer to all possible streams 2380 * @count: number of valid DPIA streams 2381 * 2382 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2383 */ 2384 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2385 const unsigned int count); 2386 2387 /* Sink Interfaces - A sink corresponds to a display output device */ 2388 2389 struct dc_container_id { 2390 // 128bit GUID in binary form 2391 unsigned char guid[16]; 2392 // 8 byte port ID -> ELD.PortID 2393 unsigned int portId[2]; 2394 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2395 unsigned short manufacturerName; 2396 // 2 byte product code -> ELD.ProductCode 2397 unsigned short productCode; 2398 }; 2399 2400 2401 struct dc_sink_dsc_caps { 2402 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2403 // 'false' if they are sink's DSC caps 2404 bool is_virtual_dpcd_dsc; 2405 // 'true' if MST topology supports DSC passthrough for sink 2406 // 'false' if MST topology does not support DSC passthrough 2407 bool is_dsc_passthrough_supported; 2408 struct dsc_dec_dpcd_caps dsc_dec_caps; 2409 }; 2410 2411 struct dc_sink_hblank_expansion_caps { 2412 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2413 // 'false' if they are sink's HBlank expansion caps 2414 bool is_virtual_dpcd_hblank_expansion; 2415 struct hblank_expansion_dpcd_caps dpcd_caps; 2416 }; 2417 2418 struct dc_sink_fec_caps { 2419 bool is_rx_fec_supported; 2420 bool is_topology_fec_supported; 2421 }; 2422 2423 struct scdc_caps { 2424 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2425 union hdmi_scdc_device_id_data device_id; 2426 }; 2427 2428 /* 2429 * The sink structure contains EDID and other display device properties 2430 */ 2431 struct dc_sink { 2432 enum signal_type sink_signal; 2433 struct dc_edid dc_edid; /* raw edid */ 2434 struct dc_edid_caps edid_caps; /* parse display caps */ 2435 struct dc_container_id *dc_container_id; 2436 uint32_t dongle_max_pix_clk; 2437 void *priv; 2438 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2439 bool converter_disable_audio; 2440 2441 struct scdc_caps scdc_caps; 2442 struct dc_sink_dsc_caps dsc_caps; 2443 struct dc_sink_fec_caps fec_caps; 2444 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2445 2446 bool is_vsc_sdp_colorimetry_supported; 2447 2448 /* private to DC core */ 2449 struct dc_link *link; 2450 struct dc_context *ctx; 2451 2452 uint32_t sink_id; 2453 2454 /* private to dc_sink.c */ 2455 // refcount must be the last member in dc_sink, since we want the 2456 // sink structure to be logically cloneable up to (but not including) 2457 // refcount 2458 struct kref refcount; 2459 }; 2460 2461 void dc_sink_retain(struct dc_sink *sink); 2462 void dc_sink_release(struct dc_sink *sink); 2463 2464 struct dc_sink_init_data { 2465 enum signal_type sink_signal; 2466 struct dc_link *link; 2467 uint32_t dongle_max_pix_clk; 2468 bool converter_disable_audio; 2469 }; 2470 2471 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2472 2473 /* Newer interfaces */ 2474 struct dc_cursor { 2475 struct dc_plane_address address; 2476 struct dc_cursor_attributes attributes; 2477 }; 2478 2479 2480 /* Interrupt interfaces */ 2481 enum dc_irq_source dc_interrupt_to_irq_source( 2482 struct dc *dc, 2483 uint32_t src_id, 2484 uint32_t ext_id); 2485 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2486 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2487 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2488 struct dc *dc, uint32_t link_index); 2489 2490 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2491 2492 /* Power Interfaces */ 2493 2494 void dc_set_power_state( 2495 struct dc *dc, 2496 enum dc_acpi_cm_power_state power_state); 2497 void dc_resume(struct dc *dc); 2498 2499 void dc_power_down_on_boot(struct dc *dc); 2500 2501 /* 2502 * HDCP Interfaces 2503 */ 2504 enum hdcp_message_status dc_process_hdcp_msg( 2505 enum signal_type signal, 2506 struct dc_link *link, 2507 struct hdcp_protection_message *message_info); 2508 bool dc_is_dmcu_initialized(struct dc *dc); 2509 2510 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2511 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2512 2513 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2514 unsigned int pitch, 2515 unsigned int height, 2516 enum surface_pixel_format format, 2517 struct dc_cursor_attributes *cursor_attr); 2518 2519 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2520 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2521 2522 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2523 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2524 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2525 2526 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2527 void dc_unlock_memory_clock_frequency(struct dc *dc); 2528 2529 /* set min memory clock to the min required for current mode, max to maxDPM */ 2530 void dc_lock_memory_clock_frequency(struct dc *dc); 2531 2532 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2533 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2534 2535 /* cleanup on driver unload */ 2536 void dc_hardware_release(struct dc *dc); 2537 2538 /* disables fw based mclk switch */ 2539 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2540 2541 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2542 2543 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2544 2545 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2546 2547 void dc_z10_restore(const struct dc *dc); 2548 void dc_z10_save_init(struct dc *dc); 2549 2550 bool dc_is_dmub_outbox_supported(struct dc *dc); 2551 bool dc_enable_dmub_notifications(struct dc *dc); 2552 2553 bool dc_abm_save_restore( 2554 struct dc *dc, 2555 struct dc_stream_state *stream, 2556 struct abm_save_restore *pData); 2557 2558 void dc_enable_dmub_outbox(struct dc *dc); 2559 2560 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2561 uint32_t link_index, 2562 struct aux_payload *payload); 2563 2564 /* Get dc link index from dpia port index */ 2565 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2566 uint8_t dpia_port_index); 2567 2568 bool dc_process_dmub_set_config_async(struct dc *dc, 2569 uint32_t link_index, 2570 struct set_config_cmd_payload *payload, 2571 struct dmub_notification *notify); 2572 2573 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2574 uint32_t link_index, 2575 uint8_t mst_alloc_slots, 2576 uint8_t *mst_slots_in_use); 2577 2578 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2579 2580 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2581 uint32_t hpd_int_enable); 2582 2583 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2584 2585 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2586 2587 struct dc_power_profile { 2588 int power_level; /* Lower is better */ 2589 }; 2590 2591 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2592 2593 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2594 2595 /* DSC Interfaces */ 2596 #include "dc_dsc.h" 2597 2598 void dc_get_visual_confirm_for_stream( 2599 struct dc *dc, 2600 struct dc_stream_state *stream_state, 2601 struct tg_color *color); 2602 2603 /* Disable acc mode Interfaces */ 2604 void dc_disable_accelerated_mode(struct dc *dc); 2605 2606 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2607 struct dc_stream_state *new_stream); 2608 2609 #endif /* DC_INTERFACE_H_ */ 2610