1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.27" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dc_caps { 52 uint32_t max_streams; 53 uint32_t max_links; 54 uint32_t max_audios; 55 uint32_t max_slave_planes; 56 uint32_t max_planes; 57 uint32_t max_downscale_ratio; 58 uint32_t i2c_speed_in_khz; 59 unsigned int max_cursor_size; 60 unsigned int max_video_width; 61 int linear_pitch_alignment; 62 bool dcc_const_color; 63 bool dynamic_audio; 64 bool is_apu; 65 bool dual_link_dvi; 66 }; 67 68 struct dc_dcc_surface_param { 69 struct dc_size surface_size; 70 enum surface_pixel_format format; 71 enum swizzle_mode_values swizzle_mode; 72 enum dc_scan_direction scan; 73 }; 74 75 struct dc_dcc_setting { 76 unsigned int max_compressed_blk_size; 77 unsigned int max_uncompressed_blk_size; 78 bool independent_64b_blks; 79 }; 80 81 struct dc_surface_dcc_cap { 82 union { 83 struct { 84 struct dc_dcc_setting rgb; 85 } grph; 86 87 struct { 88 struct dc_dcc_setting luma; 89 struct dc_dcc_setting chroma; 90 } video; 91 }; 92 93 bool capable; 94 bool const_color_support; 95 }; 96 97 struct dc_static_screen_events { 98 bool cursor_update; 99 bool surface_update; 100 bool overlay_update; 101 }; 102 103 104 /* Surface update type is used by dc_update_surfaces_and_stream 105 * The update type is determined at the very beginning of the function based 106 * on parameters passed in and decides how much programming (or updating) is 107 * going to be done during the call. 108 * 109 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 110 * logical calculations or hardware register programming. This update MUST be 111 * ISR safe on windows. Currently fast update will only be used to flip surface 112 * address. 113 * 114 * UPDATE_TYPE_MED is used for slower updates which require significant hw 115 * re-programming however do not affect bandwidth consumption or clock 116 * requirements. At present, this is the level at which front end updates 117 * that do not require us to run bw_calcs happen. These are in/out transfer func 118 * updates, viewport offset changes, recout size changes and pixel depth changes. 119 * This update can be done at ISR, but we want to minimize how often this happens. 120 * 121 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 122 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 123 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 124 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 125 * a full update. This cannot be done at ISR level and should be a rare event. 126 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 127 * underscan we don't expect to see this call at all. 128 */ 129 130 enum surface_update_type { 131 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 132 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 133 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 134 }; 135 136 /* Forward declaration*/ 137 struct dc; 138 struct dc_plane_state; 139 struct dc_state; 140 141 142 struct dc_cap_funcs { 143 bool (*get_dcc_compression_cap)(const struct dc *dc, 144 const struct dc_dcc_surface_param *input, 145 struct dc_surface_dcc_cap *output); 146 }; 147 148 struct link_training_settings; 149 150 151 /* Structure to hold configuration flags set by dm at dc creation. */ 152 struct dc_config { 153 bool gpu_vm_support; 154 bool disable_disp_pll_sharing; 155 }; 156 157 enum dcc_option { 158 DCC_ENABLE = 0, 159 DCC_DISABLE = 1, 160 DCC_HALF_REQ_DISALBE = 2, 161 }; 162 163 enum pipe_split_policy { 164 MPC_SPLIT_DYNAMIC = 0, 165 MPC_SPLIT_AVOID = 1, 166 MPC_SPLIT_AVOID_MULT_DISP = 2, 167 }; 168 169 enum wm_report_mode { 170 WM_REPORT_DEFAULT = 0, 171 WM_REPORT_OVERRIDE = 1, 172 }; 173 174 struct dc_debug { 175 bool surface_visual_confirm; 176 bool sanity_checks; 177 bool max_disp_clk; 178 bool surface_trace; 179 bool timing_trace; 180 bool clock_trace; 181 bool validation_trace; 182 183 /* stutter efficiency related */ 184 bool disable_stutter; 185 bool use_max_lb; 186 enum dcc_option disable_dcc; 187 enum pipe_split_policy pipe_split_policy; 188 bool force_single_disp_pipe_split; 189 bool voltage_align_fclk; 190 191 bool disable_dfs_bypass; 192 bool disable_dpp_power_gate; 193 bool disable_hubp_power_gate; 194 bool disable_pplib_wm_range; 195 enum wm_report_mode pplib_wm_report_mode; 196 unsigned int min_disp_clk_khz; 197 int sr_exit_time_dpm0_ns; 198 int sr_enter_plus_exit_time_dpm0_ns; 199 int sr_exit_time_ns; 200 int sr_enter_plus_exit_time_ns; 201 int urgent_latency_ns; 202 int percent_of_ideal_drambw; 203 int dram_clock_change_latency_ns; 204 int always_scale; 205 bool disable_pplib_clock_request; 206 bool disable_clock_gate; 207 bool disable_dmcu; 208 bool disable_psr; 209 bool force_abm_enable; 210 bool disable_hbup_pg; 211 bool disable_dpp_pg; 212 bool disable_stereo_support; 213 bool vsr_support; 214 bool performance_trace; 215 }; 216 struct dc_state; 217 struct resource_pool; 218 struct dce_hwseq; 219 struct dc { 220 struct dc_caps caps; 221 struct dc_cap_funcs cap_funcs; 222 struct dc_config config; 223 struct dc_debug debug; 224 225 struct dc_context *ctx; 226 227 uint8_t link_count; 228 struct dc_link *links[MAX_PIPES * 2]; 229 230 struct dc_state *current_state; 231 struct resource_pool *res_pool; 232 233 /* Display Engine Clock levels */ 234 struct dm_pp_clock_levels sclk_lvls; 235 236 /* Inputs into BW and WM calculations. */ 237 struct bw_calcs_dceip *bw_dceip; 238 struct bw_calcs_vbios *bw_vbios; 239 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 240 struct dcn_soc_bounding_box *dcn_soc; 241 struct dcn_ip_params *dcn_ip; 242 struct display_mode_lib dml; 243 #endif 244 245 /* HW functions */ 246 struct hw_sequencer_funcs hwss; 247 struct dce_hwseq *hwseq; 248 249 /* temp store of dm_pp_display_configuration 250 * to compare to see if display config changed 251 */ 252 struct dm_pp_display_configuration prev_display_config; 253 254 bool optimized_required; 255 256 /* FBC compressor */ 257 #if defined(CONFIG_DRM_AMD_DC_FBC) 258 struct compressor *fbc_compressor; 259 #endif 260 }; 261 262 enum frame_buffer_mode { 263 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 264 FRAME_BUFFER_MODE_ZFB_ONLY, 265 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 266 } ; 267 268 struct dchub_init_data { 269 int64_t zfb_phys_addr_base; 270 int64_t zfb_mc_base_addr; 271 uint64_t zfb_size_in_byte; 272 enum frame_buffer_mode fb_mode; 273 bool dchub_initialzied; 274 bool dchub_info_valid; 275 }; 276 277 struct dc_init_data { 278 struct hw_asic_id asic_id; 279 void *driver; /* ctx */ 280 struct cgs_device *cgs_device; 281 282 int num_virtual_links; 283 /* 284 * If 'vbios_override' not NULL, it will be called instead 285 * of the real VBIOS. Intended use is Diagnostics on FPGA. 286 */ 287 struct dc_bios *vbios_override; 288 enum dce_environment dce_environment; 289 290 struct dc_config flags; 291 uint32_t log_mask; 292 #if defined(CONFIG_DRM_AMD_DC_FBC) 293 uint64_t fbc_gpu_addr; 294 #endif 295 }; 296 297 struct dc *dc_create(const struct dc_init_data *init_params); 298 299 void dc_destroy(struct dc **dc); 300 301 /******************************************************************************* 302 * Surface Interfaces 303 ******************************************************************************/ 304 305 enum { 306 TRANSFER_FUNC_POINTS = 1025 307 }; 308 309 // Moved here from color module for linux 310 enum color_transfer_func { 311 transfer_func_unknown, 312 transfer_func_srgb, 313 transfer_func_bt709, 314 transfer_func_pq2084, 315 transfer_func_pq2084_interim, 316 transfer_func_linear_0_1, 317 transfer_func_linear_0_125, 318 transfer_func_dolbyvision, 319 transfer_func_gamma_22, 320 transfer_func_gamma_26 321 }; 322 323 struct dc_hdr_static_metadata { 324 /* display chromaticities and white point in units of 0.00001 */ 325 unsigned int chromaticity_green_x; 326 unsigned int chromaticity_green_y; 327 unsigned int chromaticity_blue_x; 328 unsigned int chromaticity_blue_y; 329 unsigned int chromaticity_red_x; 330 unsigned int chromaticity_red_y; 331 unsigned int chromaticity_white_point_x; 332 unsigned int chromaticity_white_point_y; 333 334 uint32_t min_luminance; 335 uint32_t max_luminance; 336 uint32_t maximum_content_light_level; 337 uint32_t maximum_frame_average_light_level; 338 339 bool hdr_supported; 340 bool is_hdr; 341 }; 342 343 enum dc_transfer_func_type { 344 TF_TYPE_PREDEFINED, 345 TF_TYPE_DISTRIBUTED_POINTS, 346 TF_TYPE_BYPASS, 347 }; 348 349 struct dc_transfer_func_distributed_points { 350 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 351 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 352 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 353 354 uint16_t end_exponent; 355 uint16_t x_point_at_y1_red; 356 uint16_t x_point_at_y1_green; 357 uint16_t x_point_at_y1_blue; 358 }; 359 360 enum dc_transfer_func_predefined { 361 TRANSFER_FUNCTION_SRGB, 362 TRANSFER_FUNCTION_BT709, 363 TRANSFER_FUNCTION_PQ, 364 TRANSFER_FUNCTION_LINEAR, 365 TRANSFER_FUNCTION_UNITY, 366 }; 367 368 struct dc_transfer_func { 369 struct kref refcount; 370 struct dc_transfer_func_distributed_points tf_pts; 371 enum dc_transfer_func_type type; 372 enum dc_transfer_func_predefined tf; 373 struct dc_context *ctx; 374 }; 375 376 /* 377 * This structure is filled in by dc_surface_get_status and contains 378 * the last requested address and the currently active address so the called 379 * can determine if there are any outstanding flips 380 */ 381 struct dc_plane_status { 382 struct dc_plane_address requested_address; 383 struct dc_plane_address current_address; 384 bool is_flip_pending; 385 bool is_right_eye; 386 }; 387 388 union surface_update_flags { 389 390 struct { 391 /* Medium updates */ 392 uint32_t dcc_change:1; 393 uint32_t color_space_change:1; 394 uint32_t input_tf_change:1; 395 uint32_t horizontal_mirror_change:1; 396 uint32_t per_pixel_alpha_change:1; 397 uint32_t rotation_change:1; 398 uint32_t swizzle_change:1; 399 uint32_t scaling_change:1; 400 uint32_t position_change:1; 401 uint32_t in_transfer_func:1; 402 uint32_t input_csc_change:1; 403 404 /* Full updates */ 405 uint32_t new_plane:1; 406 uint32_t bpp_change:1; 407 uint32_t bandwidth_change:1; 408 uint32_t clock_change:1; 409 uint32_t stereo_format_change:1; 410 uint32_t full_update:1; 411 } bits; 412 413 uint32_t raw; 414 }; 415 416 struct dc_plane_state { 417 struct dc_plane_address address; 418 struct scaling_taps scaling_quality; 419 struct rect src_rect; 420 struct rect dst_rect; 421 struct rect clip_rect; 422 423 union plane_size plane_size; 424 union dc_tiling_info tiling_info; 425 426 struct dc_plane_dcc_param dcc; 427 428 struct dc_gamma *gamma_correction; 429 struct dc_transfer_func *in_transfer_func; 430 struct dc_bias_and_scale *bias_and_scale; 431 struct csc_transform input_csc_color_matrix; 432 struct fixed31_32 coeff_reduction_factor; 433 434 // TODO: No longer used, remove 435 struct dc_hdr_static_metadata hdr_static_ctx; 436 437 enum dc_color_space color_space; 438 enum color_transfer_func input_tf; 439 440 enum surface_pixel_format format; 441 enum dc_rotation_angle rotation; 442 enum plane_stereo_format stereo_format; 443 444 bool is_tiling_rotated; 445 bool per_pixel_alpha; 446 bool visible; 447 bool flip_immediate; 448 bool horizontal_mirror; 449 450 union surface_update_flags update_flags; 451 /* private to DC core */ 452 struct dc_plane_status status; 453 struct dc_context *ctx; 454 455 /* private to dc_surface.c */ 456 enum dc_irq_source irq_source; 457 struct kref refcount; 458 }; 459 460 struct dc_plane_info { 461 union plane_size plane_size; 462 union dc_tiling_info tiling_info; 463 struct dc_plane_dcc_param dcc; 464 enum surface_pixel_format format; 465 enum dc_rotation_angle rotation; 466 enum plane_stereo_format stereo_format; 467 enum dc_color_space color_space; 468 enum color_transfer_func input_tf; 469 bool horizontal_mirror; 470 bool visible; 471 bool per_pixel_alpha; 472 bool input_csc_enabled; 473 }; 474 475 struct dc_scaling_info { 476 struct rect src_rect; 477 struct rect dst_rect; 478 struct rect clip_rect; 479 struct scaling_taps scaling_quality; 480 }; 481 482 struct dc_surface_update { 483 struct dc_plane_state *surface; 484 485 /* isr safe update parameters. null means no updates */ 486 struct dc_flip_addrs *flip_addr; 487 struct dc_plane_info *plane_info; 488 struct dc_scaling_info *scaling_info; 489 490 /* following updates require alloc/sleep/spin that is not isr safe, 491 * null means no updates 492 */ 493 /* gamma TO BE REMOVED */ 494 struct dc_gamma *gamma; 495 enum color_transfer_func color_input_tf; 496 enum color_transfer_func color_output_tf; 497 struct dc_transfer_func *in_transfer_func; 498 499 struct csc_transform *input_csc_color_matrix; 500 struct fixed31_32 *coeff_reduction_factor; 501 }; 502 503 /* 504 * Create a new surface with default parameters; 505 */ 506 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 507 const struct dc_plane_status *dc_plane_get_status( 508 const struct dc_plane_state *plane_state); 509 510 void dc_plane_state_retain(struct dc_plane_state *plane_state); 511 void dc_plane_state_release(struct dc_plane_state *plane_state); 512 513 void dc_gamma_retain(struct dc_gamma *dc_gamma); 514 void dc_gamma_release(struct dc_gamma **dc_gamma); 515 struct dc_gamma *dc_create_gamma(void); 516 517 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 518 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 519 struct dc_transfer_func *dc_create_transfer_func(void); 520 521 /* 522 * This structure holds a surface address. There could be multiple addresses 523 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 524 * as frame durations and DCC format can also be set. 525 */ 526 struct dc_flip_addrs { 527 struct dc_plane_address address; 528 bool flip_immediate; 529 /* TODO: add flip duration for FreeSync */ 530 }; 531 532 bool dc_post_update_surfaces_to_stream( 533 struct dc *dc); 534 535 #include "dc_stream.h" 536 537 /* 538 * Structure to store surface/stream associations for validation 539 */ 540 struct dc_validation_set { 541 struct dc_stream_state *stream; 542 struct dc_plane_state *plane_states[MAX_SURFACES]; 543 uint8_t plane_count; 544 }; 545 546 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 547 548 enum dc_status dc_validate_global_state( 549 struct dc *dc, 550 struct dc_state *new_ctx); 551 552 553 void dc_resource_state_construct( 554 const struct dc *dc, 555 struct dc_state *dst_ctx); 556 557 void dc_resource_state_copy_construct( 558 const struct dc_state *src_ctx, 559 struct dc_state *dst_ctx); 560 561 void dc_resource_state_copy_construct_current( 562 const struct dc *dc, 563 struct dc_state *dst_ctx); 564 565 void dc_resource_state_destruct(struct dc_state *context); 566 567 /* 568 * TODO update to make it about validation sets 569 * Set up streams and links associated to drive sinks 570 * The streams parameter is an absolute set of all active streams. 571 * 572 * After this call: 573 * Phy, Encoder, Timing Generator are programmed and enabled. 574 * New streams are enabled with blank stream; no memory read. 575 */ 576 bool dc_commit_state(struct dc *dc, struct dc_state *context); 577 578 579 struct dc_state *dc_create_state(void); 580 void dc_retain_state(struct dc_state *context); 581 void dc_release_state(struct dc_state *context); 582 583 /******************************************************************************* 584 * Link Interfaces 585 ******************************************************************************/ 586 587 struct dpcd_caps { 588 union dpcd_rev dpcd_rev; 589 union max_lane_count max_ln_count; 590 union max_down_spread max_down_spread; 591 592 /* dongle type (DP converter, CV smart dongle) */ 593 enum display_dongle_type dongle_type; 594 /* Dongle's downstream count. */ 595 union sink_count sink_count; 596 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 597 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 598 struct dc_dongle_caps dongle_caps; 599 600 uint32_t sink_dev_id; 601 uint32_t branch_dev_id; 602 int8_t branch_dev_name[6]; 603 int8_t branch_hw_revision; 604 605 bool allow_invalid_MSA_timing_param; 606 bool panel_mode_edp; 607 bool dpcd_display_control_capable; 608 }; 609 610 #include "dc_link.h" 611 612 /******************************************************************************* 613 * Sink Interfaces - A sink corresponds to a display output device 614 ******************************************************************************/ 615 616 struct dc_container_id { 617 // 128bit GUID in binary form 618 unsigned char guid[16]; 619 // 8 byte port ID -> ELD.PortID 620 unsigned int portId[2]; 621 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 622 unsigned short manufacturerName; 623 // 2 byte product code -> ELD.ProductCode 624 unsigned short productCode; 625 }; 626 627 628 629 /* 630 * The sink structure contains EDID and other display device properties 631 */ 632 struct dc_sink { 633 enum signal_type sink_signal; 634 struct dc_edid dc_edid; /* raw edid */ 635 struct dc_edid_caps edid_caps; /* parse display caps */ 636 struct dc_container_id *dc_container_id; 637 uint32_t dongle_max_pix_clk; 638 void *priv; 639 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 640 bool converter_disable_audio; 641 642 /* private to DC core */ 643 struct dc_link *link; 644 struct dc_context *ctx; 645 646 /* private to dc_sink.c */ 647 struct kref refcount; 648 649 }; 650 651 void dc_sink_retain(struct dc_sink *sink); 652 void dc_sink_release(struct dc_sink *sink); 653 654 struct dc_sink_init_data { 655 enum signal_type sink_signal; 656 struct dc_link *link; 657 uint32_t dongle_max_pix_clk; 658 bool converter_disable_audio; 659 }; 660 661 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 662 663 /* Newer interfaces */ 664 struct dc_cursor { 665 struct dc_plane_address address; 666 struct dc_cursor_attributes attributes; 667 }; 668 669 /******************************************************************************* 670 * Interrupt interfaces 671 ******************************************************************************/ 672 enum dc_irq_source dc_interrupt_to_irq_source( 673 struct dc *dc, 674 uint32_t src_id, 675 uint32_t ext_id); 676 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 677 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 678 enum dc_irq_source dc_get_hpd_irq_source_at_index( 679 struct dc *dc, uint32_t link_index); 680 681 /******************************************************************************* 682 * Power Interfaces 683 ******************************************************************************/ 684 685 void dc_set_power_state( 686 struct dc *dc, 687 enum dc_acpi_cm_power_state power_state); 688 void dc_resume(struct dc *dc); 689 690 #endif /* DC_INTERFACE_H_ */ 691