1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.41" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 115 bool hw_3d_lut; 116 #endif 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 121 struct dc_bug_wa { 122 bool no_connect_phy_config; 123 bool dedcn20_305_wa; 124 }; 125 #endif 126 127 struct dc_dcc_surface_param { 128 struct dc_size surface_size; 129 enum surface_pixel_format format; 130 enum swizzle_mode_values swizzle_mode; 131 enum dc_scan_direction scan; 132 }; 133 134 struct dc_dcc_setting { 135 unsigned int max_compressed_blk_size; 136 unsigned int max_uncompressed_blk_size; 137 bool independent_64b_blks; 138 }; 139 140 struct dc_surface_dcc_cap { 141 union { 142 struct { 143 struct dc_dcc_setting rgb; 144 } grph; 145 146 struct { 147 struct dc_dcc_setting luma; 148 struct dc_dcc_setting chroma; 149 } video; 150 }; 151 152 bool capable; 153 bool const_color_support; 154 }; 155 156 struct dc_static_screen_events { 157 bool force_trigger; 158 bool cursor_update; 159 bool surface_update; 160 bool overlay_update; 161 }; 162 163 164 /* Surface update type is used by dc_update_surfaces_and_stream 165 * The update type is determined at the very beginning of the function based 166 * on parameters passed in and decides how much programming (or updating) is 167 * going to be done during the call. 168 * 169 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 170 * logical calculations or hardware register programming. This update MUST be 171 * ISR safe on windows. Currently fast update will only be used to flip surface 172 * address. 173 * 174 * UPDATE_TYPE_MED is used for slower updates which require significant hw 175 * re-programming however do not affect bandwidth consumption or clock 176 * requirements. At present, this is the level at which front end updates 177 * that do not require us to run bw_calcs happen. These are in/out transfer func 178 * updates, viewport offset changes, recout size changes and pixel depth changes. 179 * This update can be done at ISR, but we want to minimize how often this happens. 180 * 181 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 182 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 183 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 184 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 185 * a full update. This cannot be done at ISR level and should be a rare event. 186 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 187 * underscan we don't expect to see this call at all. 188 */ 189 190 enum surface_update_type { 191 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 192 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 193 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 194 }; 195 196 /* Forward declaration*/ 197 struct dc; 198 struct dc_plane_state; 199 struct dc_state; 200 201 202 struct dc_cap_funcs { 203 bool (*get_dcc_compression_cap)(const struct dc *dc, 204 const struct dc_dcc_surface_param *input, 205 struct dc_surface_dcc_cap *output); 206 }; 207 208 struct link_training_settings; 209 210 211 /* Structure to hold configuration flags set by dm at dc creation. */ 212 struct dc_config { 213 bool gpu_vm_support; 214 bool disable_disp_pll_sharing; 215 bool fbc_support; 216 bool optimize_edp_link_rate; 217 bool disable_fractional_pwm; 218 bool allow_seamless_boot_optimization; 219 bool power_down_display_on_boot; 220 bool edp_not_connected; 221 bool forced_clocks; 222 223 }; 224 225 enum visual_confirm { 226 VISUAL_CONFIRM_DISABLE = 0, 227 VISUAL_CONFIRM_SURFACE = 1, 228 VISUAL_CONFIRM_HDR = 2, 229 }; 230 231 enum dcc_option { 232 DCC_ENABLE = 0, 233 DCC_DISABLE = 1, 234 DCC_HALF_REQ_DISALBE = 2, 235 }; 236 237 enum pipe_split_policy { 238 MPC_SPLIT_DYNAMIC = 0, 239 MPC_SPLIT_AVOID = 1, 240 MPC_SPLIT_AVOID_MULT_DISP = 2, 241 }; 242 243 enum wm_report_mode { 244 WM_REPORT_DEFAULT = 0, 245 WM_REPORT_OVERRIDE = 1, 246 }; 247 248 /* 249 * For any clocks that may differ per pipe 250 * only the max is stored in this structure 251 */ 252 struct dc_clocks { 253 int dispclk_khz; 254 int max_supported_dppclk_khz; 255 int dppclk_khz; 256 int dcfclk_khz; 257 int socclk_khz; 258 int dcfclk_deep_sleep_khz; 259 int fclk_khz; 260 int phyclk_khz; 261 int dramclk_khz; 262 bool p_state_change_support; 263 }; 264 265 struct dc_bw_validation_profile { 266 bool enable; 267 268 unsigned long long total_ticks; 269 unsigned long long voltage_level_ticks; 270 unsigned long long watermark_ticks; 271 unsigned long long rq_dlg_ticks; 272 273 unsigned long long total_count; 274 unsigned long long skip_fast_count; 275 unsigned long long skip_pass_count; 276 unsigned long long skip_fail_count; 277 }; 278 279 #define BW_VAL_TRACE_SETUP() \ 280 unsigned long long end_tick = 0; \ 281 unsigned long long voltage_level_tick = 0; \ 282 unsigned long long watermark_tick = 0; \ 283 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 284 dm_get_timestamp(dc->ctx) : 0 285 286 #define BW_VAL_TRACE_COUNT() \ 287 if (dc->debug.bw_val_profile.enable) \ 288 dc->debug.bw_val_profile.total_count++ 289 290 #define BW_VAL_TRACE_SKIP(status) \ 291 if (dc->debug.bw_val_profile.enable) { \ 292 if (!voltage_level_tick) \ 293 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 294 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 295 } 296 297 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 298 if (dc->debug.bw_val_profile.enable) \ 299 voltage_level_tick = dm_get_timestamp(dc->ctx) 300 301 #define BW_VAL_TRACE_END_WATERMARKS() \ 302 if (dc->debug.bw_val_profile.enable) \ 303 watermark_tick = dm_get_timestamp(dc->ctx) 304 305 #define BW_VAL_TRACE_FINISH() \ 306 if (dc->debug.bw_val_profile.enable) { \ 307 end_tick = dm_get_timestamp(dc->ctx); \ 308 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 309 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 310 if (watermark_tick) { \ 311 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 312 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 313 } \ 314 } 315 316 struct dc_debug_options { 317 enum visual_confirm visual_confirm; 318 bool sanity_checks; 319 bool max_disp_clk; 320 bool surface_trace; 321 bool timing_trace; 322 bool clock_trace; 323 bool validation_trace; 324 bool bandwidth_calcs_trace; 325 int max_downscale_src_width; 326 327 /* stutter efficiency related */ 328 bool disable_stutter; 329 bool use_max_lb; 330 enum dcc_option disable_dcc; 331 enum pipe_split_policy pipe_split_policy; 332 bool force_single_disp_pipe_split; 333 bool voltage_align_fclk; 334 335 bool disable_dfs_bypass; 336 bool disable_dpp_power_gate; 337 bool disable_hubp_power_gate; 338 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 339 bool disable_dsc_power_gate; 340 #endif 341 bool disable_pplib_wm_range; 342 enum wm_report_mode pplib_wm_report_mode; 343 unsigned int min_disp_clk_khz; 344 int sr_exit_time_dpm0_ns; 345 int sr_enter_plus_exit_time_dpm0_ns; 346 int sr_exit_time_ns; 347 int sr_enter_plus_exit_time_ns; 348 int urgent_latency_ns; 349 uint32_t underflow_assert_delay_us; 350 int percent_of_ideal_drambw; 351 int dram_clock_change_latency_ns; 352 bool optimized_watermark; 353 int always_scale; 354 bool disable_pplib_clock_request; 355 bool disable_clock_gate; 356 bool disable_dmcu; 357 bool disable_psr; 358 bool force_abm_enable; 359 bool disable_stereo_support; 360 bool vsr_support; 361 bool performance_trace; 362 bool az_endpoint_mute_only; 363 bool always_use_regamma; 364 bool p010_mpo_support; 365 bool recovery_enabled; 366 bool avoid_vbios_exec_table; 367 bool scl_reset_length10; 368 bool hdmi20_disable; 369 bool skip_detection_link_training; 370 unsigned int force_odm_combine; //bit vector based on otg inst 371 unsigned int force_fclk_khz; 372 bool disable_tri_buf; 373 struct dc_bw_validation_profile bw_val_profile; 374 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 375 bool disable_fec; 376 #endif 377 /* This forces a hard min on the DCFCLK requested to SMU/PP 378 * watermarks are not affected. 379 */ 380 unsigned int force_min_dcfclk_mhz; 381 bool disable_timing_sync; 382 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 383 bool cm_in_bypass; 384 #endif 385 }; 386 387 struct dc_debug_data { 388 uint32_t ltFailCount; 389 uint32_t i2cErrorCount; 390 uint32_t auxErrorCount; 391 }; 392 393 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 394 struct dc_phy_addr_space_config { 395 struct { 396 uint64_t start_addr; 397 uint64_t end_addr; 398 uint64_t fb_top; 399 uint64_t fb_offset; 400 uint64_t fb_base; 401 uint64_t agp_top; 402 uint64_t agp_bot; 403 uint64_t agp_base; 404 } system_aperture; 405 406 struct { 407 uint64_t page_table_start_addr; 408 uint64_t page_table_end_addr; 409 uint64_t page_table_base_addr; 410 } gart_config; 411 412 bool valid; 413 }; 414 415 struct dc_virtual_addr_space_config { 416 uint64_t page_table_base_addr; 417 uint64_t page_table_start_addr; 418 uint64_t page_table_end_addr; 419 uint32_t page_table_block_size_in_bytes; 420 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 421 }; 422 #endif 423 424 struct dc_bounding_box_overrides { 425 int sr_exit_time_ns; 426 int sr_enter_plus_exit_time_ns; 427 int urgent_latency_ns; 428 int percent_of_ideal_drambw; 429 int dram_clock_change_latency_ns; 430 /* This forces a hard min on the DCFCLK we use 431 * for DML. Unlike the debug option for forcing 432 * DCFCLK, this override affects watermark calculations 433 */ 434 int min_dcfclk_mhz; 435 }; 436 437 struct dc_state; 438 struct resource_pool; 439 struct dce_hwseq; 440 struct gpu_info_soc_bounding_box_v1_0; 441 struct dc { 442 struct dc_versions versions; 443 struct dc_caps caps; 444 struct dc_cap_funcs cap_funcs; 445 struct dc_config config; 446 struct dc_debug_options debug; 447 struct dc_bounding_box_overrides bb_overrides; 448 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 449 struct dc_bug_wa work_arounds; 450 #endif 451 struct dc_context *ctx; 452 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 453 struct dc_phy_addr_space_config vm_pa_config; 454 #endif 455 456 uint8_t link_count; 457 struct dc_link *links[MAX_PIPES * 2]; 458 459 struct dc_state *current_state; 460 struct resource_pool *res_pool; 461 462 struct clk_mgr *clk_mgr; 463 464 /* Display Engine Clock levels */ 465 struct dm_pp_clock_levels sclk_lvls; 466 467 /* Inputs into BW and WM calculations. */ 468 struct bw_calcs_dceip *bw_dceip; 469 struct bw_calcs_vbios *bw_vbios; 470 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 471 struct dcn_soc_bounding_box *dcn_soc; 472 struct dcn_ip_params *dcn_ip; 473 struct display_mode_lib dml; 474 #endif 475 476 /* HW functions */ 477 struct hw_sequencer_funcs hwss; 478 struct dce_hwseq *hwseq; 479 480 /* Require to optimize clocks and bandwidth for added/removed planes */ 481 bool optimized_required; 482 483 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 484 bool optimize_seamless_boot; 485 486 /* FBC compressor */ 487 struct compressor *fbc_compressor; 488 489 struct dc_debug_data debug_data; 490 491 const char *build_id; 492 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 493 struct vm_helper *vm_helper; 494 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 495 #endif 496 }; 497 498 enum frame_buffer_mode { 499 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 500 FRAME_BUFFER_MODE_ZFB_ONLY, 501 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 502 } ; 503 504 struct dchub_init_data { 505 int64_t zfb_phys_addr_base; 506 int64_t zfb_mc_base_addr; 507 uint64_t zfb_size_in_byte; 508 enum frame_buffer_mode fb_mode; 509 bool dchub_initialzied; 510 bool dchub_info_valid; 511 }; 512 513 struct dc_init_data { 514 struct hw_asic_id asic_id; 515 void *driver; /* ctx */ 516 struct cgs_device *cgs_device; 517 struct dc_bounding_box_overrides bb_overrides; 518 519 int num_virtual_links; 520 /* 521 * If 'vbios_override' not NULL, it will be called instead 522 * of the real VBIOS. Intended use is Diagnostics on FPGA. 523 */ 524 struct dc_bios *vbios_override; 525 enum dce_environment dce_environment; 526 527 struct dc_config flags; 528 uint32_t log_mask; 529 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 530 /** 531 * gpu_info FW provided soc bounding box struct or 0 if not 532 * available in FW 533 */ 534 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 535 #endif 536 }; 537 538 struct dc_callback_init { 539 uint8_t reserved; 540 }; 541 542 struct dc *dc_create(const struct dc_init_data *init_params); 543 int dc_get_vmid_use_vector(struct dc *dc); 544 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 545 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 546 /* Returns the number of vmids supported */ 547 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 548 #endif 549 void dc_init_callbacks(struct dc *dc, 550 const struct dc_callback_init *init_params); 551 void dc_destroy(struct dc **dc); 552 553 /******************************************************************************* 554 * Surface Interfaces 555 ******************************************************************************/ 556 557 enum { 558 TRANSFER_FUNC_POINTS = 1025 559 }; 560 561 struct dc_hdr_static_metadata { 562 /* display chromaticities and white point in units of 0.00001 */ 563 unsigned int chromaticity_green_x; 564 unsigned int chromaticity_green_y; 565 unsigned int chromaticity_blue_x; 566 unsigned int chromaticity_blue_y; 567 unsigned int chromaticity_red_x; 568 unsigned int chromaticity_red_y; 569 unsigned int chromaticity_white_point_x; 570 unsigned int chromaticity_white_point_y; 571 572 uint32_t min_luminance; 573 uint32_t max_luminance; 574 uint32_t maximum_content_light_level; 575 uint32_t maximum_frame_average_light_level; 576 }; 577 578 enum dc_transfer_func_type { 579 TF_TYPE_PREDEFINED, 580 TF_TYPE_DISTRIBUTED_POINTS, 581 TF_TYPE_BYPASS, 582 TF_TYPE_HWPWL 583 }; 584 585 struct dc_transfer_func_distributed_points { 586 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 587 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 588 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 589 590 uint16_t end_exponent; 591 uint16_t x_point_at_y1_red; 592 uint16_t x_point_at_y1_green; 593 uint16_t x_point_at_y1_blue; 594 }; 595 596 enum dc_transfer_func_predefined { 597 TRANSFER_FUNCTION_SRGB, 598 TRANSFER_FUNCTION_BT709, 599 TRANSFER_FUNCTION_PQ, 600 TRANSFER_FUNCTION_LINEAR, 601 TRANSFER_FUNCTION_UNITY, 602 TRANSFER_FUNCTION_HLG, 603 TRANSFER_FUNCTION_HLG12, 604 TRANSFER_FUNCTION_GAMMA22 605 }; 606 607 struct dc_transfer_func { 608 struct kref refcount; 609 enum dc_transfer_func_type type; 610 enum dc_transfer_func_predefined tf; 611 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 612 uint32_t sdr_ref_white_level; 613 struct dc_context *ctx; 614 union { 615 struct pwl_params pwl; 616 struct dc_transfer_func_distributed_points tf_pts; 617 }; 618 }; 619 620 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 621 622 union dc_3dlut_state { 623 struct { 624 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 625 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 626 uint32_t rmu_mux_num:3; /*index of mux to use*/ 627 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 628 uint32_t mpc_rmu1_mux:4; 629 uint32_t mpc_rmu2_mux:4; 630 uint32_t reserved:15; 631 } bits; 632 uint32_t raw; 633 }; 634 635 636 struct dc_3dlut { 637 struct kref refcount; 638 struct tetrahedral_params lut_3d; 639 uint32_t hdr_multiplier; 640 bool initialized; /*remove after diag fix*/ 641 union dc_3dlut_state state; 642 struct dc_context *ctx; 643 }; 644 #endif 645 /* 646 * This structure is filled in by dc_surface_get_status and contains 647 * the last requested address and the currently active address so the called 648 * can determine if there are any outstanding flips 649 */ 650 struct dc_plane_status { 651 struct dc_plane_address requested_address; 652 struct dc_plane_address current_address; 653 bool is_flip_pending; 654 bool is_right_eye; 655 }; 656 657 union surface_update_flags { 658 659 struct { 660 uint32_t addr_update:1; 661 /* Medium updates */ 662 uint32_t dcc_change:1; 663 uint32_t color_space_change:1; 664 uint32_t horizontal_mirror_change:1; 665 uint32_t per_pixel_alpha_change:1; 666 uint32_t global_alpha_change:1; 667 uint32_t sdr_white_level:1; 668 uint32_t rotation_change:1; 669 uint32_t swizzle_change:1; 670 uint32_t scaling_change:1; 671 uint32_t position_change:1; 672 uint32_t in_transfer_func_change:1; 673 uint32_t input_csc_change:1; 674 uint32_t coeff_reduction_change:1; 675 uint32_t output_tf_change:1; 676 uint32_t pixel_format_change:1; 677 uint32_t plane_size_change:1; 678 679 /* Full updates */ 680 uint32_t new_plane:1; 681 uint32_t bpp_change:1; 682 uint32_t gamma_change:1; 683 uint32_t bandwidth_change:1; 684 uint32_t clock_change:1; 685 uint32_t stereo_format_change:1; 686 uint32_t full_update:1; 687 } bits; 688 689 uint32_t raw; 690 }; 691 692 struct dc_plane_state { 693 struct dc_plane_address address; 694 struct dc_plane_flip_time time; 695 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 696 bool triplebuffer_flips; 697 #endif 698 struct scaling_taps scaling_quality; 699 struct rect src_rect; 700 struct rect dst_rect; 701 struct rect clip_rect; 702 703 union plane_size plane_size; 704 union dc_tiling_info tiling_info; 705 706 struct dc_plane_dcc_param dcc; 707 708 struct dc_gamma *gamma_correction; 709 struct dc_transfer_func *in_transfer_func; 710 struct dc_bias_and_scale *bias_and_scale; 711 struct dc_csc_transform input_csc_color_matrix; 712 struct fixed31_32 coeff_reduction_factor; 713 uint32_t sdr_white_level; 714 715 // TODO: No longer used, remove 716 struct dc_hdr_static_metadata hdr_static_ctx; 717 718 enum dc_color_space color_space; 719 720 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 721 struct dc_3dlut *lut3d_func; 722 struct dc_transfer_func *in_shaper_func; 723 struct dc_transfer_func *blend_tf; 724 #endif 725 726 enum surface_pixel_format format; 727 enum dc_rotation_angle rotation; 728 enum plane_stereo_format stereo_format; 729 730 bool is_tiling_rotated; 731 bool per_pixel_alpha; 732 bool global_alpha; 733 int global_alpha_value; 734 bool visible; 735 bool flip_immediate; 736 bool horizontal_mirror; 737 738 union surface_update_flags update_flags; 739 /* private to DC core */ 740 struct dc_plane_status status; 741 struct dc_context *ctx; 742 743 /* HACK: Workaround for forcing full reprogramming under some conditions */ 744 bool force_full_update; 745 746 /* private to dc_surface.c */ 747 enum dc_irq_source irq_source; 748 struct kref refcount; 749 }; 750 751 struct dc_plane_info { 752 union plane_size plane_size; 753 union dc_tiling_info tiling_info; 754 struct dc_plane_dcc_param dcc; 755 enum surface_pixel_format format; 756 enum dc_rotation_angle rotation; 757 enum plane_stereo_format stereo_format; 758 enum dc_color_space color_space; 759 unsigned int sdr_white_level; 760 bool horizontal_mirror; 761 bool visible; 762 bool per_pixel_alpha; 763 bool global_alpha; 764 int global_alpha_value; 765 bool input_csc_enabled; 766 }; 767 768 struct dc_scaling_info { 769 struct rect src_rect; 770 struct rect dst_rect; 771 struct rect clip_rect; 772 struct scaling_taps scaling_quality; 773 }; 774 775 struct dc_surface_update { 776 struct dc_plane_state *surface; 777 778 /* isr safe update parameters. null means no updates */ 779 const struct dc_flip_addrs *flip_addr; 780 const struct dc_plane_info *plane_info; 781 const struct dc_scaling_info *scaling_info; 782 783 /* following updates require alloc/sleep/spin that is not isr safe, 784 * null means no updates 785 */ 786 const struct dc_gamma *gamma; 787 const struct dc_transfer_func *in_transfer_func; 788 789 const struct dc_csc_transform *input_csc_color_matrix; 790 const struct fixed31_32 *coeff_reduction_factor; 791 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 792 const struct dc_transfer_func *func_shaper; 793 const struct dc_3dlut *lut3d_func; 794 const struct dc_transfer_func *blend_tf; 795 #endif 796 }; 797 798 /* 799 * Create a new surface with default parameters; 800 */ 801 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 802 const struct dc_plane_status *dc_plane_get_status( 803 const struct dc_plane_state *plane_state); 804 805 void dc_plane_state_retain(struct dc_plane_state *plane_state); 806 void dc_plane_state_release(struct dc_plane_state *plane_state); 807 808 void dc_gamma_retain(struct dc_gamma *dc_gamma); 809 void dc_gamma_release(struct dc_gamma **dc_gamma); 810 struct dc_gamma *dc_create_gamma(void); 811 812 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 813 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 814 struct dc_transfer_func *dc_create_transfer_func(void); 815 816 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 817 struct dc_3dlut *dc_create_3dlut_func(void); 818 void dc_3dlut_func_release(struct dc_3dlut *lut); 819 void dc_3dlut_func_retain(struct dc_3dlut *lut); 820 #endif 821 /* 822 * This structure holds a surface address. There could be multiple addresses 823 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 824 * as frame durations and DCC format can also be set. 825 */ 826 struct dc_flip_addrs { 827 struct dc_plane_address address; 828 unsigned int flip_timestamp_in_us; 829 bool flip_immediate; 830 /* TODO: add flip duration for FreeSync */ 831 }; 832 833 bool dc_post_update_surfaces_to_stream( 834 struct dc *dc); 835 836 #include "dc_stream.h" 837 838 /* 839 * Structure to store surface/stream associations for validation 840 */ 841 struct dc_validation_set { 842 struct dc_stream_state *stream; 843 struct dc_plane_state *plane_states[MAX_SURFACES]; 844 uint8_t plane_count; 845 }; 846 847 bool dc_validate_seamless_boot_timing(const struct dc *dc, 848 const struct dc_sink *sink, 849 struct dc_crtc_timing *crtc_timing); 850 851 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 852 853 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 854 855 bool dc_set_generic_gpio_for_stereo(bool enable, 856 struct gpio_service *gpio_service); 857 858 /* 859 * fast_validate: we return after determining if we can support the new state, 860 * but before we populate the programming info 861 */ 862 enum dc_status dc_validate_global_state( 863 struct dc *dc, 864 struct dc_state *new_ctx, 865 bool fast_validate); 866 867 868 void dc_resource_state_construct( 869 const struct dc *dc, 870 struct dc_state *dst_ctx); 871 872 void dc_resource_state_copy_construct( 873 const struct dc_state *src_ctx, 874 struct dc_state *dst_ctx); 875 876 void dc_resource_state_copy_construct_current( 877 const struct dc *dc, 878 struct dc_state *dst_ctx); 879 880 void dc_resource_state_destruct(struct dc_state *context); 881 882 /* 883 * TODO update to make it about validation sets 884 * Set up streams and links associated to drive sinks 885 * The streams parameter is an absolute set of all active streams. 886 * 887 * After this call: 888 * Phy, Encoder, Timing Generator are programmed and enabled. 889 * New streams are enabled with blank stream; no memory read. 890 */ 891 bool dc_commit_state(struct dc *dc, struct dc_state *context); 892 893 894 struct dc_state *dc_create_state(struct dc *dc); 895 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 896 void dc_retain_state(struct dc_state *context); 897 void dc_release_state(struct dc_state *context); 898 899 /******************************************************************************* 900 * Link Interfaces 901 ******************************************************************************/ 902 903 struct dpcd_caps { 904 union dpcd_rev dpcd_rev; 905 union max_lane_count max_ln_count; 906 union max_down_spread max_down_spread; 907 union dprx_feature dprx_feature; 908 909 /* valid only for eDP v1.4 or higher*/ 910 uint8_t edp_supported_link_rates_count; 911 enum dc_link_rate edp_supported_link_rates[8]; 912 913 /* dongle type (DP converter, CV smart dongle) */ 914 enum display_dongle_type dongle_type; 915 /* branch device or sink device */ 916 bool is_branch_dev; 917 /* Dongle's downstream count. */ 918 union sink_count sink_count; 919 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 920 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 921 struct dc_dongle_caps dongle_caps; 922 923 uint32_t sink_dev_id; 924 int8_t sink_dev_id_str[6]; 925 int8_t sink_hw_revision; 926 int8_t sink_fw_revision[2]; 927 928 uint32_t branch_dev_id; 929 int8_t branch_dev_name[6]; 930 int8_t branch_hw_revision; 931 int8_t branch_fw_revision[2]; 932 933 bool allow_invalid_MSA_timing_param; 934 bool panel_mode_edp; 935 bool dpcd_display_control_capable; 936 bool ext_receiver_cap_field_present; 937 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 938 union dpcd_fec_capability fec_cap; 939 struct dpcd_dsc_capabilities dsc_caps; 940 #endif 941 }; 942 943 #include "dc_link.h" 944 945 /******************************************************************************* 946 * Sink Interfaces - A sink corresponds to a display output device 947 ******************************************************************************/ 948 949 struct dc_container_id { 950 // 128bit GUID in binary form 951 unsigned char guid[16]; 952 // 8 byte port ID -> ELD.PortID 953 unsigned int portId[2]; 954 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 955 unsigned short manufacturerName; 956 // 2 byte product code -> ELD.ProductCode 957 unsigned short productCode; 958 }; 959 960 961 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 962 struct dc_sink_dsc_caps { 963 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 964 // 'false' if they are sink's DSC caps 965 bool is_virtual_dpcd_dsc; 966 struct dsc_dec_dpcd_caps dsc_dec_caps; 967 }; 968 #endif 969 970 /* 971 * The sink structure contains EDID and other display device properties 972 */ 973 struct dc_sink { 974 enum signal_type sink_signal; 975 struct dc_edid dc_edid; /* raw edid */ 976 struct dc_edid_caps edid_caps; /* parse display caps */ 977 struct dc_container_id *dc_container_id; 978 uint32_t dongle_max_pix_clk; 979 void *priv; 980 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 981 bool converter_disable_audio; 982 983 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 984 struct dc_sink_dsc_caps sink_dsc_caps; 985 #endif 986 987 /* private to DC core */ 988 struct dc_link *link; 989 struct dc_context *ctx; 990 991 uint32_t sink_id; 992 993 /* private to dc_sink.c */ 994 // refcount must be the last member in dc_sink, since we want the 995 // sink structure to be logically cloneable up to (but not including) 996 // refcount 997 struct kref refcount; 998 }; 999 1000 void dc_sink_retain(struct dc_sink *sink); 1001 void dc_sink_release(struct dc_sink *sink); 1002 1003 struct dc_sink_init_data { 1004 enum signal_type sink_signal; 1005 struct dc_link *link; 1006 uint32_t dongle_max_pix_clk; 1007 bool converter_disable_audio; 1008 }; 1009 1010 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1011 1012 /* Newer interfaces */ 1013 struct dc_cursor { 1014 struct dc_plane_address address; 1015 struct dc_cursor_attributes attributes; 1016 }; 1017 1018 1019 /******************************************************************************* 1020 * Interrupt interfaces 1021 ******************************************************************************/ 1022 enum dc_irq_source dc_interrupt_to_irq_source( 1023 struct dc *dc, 1024 uint32_t src_id, 1025 uint32_t ext_id); 1026 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1027 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1028 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1029 struct dc *dc, uint32_t link_index); 1030 1031 /******************************************************************************* 1032 * Power Interfaces 1033 ******************************************************************************/ 1034 1035 void dc_set_power_state( 1036 struct dc *dc, 1037 enum dc_acpi_cm_power_state power_state); 1038 void dc_resume(struct dc *dc); 1039 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1040 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1041 1042 bool dc_is_dmcu_initialized(struct dc *dc); 1043 1044 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1045 /******************************************************************************* 1046 * DSC Interfaces 1047 ******************************************************************************/ 1048 #include "dc_dsc.h" 1049 #endif 1050 #endif /* DC_INTERFACE_H_ */ 1051