1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "spl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 58 #define DC_VER "3.2.314" 59 60 #define MAX_SURFACES 3 61 #define MAX_PLANES 6 62 #define MAX_STREAMS 6 63 #define MIN_VIEWPORT_SIZE 12 64 #define MAX_NUM_EDP 2 65 #define MAX_HOST_ROUTERS_NUM 2 66 67 /* Display Core Interfaces */ 68 struct dc_versions { 69 const char *dc_ver; 70 struct dmcu_version dmcu_version; 71 }; 72 73 enum dp_protocol_version { 74 DP_VERSION_1_4 = 0, 75 DP_VERSION_2_1, 76 DP_VERSION_UNKNOWN, 77 }; 78 79 enum dc_plane_type { 80 DC_PLANE_TYPE_INVALID, 81 DC_PLANE_TYPE_DCE_RGB, 82 DC_PLANE_TYPE_DCE_UNDERLAY, 83 DC_PLANE_TYPE_DCN_UNIVERSAL, 84 }; 85 86 // Sizes defined as multiples of 64KB 87 enum det_size { 88 DET_SIZE_DEFAULT = 0, 89 DET_SIZE_192KB = 3, 90 DET_SIZE_256KB = 4, 91 DET_SIZE_320KB = 5, 92 DET_SIZE_384KB = 6 93 }; 94 95 96 struct dc_plane_cap { 97 enum dc_plane_type type; 98 uint32_t per_pixel_alpha : 1; 99 struct { 100 uint32_t argb8888 : 1; 101 uint32_t nv12 : 1; 102 uint32_t fp16 : 1; 103 uint32_t p010 : 1; 104 uint32_t ayuv : 1; 105 } pixel_format_support; 106 // max upscaling factor x1000 107 // upscaling factors are always >= 1 108 // for example, 1080p -> 8K is 4.0, or 4000 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_upscale_factor; 114 // max downscale factor x1000 115 // downscale factors are always <= 1 116 // for example, 8K -> 1080p is 0.25, or 250 raw value 117 struct { 118 uint32_t argb8888; 119 uint32_t nv12; 120 uint32_t fp16; 121 } max_downscale_factor; 122 // minimal width/height 123 uint32_t min_width; 124 uint32_t min_height; 125 }; 126 127 /** 128 * DOC: color-management-caps 129 * 130 * **Color management caps (DPP and MPC)** 131 * 132 * Modules/color calculates various color operations which are translated to 133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 134 * DCN1, every new generation comes with fairly major differences in color 135 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 136 * decide mapping to HW block based on logical capabilities. 137 */ 138 139 /** 140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 141 * @srgb: RGB color space transfer func 142 * @bt2020: BT.2020 transfer func 143 * @gamma2_2: standard gamma 144 * @pq: perceptual quantizer transfer function 145 * @hlg: hybrid log–gamma transfer function 146 */ 147 struct rom_curve_caps { 148 uint16_t srgb : 1; 149 uint16_t bt2020 : 1; 150 uint16_t gamma2_2 : 1; 151 uint16_t pq : 1; 152 uint16_t hlg : 1; 153 }; 154 155 /** 156 * struct dpp_color_caps - color pipeline capabilities for display pipe and 157 * plane blocks 158 * 159 * @dcn_arch: all DCE generations treated the same 160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 161 * just plain 256-entry lookup 162 * @icsc: input color space conversion 163 * @dgam_ram: programmable degamma LUT 164 * @post_csc: post color space conversion, before gamut remap 165 * @gamma_corr: degamma correction 166 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 167 * with MPC by setting mpc:shared_3d_lut flag 168 * @ogam_ram: programmable out/blend gamma LUT 169 * @ocsc: output color space conversion 170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 173 * 174 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 175 */ 176 struct dpp_color_caps { 177 uint16_t dcn_arch : 1; 178 uint16_t input_lut_shared : 1; 179 uint16_t icsc : 1; 180 uint16_t dgam_ram : 1; 181 uint16_t post_csc : 1; 182 uint16_t gamma_corr : 1; 183 uint16_t hw_3d_lut : 1; 184 uint16_t ogam_ram : 1; 185 uint16_t ocsc : 1; 186 uint16_t dgam_rom_for_yuv : 1; 187 struct rom_curve_caps dgam_rom_caps; 188 struct rom_curve_caps ogam_rom_caps; 189 }; 190 191 /** 192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 193 * plane combined blocks 194 * 195 * @gamut_remap: color transformation matrix 196 * @ogam_ram: programmable out gamma LUT 197 * @ocsc: output color space conversion matrix 198 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 199 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 200 * instance 201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 202 */ 203 struct mpc_color_caps { 204 uint16_t gamut_remap : 1; 205 uint16_t ogam_ram : 1; 206 uint16_t ocsc : 1; 207 uint16_t num_3dluts : 3; 208 uint16_t shared_3d_lut:1; 209 struct rom_curve_caps ogam_rom_caps; 210 }; 211 212 /** 213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 214 * @dpp: color pipes caps for DPP 215 * @mpc: color pipes caps for MPC 216 */ 217 struct dc_color_caps { 218 struct dpp_color_caps dpp; 219 struct mpc_color_caps mpc; 220 }; 221 222 struct dc_dmub_caps { 223 bool psr; 224 bool mclk_sw; 225 bool subvp_psr; 226 bool gecc_enable; 227 uint8_t fams_ver; 228 bool aux_backlight_support; 229 }; 230 231 struct dc_scl_caps { 232 bool sharpener_support; 233 }; 234 235 struct dc_caps { 236 uint32_t max_streams; 237 uint32_t max_links; 238 uint32_t max_audios; 239 uint32_t max_slave_planes; 240 uint32_t max_slave_yuv_planes; 241 uint32_t max_slave_rgb_planes; 242 uint32_t max_planes; 243 uint32_t max_downscale_ratio; 244 uint32_t i2c_speed_in_khz; 245 uint32_t i2c_speed_in_khz_hdcp; 246 uint32_t dmdata_alloc_size; 247 unsigned int max_cursor_size; 248 unsigned int max_video_width; 249 /* 250 * max video plane width that can be safely assumed to be always 251 * supported by single DPP pipe. 252 */ 253 unsigned int max_optimizable_video_width; 254 unsigned int min_horizontal_blanking_period; 255 int linear_pitch_alignment; 256 bool dcc_const_color; 257 bool dynamic_audio; 258 bool is_apu; 259 bool dual_link_dvi; 260 bool post_blend_color_processing; 261 bool force_dp_tps4_for_cp2520; 262 bool disable_dp_clk_share; 263 bool psp_setup_panel_mode; 264 bool extended_aux_timeout_support; 265 bool dmcub_support; 266 bool zstate_support; 267 bool ips_support; 268 uint32_t num_of_internal_disp; 269 enum dp_protocol_version max_dp_protocol_version; 270 unsigned int mall_size_per_mem_channel; 271 unsigned int mall_size_total; 272 unsigned int cursor_cache_size; 273 struct dc_plane_cap planes[MAX_PLANES]; 274 struct dc_color_caps color; 275 struct dc_dmub_caps dmub_caps; 276 bool dp_hpo; 277 bool dp_hdmi21_pcon_support; 278 bool edp_dsc_support; 279 bool vbios_lttpr_aware; 280 bool vbios_lttpr_enable; 281 uint32_t max_otg_num; 282 uint32_t max_cab_allocation_bytes; 283 uint32_t cache_line_size; 284 uint32_t cache_num_ways; 285 uint16_t subvp_fw_processing_delay_us; 286 uint8_t subvp_drr_max_vblank_margin_us; 287 uint16_t subvp_prefetch_end_to_mall_start_us; 288 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 289 uint16_t subvp_pstate_allow_width_us; 290 uint16_t subvp_vertical_int_margin_us; 291 bool seamless_odm; 292 uint32_t max_v_total; 293 bool vtotal_limited_by_fp2; 294 uint32_t max_disp_clock_khz_at_vmin; 295 uint8_t subvp_drr_vblank_start_margin_us; 296 bool cursor_not_scaled; 297 bool dcmode_power_limits_present; 298 bool sequential_ono; 299 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 300 uint32_t dcc_plane_width_limit; 301 struct dc_scl_caps scl_caps; 302 }; 303 304 struct dc_bug_wa { 305 bool no_connect_phy_config; 306 bool dedcn20_305_wa; 307 bool skip_clock_update; 308 bool lt_early_cr_pattern; 309 struct { 310 uint8_t uclk : 1; 311 uint8_t fclk : 1; 312 uint8_t dcfclk : 1; 313 uint8_t dcfclk_ds: 1; 314 } clock_update_disable_mask; 315 bool skip_psr_ips_crtc_disable; 316 }; 317 struct dc_dcc_surface_param { 318 struct dc_size surface_size; 319 enum surface_pixel_format format; 320 unsigned int plane0_pitch; 321 struct dc_size plane1_size; 322 unsigned int plane1_pitch; 323 union { 324 enum swizzle_mode_values swizzle_mode; 325 enum swizzle_mode_addr3_values swizzle_mode_addr3; 326 }; 327 enum dc_scan_direction scan; 328 }; 329 330 struct dc_dcc_setting { 331 unsigned int max_compressed_blk_size; 332 unsigned int max_uncompressed_blk_size; 333 bool independent_64b_blks; 334 //These bitfields to be used starting with DCN 3.0 335 struct { 336 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 337 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 338 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 339 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 340 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 341 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 342 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 343 } dcc_controls; 344 }; 345 346 struct dc_surface_dcc_cap { 347 union { 348 struct { 349 struct dc_dcc_setting rgb; 350 } grph; 351 352 struct { 353 struct dc_dcc_setting luma; 354 struct dc_dcc_setting chroma; 355 } video; 356 }; 357 358 bool capable; 359 bool const_color_support; 360 }; 361 362 struct dc_static_screen_params { 363 struct { 364 bool force_trigger; 365 bool cursor_update; 366 bool surface_update; 367 bool overlay_update; 368 } triggers; 369 unsigned int num_frames; 370 }; 371 372 373 /* Surface update type is used by dc_update_surfaces_and_stream 374 * The update type is determined at the very beginning of the function based 375 * on parameters passed in and decides how much programming (or updating) is 376 * going to be done during the call. 377 * 378 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 379 * logical calculations or hardware register programming. This update MUST be 380 * ISR safe on windows. Currently fast update will only be used to flip surface 381 * address. 382 * 383 * UPDATE_TYPE_MED is used for slower updates which require significant hw 384 * re-programming however do not affect bandwidth consumption or clock 385 * requirements. At present, this is the level at which front end updates 386 * that do not require us to run bw_calcs happen. These are in/out transfer func 387 * updates, viewport offset changes, recout size changes and pixel depth changes. 388 * This update can be done at ISR, but we want to minimize how often this happens. 389 * 390 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 391 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 392 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 393 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 394 * a full update. This cannot be done at ISR level and should be a rare event. 395 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 396 * underscan we don't expect to see this call at all. 397 */ 398 399 enum surface_update_type { 400 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 401 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 402 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 403 }; 404 405 /* Forward declaration*/ 406 struct dc; 407 struct dc_plane_state; 408 struct dc_state; 409 410 struct dc_cap_funcs { 411 bool (*get_dcc_compression_cap)(const struct dc *dc, 412 const struct dc_dcc_surface_param *input, 413 struct dc_surface_dcc_cap *output); 414 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 415 }; 416 417 struct link_training_settings; 418 419 union allow_lttpr_non_transparent_mode { 420 struct { 421 bool DP1_4A : 1; 422 bool DP2_0 : 1; 423 } bits; 424 unsigned char raw; 425 }; 426 427 /* Structure to hold configuration flags set by dm at dc creation. */ 428 struct dc_config { 429 bool gpu_vm_support; 430 bool disable_disp_pll_sharing; 431 bool fbc_support; 432 bool disable_fractional_pwm; 433 bool allow_seamless_boot_optimization; 434 bool seamless_boot_edp_requested; 435 bool edp_not_connected; 436 bool edp_no_power_sequencing; 437 bool force_enum_edp; 438 bool forced_clocks; 439 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 440 bool multi_mon_pp_mclk_switch; 441 bool disable_dmcu; 442 bool enable_4to1MPC; 443 bool enable_windowed_mpo_odm; 444 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 445 uint32_t allow_edp_hotplug_detection; 446 bool clamp_min_dcfclk; 447 uint64_t vblank_alignment_dto_params; 448 uint8_t vblank_alignment_max_frame_time_diff; 449 bool is_asymmetric_memory; 450 bool is_single_rank_dimm; 451 bool is_vmin_only_asic; 452 bool use_spl; 453 bool prefer_easf; 454 bool use_pipe_ctx_sync_logic; 455 bool ignore_dpref_ss; 456 bool enable_mipi_converter_optimization; 457 bool use_default_clock_table; 458 bool force_bios_enable_lttpr; 459 uint8_t force_bios_fixed_vs; 460 int sdpif_request_limit_words_per_umc; 461 bool dc_mode_clk_limit_support; 462 bool EnableMinDispClkODM; 463 bool enable_auto_dpm_test_logs; 464 unsigned int disable_ips; 465 unsigned int disable_ips_in_vpb; 466 bool disable_ips_in_dpms_off; 467 bool usb4_bw_alloc_support; 468 bool allow_0_dtb_clk; 469 bool use_assr_psp_message; 470 bool support_edp0_on_dp1; 471 unsigned int enable_fpo_flicker_detection; 472 bool disable_hbr_audio_dp2; 473 bool consolidated_dpia_dp_lt; 474 bool set_pipe_unlock_order; 475 }; 476 477 enum visual_confirm { 478 VISUAL_CONFIRM_DISABLE = 0, 479 VISUAL_CONFIRM_SURFACE = 1, 480 VISUAL_CONFIRM_HDR = 2, 481 VISUAL_CONFIRM_MPCTREE = 4, 482 VISUAL_CONFIRM_PSR = 5, 483 VISUAL_CONFIRM_SWAPCHAIN = 6, 484 VISUAL_CONFIRM_FAMS = 7, 485 VISUAL_CONFIRM_SWIZZLE = 9, 486 VISUAL_CONFIRM_REPLAY = 12, 487 VISUAL_CONFIRM_SUBVP = 14, 488 VISUAL_CONFIRM_MCLK_SWITCH = 16, 489 VISUAL_CONFIRM_FAMS2 = 19, 490 VISUAL_CONFIRM_HW_CURSOR = 20, 491 }; 492 493 enum dc_psr_power_opts { 494 psr_power_opt_invalid = 0x0, 495 psr_power_opt_smu_opt_static_screen = 0x1, 496 psr_power_opt_z10_static_screen = 0x10, 497 psr_power_opt_ds_disable_allow = 0x100, 498 }; 499 500 enum dml_hostvm_override_opts { 501 DML_HOSTVM_NO_OVERRIDE = 0x0, 502 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 503 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 504 }; 505 506 enum dc_replay_power_opts { 507 replay_power_opt_invalid = 0x0, 508 replay_power_opt_smu_opt_static_screen = 0x1, 509 replay_power_opt_z10_static_screen = 0x10, 510 }; 511 512 enum dcc_option { 513 DCC_ENABLE = 0, 514 DCC_DISABLE = 1, 515 DCC_HALF_REQ_DISALBE = 2, 516 }; 517 518 enum in_game_fams_config { 519 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 520 INGAME_FAMS_DISABLE, // disable in-game fams 521 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 522 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 523 }; 524 525 /** 526 * enum pipe_split_policy - Pipe split strategy supported by DCN 527 * 528 * This enum is used to define the pipe split policy supported by DCN. By 529 * default, DC favors MPC_SPLIT_DYNAMIC. 530 */ 531 enum pipe_split_policy { 532 /** 533 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 534 * pipe in order to bring the best trade-off between performance and 535 * power consumption. This is the recommended option. 536 */ 537 MPC_SPLIT_DYNAMIC = 0, 538 539 /** 540 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 541 * try any sort of split optimization. 542 */ 543 MPC_SPLIT_AVOID = 1, 544 545 /** 546 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 547 * optimize the pipe utilization when using a single display; if the 548 * user connects to a second display, DC will avoid pipe split. 549 */ 550 MPC_SPLIT_AVOID_MULT_DISP = 2, 551 }; 552 553 enum wm_report_mode { 554 WM_REPORT_DEFAULT = 0, 555 WM_REPORT_OVERRIDE = 1, 556 }; 557 enum dtm_pstate{ 558 dtm_level_p0 = 0,/*highest voltage*/ 559 dtm_level_p1, 560 dtm_level_p2, 561 dtm_level_p3, 562 dtm_level_p4,/*when active_display_count = 0*/ 563 }; 564 565 enum dcn_pwr_state { 566 DCN_PWR_STATE_UNKNOWN = -1, 567 DCN_PWR_STATE_MISSION_MODE = 0, 568 DCN_PWR_STATE_LOW_POWER = 3, 569 }; 570 571 enum dcn_zstate_support_state { 572 DCN_ZSTATE_SUPPORT_UNKNOWN, 573 DCN_ZSTATE_SUPPORT_ALLOW, 574 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 575 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 576 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 577 DCN_ZSTATE_SUPPORT_DISALLOW, 578 }; 579 580 /* 581 * struct dc_clocks - DC pipe clocks 582 * 583 * For any clocks that may differ per pipe only the max is stored in this 584 * structure 585 */ 586 struct dc_clocks { 587 int dispclk_khz; 588 int actual_dispclk_khz; 589 int dppclk_khz; 590 int actual_dppclk_khz; 591 int disp_dpp_voltage_level_khz; 592 int dcfclk_khz; 593 int socclk_khz; 594 int dcfclk_deep_sleep_khz; 595 int fclk_khz; 596 int phyclk_khz; 597 int dramclk_khz; 598 bool p_state_change_support; 599 enum dcn_zstate_support_state zstate_support; 600 bool dtbclk_en; 601 int ref_dtbclk_khz; 602 bool fclk_p_state_change_support; 603 enum dcn_pwr_state pwr_state; 604 /* 605 * Elements below are not compared for the purposes of 606 * optimization required 607 */ 608 bool prev_p_state_change_support; 609 bool fclk_prev_p_state_change_support; 610 int num_ways; 611 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 612 613 /* 614 * @fw_based_mclk_switching 615 * 616 * DC has a mechanism that leverage the variable refresh rate to switch 617 * memory clock in cases that we have a large latency to achieve the 618 * memory clock change and a short vblank window. DC has some 619 * requirements to enable this feature, and this field describes if the 620 * system support or not such a feature. 621 */ 622 bool fw_based_mclk_switching; 623 bool fw_based_mclk_switching_shut_down; 624 int prev_num_ways; 625 enum dtm_pstate dtm_level; 626 int max_supported_dppclk_khz; 627 int max_supported_dispclk_khz; 628 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 629 int bw_dispclk_khz; 630 int idle_dramclk_khz; 631 int idle_fclk_khz; 632 int subvp_prefetch_dramclk_khz; 633 int subvp_prefetch_fclk_khz; 634 }; 635 636 struct dc_bw_validation_profile { 637 bool enable; 638 639 unsigned long long total_ticks; 640 unsigned long long voltage_level_ticks; 641 unsigned long long watermark_ticks; 642 unsigned long long rq_dlg_ticks; 643 644 unsigned long long total_count; 645 unsigned long long skip_fast_count; 646 unsigned long long skip_pass_count; 647 unsigned long long skip_fail_count; 648 }; 649 650 #define BW_VAL_TRACE_SETUP() \ 651 unsigned long long end_tick = 0; \ 652 unsigned long long voltage_level_tick = 0; \ 653 unsigned long long watermark_tick = 0; \ 654 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 655 dm_get_timestamp(dc->ctx) : 0 656 657 #define BW_VAL_TRACE_COUNT() \ 658 if (dc->debug.bw_val_profile.enable) \ 659 dc->debug.bw_val_profile.total_count++ 660 661 #define BW_VAL_TRACE_SKIP(status) \ 662 if (dc->debug.bw_val_profile.enable) { \ 663 if (!voltage_level_tick) \ 664 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 665 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 666 } 667 668 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 669 if (dc->debug.bw_val_profile.enable) \ 670 voltage_level_tick = dm_get_timestamp(dc->ctx) 671 672 #define BW_VAL_TRACE_END_WATERMARKS() \ 673 if (dc->debug.bw_val_profile.enable) \ 674 watermark_tick = dm_get_timestamp(dc->ctx) 675 676 #define BW_VAL_TRACE_FINISH() \ 677 if (dc->debug.bw_val_profile.enable) { \ 678 end_tick = dm_get_timestamp(dc->ctx); \ 679 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 680 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 681 if (watermark_tick) { \ 682 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 683 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 684 } \ 685 } 686 687 union mem_low_power_enable_options { 688 struct { 689 bool vga: 1; 690 bool i2c: 1; 691 bool dmcu: 1; 692 bool dscl: 1; 693 bool cm: 1; 694 bool mpc: 1; 695 bool optc: 1; 696 bool vpg: 1; 697 bool afmt: 1; 698 } bits; 699 uint32_t u32All; 700 }; 701 702 union root_clock_optimization_options { 703 struct { 704 bool dpp: 1; 705 bool dsc: 1; 706 bool hdmistream: 1; 707 bool hdmichar: 1; 708 bool dpstream: 1; 709 bool symclk32_se: 1; 710 bool symclk32_le: 1; 711 bool symclk_fe: 1; 712 bool physymclk: 1; 713 bool dpiasymclk: 1; 714 uint32_t reserved: 22; 715 } bits; 716 uint32_t u32All; 717 }; 718 719 union fine_grain_clock_gating_enable_options { 720 struct { 721 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 722 bool dchub : 1; /* Display controller hub */ 723 bool dchubbub : 1; 724 bool dpp : 1; /* Display pipes and planes */ 725 bool opp : 1; /* Output pixel processing */ 726 bool optc : 1; /* Output pipe timing combiner */ 727 bool dio : 1; /* Display output */ 728 bool dwb : 1; /* Display writeback */ 729 bool mmhubbub : 1; /* Multimedia hub */ 730 bool dmu : 1; /* Display core management unit */ 731 bool az : 1; /* Azalia */ 732 bool dchvm : 1; 733 bool dsc : 1; /* Display stream compression */ 734 735 uint32_t reserved : 19; 736 } bits; 737 uint32_t u32All; 738 }; 739 740 enum pg_hw_pipe_resources { 741 PG_HUBP = 0, 742 PG_DPP, 743 PG_DSC, 744 PG_MPCC, 745 PG_OPP, 746 PG_OPTC, 747 PG_DPSTREAM, 748 PG_HDMISTREAM, 749 PG_PHYSYMCLK, 750 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 751 }; 752 753 enum pg_hw_resources { 754 PG_DCCG = 0, 755 PG_DCIO, 756 PG_DIO, 757 PG_DCHUBBUB, 758 PG_DCHVM, 759 PG_DWB, 760 PG_HPO, 761 PG_HW_RESOURCES_NUM_ELEMENT 762 }; 763 764 struct pg_block_update { 765 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 766 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 767 }; 768 769 union dpia_debug_options { 770 struct { 771 uint32_t disable_dpia:1; /* bit 0 */ 772 uint32_t force_non_lttpr:1; /* bit 1 */ 773 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 774 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 775 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 776 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 777 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 778 uint32_t reserved:25; 779 } bits; 780 uint32_t raw; 781 }; 782 783 /* AUX wake work around options 784 * 0: enable/disable work around 785 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 786 * 15-2: reserved 787 * 31-16: timeout in ms 788 */ 789 union aux_wake_wa_options { 790 struct { 791 uint32_t enable_wa : 1; 792 uint32_t use_default_timeout : 1; 793 uint32_t rsvd: 14; 794 uint32_t timeout_ms : 16; 795 } bits; 796 uint32_t raw; 797 }; 798 799 struct dc_debug_data { 800 uint32_t ltFailCount; 801 uint32_t i2cErrorCount; 802 uint32_t auxErrorCount; 803 }; 804 805 struct dc_phy_addr_space_config { 806 struct { 807 uint64_t start_addr; 808 uint64_t end_addr; 809 uint64_t fb_top; 810 uint64_t fb_offset; 811 uint64_t fb_base; 812 uint64_t agp_top; 813 uint64_t agp_bot; 814 uint64_t agp_base; 815 } system_aperture; 816 817 struct { 818 uint64_t page_table_start_addr; 819 uint64_t page_table_end_addr; 820 uint64_t page_table_base_addr; 821 bool base_addr_is_mc_addr; 822 } gart_config; 823 824 bool valid; 825 bool is_hvm_enabled; 826 uint64_t page_table_default_page_addr; 827 }; 828 829 struct dc_virtual_addr_space_config { 830 uint64_t page_table_base_addr; 831 uint64_t page_table_start_addr; 832 uint64_t page_table_end_addr; 833 uint32_t page_table_block_size_in_bytes; 834 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 835 }; 836 837 struct dc_bounding_box_overrides { 838 int sr_exit_time_ns; 839 int sr_enter_plus_exit_time_ns; 840 int sr_exit_z8_time_ns; 841 int sr_enter_plus_exit_z8_time_ns; 842 int urgent_latency_ns; 843 int percent_of_ideal_drambw; 844 int dram_clock_change_latency_ns; 845 int dummy_clock_change_latency_ns; 846 int fclk_clock_change_latency_ns; 847 /* This forces a hard min on the DCFCLK we use 848 * for DML. Unlike the debug option for forcing 849 * DCFCLK, this override affects watermark calculations 850 */ 851 int min_dcfclk_mhz; 852 }; 853 854 struct dc_state; 855 struct resource_pool; 856 struct dce_hwseq; 857 struct link_service; 858 859 /* 860 * struct dc_debug_options - DC debug struct 861 * 862 * This struct provides a simple mechanism for developers to change some 863 * configurations, enable/disable features, and activate extra debug options. 864 * This can be very handy to narrow down whether some specific feature is 865 * causing an issue or not. 866 */ 867 struct dc_debug_options { 868 bool native422_support; 869 bool disable_dsc; 870 enum visual_confirm visual_confirm; 871 int visual_confirm_rect_height; 872 873 bool sanity_checks; 874 bool max_disp_clk; 875 bool surface_trace; 876 bool clock_trace; 877 bool validation_trace; 878 bool bandwidth_calcs_trace; 879 int max_downscale_src_width; 880 881 /* stutter efficiency related */ 882 bool disable_stutter; 883 bool use_max_lb; 884 enum dcc_option disable_dcc; 885 886 /* 887 * @pipe_split_policy: Define which pipe split policy is used by the 888 * display core. 889 */ 890 enum pipe_split_policy pipe_split_policy; 891 bool force_single_disp_pipe_split; 892 bool voltage_align_fclk; 893 bool disable_min_fclk; 894 895 bool disable_dfs_bypass; 896 bool disable_dpp_power_gate; 897 bool disable_hubp_power_gate; 898 bool disable_dsc_power_gate; 899 bool disable_optc_power_gate; 900 bool disable_hpo_power_gate; 901 int dsc_min_slice_height_override; 902 int dsc_bpp_increment_div; 903 bool disable_pplib_wm_range; 904 enum wm_report_mode pplib_wm_report_mode; 905 unsigned int min_disp_clk_khz; 906 unsigned int min_dpp_clk_khz; 907 unsigned int min_dram_clk_khz; 908 int sr_exit_time_dpm0_ns; 909 int sr_enter_plus_exit_time_dpm0_ns; 910 int sr_exit_time_ns; 911 int sr_enter_plus_exit_time_ns; 912 int sr_exit_z8_time_ns; 913 int sr_enter_plus_exit_z8_time_ns; 914 int urgent_latency_ns; 915 uint32_t underflow_assert_delay_us; 916 int percent_of_ideal_drambw; 917 int dram_clock_change_latency_ns; 918 bool optimized_watermark; 919 int always_scale; 920 bool disable_pplib_clock_request; 921 bool disable_clock_gate; 922 bool disable_mem_low_power; 923 bool pstate_enabled; 924 bool disable_dmcu; 925 bool force_abm_enable; 926 bool disable_stereo_support; 927 bool vsr_support; 928 bool performance_trace; 929 bool az_endpoint_mute_only; 930 bool always_use_regamma; 931 bool recovery_enabled; 932 bool avoid_vbios_exec_table; 933 bool scl_reset_length10; 934 bool hdmi20_disable; 935 bool skip_detection_link_training; 936 uint32_t edid_read_retry_times; 937 unsigned int force_odm_combine; //bit vector based on otg inst 938 unsigned int seamless_boot_odm_combine; 939 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 940 int minimum_z8_residency_time; 941 int minimum_z10_residency_time; 942 bool disable_z9_mpc; 943 unsigned int force_fclk_khz; 944 bool enable_tri_buf; 945 bool ips_disallow_entry; 946 bool dmub_offload_enabled; 947 bool dmcub_emulation; 948 bool disable_idle_power_optimizations; 949 unsigned int mall_size_override; 950 unsigned int mall_additional_timer_percent; 951 bool mall_error_as_fatal; 952 bool dmub_command_table; /* for testing only */ 953 struct dc_bw_validation_profile bw_val_profile; 954 bool disable_fec; 955 bool disable_48mhz_pwrdwn; 956 /* This forces a hard min on the DCFCLK requested to SMU/PP 957 * watermarks are not affected. 958 */ 959 unsigned int force_min_dcfclk_mhz; 960 int dwb_fi_phase; 961 bool disable_timing_sync; 962 bool cm_in_bypass; 963 int force_clock_mode;/*every mode change.*/ 964 965 bool disable_dram_clock_change_vactive_support; 966 bool validate_dml_output; 967 bool enable_dmcub_surface_flip; 968 bool usbc_combo_phy_reset_wa; 969 bool enable_dram_clock_change_one_display_vactive; 970 /* TODO - remove once tested */ 971 bool legacy_dp2_lt; 972 bool set_mst_en_for_sst; 973 bool disable_uhbr; 974 bool force_dp2_lt_fallback_method; 975 bool ignore_cable_id; 976 union mem_low_power_enable_options enable_mem_low_power; 977 union root_clock_optimization_options root_clock_optimization; 978 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 979 bool hpo_optimization; 980 bool force_vblank_alignment; 981 982 /* Enable dmub aux for legacy ddc */ 983 bool enable_dmub_aux_for_legacy_ddc; 984 bool disable_fams; 985 enum in_game_fams_config disable_fams_gaming; 986 /* FEC/PSR1 sequence enable delay in 100us */ 987 uint8_t fec_enable_delay_in100us; 988 bool enable_driver_sequence_debug; 989 enum det_size crb_alloc_policy; 990 int crb_alloc_policy_min_disp_count; 991 bool disable_z10; 992 bool enable_z9_disable_interface; 993 bool psr_skip_crtc_disable; 994 uint32_t ips_skip_crtc_disable_mask; 995 union dpia_debug_options dpia_debug; 996 bool disable_fixed_vs_aux_timeout_wa; 997 uint32_t fixed_vs_aux_delay_config_wa; 998 bool force_disable_subvp; 999 bool force_subvp_mclk_switch; 1000 bool allow_sw_cursor_fallback; 1001 unsigned int force_subvp_num_ways; 1002 unsigned int force_mall_ss_num_ways; 1003 bool alloc_extra_way_for_cursor; 1004 uint32_t subvp_extra_lines; 1005 bool force_usr_allow; 1006 /* uses value at boot and disables switch */ 1007 bool disable_dtb_ref_clk_switch; 1008 bool extended_blank_optimization; 1009 union aux_wake_wa_options aux_wake_wa; 1010 uint32_t mst_start_top_delay; 1011 uint8_t psr_power_use_phy_fsm; 1012 enum dml_hostvm_override_opts dml_hostvm_override; 1013 bool dml_disallow_alternate_prefetch_modes; 1014 bool use_legacy_soc_bb_mechanism; 1015 bool exit_idle_opt_for_cursor_updates; 1016 bool using_dml2; 1017 bool enable_single_display_2to1_odm_policy; 1018 bool enable_double_buffered_dsc_pg_support; 1019 bool enable_dp_dig_pixel_rate_div_policy; 1020 bool using_dml21; 1021 enum lttpr_mode lttpr_mode_override; 1022 unsigned int dsc_delay_factor_wa_x1000; 1023 unsigned int min_prefetch_in_strobe_ns; 1024 bool disable_unbounded_requesting; 1025 bool dig_fifo_off_in_blank; 1026 bool override_dispclk_programming; 1027 bool otg_crc_db; 1028 bool disallow_dispclk_dppclk_ds; 1029 bool disable_fpo_optimizations; 1030 bool support_eDP1_5; 1031 uint32_t fpo_vactive_margin_us; 1032 bool disable_fpo_vactive; 1033 bool disable_boot_optimizations; 1034 bool override_odm_optimization; 1035 bool minimize_dispclk_using_odm; 1036 bool disable_subvp_high_refresh; 1037 bool disable_dp_plus_plus_wa; 1038 uint32_t fpo_vactive_min_active_margin_us; 1039 uint32_t fpo_vactive_max_blank_us; 1040 bool enable_hpo_pg_support; 1041 bool enable_legacy_fast_update; 1042 bool disable_dc_mode_overwrite; 1043 bool replay_skip_crtc_disabled; 1044 bool ignore_pg;/*do nothing, let pmfw control it*/ 1045 bool psp_disabled_wa; 1046 unsigned int ips2_eval_delay_us; 1047 unsigned int ips2_entry_delay_us; 1048 bool optimize_ips_handshake; 1049 bool disable_dmub_reallow_idle; 1050 bool disable_timeout; 1051 bool disable_extblankadj; 1052 bool enable_idle_reg_checks; 1053 unsigned int static_screen_wait_frames; 1054 uint32_t pwm_freq; 1055 bool force_chroma_subsampling_1tap; 1056 unsigned int dcc_meta_propagation_delay_us; 1057 bool disable_422_left_edge_pixel; 1058 bool dml21_force_pstate_method; 1059 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1060 uint32_t dml21_disable_pstate_method_mask; 1061 union fw_assisted_mclk_switch_version fams_version; 1062 union dmub_fams2_global_feature_config fams2_config; 1063 bool enable_legacy_clock_update; 1064 unsigned int force_cositing; 1065 unsigned int disable_spl; 1066 unsigned int force_easf; 1067 unsigned int force_sharpness; 1068 unsigned int force_sharpness_level; 1069 unsigned int force_lls; 1070 bool notify_dpia_hr_bw; 1071 bool enable_ips_visual_confirm; 1072 unsigned int sharpen_policy; 1073 unsigned int scale_to_sharpness_policy; 1074 bool skip_full_updated_if_possible; 1075 unsigned int enable_oled_edp_power_up_opt; 1076 bool enable_hblank_borrow; 1077 bool force_subvp_df_throttle; 1078 }; 1079 1080 1081 /* Generic structure that can be used to query properties of DC. More fields 1082 * can be added as required. 1083 */ 1084 struct dc_current_properties { 1085 unsigned int cursor_size_limit; 1086 }; 1087 1088 enum frame_buffer_mode { 1089 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1090 FRAME_BUFFER_MODE_ZFB_ONLY, 1091 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1092 } ; 1093 1094 struct dchub_init_data { 1095 int64_t zfb_phys_addr_base; 1096 int64_t zfb_mc_base_addr; 1097 uint64_t zfb_size_in_byte; 1098 enum frame_buffer_mode fb_mode; 1099 bool dchub_initialzied; 1100 bool dchub_info_valid; 1101 }; 1102 1103 struct dml2_soc_bb; 1104 1105 struct dc_init_data { 1106 struct hw_asic_id asic_id; 1107 void *driver; /* ctx */ 1108 struct cgs_device *cgs_device; 1109 struct dc_bounding_box_overrides bb_overrides; 1110 1111 int num_virtual_links; 1112 /* 1113 * If 'vbios_override' not NULL, it will be called instead 1114 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1115 */ 1116 struct dc_bios *vbios_override; 1117 enum dce_environment dce_environment; 1118 1119 struct dmub_offload_funcs *dmub_if; 1120 struct dc_reg_helper_state *dmub_offload; 1121 1122 struct dc_config flags; 1123 uint64_t log_mask; 1124 1125 struct dpcd_vendor_signature vendor_signature; 1126 bool force_smu_not_present; 1127 /* 1128 * IP offset for run time initializaion of register addresses 1129 * 1130 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1131 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1132 * before them. 1133 */ 1134 uint32_t *dcn_reg_offsets; 1135 uint32_t *nbio_reg_offsets; 1136 uint32_t *clk_reg_offsets; 1137 struct dml2_soc_bb *bb_from_dmub; 1138 }; 1139 1140 struct dc_callback_init { 1141 struct cp_psp cp_psp; 1142 }; 1143 1144 struct dc *dc_create(const struct dc_init_data *init_params); 1145 void dc_hardware_init(struct dc *dc); 1146 1147 int dc_get_vmid_use_vector(struct dc *dc); 1148 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1149 /* Returns the number of vmids supported */ 1150 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1151 void dc_init_callbacks(struct dc *dc, 1152 const struct dc_callback_init *init_params); 1153 void dc_deinit_callbacks(struct dc *dc); 1154 void dc_destroy(struct dc **dc); 1155 1156 /* Surface Interfaces */ 1157 1158 enum { 1159 TRANSFER_FUNC_POINTS = 1025 1160 }; 1161 1162 struct dc_hdr_static_metadata { 1163 /* display chromaticities and white point in units of 0.00001 */ 1164 unsigned int chromaticity_green_x; 1165 unsigned int chromaticity_green_y; 1166 unsigned int chromaticity_blue_x; 1167 unsigned int chromaticity_blue_y; 1168 unsigned int chromaticity_red_x; 1169 unsigned int chromaticity_red_y; 1170 unsigned int chromaticity_white_point_x; 1171 unsigned int chromaticity_white_point_y; 1172 1173 uint32_t min_luminance; 1174 uint32_t max_luminance; 1175 uint32_t maximum_content_light_level; 1176 uint32_t maximum_frame_average_light_level; 1177 }; 1178 1179 enum dc_transfer_func_type { 1180 TF_TYPE_PREDEFINED, 1181 TF_TYPE_DISTRIBUTED_POINTS, 1182 TF_TYPE_BYPASS, 1183 TF_TYPE_HWPWL 1184 }; 1185 1186 struct dc_transfer_func_distributed_points { 1187 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1188 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1189 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1190 1191 uint16_t end_exponent; 1192 uint16_t x_point_at_y1_red; 1193 uint16_t x_point_at_y1_green; 1194 uint16_t x_point_at_y1_blue; 1195 }; 1196 1197 enum dc_transfer_func_predefined { 1198 TRANSFER_FUNCTION_SRGB, 1199 TRANSFER_FUNCTION_BT709, 1200 TRANSFER_FUNCTION_PQ, 1201 TRANSFER_FUNCTION_LINEAR, 1202 TRANSFER_FUNCTION_UNITY, 1203 TRANSFER_FUNCTION_HLG, 1204 TRANSFER_FUNCTION_HLG12, 1205 TRANSFER_FUNCTION_GAMMA22, 1206 TRANSFER_FUNCTION_GAMMA24, 1207 TRANSFER_FUNCTION_GAMMA26 1208 }; 1209 1210 1211 struct dc_transfer_func { 1212 struct kref refcount; 1213 enum dc_transfer_func_type type; 1214 enum dc_transfer_func_predefined tf; 1215 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1216 uint32_t sdr_ref_white_level; 1217 union { 1218 struct pwl_params pwl; 1219 struct dc_transfer_func_distributed_points tf_pts; 1220 }; 1221 }; 1222 1223 1224 union dc_3dlut_state { 1225 struct { 1226 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1227 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1228 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1229 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1230 uint32_t mpc_rmu1_mux:4; 1231 uint32_t mpc_rmu2_mux:4; 1232 uint32_t reserved:15; 1233 } bits; 1234 uint32_t raw; 1235 }; 1236 1237 1238 struct dc_3dlut { 1239 struct kref refcount; 1240 struct tetrahedral_params lut_3d; 1241 struct fixed31_32 hdr_multiplier; 1242 union dc_3dlut_state state; 1243 }; 1244 /* 1245 * This structure is filled in by dc_surface_get_status and contains 1246 * the last requested address and the currently active address so the called 1247 * can determine if there are any outstanding flips 1248 */ 1249 struct dc_plane_status { 1250 struct dc_plane_address requested_address; 1251 struct dc_plane_address current_address; 1252 bool is_flip_pending; 1253 bool is_right_eye; 1254 }; 1255 1256 union surface_update_flags { 1257 1258 struct { 1259 uint32_t addr_update:1; 1260 /* Medium updates */ 1261 uint32_t dcc_change:1; 1262 uint32_t color_space_change:1; 1263 uint32_t horizontal_mirror_change:1; 1264 uint32_t per_pixel_alpha_change:1; 1265 uint32_t global_alpha_change:1; 1266 uint32_t hdr_mult:1; 1267 uint32_t rotation_change:1; 1268 uint32_t swizzle_change:1; 1269 uint32_t scaling_change:1; 1270 uint32_t position_change:1; 1271 uint32_t in_transfer_func_change:1; 1272 uint32_t input_csc_change:1; 1273 uint32_t coeff_reduction_change:1; 1274 uint32_t output_tf_change:1; 1275 uint32_t pixel_format_change:1; 1276 uint32_t plane_size_change:1; 1277 uint32_t gamut_remap_change:1; 1278 1279 /* Full updates */ 1280 uint32_t new_plane:1; 1281 uint32_t bpp_change:1; 1282 uint32_t gamma_change:1; 1283 uint32_t bandwidth_change:1; 1284 uint32_t clock_change:1; 1285 uint32_t stereo_format_change:1; 1286 uint32_t lut_3d:1; 1287 uint32_t tmz_changed:1; 1288 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1289 uint32_t full_update:1; 1290 uint32_t sdr_white_level_nits:1; 1291 } bits; 1292 1293 uint32_t raw; 1294 }; 1295 1296 #define DC_REMOVE_PLANE_POINTERS 1 1297 1298 struct dc_plane_state { 1299 struct dc_plane_address address; 1300 struct dc_plane_flip_time time; 1301 bool triplebuffer_flips; 1302 struct scaling_taps scaling_quality; 1303 struct rect src_rect; 1304 struct rect dst_rect; 1305 struct rect clip_rect; 1306 1307 struct plane_size plane_size; 1308 union dc_tiling_info tiling_info; 1309 1310 struct dc_plane_dcc_param dcc; 1311 1312 struct dc_gamma gamma_correction; 1313 struct dc_transfer_func in_transfer_func; 1314 struct dc_bias_and_scale bias_and_scale; 1315 struct dc_csc_transform input_csc_color_matrix; 1316 struct fixed31_32 coeff_reduction_factor; 1317 struct fixed31_32 hdr_mult; 1318 struct colorspace_transform gamut_remap_matrix; 1319 1320 // TODO: No longer used, remove 1321 struct dc_hdr_static_metadata hdr_static_ctx; 1322 1323 enum dc_color_space color_space; 1324 1325 struct dc_3dlut lut3d_func; 1326 struct dc_transfer_func in_shaper_func; 1327 struct dc_transfer_func blend_tf; 1328 1329 struct dc_transfer_func *gamcor_tf; 1330 enum surface_pixel_format format; 1331 enum dc_rotation_angle rotation; 1332 enum plane_stereo_format stereo_format; 1333 1334 bool is_tiling_rotated; 1335 bool per_pixel_alpha; 1336 bool pre_multiplied_alpha; 1337 bool global_alpha; 1338 int global_alpha_value; 1339 bool visible; 1340 bool flip_immediate; 1341 bool horizontal_mirror; 1342 int layer_index; 1343 1344 union surface_update_flags update_flags; 1345 bool flip_int_enabled; 1346 bool skip_manual_trigger; 1347 1348 /* private to DC core */ 1349 struct dc_plane_status status; 1350 struct dc_context *ctx; 1351 1352 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1353 bool force_full_update; 1354 1355 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1356 1357 /* private to dc_surface.c */ 1358 enum dc_irq_source irq_source; 1359 struct kref refcount; 1360 struct tg_color visual_confirm_color; 1361 1362 bool is_statically_allocated; 1363 enum chroma_cositing cositing; 1364 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1365 bool mcm_lut1d_enable; 1366 struct dc_cm2_func_luts mcm_luts; 1367 bool lut_bank_a; 1368 enum mpcc_movable_cm_location mcm_location; 1369 struct dc_csc_transform cursor_csc_color_matrix; 1370 bool adaptive_sharpness_en; 1371 int adaptive_sharpness_policy; 1372 int sharpness_level; 1373 enum linear_light_scaling linear_light_scaling; 1374 unsigned int sdr_white_level_nits; 1375 }; 1376 1377 struct dc_plane_info { 1378 struct plane_size plane_size; 1379 union dc_tiling_info tiling_info; 1380 struct dc_plane_dcc_param dcc; 1381 enum surface_pixel_format format; 1382 enum dc_rotation_angle rotation; 1383 enum plane_stereo_format stereo_format; 1384 enum dc_color_space color_space; 1385 bool horizontal_mirror; 1386 bool visible; 1387 bool per_pixel_alpha; 1388 bool pre_multiplied_alpha; 1389 bool global_alpha; 1390 int global_alpha_value; 1391 bool input_csc_enabled; 1392 int layer_index; 1393 enum chroma_cositing cositing; 1394 }; 1395 1396 #include "dc_stream.h" 1397 1398 struct dc_scratch_space { 1399 /* used to temporarily backup plane states of a stream during 1400 * dc update. The reason is that plane states are overwritten 1401 * with surface updates in dc update. Once they are overwritten 1402 * current state is no longer valid. We want to temporarily 1403 * store current value in plane states so we can still recover 1404 * a valid current state during dc update. 1405 */ 1406 struct dc_plane_state plane_states[MAX_SURFACE_NUM]; 1407 1408 struct dc_stream_state stream_state; 1409 }; 1410 1411 struct dc { 1412 struct dc_debug_options debug; 1413 struct dc_versions versions; 1414 struct dc_caps caps; 1415 struct dc_cap_funcs cap_funcs; 1416 struct dc_config config; 1417 struct dc_bounding_box_overrides bb_overrides; 1418 struct dc_bug_wa work_arounds; 1419 struct dc_context *ctx; 1420 struct dc_phy_addr_space_config vm_pa_config; 1421 1422 uint8_t link_count; 1423 struct dc_link *links[MAX_LINKS]; 1424 struct link_service *link_srv; 1425 1426 struct dc_state *current_state; 1427 struct resource_pool *res_pool; 1428 1429 struct clk_mgr *clk_mgr; 1430 1431 /* Display Engine Clock levels */ 1432 struct dm_pp_clock_levels sclk_lvls; 1433 1434 /* Inputs into BW and WM calculations. */ 1435 struct bw_calcs_dceip *bw_dceip; 1436 struct bw_calcs_vbios *bw_vbios; 1437 struct dcn_soc_bounding_box *dcn_soc; 1438 struct dcn_ip_params *dcn_ip; 1439 struct display_mode_lib dml; 1440 1441 /* HW functions */ 1442 struct hw_sequencer_funcs hwss; 1443 struct dce_hwseq *hwseq; 1444 1445 /* Require to optimize clocks and bandwidth for added/removed planes */ 1446 bool optimized_required; 1447 bool wm_optimized_required; 1448 bool idle_optimizations_allowed; 1449 bool enable_c20_dtm_b0; 1450 1451 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1452 1453 /* FBC compressor */ 1454 struct compressor *fbc_compressor; 1455 1456 struct dc_debug_data debug_data; 1457 struct dpcd_vendor_signature vendor_signature; 1458 1459 const char *build_id; 1460 struct vm_helper *vm_helper; 1461 1462 uint32_t *dcn_reg_offsets; 1463 uint32_t *nbio_reg_offsets; 1464 uint32_t *clk_reg_offsets; 1465 1466 /* Scratch memory */ 1467 struct { 1468 struct { 1469 /* 1470 * For matching clock_limits table in driver with table 1471 * from PMFW. 1472 */ 1473 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1474 } update_bw_bounding_box; 1475 struct dc_scratch_space current_state; 1476 struct dc_scratch_space new_state; 1477 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1478 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1479 } scratch; 1480 1481 struct dml2_configuration_options dml2_options; 1482 struct dml2_configuration_options dml2_tmp; 1483 enum dc_acpi_cm_power_state power_state; 1484 1485 }; 1486 1487 struct dc_scaling_info { 1488 struct rect src_rect; 1489 struct rect dst_rect; 1490 struct rect clip_rect; 1491 struct scaling_taps scaling_quality; 1492 }; 1493 1494 struct dc_fast_update { 1495 const struct dc_flip_addrs *flip_addr; 1496 const struct dc_gamma *gamma; 1497 const struct colorspace_transform *gamut_remap_matrix; 1498 const struct dc_csc_transform *input_csc_color_matrix; 1499 const struct fixed31_32 *coeff_reduction_factor; 1500 struct dc_transfer_func *out_transfer_func; 1501 struct dc_csc_transform *output_csc_transform; 1502 const struct dc_csc_transform *cursor_csc_color_matrix; 1503 }; 1504 1505 struct dc_surface_update { 1506 struct dc_plane_state *surface; 1507 1508 /* isr safe update parameters. null means no updates */ 1509 const struct dc_flip_addrs *flip_addr; 1510 const struct dc_plane_info *plane_info; 1511 const struct dc_scaling_info *scaling_info; 1512 struct fixed31_32 hdr_mult; 1513 /* following updates require alloc/sleep/spin that is not isr safe, 1514 * null means no updates 1515 */ 1516 const struct dc_gamma *gamma; 1517 const struct dc_transfer_func *in_transfer_func; 1518 1519 const struct dc_csc_transform *input_csc_color_matrix; 1520 const struct fixed31_32 *coeff_reduction_factor; 1521 const struct dc_transfer_func *func_shaper; 1522 const struct dc_3dlut *lut3d_func; 1523 const struct dc_transfer_func *blend_tf; 1524 const struct colorspace_transform *gamut_remap_matrix; 1525 /* 1526 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1527 * 1528 * change cm2_params.component_settings: Full update 1529 * change cm2_params.cm2_luts: Fast update 1530 */ 1531 const struct dc_cm2_parameters *cm2_params; 1532 const struct dc_csc_transform *cursor_csc_color_matrix; 1533 unsigned int sdr_white_level_nits; 1534 struct dc_bias_and_scale bias_and_scale; 1535 }; 1536 1537 /* 1538 * Create a new surface with default parameters; 1539 */ 1540 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1541 void dc_gamma_release(struct dc_gamma **dc_gamma); 1542 struct dc_gamma *dc_create_gamma(void); 1543 1544 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1545 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1546 struct dc_transfer_func *dc_create_transfer_func(void); 1547 1548 struct dc_3dlut *dc_create_3dlut_func(void); 1549 void dc_3dlut_func_release(struct dc_3dlut *lut); 1550 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1551 1552 void dc_post_update_surfaces_to_stream( 1553 struct dc *dc); 1554 1555 #include "dc_stream.h" 1556 1557 /** 1558 * struct dc_validation_set - Struct to store surface/stream associations for validation 1559 */ 1560 struct dc_validation_set { 1561 /** 1562 * @stream: Stream state properties 1563 */ 1564 struct dc_stream_state *stream; 1565 1566 /** 1567 * @plane_states: Surface state 1568 */ 1569 struct dc_plane_state *plane_states[MAX_SURFACES]; 1570 1571 /** 1572 * @plane_count: Total of active planes 1573 */ 1574 uint8_t plane_count; 1575 }; 1576 1577 bool dc_validate_boot_timing(const struct dc *dc, 1578 const struct dc_sink *sink, 1579 struct dc_crtc_timing *crtc_timing); 1580 1581 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1582 1583 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1584 1585 enum dc_status dc_validate_with_context(struct dc *dc, 1586 const struct dc_validation_set set[], 1587 int set_count, 1588 struct dc_state *context, 1589 bool fast_validate); 1590 1591 bool dc_set_generic_gpio_for_stereo(bool enable, 1592 struct gpio_service *gpio_service); 1593 1594 /* 1595 * fast_validate: we return after determining if we can support the new state, 1596 * but before we populate the programming info 1597 */ 1598 enum dc_status dc_validate_global_state( 1599 struct dc *dc, 1600 struct dc_state *new_ctx, 1601 bool fast_validate); 1602 1603 bool dc_acquire_release_mpc_3dlut( 1604 struct dc *dc, bool acquire, 1605 struct dc_stream_state *stream, 1606 struct dc_3dlut **lut, 1607 struct dc_transfer_func **shaper); 1608 1609 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1610 void get_audio_check(struct audio_info *aud_modes, 1611 struct audio_check *aud_chk); 1612 1613 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1614 void populate_fast_updates(struct dc_fast_update *fast_update, 1615 struct dc_surface_update *srf_updates, 1616 int surface_count, 1617 struct dc_stream_update *stream_update); 1618 /* 1619 * Set up streams and links associated to drive sinks 1620 * The streams parameter is an absolute set of all active streams. 1621 * 1622 * After this call: 1623 * Phy, Encoder, Timing Generator are programmed and enabled. 1624 * New streams are enabled with blank stream; no memory read. 1625 */ 1626 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1627 1628 1629 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1630 struct dc_stream_state *stream, 1631 int mpcc_inst); 1632 1633 1634 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1635 1636 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1637 1638 /* The function returns minimum bandwidth required to drive a given timing 1639 * return - minimum required timing bandwidth in kbps. 1640 */ 1641 uint32_t dc_bandwidth_in_kbps_from_timing( 1642 const struct dc_crtc_timing *timing, 1643 const enum dc_link_encoding_format link_encoding); 1644 1645 /* Link Interfaces */ 1646 /* 1647 * A link contains one or more sinks and their connected status. 1648 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1649 */ 1650 struct dc_link { 1651 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1652 unsigned int sink_count; 1653 struct dc_sink *local_sink; 1654 unsigned int link_index; 1655 enum dc_connection_type type; 1656 enum signal_type connector_signal; 1657 enum dc_irq_source irq_source_hpd; 1658 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1659 1660 bool is_hpd_filter_disabled; 1661 bool dp_ss_off; 1662 1663 /** 1664 * @link_state_valid: 1665 * 1666 * If there is no link and local sink, this variable should be set to 1667 * false. Otherwise, it should be set to true; usually, the function 1668 * core_link_enable_stream sets this field to true. 1669 */ 1670 bool link_state_valid; 1671 bool aux_access_disabled; 1672 bool sync_lt_in_progress; 1673 bool skip_stream_reenable; 1674 bool is_internal_display; 1675 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1676 bool is_dig_mapping_flexible; 1677 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1678 bool is_hpd_pending; /* Indicates a new received hpd */ 1679 1680 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1681 * for every link training. This is incompatible with DP LL compliance automation, 1682 * which expects the same link settings to be used every retry on a link loss. 1683 * This flag is used to skip the fallback when link loss occurs during automation. 1684 */ 1685 bool skip_fallback_on_link_loss; 1686 1687 bool edp_sink_present; 1688 1689 struct dp_trace dp_trace; 1690 1691 /* caps is the same as reported_link_cap. link_traing use 1692 * reported_link_cap. Will clean up. TODO 1693 */ 1694 struct dc_link_settings reported_link_cap; 1695 struct dc_link_settings verified_link_cap; 1696 struct dc_link_settings cur_link_settings; 1697 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1698 struct dc_link_settings preferred_link_setting; 1699 /* preferred_training_settings are override values that 1700 * come from DM. DM is responsible for the memory 1701 * management of the override pointers. 1702 */ 1703 struct dc_link_training_overrides preferred_training_settings; 1704 struct dp_audio_test_data audio_test_data; 1705 1706 uint8_t ddc_hw_inst; 1707 1708 uint8_t hpd_src; 1709 1710 uint8_t link_enc_hw_inst; 1711 /* DIG link encoder ID. Used as index in link encoder resource pool. 1712 * For links with fixed mapping to DIG, this is not changed after dc_link 1713 * object creation. 1714 */ 1715 enum engine_id eng_id; 1716 enum engine_id dpia_preferred_eng_id; 1717 1718 bool test_pattern_enabled; 1719 /* Pending/Current test pattern are only used to perform and track 1720 * FIXED_VS retimer test pattern/lane adjustment override state. 1721 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1722 * to perform specific lane adjust overrides before setting certain 1723 * PHY test patterns. In cases when lane adjust and set test pattern 1724 * calls are not performed atomically (i.e. performing link training), 1725 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1726 * and current_test_pattern will contain required context for any future 1727 * set pattern/set lane adjust to transition between override state(s). 1728 * */ 1729 enum dp_test_pattern current_test_pattern; 1730 enum dp_test_pattern pending_test_pattern; 1731 1732 union compliance_test_state compliance_test_state; 1733 1734 void *priv; 1735 1736 struct ddc_service *ddc; 1737 1738 enum dp_panel_mode panel_mode; 1739 bool aux_mode; 1740 1741 /* Private to DC core */ 1742 1743 const struct dc *dc; 1744 1745 struct dc_context *ctx; 1746 1747 struct panel_cntl *panel_cntl; 1748 struct link_encoder *link_enc; 1749 struct graphics_object_id link_id; 1750 /* Endpoint type distinguishes display endpoints which do not have entries 1751 * in the BIOS connector table from those that do. Helps when tracking link 1752 * encoder to display endpoint assignments. 1753 */ 1754 enum display_endpoint_type ep_type; 1755 union ddi_channel_mapping ddi_channel_mapping; 1756 struct connector_device_tag_info device_tag; 1757 struct dpcd_caps dpcd_caps; 1758 uint32_t dongle_max_pix_clk; 1759 unsigned short chip_caps; 1760 unsigned int dpcd_sink_count; 1761 struct hdcp_caps hdcp_caps; 1762 enum edp_revision edp_revision; 1763 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1764 1765 struct psr_settings psr_settings; 1766 struct replay_settings replay_settings; 1767 1768 /* Drive settings read from integrated info table */ 1769 struct dc_lane_settings bios_forced_drive_settings; 1770 1771 /* Vendor specific LTTPR workaround variables */ 1772 uint8_t vendor_specific_lttpr_link_rate_wa; 1773 bool apply_vendor_specific_lttpr_link_rate_wa; 1774 1775 /* MST record stream using this link */ 1776 struct link_flags { 1777 bool dp_keep_receiver_powered; 1778 bool dp_skip_DID2; 1779 bool dp_skip_reset_segment; 1780 bool dp_skip_fs_144hz; 1781 bool dp_mot_reset_segment; 1782 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1783 bool dpia_mst_dsc_always_on; 1784 /* Forced DPIA into TBT3 compatibility mode. */ 1785 bool dpia_forced_tbt3_mode; 1786 bool dongle_mode_timing_override; 1787 bool blank_stream_on_ocs_change; 1788 bool read_dpcd204h_on_irq_hpd; 1789 } wa_flags; 1790 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1791 1792 struct dc_link_status link_status; 1793 struct dprx_states dprx_states; 1794 1795 struct gpio *hpd_gpio; 1796 enum dc_link_fec_state fec_state; 1797 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1798 1799 struct dc_panel_config panel_config; 1800 struct phy_state phy_state; 1801 // BW ALLOCATON USB4 ONLY 1802 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1803 bool skip_implict_edp_power_control; 1804 enum backlight_control_type backlight_control_type; 1805 }; 1806 1807 /* Return an enumerated dc_link. 1808 * dc_link order is constant and determined at 1809 * boot time. They cannot be created or destroyed. 1810 * Use dc_get_caps() to get number of links. 1811 */ 1812 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1813 1814 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1815 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1816 const struct dc_link *link, 1817 unsigned int *inst_out); 1818 1819 /* Return an array of link pointers to edp links. */ 1820 void dc_get_edp_links(const struct dc *dc, 1821 struct dc_link **edp_links, 1822 int *edp_num); 1823 1824 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1825 bool powerOn); 1826 1827 /* The function initiates detection handshake over the given link. It first 1828 * determines if there are display connections over the link. If so it initiates 1829 * detection protocols supported by the connected receiver device. The function 1830 * contains protocol specific handshake sequences which are sometimes mandatory 1831 * to establish a proper connection between TX and RX. So it is always 1832 * recommended to call this function as the first link operation upon HPD event 1833 * or power up event. Upon completion, the function will update link structure 1834 * in place based on latest RX capabilities. The function may also cause dpms 1835 * to be reset to off for all currently enabled streams to the link. It is DM's 1836 * responsibility to serialize detection and DPMS updates. 1837 * 1838 * @reason - Indicate which event triggers this detection. dc may customize 1839 * detection flow depending on the triggering events. 1840 * return false - if detection is not fully completed. This could happen when 1841 * there is an unrecoverable error during detection or detection is partially 1842 * completed (detection has been delegated to dm mst manager ie. 1843 * link->connection_type == dc_connection_mst_branch when returning false). 1844 * return true - detection is completed, link has been fully updated with latest 1845 * detection result. 1846 */ 1847 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1848 1849 struct dc_sink_init_data; 1850 1851 /* When link connection type is dc_connection_mst_branch, remote sink can be 1852 * added to the link. The interface creates a remote sink and associates it with 1853 * current link. The sink will be retained by link until remove remote sink is 1854 * called. 1855 * 1856 * @dc_link - link the remote sink will be added to. 1857 * @edid - byte array of EDID raw data. 1858 * @len - size of the edid in byte 1859 * @init_data - 1860 */ 1861 struct dc_sink *dc_link_add_remote_sink( 1862 struct dc_link *dc_link, 1863 const uint8_t *edid, 1864 int len, 1865 struct dc_sink_init_data *init_data); 1866 1867 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1868 * @link - link the sink should be removed from 1869 * @sink - sink to be removed. 1870 */ 1871 void dc_link_remove_remote_sink( 1872 struct dc_link *link, 1873 struct dc_sink *sink); 1874 1875 /* Enable HPD interrupt handler for a given link */ 1876 void dc_link_enable_hpd(const struct dc_link *link); 1877 1878 /* Disable HPD interrupt handler for a given link */ 1879 void dc_link_disable_hpd(const struct dc_link *link); 1880 1881 /* determine if there is a sink connected to the link 1882 * 1883 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1884 * return - false if an unexpected error occurs, true otherwise. 1885 * 1886 * NOTE: This function doesn't detect downstream sink connections i.e 1887 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1888 * return dc_connection_single if the branch device is connected despite of 1889 * downstream sink's connection status. 1890 */ 1891 bool dc_link_detect_connection_type(struct dc_link *link, 1892 enum dc_connection_type *type); 1893 1894 /* query current hpd pin value 1895 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1896 * 1897 */ 1898 bool dc_link_get_hpd_state(struct dc_link *link); 1899 1900 /* Getter for cached link status from given link */ 1901 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1902 1903 /* enable/disable hardware HPD filter. 1904 * 1905 * @link - The link the HPD pin is associated with. 1906 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1907 * handler once after no HPD change has been detected within dc default HPD 1908 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1909 * pulses within default HPD interval, no HPD event will be received until HPD 1910 * toggles have stopped. Then HPD event will be queued to irq handler once after 1911 * dc default HPD filtering interval since last HPD event. 1912 * 1913 * @enable = false - disable hardware HPD filter. HPD event will be queued 1914 * immediately to irq handler after no HPD change has been detected within 1915 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1916 */ 1917 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1918 1919 /* submit i2c read/write payloads through ddc channel 1920 * @link_index - index to a link with ddc in i2c mode 1921 * @cmd - i2c command structure 1922 * return - true if success, false otherwise. 1923 */ 1924 bool dc_submit_i2c( 1925 struct dc *dc, 1926 uint32_t link_index, 1927 struct i2c_command *cmd); 1928 1929 /* submit i2c read/write payloads through oem channel 1930 * @link_index - index to a link with ddc in i2c mode 1931 * @cmd - i2c command structure 1932 * return - true if success, false otherwise. 1933 */ 1934 bool dc_submit_i2c_oem( 1935 struct dc *dc, 1936 struct i2c_command *cmd); 1937 1938 enum aux_return_code_type; 1939 /* Attempt to transfer the given aux payload. This function does not perform 1940 * retries or handle error states. The reply is returned in the payload->reply 1941 * and the result through operation_result. Returns the number of bytes 1942 * transferred,or -1 on a failure. 1943 */ 1944 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1945 struct aux_payload *payload, 1946 enum aux_return_code_type *operation_result); 1947 1948 bool dc_is_oem_i2c_device_present( 1949 struct dc *dc, 1950 size_t slave_address 1951 ); 1952 1953 /* return true if the connected receiver supports the hdcp version */ 1954 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1955 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1956 1957 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1958 * 1959 * TODO - When defer_handling is true the function will have a different purpose. 1960 * It no longer does complete hpd rx irq handling. We should create a separate 1961 * interface specifically for this case. 1962 * 1963 * Return: 1964 * true - Downstream port status changed. DM should call DC to do the 1965 * detection. 1966 * false - no change in Downstream port status. No further action required 1967 * from DM. 1968 */ 1969 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1970 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1971 bool defer_handling, bool *has_left_work); 1972 /* handle DP specs define test automation sequence*/ 1973 void dc_link_dp_handle_automated_test(struct dc_link *link); 1974 1975 /* handle DP Link loss sequence and try to recover RX link loss with best 1976 * effort 1977 */ 1978 void dc_link_dp_handle_link_loss(struct dc_link *link); 1979 1980 /* Determine if hpd rx irq should be handled or ignored 1981 * return true - hpd rx irq should be handled. 1982 * return false - it is safe to ignore hpd rx irq event 1983 */ 1984 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1985 1986 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1987 * @link - link the hpd irq data associated with 1988 * @hpd_irq_dpcd_data - input hpd irq data 1989 * return - true if hpd irq data indicates a link lost 1990 */ 1991 bool dc_link_check_link_loss_status(struct dc_link *link, 1992 union hpd_irq_data *hpd_irq_dpcd_data); 1993 1994 /* Read hpd rx irq data from a given link 1995 * @link - link where the hpd irq data should be read from 1996 * @irq_data - output hpd irq data 1997 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1998 * read has failed. 1999 */ 2000 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2001 struct dc_link *link, 2002 union hpd_irq_data *irq_data); 2003 2004 /* The function clears recorded DP RX states in the link. DM should call this 2005 * function when it is resuming from S3 power state to previously connected links. 2006 * 2007 * TODO - in the future we should consider to expand link resume interface to 2008 * support clearing previous rx states. So we don't have to rely on dm to call 2009 * this interface explicitly. 2010 */ 2011 void dc_link_clear_dprx_states(struct dc_link *link); 2012 2013 /* Destruct the mst topology of the link and reset the allocated payload table 2014 * 2015 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2016 * still wants to reset MST topology on an unplug event */ 2017 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2018 2019 /* The function calculates effective DP link bandwidth when a given link is 2020 * using the given link settings. 2021 * 2022 * return - total effective link bandwidth in kbps. 2023 */ 2024 uint32_t dc_link_bandwidth_kbps( 2025 const struct dc_link *link, 2026 const struct dc_link_settings *link_setting); 2027 2028 /* The function takes a snapshot of current link resource allocation state 2029 * @dc: pointer to dc of the dm calling this 2030 * @map: a dc link resource snapshot defined internally to dc. 2031 * 2032 * DM needs to capture a snapshot of current link resource allocation mapping 2033 * and store it in its persistent storage. 2034 * 2035 * Some of the link resource is using first come first serve policy. 2036 * The allocation mapping depends on original hotplug order. This information 2037 * is lost after driver is loaded next time. The snapshot is used in order to 2038 * restore link resource to its previous state so user will get consistent 2039 * link capability allocation across reboot. 2040 * 2041 */ 2042 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2043 2044 /* This function restores link resource allocation state from a snapshot 2045 * @dc: pointer to dc of the dm calling this 2046 * @map: a dc link resource snapshot defined internally to dc. 2047 * 2048 * DM needs to call this function after initial link detection on boot and 2049 * before first commit streams to restore link resource allocation state 2050 * from previous boot session. 2051 * 2052 * Some of the link resource is using first come first serve policy. 2053 * The allocation mapping depends on original hotplug order. This information 2054 * is lost after driver is loaded next time. The snapshot is used in order to 2055 * restore link resource to its previous state so user will get consistent 2056 * link capability allocation across reboot. 2057 * 2058 */ 2059 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2060 2061 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2062 * interface i.e stream_update->dsc_config 2063 */ 2064 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2065 2066 /* translate a raw link rate data to bandwidth in kbps */ 2067 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2068 2069 /* determine the optimal bandwidth given link and required bw. 2070 * @link - current detected link 2071 * @req_bw - requested bandwidth in kbps 2072 * @link_settings - returned most optimal link settings that can fit the 2073 * requested bandwidth 2074 * return - false if link can't support requested bandwidth, true if link 2075 * settings is found. 2076 */ 2077 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2078 struct dc_link_settings *link_settings, 2079 uint32_t req_bw); 2080 2081 /* return the max dp link settings can be driven by the link without considering 2082 * connected RX device and its capability 2083 */ 2084 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2085 struct dc_link_settings *max_link_enc_cap); 2086 2087 /* determine when the link is driving MST mode, what DP link channel coding 2088 * format will be used. The decision will remain unchanged until next HPD event. 2089 * 2090 * @link - a link with DP RX connection 2091 * return - if stream is committed to this link with MST signal type, type of 2092 * channel coding format dc will choose. 2093 */ 2094 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2095 const struct dc_link *link); 2096 2097 /* get max dp link settings the link can enable with all things considered. (i.e 2098 * TX/RX/Cable capabilities and dp override policies. 2099 * 2100 * @link - a link with DP RX connection 2101 * return - max dp link settings the link can enable. 2102 * 2103 */ 2104 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2105 2106 /* Get the highest encoding format that the link supports; highest meaning the 2107 * encoding format which supports the maximum bandwidth. 2108 * 2109 * @link - a link with DP RX connection 2110 * return - highest encoding format link supports. 2111 */ 2112 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2113 2114 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2115 * to a link with dp connector signal type. 2116 * @link - a link with dp connector signal type 2117 * return - true if connected, false otherwise 2118 */ 2119 bool dc_link_is_dp_sink_present(struct dc_link *link); 2120 2121 /* Force DP lane settings update to main-link video signal and notify the change 2122 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2123 * tuning purpose. The interface assumes link has already been enabled with DP 2124 * signal. 2125 * 2126 * @lt_settings - a container structure with desired hw_lane_settings 2127 */ 2128 void dc_link_set_drive_settings(struct dc *dc, 2129 struct link_training_settings *lt_settings, 2130 struct dc_link *link); 2131 2132 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2133 * test or debugging purpose. The test pattern will remain until next un-plug. 2134 * 2135 * @link - active link with DP signal output enabled. 2136 * @test_pattern - desired test pattern to output. 2137 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2138 * @test_pattern_color_space - for video test pattern choose a desired color 2139 * space. 2140 * @p_link_settings - For PHY pattern choose a desired link settings 2141 * @p_custom_pattern - some test pattern will require a custom input to 2142 * customize some pattern details. Otherwise keep it to NULL. 2143 * @cust_pattern_size - size of the custom pattern input. 2144 * 2145 */ 2146 bool dc_link_dp_set_test_pattern( 2147 struct dc_link *link, 2148 enum dp_test_pattern test_pattern, 2149 enum dp_test_pattern_color_space test_pattern_color_space, 2150 const struct link_training_settings *p_link_settings, 2151 const unsigned char *p_custom_pattern, 2152 unsigned int cust_pattern_size); 2153 2154 /* Force DP link settings to always use a specific value until reboot to a 2155 * specific link. If link has already been enabled, the interface will also 2156 * switch to desired link settings immediately. This is a debug interface to 2157 * generic dp issue trouble shooting. 2158 */ 2159 void dc_link_set_preferred_link_settings(struct dc *dc, 2160 struct dc_link_settings *link_setting, 2161 struct dc_link *link); 2162 2163 /* Force DP link to customize a specific link training behavior by overriding to 2164 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2165 * display specific link training issues or apply some display specific 2166 * workaround in link training. 2167 * 2168 * @link_settings - if not NULL, force preferred link settings to the link. 2169 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2170 * will apply this particular override in future link training. If NULL is 2171 * passed in, dc resets previous overrides. 2172 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2173 * training settings. 2174 */ 2175 void dc_link_set_preferred_training_settings(struct dc *dc, 2176 struct dc_link_settings *link_setting, 2177 struct dc_link_training_overrides *lt_overrides, 2178 struct dc_link *link, 2179 bool skip_immediate_retrain); 2180 2181 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2182 bool dc_link_is_fec_supported(const struct dc_link *link); 2183 2184 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2185 * link enablement. 2186 * return - true if FEC should be enabled, false otherwise. 2187 */ 2188 bool dc_link_should_enable_fec(const struct dc_link *link); 2189 2190 /* determine lttpr mode the current link should be enabled with a specific link 2191 * settings. 2192 */ 2193 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2194 struct dc_link_settings *link_setting); 2195 2196 /* Force DP RX to update its power state. 2197 * NOTE: this interface doesn't update dp main-link. Calling this function will 2198 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2199 * RX power state back upon finish DM specific execution requiring DP RX in a 2200 * specific power state. 2201 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2202 * state. 2203 */ 2204 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2205 2206 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2207 * current value read from extended receiver cap from 02200h - 0220Fh. 2208 * Some DP RX has problems of providing accurate DP receiver caps from extended 2209 * field, this interface is a workaround to revert link back to use base caps. 2210 */ 2211 void dc_link_overwrite_extended_receiver_cap( 2212 struct dc_link *link); 2213 2214 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2215 bool wait_for_hpd); 2216 2217 /* Set backlight level of an embedded panel (eDP, LVDS). 2218 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2219 * and 16 bit fractional, where 1.0 is max backlight value. 2220 */ 2221 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2222 struct set_backlight_level_params *backlight_level_params); 2223 2224 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2225 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2226 bool isHDR, 2227 uint32_t backlight_millinits, 2228 uint32_t transition_time_in_ms); 2229 2230 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2231 uint32_t *backlight_millinits, 2232 uint32_t *backlight_millinits_peak); 2233 2234 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2235 2236 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2237 2238 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2239 bool wait, bool force_static, const unsigned int *power_opts); 2240 2241 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2242 2243 bool dc_link_setup_psr(struct dc_link *dc_link, 2244 const struct dc_stream_state *stream, struct psr_config *psr_config, 2245 struct psr_context *psr_context); 2246 2247 /* 2248 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2249 * 2250 * @link: pointer to the dc_link struct instance 2251 * @enable: enable(active) or disable(inactive) replay 2252 * @wait: state transition need to wait the active set completed. 2253 * @force_static: force disable(inactive) the replay 2254 * @power_opts: set power optimazation parameters to DMUB. 2255 * 2256 * return: allow Replay active will return true, else will return false. 2257 */ 2258 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2259 bool wait, bool force_static, const unsigned int *power_opts); 2260 2261 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2262 2263 /* On eDP links this function call will stall until T12 has elapsed. 2264 * If the panel is not in power off state, this function will return 2265 * immediately. 2266 */ 2267 bool dc_link_wait_for_t12(struct dc_link *link); 2268 2269 /* Determine if dp trace has been initialized to reflect upto date result * 2270 * return - true if trace is initialized and has valid data. False dp trace 2271 * doesn't have valid result. 2272 */ 2273 bool dc_dp_trace_is_initialized(struct dc_link *link); 2274 2275 /* Query a dp trace flag to indicate if the current dp trace data has been 2276 * logged before 2277 */ 2278 bool dc_dp_trace_is_logged(struct dc_link *link, 2279 bool in_detection); 2280 2281 /* Set dp trace flag to indicate whether DM has already logged the current dp 2282 * trace data. DM can set is_logged to true upon logging and check 2283 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2284 */ 2285 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2286 bool in_detection, 2287 bool is_logged); 2288 2289 /* Obtain driver time stamp for last dp link training end. The time stamp is 2290 * formatted based on dm_get_timestamp DM function. 2291 * @in_detection - true to get link training end time stamp of last link 2292 * training in detection sequence. false to get link training end time stamp 2293 * of last link training in commit (dpms) sequence 2294 */ 2295 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2296 bool in_detection); 2297 2298 /* Get how many link training attempts dc has done with latest sequence. 2299 * @in_detection - true to get link training count of last link 2300 * training in detection sequence. false to get link training count of last link 2301 * training in commit (dpms) sequence 2302 */ 2303 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2304 bool in_detection); 2305 2306 /* Get how many link loss has happened since last link training attempts */ 2307 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2308 2309 /* 2310 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2311 */ 2312 /* 2313 * Send a request from DP-Tx requesting to allocate BW remotely after 2314 * allocating it locally. This will get processed by CM and a CB function 2315 * will be called. 2316 * 2317 * @link: pointer to the dc_link struct instance 2318 * @req_bw: The requested bw in Kbyte to allocated 2319 * 2320 * return: none 2321 */ 2322 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2323 2324 /* 2325 * Handle function for when the status of the Request above is complete. 2326 * We will find out the result of allocating on CM and update structs. 2327 * 2328 * @link: pointer to the dc_link struct instance 2329 * @bw: Allocated or Estimated BW depending on the result 2330 * @result: Response type 2331 * 2332 * return: none 2333 */ 2334 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2335 uint8_t bw, uint8_t result); 2336 2337 /* 2338 * Handle the USB4 BW Allocation related functionality here: 2339 * Plug => Try to allocate max bw from timing parameters supported by the sink 2340 * Unplug => de-allocate bw 2341 * 2342 * @link: pointer to the dc_link struct instance 2343 * @peak_bw: Peak bw used by the link/sink 2344 * 2345 * return: allocated bw else return 0 2346 */ 2347 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2348 struct dc_link *link, int peak_bw); 2349 2350 /* 2351 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2352 * available BW for each host router 2353 * 2354 * @dc: pointer to dc struct 2355 * @stream: pointer to all possible streams 2356 * @count: number of valid DPIA streams 2357 * 2358 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2359 */ 2360 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2361 const unsigned int count); 2362 2363 /* Sink Interfaces - A sink corresponds to a display output device */ 2364 2365 struct dc_container_id { 2366 // 128bit GUID in binary form 2367 unsigned char guid[16]; 2368 // 8 byte port ID -> ELD.PortID 2369 unsigned int portId[2]; 2370 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2371 unsigned short manufacturerName; 2372 // 2 byte product code -> ELD.ProductCode 2373 unsigned short productCode; 2374 }; 2375 2376 2377 struct dc_sink_dsc_caps { 2378 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2379 // 'false' if they are sink's DSC caps 2380 bool is_virtual_dpcd_dsc; 2381 // 'true' if MST topology supports DSC passthrough for sink 2382 // 'false' if MST topology does not support DSC passthrough 2383 bool is_dsc_passthrough_supported; 2384 struct dsc_dec_dpcd_caps dsc_dec_caps; 2385 }; 2386 2387 struct dc_sink_fec_caps { 2388 bool is_rx_fec_supported; 2389 bool is_topology_fec_supported; 2390 }; 2391 2392 struct scdc_caps { 2393 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2394 union hdmi_scdc_device_id_data device_id; 2395 }; 2396 2397 /* 2398 * The sink structure contains EDID and other display device properties 2399 */ 2400 struct dc_sink { 2401 enum signal_type sink_signal; 2402 struct dc_edid dc_edid; /* raw edid */ 2403 struct dc_edid_caps edid_caps; /* parse display caps */ 2404 struct dc_container_id *dc_container_id; 2405 uint32_t dongle_max_pix_clk; 2406 void *priv; 2407 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2408 bool converter_disable_audio; 2409 2410 struct scdc_caps scdc_caps; 2411 struct dc_sink_dsc_caps dsc_caps; 2412 struct dc_sink_fec_caps fec_caps; 2413 2414 bool is_vsc_sdp_colorimetry_supported; 2415 2416 /* private to DC core */ 2417 struct dc_link *link; 2418 struct dc_context *ctx; 2419 2420 uint32_t sink_id; 2421 2422 /* private to dc_sink.c */ 2423 // refcount must be the last member in dc_sink, since we want the 2424 // sink structure to be logically cloneable up to (but not including) 2425 // refcount 2426 struct kref refcount; 2427 }; 2428 2429 void dc_sink_retain(struct dc_sink *sink); 2430 void dc_sink_release(struct dc_sink *sink); 2431 2432 struct dc_sink_init_data { 2433 enum signal_type sink_signal; 2434 struct dc_link *link; 2435 uint32_t dongle_max_pix_clk; 2436 bool converter_disable_audio; 2437 }; 2438 2439 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2440 2441 /* Newer interfaces */ 2442 struct dc_cursor { 2443 struct dc_plane_address address; 2444 struct dc_cursor_attributes attributes; 2445 }; 2446 2447 2448 /* Interrupt interfaces */ 2449 enum dc_irq_source dc_interrupt_to_irq_source( 2450 struct dc *dc, 2451 uint32_t src_id, 2452 uint32_t ext_id); 2453 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2454 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2455 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2456 struct dc *dc, uint32_t link_index); 2457 2458 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2459 2460 /* Power Interfaces */ 2461 2462 void dc_set_power_state( 2463 struct dc *dc, 2464 enum dc_acpi_cm_power_state power_state); 2465 void dc_resume(struct dc *dc); 2466 2467 void dc_power_down_on_boot(struct dc *dc); 2468 2469 /* 2470 * HDCP Interfaces 2471 */ 2472 enum hdcp_message_status dc_process_hdcp_msg( 2473 enum signal_type signal, 2474 struct dc_link *link, 2475 struct hdcp_protection_message *message_info); 2476 bool dc_is_dmcu_initialized(struct dc *dc); 2477 2478 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2479 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2480 2481 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2482 unsigned int pitch, 2483 unsigned int height, 2484 enum surface_pixel_format format, 2485 struct dc_cursor_attributes *cursor_attr); 2486 2487 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2488 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2489 2490 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2491 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2492 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2493 2494 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2495 void dc_unlock_memory_clock_frequency(struct dc *dc); 2496 2497 /* set min memory clock to the min required for current mode, max to maxDPM */ 2498 void dc_lock_memory_clock_frequency(struct dc *dc); 2499 2500 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2501 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2502 2503 /* cleanup on driver unload */ 2504 void dc_hardware_release(struct dc *dc); 2505 2506 /* disables fw based mclk switch */ 2507 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2508 2509 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2510 2511 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2512 2513 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2514 2515 void dc_z10_restore(const struct dc *dc); 2516 void dc_z10_save_init(struct dc *dc); 2517 2518 bool dc_is_dmub_outbox_supported(struct dc *dc); 2519 bool dc_enable_dmub_notifications(struct dc *dc); 2520 2521 bool dc_abm_save_restore( 2522 struct dc *dc, 2523 struct dc_stream_state *stream, 2524 struct abm_save_restore *pData); 2525 2526 void dc_enable_dmub_outbox(struct dc *dc); 2527 2528 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2529 uint32_t link_index, 2530 struct aux_payload *payload); 2531 2532 /* Get dc link index from dpia port index */ 2533 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2534 uint8_t dpia_port_index); 2535 2536 bool dc_process_dmub_set_config_async(struct dc *dc, 2537 uint32_t link_index, 2538 struct set_config_cmd_payload *payload, 2539 struct dmub_notification *notify); 2540 2541 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2542 uint32_t link_index, 2543 uint8_t mst_alloc_slots, 2544 uint8_t *mst_slots_in_use); 2545 2546 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2547 2548 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2549 uint32_t hpd_int_enable); 2550 2551 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2552 2553 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2554 2555 struct dc_power_profile { 2556 int power_level; /* Lower is better */ 2557 }; 2558 2559 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2560 2561 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2562 2563 /* DSC Interfaces */ 2564 #include "dc_dsc.h" 2565 2566 /* Disable acc mode Interfaces */ 2567 void dc_disable_accelerated_mode(struct dc *dc); 2568 2569 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2570 struct dc_stream_state *new_stream); 2571 2572 #endif /* DC_INTERFACE_H_ */ 2573