1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.137" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 }; 187 188 struct dc_bug_wa { 189 bool no_connect_phy_config; 190 bool dedcn20_305_wa; 191 bool skip_clock_update; 192 bool lt_early_cr_pattern; 193 }; 194 195 struct dc_dcc_surface_param { 196 struct dc_size surface_size; 197 enum surface_pixel_format format; 198 enum swizzle_mode_values swizzle_mode; 199 enum dc_scan_direction scan; 200 }; 201 202 struct dc_dcc_setting { 203 unsigned int max_compressed_blk_size; 204 unsigned int max_uncompressed_blk_size; 205 bool independent_64b_blks; 206 #if defined(CONFIG_DRM_AMD_DC_DCN) 207 //These bitfields to be used starting with DCN 3.0 208 struct { 209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 213 } dcc_controls; 214 #endif 215 }; 216 217 struct dc_surface_dcc_cap { 218 union { 219 struct { 220 struct dc_dcc_setting rgb; 221 } grph; 222 223 struct { 224 struct dc_dcc_setting luma; 225 struct dc_dcc_setting chroma; 226 } video; 227 }; 228 229 bool capable; 230 bool const_color_support; 231 }; 232 233 struct dc_static_screen_params { 234 struct { 235 bool force_trigger; 236 bool cursor_update; 237 bool surface_update; 238 bool overlay_update; 239 } triggers; 240 unsigned int num_frames; 241 }; 242 243 244 /* Surface update type is used by dc_update_surfaces_and_stream 245 * The update type is determined at the very beginning of the function based 246 * on parameters passed in and decides how much programming (or updating) is 247 * going to be done during the call. 248 * 249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 250 * logical calculations or hardware register programming. This update MUST be 251 * ISR safe on windows. Currently fast update will only be used to flip surface 252 * address. 253 * 254 * UPDATE_TYPE_MED is used for slower updates which require significant hw 255 * re-programming however do not affect bandwidth consumption or clock 256 * requirements. At present, this is the level at which front end updates 257 * that do not require us to run bw_calcs happen. These are in/out transfer func 258 * updates, viewport offset changes, recout size changes and pixel depth changes. 259 * This update can be done at ISR, but we want to minimize how often this happens. 260 * 261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 265 * a full update. This cannot be done at ISR level and should be a rare event. 266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 267 * underscan we don't expect to see this call at all. 268 */ 269 270 enum surface_update_type { 271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 273 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 274 }; 275 276 /* Forward declaration*/ 277 struct dc; 278 struct dc_plane_state; 279 struct dc_state; 280 281 282 struct dc_cap_funcs { 283 bool (*get_dcc_compression_cap)(const struct dc *dc, 284 const struct dc_dcc_surface_param *input, 285 struct dc_surface_dcc_cap *output); 286 }; 287 288 struct link_training_settings; 289 290 291 /* Structure to hold configuration flags set by dm at dc creation. */ 292 struct dc_config { 293 bool gpu_vm_support; 294 bool disable_disp_pll_sharing; 295 bool fbc_support; 296 bool disable_fractional_pwm; 297 bool allow_seamless_boot_optimization; 298 bool power_down_display_on_boot; 299 bool edp_not_connected; 300 bool force_enum_edp; 301 bool forced_clocks; 302 bool allow_lttpr_non_transparent_mode; 303 bool multi_mon_pp_mclk_switch; 304 bool disable_dmcu; 305 bool enable_4to1MPC; 306 #if defined(CONFIG_DRM_AMD_DC_DCN) 307 bool clamp_min_dcfclk; 308 #endif 309 uint64_t vblank_alignment_dto_params; 310 uint8_t vblank_alignment_max_frame_time_diff; 311 bool is_asymmetric_memory; 312 bool is_single_rank_dimm; 313 }; 314 315 enum visual_confirm { 316 VISUAL_CONFIRM_DISABLE = 0, 317 VISUAL_CONFIRM_SURFACE = 1, 318 VISUAL_CONFIRM_HDR = 2, 319 VISUAL_CONFIRM_MPCTREE = 4, 320 VISUAL_CONFIRM_PSR = 5, 321 }; 322 323 enum dcc_option { 324 DCC_ENABLE = 0, 325 DCC_DISABLE = 1, 326 DCC_HALF_REQ_DISALBE = 2, 327 }; 328 329 enum pipe_split_policy { 330 MPC_SPLIT_DYNAMIC = 0, 331 MPC_SPLIT_AVOID = 1, 332 MPC_SPLIT_AVOID_MULT_DISP = 2, 333 }; 334 335 enum wm_report_mode { 336 WM_REPORT_DEFAULT = 0, 337 WM_REPORT_OVERRIDE = 1, 338 }; 339 enum dtm_pstate{ 340 dtm_level_p0 = 0,/*highest voltage*/ 341 dtm_level_p1, 342 dtm_level_p2, 343 dtm_level_p3, 344 dtm_level_p4,/*when active_display_count = 0*/ 345 }; 346 347 enum dcn_pwr_state { 348 DCN_PWR_STATE_UNKNOWN = -1, 349 DCN_PWR_STATE_MISSION_MODE = 0, 350 DCN_PWR_STATE_LOW_POWER = 3, 351 }; 352 353 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 354 enum dcn_z9_support_state { 355 DCN_Z9_SUPPORT_UNKNOWN, 356 DCN_Z9_SUPPORT_ALLOW, 357 DCN_Z9_SUPPORT_DISALLOW, 358 }; 359 #endif 360 /* 361 * For any clocks that may differ per pipe 362 * only the max is stored in this structure 363 */ 364 struct dc_clocks { 365 int dispclk_khz; 366 int actual_dispclk_khz; 367 int dppclk_khz; 368 int actual_dppclk_khz; 369 int disp_dpp_voltage_level_khz; 370 int dcfclk_khz; 371 int socclk_khz; 372 int dcfclk_deep_sleep_khz; 373 int fclk_khz; 374 int phyclk_khz; 375 int dramclk_khz; 376 bool p_state_change_support; 377 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 378 enum dcn_z9_support_state z9_support; 379 bool dtbclk_en; 380 #endif 381 enum dcn_pwr_state pwr_state; 382 /* 383 * Elements below are not compared for the purposes of 384 * optimization required 385 */ 386 bool prev_p_state_change_support; 387 enum dtm_pstate dtm_level; 388 int max_supported_dppclk_khz; 389 int max_supported_dispclk_khz; 390 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 391 int bw_dispclk_khz; 392 }; 393 394 struct dc_bw_validation_profile { 395 bool enable; 396 397 unsigned long long total_ticks; 398 unsigned long long voltage_level_ticks; 399 unsigned long long watermark_ticks; 400 unsigned long long rq_dlg_ticks; 401 402 unsigned long long total_count; 403 unsigned long long skip_fast_count; 404 unsigned long long skip_pass_count; 405 unsigned long long skip_fail_count; 406 }; 407 408 #define BW_VAL_TRACE_SETUP() \ 409 unsigned long long end_tick = 0; \ 410 unsigned long long voltage_level_tick = 0; \ 411 unsigned long long watermark_tick = 0; \ 412 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 413 dm_get_timestamp(dc->ctx) : 0 414 415 #define BW_VAL_TRACE_COUNT() \ 416 if (dc->debug.bw_val_profile.enable) \ 417 dc->debug.bw_val_profile.total_count++ 418 419 #define BW_VAL_TRACE_SKIP(status) \ 420 if (dc->debug.bw_val_profile.enable) { \ 421 if (!voltage_level_tick) \ 422 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 423 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 424 } 425 426 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 427 if (dc->debug.bw_val_profile.enable) \ 428 voltage_level_tick = dm_get_timestamp(dc->ctx) 429 430 #define BW_VAL_TRACE_END_WATERMARKS() \ 431 if (dc->debug.bw_val_profile.enable) \ 432 watermark_tick = dm_get_timestamp(dc->ctx) 433 434 #define BW_VAL_TRACE_FINISH() \ 435 if (dc->debug.bw_val_profile.enable) { \ 436 end_tick = dm_get_timestamp(dc->ctx); \ 437 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 438 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 439 if (watermark_tick) { \ 440 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 441 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 442 } \ 443 } 444 445 union mem_low_power_enable_options { 446 struct { 447 bool i2c: 1; 448 bool dmcu: 1; 449 bool dscl: 1; 450 bool cm: 1; 451 bool mpc: 1; 452 bool optc: 1; 453 } bits; 454 uint32_t u32All; 455 }; 456 457 struct dc_debug_options { 458 enum visual_confirm visual_confirm; 459 bool sanity_checks; 460 bool max_disp_clk; 461 bool surface_trace; 462 bool timing_trace; 463 bool clock_trace; 464 bool validation_trace; 465 bool bandwidth_calcs_trace; 466 int max_downscale_src_width; 467 468 /* stutter efficiency related */ 469 bool disable_stutter; 470 bool use_max_lb; 471 enum dcc_option disable_dcc; 472 enum pipe_split_policy pipe_split_policy; 473 bool force_single_disp_pipe_split; 474 bool voltage_align_fclk; 475 bool disable_min_fclk; 476 477 bool disable_dfs_bypass; 478 bool disable_dpp_power_gate; 479 bool disable_hubp_power_gate; 480 bool disable_dsc_power_gate; 481 int dsc_min_slice_height_override; 482 int dsc_bpp_increment_div; 483 bool native422_support; 484 bool disable_pplib_wm_range; 485 enum wm_report_mode pplib_wm_report_mode; 486 unsigned int min_disp_clk_khz; 487 unsigned int min_dpp_clk_khz; 488 int sr_exit_time_dpm0_ns; 489 int sr_enter_plus_exit_time_dpm0_ns; 490 int sr_exit_time_ns; 491 int sr_enter_plus_exit_time_ns; 492 int urgent_latency_ns; 493 uint32_t underflow_assert_delay_us; 494 int percent_of_ideal_drambw; 495 int dram_clock_change_latency_ns; 496 bool optimized_watermark; 497 int always_scale; 498 bool disable_pplib_clock_request; 499 bool disable_clock_gate; 500 bool disable_mem_low_power; 501 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 502 bool pstate_enabled; 503 #endif 504 bool disable_dmcu; 505 bool disable_psr; 506 bool force_abm_enable; 507 bool disable_stereo_support; 508 bool vsr_support; 509 bool performance_trace; 510 bool az_endpoint_mute_only; 511 bool always_use_regamma; 512 bool recovery_enabled; 513 bool avoid_vbios_exec_table; 514 bool scl_reset_length10; 515 bool hdmi20_disable; 516 bool skip_detection_link_training; 517 uint32_t edid_read_retry_times; 518 bool remove_disconnect_edp; 519 unsigned int force_odm_combine; //bit vector based on otg inst 520 #if defined(CONFIG_DRM_AMD_DC_DCN) 521 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 522 #endif 523 unsigned int force_fclk_khz; 524 bool enable_tri_buf; 525 bool dmub_offload_enabled; 526 bool dmcub_emulation; 527 #if defined(CONFIG_DRM_AMD_DC_DCN) 528 bool disable_idle_power_optimizations; 529 unsigned int mall_size_override; 530 unsigned int mall_additional_timer_percent; 531 bool mall_error_as_fatal; 532 #endif 533 bool dmub_command_table; /* for testing only */ 534 struct dc_bw_validation_profile bw_val_profile; 535 bool disable_fec; 536 bool disable_48mhz_pwrdwn; 537 /* This forces a hard min on the DCFCLK requested to SMU/PP 538 * watermarks are not affected. 539 */ 540 unsigned int force_min_dcfclk_mhz; 541 #if defined(CONFIG_DRM_AMD_DC_DCN) 542 int dwb_fi_phase; 543 #endif 544 bool disable_timing_sync; 545 bool cm_in_bypass; 546 int force_clock_mode;/*every mode change.*/ 547 548 bool disable_dram_clock_change_vactive_support; 549 bool validate_dml_output; 550 bool enable_dmcub_surface_flip; 551 bool usbc_combo_phy_reset_wa; 552 bool disable_dsc; 553 bool enable_dram_clock_change_one_display_vactive; 554 union mem_low_power_enable_options enable_mem_low_power; 555 bool force_vblank_alignment; 556 557 /* Enable dmub aux for legacy ddc */ 558 bool enable_dmub_aux_for_legacy_ddc; 559 bool optimize_edp_link_rate; /* eDP ILR */ 560 /* force enable edp FEC */ 561 bool force_enable_edp_fec; 562 /* FEC/PSR1 sequence enable delay in 100us */ 563 uint8_t fec_enable_delay_in100us; 564 }; 565 566 struct dc_debug_data { 567 uint32_t ltFailCount; 568 uint32_t i2cErrorCount; 569 uint32_t auxErrorCount; 570 }; 571 572 struct dc_phy_addr_space_config { 573 struct { 574 uint64_t start_addr; 575 uint64_t end_addr; 576 uint64_t fb_top; 577 uint64_t fb_offset; 578 uint64_t fb_base; 579 uint64_t agp_top; 580 uint64_t agp_bot; 581 uint64_t agp_base; 582 } system_aperture; 583 584 struct { 585 uint64_t page_table_start_addr; 586 uint64_t page_table_end_addr; 587 uint64_t page_table_base_addr; 588 } gart_config; 589 590 bool valid; 591 bool is_hvm_enabled; 592 uint64_t page_table_default_page_addr; 593 }; 594 595 struct dc_virtual_addr_space_config { 596 uint64_t page_table_base_addr; 597 uint64_t page_table_start_addr; 598 uint64_t page_table_end_addr; 599 uint32_t page_table_block_size_in_bytes; 600 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 601 }; 602 603 struct dc_bounding_box_overrides { 604 int sr_exit_time_ns; 605 int sr_enter_plus_exit_time_ns; 606 int urgent_latency_ns; 607 int percent_of_ideal_drambw; 608 int dram_clock_change_latency_ns; 609 int dummy_clock_change_latency_ns; 610 /* This forces a hard min on the DCFCLK we use 611 * for DML. Unlike the debug option for forcing 612 * DCFCLK, this override affects watermark calculations 613 */ 614 int min_dcfclk_mhz; 615 }; 616 617 struct resource_pool; 618 struct dce_hwseq; 619 struct gpu_info_soc_bounding_box_v1_0; 620 struct dc { 621 struct dc_versions versions; 622 struct dc_caps caps; 623 struct dc_cap_funcs cap_funcs; 624 struct dc_config config; 625 struct dc_debug_options debug; 626 struct dc_bounding_box_overrides bb_overrides; 627 struct dc_bug_wa work_arounds; 628 struct dc_context *ctx; 629 struct dc_phy_addr_space_config vm_pa_config; 630 631 uint8_t link_count; 632 struct dc_link *links[MAX_PIPES * 2]; 633 634 struct dc_state *current_state; 635 struct resource_pool *res_pool; 636 637 struct clk_mgr *clk_mgr; 638 639 /* Display Engine Clock levels */ 640 struct dm_pp_clock_levels sclk_lvls; 641 642 /* Inputs into BW and WM calculations. */ 643 struct bw_calcs_dceip *bw_dceip; 644 struct bw_calcs_vbios *bw_vbios; 645 #ifdef CONFIG_DRM_AMD_DC_DCN 646 struct dcn_soc_bounding_box *dcn_soc; 647 struct dcn_ip_params *dcn_ip; 648 struct display_mode_lib dml; 649 #endif 650 651 /* HW functions */ 652 struct hw_sequencer_funcs hwss; 653 struct dce_hwseq *hwseq; 654 655 /* Require to optimize clocks and bandwidth for added/removed planes */ 656 bool optimized_required; 657 bool wm_optimized_required; 658 #if defined(CONFIG_DRM_AMD_DC_DCN) 659 bool idle_optimizations_allowed; 660 #endif 661 662 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 663 664 /* FBC compressor */ 665 struct compressor *fbc_compressor; 666 667 struct dc_debug_data debug_data; 668 struct dpcd_vendor_signature vendor_signature; 669 670 const char *build_id; 671 struct vm_helper *vm_helper; 672 }; 673 674 enum frame_buffer_mode { 675 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 676 FRAME_BUFFER_MODE_ZFB_ONLY, 677 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 678 } ; 679 680 struct dchub_init_data { 681 int64_t zfb_phys_addr_base; 682 int64_t zfb_mc_base_addr; 683 uint64_t zfb_size_in_byte; 684 enum frame_buffer_mode fb_mode; 685 bool dchub_initialzied; 686 bool dchub_info_valid; 687 }; 688 689 struct dc_init_data { 690 struct hw_asic_id asic_id; 691 void *driver; /* ctx */ 692 struct cgs_device *cgs_device; 693 struct dc_bounding_box_overrides bb_overrides; 694 695 int num_virtual_links; 696 /* 697 * If 'vbios_override' not NULL, it will be called instead 698 * of the real VBIOS. Intended use is Diagnostics on FPGA. 699 */ 700 struct dc_bios *vbios_override; 701 enum dce_environment dce_environment; 702 703 struct dmub_offload_funcs *dmub_if; 704 struct dc_reg_helper_state *dmub_offload; 705 706 struct dc_config flags; 707 uint64_t log_mask; 708 709 struct dpcd_vendor_signature vendor_signature; 710 #if defined(CONFIG_DRM_AMD_DC_DCN) 711 bool force_smu_not_present; 712 #endif 713 }; 714 715 struct dc_callback_init { 716 #ifdef CONFIG_DRM_AMD_DC_HDCP 717 struct cp_psp cp_psp; 718 #else 719 uint8_t reserved; 720 #endif 721 }; 722 723 struct dc *dc_create(const struct dc_init_data *init_params); 724 void dc_hardware_init(struct dc *dc); 725 726 int dc_get_vmid_use_vector(struct dc *dc); 727 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 728 /* Returns the number of vmids supported */ 729 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 730 void dc_init_callbacks(struct dc *dc, 731 const struct dc_callback_init *init_params); 732 void dc_deinit_callbacks(struct dc *dc); 733 void dc_destroy(struct dc **dc); 734 735 /******************************************************************************* 736 * Surface Interfaces 737 ******************************************************************************/ 738 739 enum { 740 TRANSFER_FUNC_POINTS = 1025 741 }; 742 743 struct dc_hdr_static_metadata { 744 /* display chromaticities and white point in units of 0.00001 */ 745 unsigned int chromaticity_green_x; 746 unsigned int chromaticity_green_y; 747 unsigned int chromaticity_blue_x; 748 unsigned int chromaticity_blue_y; 749 unsigned int chromaticity_red_x; 750 unsigned int chromaticity_red_y; 751 unsigned int chromaticity_white_point_x; 752 unsigned int chromaticity_white_point_y; 753 754 uint32_t min_luminance; 755 uint32_t max_luminance; 756 uint32_t maximum_content_light_level; 757 uint32_t maximum_frame_average_light_level; 758 }; 759 760 enum dc_transfer_func_type { 761 TF_TYPE_PREDEFINED, 762 TF_TYPE_DISTRIBUTED_POINTS, 763 TF_TYPE_BYPASS, 764 TF_TYPE_HWPWL 765 }; 766 767 struct dc_transfer_func_distributed_points { 768 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 769 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 770 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 771 772 uint16_t end_exponent; 773 uint16_t x_point_at_y1_red; 774 uint16_t x_point_at_y1_green; 775 uint16_t x_point_at_y1_blue; 776 }; 777 778 enum dc_transfer_func_predefined { 779 TRANSFER_FUNCTION_SRGB, 780 TRANSFER_FUNCTION_BT709, 781 TRANSFER_FUNCTION_PQ, 782 TRANSFER_FUNCTION_LINEAR, 783 TRANSFER_FUNCTION_UNITY, 784 TRANSFER_FUNCTION_HLG, 785 TRANSFER_FUNCTION_HLG12, 786 TRANSFER_FUNCTION_GAMMA22, 787 TRANSFER_FUNCTION_GAMMA24, 788 TRANSFER_FUNCTION_GAMMA26 789 }; 790 791 792 struct dc_transfer_func { 793 struct kref refcount; 794 enum dc_transfer_func_type type; 795 enum dc_transfer_func_predefined tf; 796 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 797 uint32_t sdr_ref_white_level; 798 union { 799 struct pwl_params pwl; 800 struct dc_transfer_func_distributed_points tf_pts; 801 }; 802 }; 803 804 805 union dc_3dlut_state { 806 struct { 807 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 808 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 809 uint32_t rmu_mux_num:3; /*index of mux to use*/ 810 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 811 uint32_t mpc_rmu1_mux:4; 812 uint32_t mpc_rmu2_mux:4; 813 uint32_t reserved:15; 814 } bits; 815 uint32_t raw; 816 }; 817 818 819 struct dc_3dlut { 820 struct kref refcount; 821 struct tetrahedral_params lut_3d; 822 struct fixed31_32 hdr_multiplier; 823 union dc_3dlut_state state; 824 }; 825 /* 826 * This structure is filled in by dc_surface_get_status and contains 827 * the last requested address and the currently active address so the called 828 * can determine if there are any outstanding flips 829 */ 830 struct dc_plane_status { 831 struct dc_plane_address requested_address; 832 struct dc_plane_address current_address; 833 bool is_flip_pending; 834 bool is_right_eye; 835 }; 836 837 union surface_update_flags { 838 839 struct { 840 uint32_t addr_update:1; 841 /* Medium updates */ 842 uint32_t dcc_change:1; 843 uint32_t color_space_change:1; 844 uint32_t horizontal_mirror_change:1; 845 uint32_t per_pixel_alpha_change:1; 846 uint32_t global_alpha_change:1; 847 uint32_t hdr_mult:1; 848 uint32_t rotation_change:1; 849 uint32_t swizzle_change:1; 850 uint32_t scaling_change:1; 851 uint32_t position_change:1; 852 uint32_t in_transfer_func_change:1; 853 uint32_t input_csc_change:1; 854 uint32_t coeff_reduction_change:1; 855 uint32_t output_tf_change:1; 856 uint32_t pixel_format_change:1; 857 uint32_t plane_size_change:1; 858 uint32_t gamut_remap_change:1; 859 860 /* Full updates */ 861 uint32_t new_plane:1; 862 uint32_t bpp_change:1; 863 uint32_t gamma_change:1; 864 uint32_t bandwidth_change:1; 865 uint32_t clock_change:1; 866 uint32_t stereo_format_change:1; 867 uint32_t full_update:1; 868 } bits; 869 870 uint32_t raw; 871 }; 872 873 struct dc_plane_state { 874 struct dc_plane_address address; 875 struct dc_plane_flip_time time; 876 bool triplebuffer_flips; 877 struct scaling_taps scaling_quality; 878 struct rect src_rect; 879 struct rect dst_rect; 880 struct rect clip_rect; 881 882 struct plane_size plane_size; 883 union dc_tiling_info tiling_info; 884 885 struct dc_plane_dcc_param dcc; 886 887 struct dc_gamma *gamma_correction; 888 struct dc_transfer_func *in_transfer_func; 889 struct dc_bias_and_scale *bias_and_scale; 890 struct dc_csc_transform input_csc_color_matrix; 891 struct fixed31_32 coeff_reduction_factor; 892 struct fixed31_32 hdr_mult; 893 struct colorspace_transform gamut_remap_matrix; 894 895 // TODO: No longer used, remove 896 struct dc_hdr_static_metadata hdr_static_ctx; 897 898 enum dc_color_space color_space; 899 900 struct dc_3dlut *lut3d_func; 901 struct dc_transfer_func *in_shaper_func; 902 struct dc_transfer_func *blend_tf; 903 904 #if defined(CONFIG_DRM_AMD_DC_DCN) 905 struct dc_transfer_func *gamcor_tf; 906 #endif 907 enum surface_pixel_format format; 908 enum dc_rotation_angle rotation; 909 enum plane_stereo_format stereo_format; 910 911 bool is_tiling_rotated; 912 bool per_pixel_alpha; 913 bool global_alpha; 914 int global_alpha_value; 915 bool visible; 916 bool flip_immediate; 917 bool horizontal_mirror; 918 int layer_index; 919 920 union surface_update_flags update_flags; 921 bool flip_int_enabled; 922 bool skip_manual_trigger; 923 924 /* private to DC core */ 925 struct dc_plane_status status; 926 struct dc_context *ctx; 927 928 /* HACK: Workaround for forcing full reprogramming under some conditions */ 929 bool force_full_update; 930 931 /* private to dc_surface.c */ 932 enum dc_irq_source irq_source; 933 struct kref refcount; 934 }; 935 936 struct dc_plane_info { 937 struct plane_size plane_size; 938 union dc_tiling_info tiling_info; 939 struct dc_plane_dcc_param dcc; 940 enum surface_pixel_format format; 941 enum dc_rotation_angle rotation; 942 enum plane_stereo_format stereo_format; 943 enum dc_color_space color_space; 944 bool horizontal_mirror; 945 bool visible; 946 bool per_pixel_alpha; 947 bool global_alpha; 948 int global_alpha_value; 949 bool input_csc_enabled; 950 int layer_index; 951 }; 952 953 struct dc_scaling_info { 954 struct rect src_rect; 955 struct rect dst_rect; 956 struct rect clip_rect; 957 struct scaling_taps scaling_quality; 958 }; 959 960 struct dc_surface_update { 961 struct dc_plane_state *surface; 962 963 /* isr safe update parameters. null means no updates */ 964 const struct dc_flip_addrs *flip_addr; 965 const struct dc_plane_info *plane_info; 966 const struct dc_scaling_info *scaling_info; 967 struct fixed31_32 hdr_mult; 968 /* following updates require alloc/sleep/spin that is not isr safe, 969 * null means no updates 970 */ 971 const struct dc_gamma *gamma; 972 const struct dc_transfer_func *in_transfer_func; 973 974 const struct dc_csc_transform *input_csc_color_matrix; 975 const struct fixed31_32 *coeff_reduction_factor; 976 const struct dc_transfer_func *func_shaper; 977 const struct dc_3dlut *lut3d_func; 978 const struct dc_transfer_func *blend_tf; 979 const struct colorspace_transform *gamut_remap_matrix; 980 }; 981 982 /* 983 * Create a new surface with default parameters; 984 */ 985 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 986 const struct dc_plane_status *dc_plane_get_status( 987 const struct dc_plane_state *plane_state); 988 989 void dc_plane_state_retain(struct dc_plane_state *plane_state); 990 void dc_plane_state_release(struct dc_plane_state *plane_state); 991 992 void dc_gamma_retain(struct dc_gamma *dc_gamma); 993 void dc_gamma_release(struct dc_gamma **dc_gamma); 994 struct dc_gamma *dc_create_gamma(void); 995 996 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 997 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 998 struct dc_transfer_func *dc_create_transfer_func(void); 999 1000 struct dc_3dlut *dc_create_3dlut_func(void); 1001 void dc_3dlut_func_release(struct dc_3dlut *lut); 1002 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1003 /* 1004 * This structure holds a surface address. There could be multiple addresses 1005 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1006 * as frame durations and DCC format can also be set. 1007 */ 1008 struct dc_flip_addrs { 1009 struct dc_plane_address address; 1010 unsigned int flip_timestamp_in_us; 1011 bool flip_immediate; 1012 /* TODO: add flip duration for FreeSync */ 1013 bool triplebuffer_flips; 1014 }; 1015 1016 void dc_post_update_surfaces_to_stream( 1017 struct dc *dc); 1018 1019 #include "dc_stream.h" 1020 1021 /* 1022 * Structure to store surface/stream associations for validation 1023 */ 1024 struct dc_validation_set { 1025 struct dc_stream_state *stream; 1026 struct dc_plane_state *plane_states[MAX_SURFACES]; 1027 uint8_t plane_count; 1028 }; 1029 1030 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1031 const struct dc_sink *sink, 1032 struct dc_crtc_timing *crtc_timing); 1033 1034 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1035 1036 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1037 1038 bool dc_set_generic_gpio_for_stereo(bool enable, 1039 struct gpio_service *gpio_service); 1040 1041 /* 1042 * fast_validate: we return after determining if we can support the new state, 1043 * but before we populate the programming info 1044 */ 1045 enum dc_status dc_validate_global_state( 1046 struct dc *dc, 1047 struct dc_state *new_ctx, 1048 bool fast_validate); 1049 1050 1051 void dc_resource_state_construct( 1052 const struct dc *dc, 1053 struct dc_state *dst_ctx); 1054 1055 #if defined(CONFIG_DRM_AMD_DC_DCN) 1056 bool dc_acquire_release_mpc_3dlut( 1057 struct dc *dc, bool acquire, 1058 struct dc_stream_state *stream, 1059 struct dc_3dlut **lut, 1060 struct dc_transfer_func **shaper); 1061 #endif 1062 1063 void dc_resource_state_copy_construct( 1064 const struct dc_state *src_ctx, 1065 struct dc_state *dst_ctx); 1066 1067 void dc_resource_state_copy_construct_current( 1068 const struct dc *dc, 1069 struct dc_state *dst_ctx); 1070 1071 void dc_resource_state_destruct(struct dc_state *context); 1072 1073 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1074 1075 /* 1076 * TODO update to make it about validation sets 1077 * Set up streams and links associated to drive sinks 1078 * The streams parameter is an absolute set of all active streams. 1079 * 1080 * After this call: 1081 * Phy, Encoder, Timing Generator are programmed and enabled. 1082 * New streams are enabled with blank stream; no memory read. 1083 */ 1084 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1085 1086 struct dc_state *dc_create_state(struct dc *dc); 1087 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1088 void dc_retain_state(struct dc_state *context); 1089 void dc_release_state(struct dc_state *context); 1090 1091 /******************************************************************************* 1092 * Link Interfaces 1093 ******************************************************************************/ 1094 1095 struct dpcd_caps { 1096 union dpcd_rev dpcd_rev; 1097 union max_lane_count max_ln_count; 1098 union max_down_spread max_down_spread; 1099 union dprx_feature dprx_feature; 1100 1101 /* valid only for eDP v1.4 or higher*/ 1102 uint8_t edp_supported_link_rates_count; 1103 enum dc_link_rate edp_supported_link_rates[8]; 1104 1105 /* dongle type (DP converter, CV smart dongle) */ 1106 enum display_dongle_type dongle_type; 1107 /* branch device or sink device */ 1108 bool is_branch_dev; 1109 /* Dongle's downstream count. */ 1110 union sink_count sink_count; 1111 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1112 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1113 struct dc_dongle_caps dongle_caps; 1114 1115 uint32_t sink_dev_id; 1116 int8_t sink_dev_id_str[6]; 1117 int8_t sink_hw_revision; 1118 int8_t sink_fw_revision[2]; 1119 1120 uint32_t branch_dev_id; 1121 int8_t branch_dev_name[6]; 1122 int8_t branch_hw_revision; 1123 int8_t branch_fw_revision[2]; 1124 1125 bool allow_invalid_MSA_timing_param; 1126 bool panel_mode_edp; 1127 bool dpcd_display_control_capable; 1128 bool ext_receiver_cap_field_present; 1129 bool dynamic_backlight_capable_edp; 1130 union dpcd_fec_capability fec_cap; 1131 struct dpcd_dsc_capabilities dsc_caps; 1132 struct dc_lttpr_caps lttpr_caps; 1133 struct psr_caps psr_caps; 1134 1135 }; 1136 1137 union dpcd_sink_ext_caps { 1138 struct { 1139 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1140 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1141 */ 1142 uint8_t sdr_aux_backlight_control : 1; 1143 uint8_t hdr_aux_backlight_control : 1; 1144 uint8_t reserved_1 : 2; 1145 uint8_t oled : 1; 1146 uint8_t reserved : 3; 1147 } bits; 1148 uint8_t raw; 1149 }; 1150 1151 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1152 union hdcp_rx_caps { 1153 struct { 1154 uint8_t version; 1155 uint8_t reserved; 1156 struct { 1157 uint8_t repeater : 1; 1158 uint8_t hdcp_capable : 1; 1159 uint8_t reserved : 6; 1160 } byte0; 1161 } fields; 1162 uint8_t raw[3]; 1163 }; 1164 1165 union hdcp_bcaps { 1166 struct { 1167 uint8_t HDCP_CAPABLE:1; 1168 uint8_t REPEATER:1; 1169 uint8_t RESERVED:6; 1170 } bits; 1171 uint8_t raw; 1172 }; 1173 1174 struct hdcp_caps { 1175 union hdcp_rx_caps rx_caps; 1176 union hdcp_bcaps bcaps; 1177 }; 1178 #endif 1179 1180 #include "dc_link.h" 1181 1182 #if defined(CONFIG_DRM_AMD_DC_DCN) 1183 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1184 1185 #endif 1186 /******************************************************************************* 1187 * Sink Interfaces - A sink corresponds to a display output device 1188 ******************************************************************************/ 1189 1190 struct dc_container_id { 1191 // 128bit GUID in binary form 1192 unsigned char guid[16]; 1193 // 8 byte port ID -> ELD.PortID 1194 unsigned int portId[2]; 1195 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1196 unsigned short manufacturerName; 1197 // 2 byte product code -> ELD.ProductCode 1198 unsigned short productCode; 1199 }; 1200 1201 1202 struct dc_sink_dsc_caps { 1203 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1204 // 'false' if they are sink's DSC caps 1205 bool is_virtual_dpcd_dsc; 1206 struct dsc_dec_dpcd_caps dsc_dec_caps; 1207 }; 1208 1209 struct dc_sink_fec_caps { 1210 bool is_rx_fec_supported; 1211 bool is_topology_fec_supported; 1212 }; 1213 1214 /* 1215 * The sink structure contains EDID and other display device properties 1216 */ 1217 struct dc_sink { 1218 enum signal_type sink_signal; 1219 struct dc_edid dc_edid; /* raw edid */ 1220 struct dc_edid_caps edid_caps; /* parse display caps */ 1221 struct dc_container_id *dc_container_id; 1222 uint32_t dongle_max_pix_clk; 1223 void *priv; 1224 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1225 bool converter_disable_audio; 1226 1227 struct dc_sink_dsc_caps dsc_caps; 1228 struct dc_sink_fec_caps fec_caps; 1229 1230 bool is_vsc_sdp_colorimetry_supported; 1231 1232 /* private to DC core */ 1233 struct dc_link *link; 1234 struct dc_context *ctx; 1235 1236 uint32_t sink_id; 1237 1238 /* private to dc_sink.c */ 1239 // refcount must be the last member in dc_sink, since we want the 1240 // sink structure to be logically cloneable up to (but not including) 1241 // refcount 1242 struct kref refcount; 1243 }; 1244 1245 void dc_sink_retain(struct dc_sink *sink); 1246 void dc_sink_release(struct dc_sink *sink); 1247 1248 struct dc_sink_init_data { 1249 enum signal_type sink_signal; 1250 struct dc_link *link; 1251 uint32_t dongle_max_pix_clk; 1252 bool converter_disable_audio; 1253 }; 1254 1255 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1256 1257 /* Newer interfaces */ 1258 struct dc_cursor { 1259 struct dc_plane_address address; 1260 struct dc_cursor_attributes attributes; 1261 }; 1262 1263 1264 /******************************************************************************* 1265 * Interrupt interfaces 1266 ******************************************************************************/ 1267 enum dc_irq_source dc_interrupt_to_irq_source( 1268 struct dc *dc, 1269 uint32_t src_id, 1270 uint32_t ext_id); 1271 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1272 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1273 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1274 struct dc *dc, uint32_t link_index); 1275 1276 /******************************************************************************* 1277 * Power Interfaces 1278 ******************************************************************************/ 1279 1280 void dc_set_power_state( 1281 struct dc *dc, 1282 enum dc_acpi_cm_power_state power_state); 1283 void dc_resume(struct dc *dc); 1284 1285 void dc_power_down_on_boot(struct dc *dc); 1286 1287 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1288 /* 1289 * HDCP Interfaces 1290 */ 1291 enum hdcp_message_status dc_process_hdcp_msg( 1292 enum signal_type signal, 1293 struct dc_link *link, 1294 struct hdcp_protection_message *message_info); 1295 #endif 1296 bool dc_is_dmcu_initialized(struct dc *dc); 1297 1298 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1299 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1300 #if defined(CONFIG_DRM_AMD_DC_DCN) 1301 1302 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1303 struct dc_cursor_attributes *cursor_attr); 1304 1305 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1306 1307 /* 1308 * blank all streams, and set min and max memory clock to 1309 * lowest and highest DPM level, respectively 1310 */ 1311 void dc_unlock_memory_clock_frequency(struct dc *dc); 1312 1313 /* 1314 * set min memory clock to the min required for current mode, 1315 * max to maxDPM, and unblank streams 1316 */ 1317 void dc_lock_memory_clock_frequency(struct dc *dc); 1318 1319 /* cleanup on driver unload */ 1320 void dc_hardware_release(struct dc *dc); 1321 1322 #endif 1323 1324 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1325 1326 bool dc_enable_dmub_notifications(struct dc *dc); 1327 1328 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1329 uint32_t link_index, 1330 struct aux_payload *payload); 1331 1332 /******************************************************************************* 1333 * DSC Interfaces 1334 ******************************************************************************/ 1335 #include "dc_dsc.h" 1336 1337 /******************************************************************************* 1338 * Disable acc mode Interfaces 1339 ******************************************************************************/ 1340 void dc_disable_accelerated_mode(struct dc *dc); 1341 1342 #endif /* DC_INTERFACE_H_ */ 1343