1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.35" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 115 bool hw_3d_lut; 116 #endif 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 121 struct dc_bug_wa { 122 bool no_connect_phy_config; 123 bool dedcn20_305_wa; 124 }; 125 #endif 126 127 struct dc_dcc_surface_param { 128 struct dc_size surface_size; 129 enum surface_pixel_format format; 130 enum swizzle_mode_values swizzle_mode; 131 enum dc_scan_direction scan; 132 }; 133 134 struct dc_dcc_setting { 135 unsigned int max_compressed_blk_size; 136 unsigned int max_uncompressed_blk_size; 137 bool independent_64b_blks; 138 }; 139 140 struct dc_surface_dcc_cap { 141 union { 142 struct { 143 struct dc_dcc_setting rgb; 144 } grph; 145 146 struct { 147 struct dc_dcc_setting luma; 148 struct dc_dcc_setting chroma; 149 } video; 150 }; 151 152 bool capable; 153 bool const_color_support; 154 }; 155 156 struct dc_static_screen_events { 157 bool force_trigger; 158 bool cursor_update; 159 bool surface_update; 160 bool overlay_update; 161 }; 162 163 164 /* Surface update type is used by dc_update_surfaces_and_stream 165 * The update type is determined at the very beginning of the function based 166 * on parameters passed in and decides how much programming (or updating) is 167 * going to be done during the call. 168 * 169 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 170 * logical calculations or hardware register programming. This update MUST be 171 * ISR safe on windows. Currently fast update will only be used to flip surface 172 * address. 173 * 174 * UPDATE_TYPE_MED is used for slower updates which require significant hw 175 * re-programming however do not affect bandwidth consumption or clock 176 * requirements. At present, this is the level at which front end updates 177 * that do not require us to run bw_calcs happen. These are in/out transfer func 178 * updates, viewport offset changes, recout size changes and pixel depth changes. 179 * This update can be done at ISR, but we want to minimize how often this happens. 180 * 181 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 182 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 183 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 184 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 185 * a full update. This cannot be done at ISR level and should be a rare event. 186 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 187 * underscan we don't expect to see this call at all. 188 */ 189 190 enum surface_update_type { 191 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 192 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 193 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 194 }; 195 196 /* Forward declaration*/ 197 struct dc; 198 struct dc_plane_state; 199 struct dc_state; 200 201 202 struct dc_cap_funcs { 203 bool (*get_dcc_compression_cap)(const struct dc *dc, 204 const struct dc_dcc_surface_param *input, 205 struct dc_surface_dcc_cap *output); 206 }; 207 208 struct link_training_settings; 209 210 211 /* Structure to hold configuration flags set by dm at dc creation. */ 212 struct dc_config { 213 bool gpu_vm_support; 214 bool disable_disp_pll_sharing; 215 bool fbc_support; 216 bool optimize_edp_link_rate; 217 bool disable_fractional_pwm; 218 bool allow_seamless_boot_optimization; 219 bool power_down_display_on_boot; 220 bool edp_not_connected; 221 bool forced_clocks; 222 223 }; 224 225 enum visual_confirm { 226 VISUAL_CONFIRM_DISABLE = 0, 227 VISUAL_CONFIRM_SURFACE = 1, 228 VISUAL_CONFIRM_HDR = 2, 229 }; 230 231 enum dcc_option { 232 DCC_ENABLE = 0, 233 DCC_DISABLE = 1, 234 DCC_HALF_REQ_DISALBE = 2, 235 }; 236 237 enum pipe_split_policy { 238 MPC_SPLIT_DYNAMIC = 0, 239 MPC_SPLIT_AVOID = 1, 240 MPC_SPLIT_AVOID_MULT_DISP = 2, 241 }; 242 243 enum wm_report_mode { 244 WM_REPORT_DEFAULT = 0, 245 WM_REPORT_OVERRIDE = 1, 246 }; 247 248 /* 249 * For any clocks that may differ per pipe 250 * only the max is stored in this structure 251 */ 252 struct dc_clocks { 253 int dispclk_khz; 254 int max_supported_dppclk_khz; 255 int dppclk_khz; 256 int dcfclk_khz; 257 int socclk_khz; 258 int dcfclk_deep_sleep_khz; 259 int fclk_khz; 260 int phyclk_khz; 261 int dramclk_khz; 262 bool p_state_change_support; 263 }; 264 265 struct dc_bw_validation_profile { 266 bool enable; 267 268 unsigned long long total_ticks; 269 unsigned long long voltage_level_ticks; 270 unsigned long long watermark_ticks; 271 unsigned long long rq_dlg_ticks; 272 273 unsigned long long total_count; 274 unsigned long long skip_fast_count; 275 unsigned long long skip_pass_count; 276 unsigned long long skip_fail_count; 277 }; 278 279 #define BW_VAL_TRACE_SETUP() \ 280 unsigned long long end_tick = 0; \ 281 unsigned long long voltage_level_tick = 0; \ 282 unsigned long long watermark_tick = 0; \ 283 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 284 dm_get_timestamp(dc->ctx) : 0 285 286 #define BW_VAL_TRACE_COUNT() \ 287 if (dc->debug.bw_val_profile.enable) \ 288 dc->debug.bw_val_profile.total_count++ 289 290 #define BW_VAL_TRACE_SKIP(status) \ 291 if (dc->debug.bw_val_profile.enable) { \ 292 if (!voltage_level_tick) \ 293 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 294 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 295 } 296 297 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 298 if (dc->debug.bw_val_profile.enable) \ 299 voltage_level_tick = dm_get_timestamp(dc->ctx) 300 301 #define BW_VAL_TRACE_END_WATERMARKS() \ 302 if (dc->debug.bw_val_profile.enable) \ 303 watermark_tick = dm_get_timestamp(dc->ctx) 304 305 #define BW_VAL_TRACE_FINISH() \ 306 if (dc->debug.bw_val_profile.enable) { \ 307 end_tick = dm_get_timestamp(dc->ctx); \ 308 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 309 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 310 if (watermark_tick) { \ 311 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 312 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 313 } \ 314 } 315 316 struct dc_debug_options { 317 enum visual_confirm visual_confirm; 318 bool sanity_checks; 319 bool max_disp_clk; 320 bool surface_trace; 321 bool timing_trace; 322 bool clock_trace; 323 bool validation_trace; 324 bool bandwidth_calcs_trace; 325 int max_downscale_src_width; 326 327 /* stutter efficiency related */ 328 bool disable_stutter; 329 bool use_max_lb; 330 enum dcc_option disable_dcc; 331 enum pipe_split_policy pipe_split_policy; 332 bool force_single_disp_pipe_split; 333 bool voltage_align_fclk; 334 335 bool disable_dfs_bypass; 336 bool disable_dpp_power_gate; 337 bool disable_hubp_power_gate; 338 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 339 bool disable_dsc_power_gate; 340 #endif 341 bool disable_pplib_wm_range; 342 enum wm_report_mode pplib_wm_report_mode; 343 unsigned int min_disp_clk_khz; 344 int sr_exit_time_dpm0_ns; 345 int sr_enter_plus_exit_time_dpm0_ns; 346 int sr_exit_time_ns; 347 int sr_enter_plus_exit_time_ns; 348 int urgent_latency_ns; 349 int percent_of_ideal_drambw; 350 int dram_clock_change_latency_ns; 351 bool optimized_watermark; 352 int always_scale; 353 bool disable_pplib_clock_request; 354 bool disable_clock_gate; 355 bool disable_dmcu; 356 bool disable_psr; 357 bool force_abm_enable; 358 bool disable_stereo_support; 359 bool vsr_support; 360 bool performance_trace; 361 bool az_endpoint_mute_only; 362 bool always_use_regamma; 363 bool p010_mpo_support; 364 bool recovery_enabled; 365 bool avoid_vbios_exec_table; 366 bool scl_reset_length10; 367 bool hdmi20_disable; 368 bool skip_detection_link_training; 369 unsigned int force_odm_combine; //bit vector based on otg inst 370 unsigned int force_fclk_khz; 371 bool disable_tri_buf; 372 struct dc_bw_validation_profile bw_val_profile; 373 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 374 bool disable_fec; 375 #endif 376 /* This forces a hard min on the DCFCLK requested to SMU/PP 377 * watermarks are not affected. 378 */ 379 unsigned int force_min_dcfclk_mhz; 380 }; 381 382 struct dc_debug_data { 383 uint32_t ltFailCount; 384 uint32_t i2cErrorCount; 385 uint32_t auxErrorCount; 386 }; 387 388 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 389 struct dc_phy_addr_space_config { 390 struct { 391 uint64_t start_addr; 392 uint64_t end_addr; 393 uint64_t fb_top; 394 uint64_t fb_offset; 395 uint64_t fb_base; 396 uint64_t agp_top; 397 uint64_t agp_bot; 398 uint64_t agp_base; 399 } system_aperture; 400 401 struct { 402 uint64_t page_table_start_addr; 403 uint64_t page_table_end_addr; 404 uint64_t page_table_base_addr; 405 } gart_config; 406 407 bool valid; 408 }; 409 410 struct dc_virtual_addr_space_config { 411 uint64_t page_table_base_addr; 412 uint64_t page_table_start_addr; 413 uint64_t page_table_end_addr; 414 uint32_t page_table_block_size_in_bytes; 415 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 416 }; 417 #endif 418 419 struct dc_bounding_box_overrides { 420 int sr_exit_time_ns; 421 int sr_enter_plus_exit_time_ns; 422 int urgent_latency_ns; 423 int percent_of_ideal_drambw; 424 int dram_clock_change_latency_ns; 425 /* This forces a hard min on the DCFCLK we use 426 * for DML. Unlike the debug option for forcing 427 * DCFCLK, this override affects watermark calculations 428 */ 429 int min_dcfclk_mhz; 430 }; 431 432 struct dc_state; 433 struct resource_pool; 434 struct dce_hwseq; 435 struct gpu_info_soc_bounding_box_v1_0; 436 struct dc { 437 struct dc_versions versions; 438 struct dc_caps caps; 439 struct dc_cap_funcs cap_funcs; 440 struct dc_config config; 441 struct dc_debug_options debug; 442 struct dc_bounding_box_overrides bb_overrides; 443 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 444 struct dc_bug_wa work_arounds; 445 #endif 446 struct dc_context *ctx; 447 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 448 struct dc_phy_addr_space_config vm_pa_config; 449 #endif 450 451 uint8_t link_count; 452 struct dc_link *links[MAX_PIPES * 2]; 453 454 struct dc_state *current_state; 455 struct resource_pool *res_pool; 456 457 struct clk_mgr *clk_mgr; 458 459 /* Display Engine Clock levels */ 460 struct dm_pp_clock_levels sclk_lvls; 461 462 /* Inputs into BW and WM calculations. */ 463 struct bw_calcs_dceip *bw_dceip; 464 struct bw_calcs_vbios *bw_vbios; 465 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 466 struct dcn_soc_bounding_box *dcn_soc; 467 struct dcn_ip_params *dcn_ip; 468 struct display_mode_lib dml; 469 #endif 470 471 /* HW functions */ 472 struct hw_sequencer_funcs hwss; 473 struct dce_hwseq *hwseq; 474 475 /* Require to optimize clocks and bandwidth for added/removed planes */ 476 bool optimized_required; 477 478 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 479 bool optimize_seamless_boot; 480 481 /* FBC compressor */ 482 struct compressor *fbc_compressor; 483 484 struct dc_debug_data debug_data; 485 486 const char *build_id; 487 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 488 struct vm_helper *vm_helper; 489 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 490 #endif 491 }; 492 493 enum frame_buffer_mode { 494 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 495 FRAME_BUFFER_MODE_ZFB_ONLY, 496 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 497 } ; 498 499 struct dchub_init_data { 500 int64_t zfb_phys_addr_base; 501 int64_t zfb_mc_base_addr; 502 uint64_t zfb_size_in_byte; 503 enum frame_buffer_mode fb_mode; 504 bool dchub_initialzied; 505 bool dchub_info_valid; 506 }; 507 508 struct dc_init_data { 509 struct hw_asic_id asic_id; 510 void *driver; /* ctx */ 511 struct cgs_device *cgs_device; 512 struct dc_bounding_box_overrides bb_overrides; 513 514 int num_virtual_links; 515 /* 516 * If 'vbios_override' not NULL, it will be called instead 517 * of the real VBIOS. Intended use is Diagnostics on FPGA. 518 */ 519 struct dc_bios *vbios_override; 520 enum dce_environment dce_environment; 521 522 struct dc_config flags; 523 uint32_t log_mask; 524 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 525 /** 526 * gpu_info FW provided soc bounding box struct or 0 if not 527 * available in FW 528 */ 529 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 530 #endif 531 }; 532 533 struct dc_callback_init { 534 uint8_t reserved; 535 }; 536 537 struct dc *dc_create(const struct dc_init_data *init_params); 538 int dc_get_vmid_use_vector(struct dc *dc); 539 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 540 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 541 /* Returns the number of vmids supported */ 542 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 543 #endif 544 void dc_init_callbacks(struct dc *dc, 545 const struct dc_callback_init *init_params); 546 void dc_destroy(struct dc **dc); 547 548 /******************************************************************************* 549 * Surface Interfaces 550 ******************************************************************************/ 551 552 enum { 553 TRANSFER_FUNC_POINTS = 1025 554 }; 555 556 struct dc_hdr_static_metadata { 557 /* display chromaticities and white point in units of 0.00001 */ 558 unsigned int chromaticity_green_x; 559 unsigned int chromaticity_green_y; 560 unsigned int chromaticity_blue_x; 561 unsigned int chromaticity_blue_y; 562 unsigned int chromaticity_red_x; 563 unsigned int chromaticity_red_y; 564 unsigned int chromaticity_white_point_x; 565 unsigned int chromaticity_white_point_y; 566 567 uint32_t min_luminance; 568 uint32_t max_luminance; 569 uint32_t maximum_content_light_level; 570 uint32_t maximum_frame_average_light_level; 571 }; 572 573 enum dc_transfer_func_type { 574 TF_TYPE_PREDEFINED, 575 TF_TYPE_DISTRIBUTED_POINTS, 576 TF_TYPE_BYPASS, 577 TF_TYPE_HWPWL 578 }; 579 580 struct dc_transfer_func_distributed_points { 581 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 582 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 583 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 584 585 uint16_t end_exponent; 586 uint16_t x_point_at_y1_red; 587 uint16_t x_point_at_y1_green; 588 uint16_t x_point_at_y1_blue; 589 }; 590 591 enum dc_transfer_func_predefined { 592 TRANSFER_FUNCTION_SRGB, 593 TRANSFER_FUNCTION_BT709, 594 TRANSFER_FUNCTION_PQ, 595 TRANSFER_FUNCTION_LINEAR, 596 TRANSFER_FUNCTION_UNITY, 597 TRANSFER_FUNCTION_HLG, 598 TRANSFER_FUNCTION_HLG12, 599 TRANSFER_FUNCTION_GAMMA22 600 }; 601 602 struct dc_transfer_func { 603 struct kref refcount; 604 enum dc_transfer_func_type type; 605 enum dc_transfer_func_predefined tf; 606 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 607 uint32_t sdr_ref_white_level; 608 struct dc_context *ctx; 609 union { 610 struct pwl_params pwl; 611 struct dc_transfer_func_distributed_points tf_pts; 612 }; 613 }; 614 615 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 616 617 618 struct dc_3dlut { 619 struct kref refcount; 620 struct tetrahedral_params lut_3d; 621 uint32_t hdr_multiplier; 622 bool initialized; 623 struct dc_context *ctx; 624 }; 625 #endif 626 /* 627 * This structure is filled in by dc_surface_get_status and contains 628 * the last requested address and the currently active address so the called 629 * can determine if there are any outstanding flips 630 */ 631 struct dc_plane_status { 632 struct dc_plane_address requested_address; 633 struct dc_plane_address current_address; 634 bool is_flip_pending; 635 bool is_right_eye; 636 }; 637 638 union surface_update_flags { 639 640 struct { 641 uint32_t addr_update:1; 642 /* Medium updates */ 643 uint32_t dcc_change:1; 644 uint32_t color_space_change:1; 645 uint32_t horizontal_mirror_change:1; 646 uint32_t per_pixel_alpha_change:1; 647 uint32_t global_alpha_change:1; 648 uint32_t sdr_white_level:1; 649 uint32_t rotation_change:1; 650 uint32_t swizzle_change:1; 651 uint32_t scaling_change:1; 652 uint32_t position_change:1; 653 uint32_t in_transfer_func_change:1; 654 uint32_t input_csc_change:1; 655 uint32_t coeff_reduction_change:1; 656 uint32_t output_tf_change:1; 657 uint32_t pixel_format_change:1; 658 uint32_t plane_size_change:1; 659 660 /* Full updates */ 661 uint32_t new_plane:1; 662 uint32_t bpp_change:1; 663 uint32_t gamma_change:1; 664 uint32_t bandwidth_change:1; 665 uint32_t clock_change:1; 666 uint32_t stereo_format_change:1; 667 uint32_t full_update:1; 668 } bits; 669 670 uint32_t raw; 671 }; 672 673 struct dc_plane_state { 674 struct dc_plane_address address; 675 struct dc_plane_flip_time time; 676 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 677 bool triplebuffer_flips; 678 #endif 679 struct scaling_taps scaling_quality; 680 struct rect src_rect; 681 struct rect dst_rect; 682 struct rect clip_rect; 683 684 union plane_size plane_size; 685 union dc_tiling_info tiling_info; 686 687 struct dc_plane_dcc_param dcc; 688 689 struct dc_gamma *gamma_correction; 690 struct dc_transfer_func *in_transfer_func; 691 struct dc_bias_and_scale *bias_and_scale; 692 struct dc_csc_transform input_csc_color_matrix; 693 struct fixed31_32 coeff_reduction_factor; 694 uint32_t sdr_white_level; 695 696 // TODO: No longer used, remove 697 struct dc_hdr_static_metadata hdr_static_ctx; 698 699 enum dc_color_space color_space; 700 701 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 702 struct dc_3dlut *lut3d_func; 703 struct dc_transfer_func *in_shaper_func; 704 struct dc_transfer_func *blend_tf; 705 #endif 706 707 enum surface_pixel_format format; 708 enum dc_rotation_angle rotation; 709 enum plane_stereo_format stereo_format; 710 711 bool is_tiling_rotated; 712 bool per_pixel_alpha; 713 bool global_alpha; 714 int global_alpha_value; 715 bool visible; 716 bool flip_immediate; 717 bool horizontal_mirror; 718 719 union surface_update_flags update_flags; 720 /* private to DC core */ 721 struct dc_plane_status status; 722 struct dc_context *ctx; 723 724 /* HACK: Workaround for forcing full reprogramming under some conditions */ 725 bool force_full_update; 726 727 /* private to dc_surface.c */ 728 enum dc_irq_source irq_source; 729 struct kref refcount; 730 }; 731 732 struct dc_plane_info { 733 union plane_size plane_size; 734 union dc_tiling_info tiling_info; 735 struct dc_plane_dcc_param dcc; 736 enum surface_pixel_format format; 737 enum dc_rotation_angle rotation; 738 enum plane_stereo_format stereo_format; 739 enum dc_color_space color_space; 740 unsigned int sdr_white_level; 741 bool horizontal_mirror; 742 bool visible; 743 bool per_pixel_alpha; 744 bool global_alpha; 745 int global_alpha_value; 746 bool input_csc_enabled; 747 }; 748 749 struct dc_scaling_info { 750 struct rect src_rect; 751 struct rect dst_rect; 752 struct rect clip_rect; 753 struct scaling_taps scaling_quality; 754 }; 755 756 struct dc_surface_update { 757 struct dc_plane_state *surface; 758 759 /* isr safe update parameters. null means no updates */ 760 const struct dc_flip_addrs *flip_addr; 761 const struct dc_plane_info *plane_info; 762 const struct dc_scaling_info *scaling_info; 763 764 /* following updates require alloc/sleep/spin that is not isr safe, 765 * null means no updates 766 */ 767 const struct dc_gamma *gamma; 768 const struct dc_transfer_func *in_transfer_func; 769 770 const struct dc_csc_transform *input_csc_color_matrix; 771 const struct fixed31_32 *coeff_reduction_factor; 772 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 773 const struct dc_transfer_func *func_shaper; 774 const struct dc_3dlut *lut3d_func; 775 const struct dc_transfer_func *blend_tf; 776 #endif 777 }; 778 779 /* 780 * Create a new surface with default parameters; 781 */ 782 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 783 const struct dc_plane_status *dc_plane_get_status( 784 const struct dc_plane_state *plane_state); 785 786 void dc_plane_state_retain(struct dc_plane_state *plane_state); 787 void dc_plane_state_release(struct dc_plane_state *plane_state); 788 789 void dc_gamma_retain(struct dc_gamma *dc_gamma); 790 void dc_gamma_release(struct dc_gamma **dc_gamma); 791 struct dc_gamma *dc_create_gamma(void); 792 793 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 794 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 795 struct dc_transfer_func *dc_create_transfer_func(void); 796 797 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 798 struct dc_3dlut *dc_create_3dlut_func(void); 799 void dc_3dlut_func_release(struct dc_3dlut *lut); 800 void dc_3dlut_func_retain(struct dc_3dlut *lut); 801 #endif 802 /* 803 * This structure holds a surface address. There could be multiple addresses 804 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 805 * as frame durations and DCC format can also be set. 806 */ 807 struct dc_flip_addrs { 808 struct dc_plane_address address; 809 unsigned int flip_timestamp_in_us; 810 bool flip_immediate; 811 /* TODO: add flip duration for FreeSync */ 812 }; 813 814 bool dc_post_update_surfaces_to_stream( 815 struct dc *dc); 816 817 #include "dc_stream.h" 818 819 /* 820 * Structure to store surface/stream associations for validation 821 */ 822 struct dc_validation_set { 823 struct dc_stream_state *stream; 824 struct dc_plane_state *plane_states[MAX_SURFACES]; 825 uint8_t plane_count; 826 }; 827 828 bool dc_validate_seamless_boot_timing(const struct dc *dc, 829 const struct dc_sink *sink, 830 struct dc_crtc_timing *crtc_timing); 831 832 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 833 834 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 835 836 /* 837 * fast_validate: we return after determining if we can support the new state, 838 * but before we populate the programming info 839 */ 840 enum dc_status dc_validate_global_state( 841 struct dc *dc, 842 struct dc_state *new_ctx, 843 bool fast_validate); 844 845 846 void dc_resource_state_construct( 847 const struct dc *dc, 848 struct dc_state *dst_ctx); 849 850 void dc_resource_state_copy_construct( 851 const struct dc_state *src_ctx, 852 struct dc_state *dst_ctx); 853 854 void dc_resource_state_copy_construct_current( 855 const struct dc *dc, 856 struct dc_state *dst_ctx); 857 858 void dc_resource_state_destruct(struct dc_state *context); 859 860 /* 861 * TODO update to make it about validation sets 862 * Set up streams and links associated to drive sinks 863 * The streams parameter is an absolute set of all active streams. 864 * 865 * After this call: 866 * Phy, Encoder, Timing Generator are programmed and enabled. 867 * New streams are enabled with blank stream; no memory read. 868 */ 869 bool dc_commit_state(struct dc *dc, struct dc_state *context); 870 871 872 struct dc_state *dc_create_state(struct dc *dc); 873 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 874 void dc_retain_state(struct dc_state *context); 875 void dc_release_state(struct dc_state *context); 876 877 /******************************************************************************* 878 * Link Interfaces 879 ******************************************************************************/ 880 881 struct dpcd_caps { 882 union dpcd_rev dpcd_rev; 883 union max_lane_count max_ln_count; 884 union max_down_spread max_down_spread; 885 union dprx_feature dprx_feature; 886 887 /* valid only for eDP v1.4 or higher*/ 888 uint8_t edp_supported_link_rates_count; 889 enum dc_link_rate edp_supported_link_rates[8]; 890 891 /* dongle type (DP converter, CV smart dongle) */ 892 enum display_dongle_type dongle_type; 893 /* branch device or sink device */ 894 bool is_branch_dev; 895 /* Dongle's downstream count. */ 896 union sink_count sink_count; 897 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 898 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 899 struct dc_dongle_caps dongle_caps; 900 901 uint32_t sink_dev_id; 902 int8_t sink_dev_id_str[6]; 903 int8_t sink_hw_revision; 904 int8_t sink_fw_revision[2]; 905 906 uint32_t branch_dev_id; 907 int8_t branch_dev_name[6]; 908 int8_t branch_hw_revision; 909 int8_t branch_fw_revision[2]; 910 911 bool allow_invalid_MSA_timing_param; 912 bool panel_mode_edp; 913 bool dpcd_display_control_capable; 914 bool ext_receiver_cap_field_present; 915 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 916 union dpcd_fec_capability fec_cap; 917 struct dpcd_dsc_capabilities dsc_caps; 918 #endif 919 }; 920 921 #include "dc_link.h" 922 923 /******************************************************************************* 924 * Sink Interfaces - A sink corresponds to a display output device 925 ******************************************************************************/ 926 927 struct dc_container_id { 928 // 128bit GUID in binary form 929 unsigned char guid[16]; 930 // 8 byte port ID -> ELD.PortID 931 unsigned int portId[2]; 932 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 933 unsigned short manufacturerName; 934 // 2 byte product code -> ELD.ProductCode 935 unsigned short productCode; 936 }; 937 938 939 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 940 struct dc_sink_dsc_caps { 941 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 942 // 'false' if they are sink's DSC caps 943 bool is_virtual_dpcd_dsc; 944 struct dsc_dec_dpcd_caps dsc_dec_caps; 945 }; 946 #endif 947 948 /* 949 * The sink structure contains EDID and other display device properties 950 */ 951 struct dc_sink { 952 enum signal_type sink_signal; 953 struct dc_edid dc_edid; /* raw edid */ 954 struct dc_edid_caps edid_caps; /* parse display caps */ 955 struct dc_container_id *dc_container_id; 956 uint32_t dongle_max_pix_clk; 957 void *priv; 958 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 959 bool converter_disable_audio; 960 961 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 962 struct dc_sink_dsc_caps sink_dsc_caps; 963 #endif 964 965 /* private to DC core */ 966 struct dc_link *link; 967 struct dc_context *ctx; 968 969 uint32_t sink_id; 970 971 /* private to dc_sink.c */ 972 // refcount must be the last member in dc_sink, since we want the 973 // sink structure to be logically cloneable up to (but not including) 974 // refcount 975 struct kref refcount; 976 }; 977 978 void dc_sink_retain(struct dc_sink *sink); 979 void dc_sink_release(struct dc_sink *sink); 980 981 struct dc_sink_init_data { 982 enum signal_type sink_signal; 983 struct dc_link *link; 984 uint32_t dongle_max_pix_clk; 985 bool converter_disable_audio; 986 }; 987 988 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 989 990 /* Newer interfaces */ 991 struct dc_cursor { 992 struct dc_plane_address address; 993 struct dc_cursor_attributes attributes; 994 }; 995 996 997 /******************************************************************************* 998 * Interrupt interfaces 999 ******************************************************************************/ 1000 enum dc_irq_source dc_interrupt_to_irq_source( 1001 struct dc *dc, 1002 uint32_t src_id, 1003 uint32_t ext_id); 1004 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1005 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1006 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1007 struct dc *dc, uint32_t link_index); 1008 1009 /******************************************************************************* 1010 * Power Interfaces 1011 ******************************************************************************/ 1012 1013 void dc_set_power_state( 1014 struct dc *dc, 1015 enum dc_acpi_cm_power_state power_state); 1016 void dc_resume(struct dc *dc); 1017 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1018 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1019 1020 bool dc_is_dmcu_initialized(struct dc *dc); 1021 1022 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1023 /******************************************************************************* 1024 * DSC Interfaces 1025 ******************************************************************************/ 1026 #include "dc_dsc.h" 1027 #endif 1028 #endif /* DC_INTERFACE_H_ */ 1029