1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2_0/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "dml/dml1_frl_cap_chk.h" 50 51 #include "sspl/dc_spl_types.h" 52 53 struct abm_save_restore; 54 55 /* forward declaration */ 56 struct aux_payload; 57 struct set_config_cmd_payload; 58 struct dmub_notification; 59 struct dcn_hubbub_reg_state; 60 struct dcn_hubp_reg_state; 61 struct dcn_dpp_reg_state; 62 struct dcn_mpc_reg_state; 63 struct dcn_opp_reg_state; 64 struct dcn_dsc_reg_state; 65 struct dcn_optc_reg_state; 66 struct dcn_dccg_reg_state; 67 68 #define DC_VER "3.2.388" 69 70 /** 71 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 72 */ 73 #define MAX_SURFACES 4 74 /** 75 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 76 */ 77 #define MAX_PLANES 6 78 #define MAX_STREAMS 6 79 #define MIN_VIEWPORT_SIZE 12 80 #define MAX_NUM_EDP 2 81 #define MAX_SUPPORTED_FORMATS 7 82 83 #define MAX_HOST_ROUTERS_NUM 3 84 #define MAX_DPIA_PER_HOST_ROUTER 3 85 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 86 87 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 88 89 struct frl_cap_chk_intermediates_fixed31_32 { 90 int c_frl_sb; 91 struct fixed31_32 overhead_sb; 92 struct fixed31_32 overhead_rs; 93 struct fixed31_32 overhead_map; 94 struct fixed31_32 overhead_min; 95 struct fixed31_32 overhead_max; 96 struct fixed31_32 f_pixel_clock_max; 97 struct fixed31_32 t_line; 98 struct fixed31_32 r_bit_min; 99 struct fixed31_32 r_frl_char_min; 100 struct fixed31_32 c_frl_line; 101 struct fixed31_32 ap; 102 struct fixed31_32 r_ap; 103 struct fixed31_32 avg_audio_packets_line; 104 struct fixed31_32 margin; 105 int audio_packets_line; 106 int blank_audio_min; 107 }; 108 109 struct frl_cap_chk_params_fixed31_32 { 110 int lanes; 111 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 112 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ 113 int audio_packet_type; 114 struct fixed31_32 f_audio; /* Audio rate (Hz) */ 115 int h_active; /* Active pixels per line */ 116 int h_blank; /* Blanking pixels per line */ 117 int bpc; /* Bits per component */ 118 int vic; /* Video Identification Code */ 119 120 enum hdmi_frl_pixel_encoding pixel_encoding; 121 122 bool compressed; /* set to true if DSC is enabled */ 123 bool bypass_hc_target_calc; /* debug only */ 124 bool allow_all_bpp; /* dsc_all_bpp */ 125 126 /* DSC parameters */ 127 int slices; 128 int slice_width; 129 struct fixed31_32 bpp_target; 130 int layout; 131 int acat; /* not supported */ 132 133 /* outputs */ 134 struct frl_dml_borrow_params borrow_params; 135 int average_tribyte_rate; 136 }; 137 138 /* Display Core Interfaces */ 139 struct dc_versions { 140 const char *dc_ver; 141 struct dmcu_version dmcu_version; 142 }; 143 144 enum dp_protocol_version { 145 DP_VERSION_1_4 = 0, 146 DP_VERSION_2_1, 147 DP_VERSION_UNKNOWN, 148 }; 149 150 enum dc_plane_type { 151 DC_PLANE_TYPE_INVALID, 152 DC_PLANE_TYPE_DCE_RGB, 153 DC_PLANE_TYPE_DCE_UNDERLAY, 154 DC_PLANE_TYPE_DCN_UNIVERSAL, 155 }; 156 157 // Sizes defined as multiples of 64KB 158 enum det_size { 159 DET_SIZE_DEFAULT = 0, 160 DET_SIZE_192KB = 3, 161 DET_SIZE_256KB = 4, 162 DET_SIZE_320KB = 5, 163 DET_SIZE_384KB = 6 164 }; 165 166 167 struct dc_plane_cap { 168 enum dc_plane_type type; 169 uint32_t per_pixel_alpha : 1; 170 struct { 171 uint32_t argb8888 : 1; 172 uint32_t nv12 : 1; 173 uint32_t fp16 : 1; 174 uint32_t p010 : 1; 175 uint32_t ayuv : 1; 176 } pixel_format_support; 177 // max upscaling factor x1000 178 // upscaling factors are always >= 1 179 // for example, 1080p -> 8K is 4.0, or 4000 raw value 180 struct { 181 uint32_t argb8888; 182 uint32_t nv12; 183 uint32_t fp16; 184 } max_upscale_factor; 185 // max downscale factor x1000 186 // downscale factors are always <= 1 187 // for example, 8K -> 1080p is 0.25, or 250 raw value 188 struct { 189 uint32_t argb8888; 190 uint32_t nv12; 191 uint32_t fp16; 192 } max_downscale_factor; 193 // minimal width/height 194 uint32_t min_width; 195 uint32_t min_height; 196 }; 197 198 /** 199 * DOC: color-management-caps 200 * 201 * **Color management caps (DPP and MPC)** 202 * 203 * Modules/color calculates various color operations which are translated to 204 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 205 * DCN1, every new generation comes with fairly major differences in color 206 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 207 * decide mapping to HW block based on logical capabilities. 208 */ 209 210 /** 211 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 212 * @srgb: RGB color space transfer func 213 * @bt2020: BT.2020 transfer func 214 * @gamma2_2: standard gamma 215 * @pq: perceptual quantizer transfer function 216 * @hlg: hybrid log–gamma transfer function 217 */ 218 struct rom_curve_caps { 219 uint16_t srgb : 1; 220 uint16_t bt2020 : 1; 221 uint16_t gamma2_2 : 1; 222 uint16_t pq : 1; 223 uint16_t hlg : 1; 224 }; 225 226 /** 227 * struct dpp_color_caps - color pipeline capabilities for display pipe and 228 * plane blocks 229 * 230 * @dcn_arch: all DCE generations treated the same 231 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 232 * just plain 256-entry lookup 233 * @icsc: input color space conversion 234 * @dgam_ram: programmable degamma LUT 235 * @post_csc: post color space conversion, before gamut remap 236 * @gamma_corr: degamma correction 237 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 238 * with MPC by setting mpc:shared_3d_lut flag 239 * @ogam_ram: programmable out/blend gamma LUT 240 * @ocsc: output color space conversion 241 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 242 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 243 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 244 * 245 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 246 */ 247 struct dpp_color_caps { 248 uint16_t dcn_arch : 1; 249 uint16_t input_lut_shared : 1; 250 uint16_t icsc : 1; 251 uint16_t dgam_ram : 1; 252 uint16_t post_csc : 1; 253 uint16_t gamma_corr : 1; 254 uint16_t hw_3d_lut : 1; 255 uint16_t ogam_ram : 1; 256 uint16_t ocsc : 1; 257 uint16_t dgam_rom_for_yuv : 1; 258 struct rom_curve_caps dgam_rom_caps; 259 struct rom_curve_caps ogam_rom_caps; 260 }; 261 262 /* Below structure is to describe the HW support for mem layout, extend support 263 range to match what OS could handle in the roadmap */ 264 struct lut3d_caps { 265 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 266 struct { 267 uint32_t swizzle_3d_rgb : 1; 268 uint32_t swizzle_3d_bgr : 1; 269 uint32_t linear_1d : 1; 270 } mem_layout_support; 271 struct { 272 uint32_t unorm_12msb : 1; 273 uint32_t unorm_12lsb : 1; 274 uint32_t float_fp1_5_10 : 1; 275 } mem_format_support; 276 struct { 277 uint32_t order_rgba : 1; 278 uint32_t order_bgra : 1; 279 } mem_pixel_order_support; 280 /*< size options are 9, 17, 33, 45, 65 */ 281 struct { 282 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 283 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 284 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 285 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 286 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 287 } lut_dim_caps; 288 }; 289 290 /** 291 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 292 * plane combined blocks 293 * 294 * @gamut_remap: color transformation matrix 295 * @ogam_ram: programmable out gamma LUT 296 * @ocsc: output color space conversion matrix 297 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 298 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 299 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 300 * instance 301 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 302 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 303 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 304 * @preblend: whether color manager supports preblend with MPC 305 */ 306 struct mpc_color_caps { 307 uint16_t gamut_remap : 1; 308 uint16_t ogam_ram : 1; 309 uint16_t ocsc : 1; 310 uint16_t num_3dluts : 3; 311 uint16_t num_rmcm_3dluts : 3; 312 uint16_t shared_3d_lut:1; 313 struct rom_curve_caps ogam_rom_caps; 314 struct lut3d_caps mcm_3d_lut_caps; 315 struct lut3d_caps rmcm_3d_lut_caps; 316 bool preblend; 317 }; 318 319 /** 320 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 321 * @dpp: color pipes caps for DPP 322 * @mpc: color pipes caps for MPC 323 */ 324 struct dc_color_caps { 325 struct dpp_color_caps dpp; 326 struct mpc_color_caps mpc; 327 }; 328 329 struct dc_dmub_caps { 330 bool psr; 331 bool mclk_sw; 332 bool subvp_psr; 333 bool gecc_enable; 334 uint8_t fams_ver; 335 bool aux_backlight_support; 336 }; 337 338 struct dc_scl_caps { 339 bool sharpener_support; 340 }; 341 342 struct dc_check_config { 343 /** 344 * max video plane width that can be safely assumed to be always 345 * supported by single DPP pipe. 346 */ 347 unsigned int max_optimizable_video_width; 348 bool enable_legacy_fast_update; 349 350 bool deferred_transition_state; 351 unsigned int transition_countdown_to_steady_state; 352 }; 353 354 struct dc_caps { 355 uint32_t max_streams; 356 uint32_t max_links; 357 uint32_t max_audios; 358 uint32_t max_slave_planes; 359 uint32_t max_slave_yuv_planes; 360 uint32_t max_slave_rgb_planes; 361 uint32_t max_planes; 362 uint32_t max_downscale_ratio; 363 uint32_t i2c_speed_in_khz; 364 uint32_t i2c_speed_in_khz_hdcp; 365 uint32_t dmdata_alloc_size; 366 unsigned int max_cursor_size; 367 unsigned int max_buffered_cursor_size; 368 unsigned int max_video_width; 369 unsigned int min_horizontal_blanking_period; 370 int linear_pitch_alignment; 371 bool dcc_const_color; 372 bool dynamic_audio; 373 bool is_apu; 374 bool dual_link_dvi; 375 bool post_blend_color_processing; 376 bool force_dp_tps4_for_cp2520; 377 bool disable_dp_clk_share; 378 bool psp_setup_panel_mode; 379 bool extended_aux_timeout_support; 380 bool dmcub_support; 381 bool zstate_support; 382 bool ips_support; 383 bool ips_v2_support; 384 uint32_t num_of_internal_disp; 385 enum dp_protocol_version max_dp_protocol_version; 386 bool hdmi_hpo; 387 unsigned int mall_size_per_mem_channel; 388 unsigned int mall_size_total; 389 unsigned int cursor_cache_size; 390 struct dc_plane_cap planes[MAX_PLANES]; 391 struct dc_color_caps color; 392 struct dc_dmub_caps dmub_caps; 393 bool dp_hpo; 394 bool dp_hdmi21_pcon_support; 395 bool edp_dsc_support; 396 bool vbios_lttpr_aware; 397 bool vbios_lttpr_enable; 398 bool fused_io_supported; 399 uint32_t max_otg_num; 400 uint32_t max_cab_allocation_bytes; 401 uint32_t cache_line_size; 402 uint32_t cache_num_ways; 403 uint16_t subvp_fw_processing_delay_us; 404 uint8_t subvp_drr_max_vblank_margin_us; 405 uint16_t subvp_prefetch_end_to_mall_start_us; 406 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 407 uint16_t subvp_pstate_allow_width_us; 408 uint16_t subvp_vertical_int_margin_us; 409 bool seamless_odm; 410 uint32_t max_v_total; 411 bool vtotal_limited_by_fp2; 412 uint32_t max_disp_clock_khz_at_vmin; 413 uint8_t subvp_drr_vblank_start_margin_us; 414 bool cursor_not_scaled; 415 bool dcmode_power_limits_present; 416 bool sequential_ono; 417 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 418 uint32_t dcc_plane_width_limit; 419 struct dc_scl_caps scl_caps; 420 uint8_t num_of_host_routers; 421 uint8_t num_of_dpias_per_host_router; 422 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 423 uint8_t max_odm_combine_factor; 424 }; 425 426 struct dc_bug_wa { 427 bool no_connect_phy_config; 428 bool dedcn20_305_wa; 429 bool skip_clock_update; 430 bool lt_early_cr_pattern; 431 struct { 432 uint8_t uclk : 1; 433 uint8_t fclk : 1; 434 uint8_t dcfclk : 1; 435 uint8_t dcfclk_ds: 1; 436 } clock_update_disable_mask; 437 bool skip_psr_ips_crtc_disable; 438 }; 439 struct dc_dcc_surface_param { 440 struct dc_size surface_size; 441 enum surface_pixel_format format; 442 unsigned int plane0_pitch; 443 struct dc_size plane1_size; 444 unsigned int plane1_pitch; 445 union { 446 enum swizzle_mode_values swizzle_mode; 447 enum swizzle_mode_addr3_values swizzle_mode_addr3; 448 }; 449 enum dc_scan_direction scan; 450 }; 451 452 struct dc_dcc_setting { 453 unsigned int max_compressed_blk_size; 454 unsigned int max_uncompressed_blk_size; 455 bool independent_64b_blks; 456 //These bitfields to be used starting with DCN 3.0 457 struct { 458 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 459 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 460 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 461 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 462 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 463 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 464 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 465 } dcc_controls; 466 }; 467 468 struct dc_surface_dcc_cap { 469 union { 470 struct { 471 struct dc_dcc_setting rgb; 472 } grph; 473 474 struct { 475 struct dc_dcc_setting luma; 476 struct dc_dcc_setting chroma; 477 } video; 478 }; 479 480 bool capable; 481 bool const_color_support; 482 }; 483 484 struct dc_static_screen_params { 485 struct { 486 bool force_trigger; 487 bool cursor_update; 488 bool surface_update; 489 bool overlay_update; 490 } triggers; 491 unsigned int num_frames; 492 }; 493 494 495 /* Surface update type is used by dc_update_surfaces_and_stream 496 * The update type is determined at the very beginning of the function based 497 * on parameters passed in and decides how much programming (or updating) is 498 * going to be done during the call. 499 * 500 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 501 * logical calculations or hardware register programming. This update MUST be 502 * ISR safe on windows. Currently fast update will only be used to flip surface 503 * address. 504 * 505 * UPDATE_TYPE_MED is used for slower updates which require significant hw 506 * re-programming however do not affect bandwidth consumption or clock 507 * requirements. At present, this is the level at which front end updates 508 * that do not require us to run bw_calcs happen. These are in/out transfer func 509 * updates, viewport offset changes, recout size changes and pixel depth changes. 510 * This update can be done at ISR, but we want to minimize how often this happens. 511 * 512 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 513 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 514 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 515 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 516 * a full update. This cannot be done at ISR level and should be a rare event. 517 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 518 * underscan we don't expect to see this call at all. 519 */ 520 521 enum surface_update_type { 522 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 523 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 524 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 525 }; 526 527 enum dc_lock_descriptor { 528 LOCK_DESCRIPTOR_NONE = 0x0, 529 LOCK_DESCRIPTOR_STREAM = 0x1, 530 LOCK_DESCRIPTOR_LINK = 0x2, 531 LOCK_DESCRIPTOR_GLOBAL = 0x4, 532 }; 533 534 struct surface_update_descriptor { 535 enum surface_update_type update_type; 536 enum dc_lock_descriptor lock_descriptor; 537 }; 538 539 /* Forward declaration*/ 540 struct dc; 541 struct dc_plane_state; 542 struct dc_state; 543 544 struct dc_cap_funcs { 545 bool (*get_dcc_compression_cap)(const struct dc *dc, 546 const struct dc_dcc_surface_param *input, 547 struct dc_surface_dcc_cap *output); 548 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 549 }; 550 551 struct link_training_settings; 552 553 union allow_lttpr_non_transparent_mode { 554 struct { 555 bool DP1_4A : 1; 556 bool DP2_0 : 1; 557 } bits; 558 unsigned char raw; 559 }; 560 /* Structure to hold configuration flags set by dm at dc creation. */ 561 struct dc_config { 562 bool gpu_vm_support; 563 bool disable_disp_pll_sharing; 564 bool fbc_support; 565 bool disable_fractional_pwm; 566 bool allow_seamless_boot_optimization; 567 bool seamless_boot_edp_requested; 568 bool edp_not_connected; 569 bool edp_no_power_sequencing; 570 bool force_enum_edp; 571 bool forced_clocks; 572 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 573 bool multi_mon_pp_mclk_switch; 574 bool disable_dmcu; 575 bool allow_4to1MPC; 576 bool enable_windowed_mpo_odm; 577 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 578 uint32_t allow_edp_hotplug_detection; 579 bool skip_riommu_prefetch_wa; 580 bool clamp_min_dcfclk; 581 uint64_t vblank_alignment_dto_params; 582 uint8_t vblank_alignment_max_frame_time_diff; 583 bool is_asymmetric_memory; 584 bool is_single_rank_dimm; 585 bool is_vmin_only_asic; 586 bool use_spl; 587 bool prefer_easf; 588 bool use_pipe_ctx_sync_logic; 589 int smart_mux_version; 590 bool ignore_dpref_ss; 591 bool enable_mipi_converter_optimization; 592 bool enable_frl; 593 bool force_hdmi21_frl_enc_enable; 594 bool use_default_clock_table; 595 bool force_bios_enable_lttpr; 596 uint8_t force_bios_fixed_vs; 597 unsigned int sdpif_request_limit_words_per_umc; 598 bool dc_mode_clk_limit_support; 599 bool EnableMinDispClkODM; 600 bool enable_auto_dpm_test_logs; 601 unsigned int disable_ips; 602 unsigned int disable_ips_rcg; 603 unsigned int disable_ips_in_vpb; 604 bool disable_ips_in_dpms_off; 605 bool usb4_bw_alloc_support; 606 bool allow_0_dtb_clk; 607 bool use_assr_psp_message; 608 bool support_edp0_on_dp1; 609 unsigned int enable_fpo_flicker_detection; 610 bool disable_hbr_audio_dp2; 611 bool consolidated_dpia_dp_lt; 612 bool set_pipe_unlock_order; 613 bool enable_dpia_pre_training; 614 bool unify_link_enc_assignment; 615 bool enable_cursor_offload; 616 bool dp_connector_no_native_i2c; 617 bool frame_update_cmd_version2; 618 struct spl_sharpness_range dcn_sharpness_range; 619 struct spl_sharpness_range dcn_override_sharpness_range; 620 bool no_native422_support; 621 }; 622 623 enum visual_confirm { 624 VISUAL_CONFIRM_DISABLE = 0, 625 VISUAL_CONFIRM_SURFACE = 1, 626 VISUAL_CONFIRM_HDR = 2, 627 VISUAL_CONFIRM_MPCTREE = 4, 628 VISUAL_CONFIRM_PSR = 5, 629 VISUAL_CONFIRM_SWAPCHAIN = 6, 630 VISUAL_CONFIRM_FAMS = 7, 631 VISUAL_CONFIRM_SWIZZLE = 9, 632 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 633 VISUAL_CONFIRM_REPLAY = 12, 634 VISUAL_CONFIRM_SUBVP = 14, 635 VISUAL_CONFIRM_MCLK_SWITCH = 16, 636 VISUAL_CONFIRM_FAMS2 = 19, 637 VISUAL_CONFIRM_HW_CURSOR = 20, 638 VISUAL_CONFIRM_VABC = 21, 639 VISUAL_CONFIRM_DCC = 22, 640 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, 641 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 642 }; 643 644 enum dc_psr_power_opts { 645 psr_power_opt_invalid = 0x0, 646 psr_power_opt_smu_opt_static_screen = 0x1, 647 psr_power_opt_z10_static_screen = 0x10, 648 psr_power_opt_ds_disable_allow = 0x100, 649 }; 650 651 enum dml_hostvm_override_opts { 652 DML_HOSTVM_NO_OVERRIDE = 0x0, 653 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 654 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 655 }; 656 657 enum dc_replay_power_opts { 658 replay_power_opt_invalid = 0x0, 659 replay_power_opt_smu_opt_static_screen = 0x1, 660 replay_power_opt_z10_static_screen = 0x10, 661 }; 662 663 enum dcc_option { 664 DCC_ENABLE = 0, 665 DCC_DISABLE = 1, 666 DCC_HALF_REQ_DISALBE = 2, 667 }; 668 669 enum in_game_fams_config { 670 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 671 INGAME_FAMS_DISABLE, // disable in-game fams 672 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 673 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 674 }; 675 676 /** 677 * enum pipe_split_policy - Pipe split strategy supported by DCN 678 * 679 * This enum is used to define the pipe split policy supported by DCN. By 680 * default, DC favors MPC_SPLIT_DYNAMIC. 681 */ 682 enum pipe_split_policy { 683 /** 684 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 685 * pipe in order to bring the best trade-off between performance and 686 * power consumption. This is the recommended option. 687 */ 688 MPC_SPLIT_DYNAMIC = 0, 689 690 /** 691 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 692 * try any sort of split optimization. 693 */ 694 MPC_SPLIT_AVOID = 1, 695 696 /** 697 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 698 * optimize the pipe utilization when using a single display; if the 699 * user connects to a second display, DC will avoid pipe split. 700 */ 701 MPC_SPLIT_AVOID_MULT_DISP = 2, 702 }; 703 704 enum wm_report_mode { 705 WM_REPORT_DEFAULT = 0, 706 WM_REPORT_OVERRIDE = 1, 707 }; 708 enum dtm_pstate{ 709 dtm_level_p0 = 0,/*highest voltage*/ 710 dtm_level_p1, 711 dtm_level_p2, 712 dtm_level_p3, 713 dtm_level_p4,/*when active_display_count = 0*/ 714 }; 715 716 enum dcn_pwr_state { 717 DCN_PWR_STATE_UNKNOWN = -1, 718 DCN_PWR_STATE_MISSION_MODE = 0, 719 DCN_PWR_STATE_LOW_POWER = 3, 720 }; 721 722 enum dcn_zstate_support_state { 723 DCN_ZSTATE_SUPPORT_UNKNOWN, 724 DCN_ZSTATE_SUPPORT_ALLOW, 725 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 726 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 727 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 728 DCN_ZSTATE_SUPPORT_DISALLOW, 729 }; 730 731 /* 732 * struct dc_clocks - DC pipe clocks 733 * 734 * For any clocks that may differ per pipe only the max is stored in this 735 * structure 736 */ 737 struct dc_clocks { 738 int dispclk_khz; 739 int actual_dispclk_khz; 740 int dppclk_khz; 741 int actual_dppclk_khz; 742 int disp_dpp_voltage_level_khz; 743 int dcfclk_khz; 744 int socclk_khz; 745 int dcfclk_deep_sleep_khz; 746 int fclk_khz; 747 int phyclk_khz; 748 int dramclk_khz; 749 bool p_state_change_support; 750 enum dcn_zstate_support_state zstate_support; 751 bool dtbclk_en; 752 int ref_dtbclk_khz; 753 bool fclk_p_state_change_support; 754 enum dcn_pwr_state pwr_state; 755 /* 756 * Elements below are not compared for the purposes of 757 * optimization required 758 */ 759 bool prev_p_state_change_support; 760 bool fclk_prev_p_state_change_support; 761 int num_ways; 762 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 763 764 /* 765 * @fw_based_mclk_switching 766 * 767 * DC has a mechanism that leverage the variable refresh rate to switch 768 * memory clock in cases that we have a large latency to achieve the 769 * memory clock change and a short vblank window. DC has some 770 * requirements to enable this feature, and this field describes if the 771 * system support or not such a feature. 772 */ 773 bool fw_based_mclk_switching; 774 bool fw_based_mclk_switching_shut_down; 775 int prev_num_ways; 776 enum dtm_pstate dtm_level; 777 int max_supported_dppclk_khz; 778 int max_supported_dispclk_khz; 779 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 780 int bw_dispclk_khz; 781 int idle_dramclk_khz; 782 int idle_fclk_khz; 783 int subvp_prefetch_dramclk_khz; 784 int subvp_prefetch_fclk_khz; 785 786 /* Stutter efficiency is technically not clock values 787 * but stored here so the values are part of the update_clocks call similar to num_ways 788 * Efficiencies are stored as percentage (0-100) 789 */ 790 struct { 791 uint8_t base_efficiency; //LP1 792 uint8_t low_power_efficiency; //LP2 793 uint8_t z8_stutter_efficiency; 794 int z8_stutter_period; 795 } stutter_efficiency; 796 }; 797 798 struct dc_bw_validation_profile { 799 bool enable; 800 801 unsigned long long total_ticks; 802 unsigned long long voltage_level_ticks; 803 unsigned long long watermark_ticks; 804 unsigned long long rq_dlg_ticks; 805 806 unsigned long long total_count; 807 unsigned long long skip_fast_count; 808 unsigned long long skip_pass_count; 809 unsigned long long skip_fail_count; 810 }; 811 812 #define BW_VAL_TRACE_SETUP() \ 813 unsigned long long end_tick = 0; \ 814 unsigned long long voltage_level_tick = 0; \ 815 unsigned long long watermark_tick = 0; \ 816 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 817 dm_get_timestamp(dc->ctx) : 0 818 819 #define BW_VAL_TRACE_COUNT() \ 820 if (dc->debug.bw_val_profile.enable) \ 821 dc->debug.bw_val_profile.total_count++ 822 823 #define BW_VAL_TRACE_SKIP(status) \ 824 if (dc->debug.bw_val_profile.enable) { \ 825 if (!voltage_level_tick) \ 826 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 827 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 828 } 829 830 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 831 if (dc->debug.bw_val_profile.enable) \ 832 voltage_level_tick = dm_get_timestamp(dc->ctx) 833 834 #define BW_VAL_TRACE_END_WATERMARKS() \ 835 if (dc->debug.bw_val_profile.enable) \ 836 watermark_tick = dm_get_timestamp(dc->ctx) 837 838 #define BW_VAL_TRACE_FINISH() \ 839 if (dc->debug.bw_val_profile.enable) { \ 840 end_tick = dm_get_timestamp(dc->ctx); \ 841 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 842 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 843 if (watermark_tick) { \ 844 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 845 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 846 } \ 847 } 848 849 union mem_low_power_enable_options { 850 struct { 851 bool vga: 1; 852 bool i2c: 1; 853 bool dmcu: 1; 854 bool dscl: 1; 855 bool cm: 1; 856 bool mpc: 1; 857 bool optc: 1; 858 bool vpg: 1; 859 bool afmt: 1; 860 } bits; 861 uint32_t u32All; 862 }; 863 864 union root_clock_optimization_options { 865 struct { 866 bool dpp: 1; 867 bool dsc: 1; 868 bool hdmistream: 1; 869 bool hdmichar: 1; 870 bool dpstream: 1; 871 bool symclk32_se: 1; 872 bool symclk32_le: 1; 873 bool symclk_fe: 1; 874 bool physymclk: 1; 875 bool dpiasymclk: 1; 876 uint32_t reserved: 22; 877 } bits; 878 uint32_t u32All; 879 }; 880 881 union fine_grain_clock_gating_enable_options { 882 struct { 883 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 884 bool dchub : 1; /* Display controller hub */ 885 bool dchubbub : 1; 886 bool dpp : 1; /* Display pipes and planes */ 887 bool opp : 1; /* Output pixel processing */ 888 bool optc : 1; /* Output pipe timing combiner */ 889 bool dio : 1; /* Display output */ 890 bool dwb : 1; /* Display writeback */ 891 bool mmhubbub : 1; /* Multimedia hub */ 892 bool dmu : 1; /* Display core management unit */ 893 bool az : 1; /* Azalia */ 894 bool dchvm : 1; 895 bool dsc : 1; /* Display stream compression */ 896 897 uint32_t reserved : 19; 898 } bits; 899 uint32_t u32All; 900 }; 901 902 enum pg_hw_pipe_resources { 903 PG_HUBP = 0, 904 PG_DPP, 905 PG_DSC, 906 PG_MPCC, 907 PG_OPP, 908 PG_OPTC, 909 PG_DPSTREAM, 910 PG_HDMISTREAM, 911 PG_PHYSYMCLK, 912 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 913 }; 914 915 enum pg_hw_resources { 916 PG_DCCG = 0, 917 PG_DCIO, 918 PG_DIO, 919 PG_DCHUBBUB, 920 PG_DCHVM, 921 PG_DWB, 922 PG_HPO, 923 PG_DCOH, 924 PG_HW_RESOURCES_NUM_ELEMENT 925 }; 926 927 struct pg_block_update { 928 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 929 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 930 }; 931 932 union dpia_debug_options { 933 struct { 934 uint32_t disable_dpia:1; /* bit 0 */ 935 uint32_t force_non_lttpr:1; /* bit 1 */ 936 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 937 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 938 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 939 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 940 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 941 uint32_t reserved:25; 942 } bits; 943 uint32_t raw; 944 }; 945 946 /* AUX wake work around options 947 * 0: enable/disable work around 948 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 949 * 15-2: reserved 950 * 31-16: timeout in ms 951 */ 952 union aux_wake_wa_options { 953 struct { 954 uint32_t enable_wa : 1; 955 uint32_t use_default_timeout : 1; 956 uint32_t rsvd: 14; 957 uint32_t timeout_ms : 16; 958 } bits; 959 uint32_t raw; 960 }; 961 962 struct dc_debug_data { 963 uint32_t ltFailCount; 964 uint32_t i2cErrorCount; 965 uint32_t auxErrorCount; 966 struct pipe_topology_history topology_history; 967 }; 968 969 struct dc_phy_addr_space_config { 970 struct { 971 uint64_t start_addr; 972 uint64_t end_addr; 973 uint64_t fb_top; 974 uint64_t fb_offset; 975 uint64_t fb_base; 976 uint64_t agp_top; 977 uint64_t agp_bot; 978 uint64_t agp_base; 979 } system_aperture; 980 981 struct { 982 uint64_t page_table_start_addr; 983 uint64_t page_table_end_addr; 984 uint64_t page_table_base_addr; 985 bool base_addr_is_mc_addr; 986 } gart_config; 987 988 bool valid; 989 bool is_hvm_enabled; 990 uint64_t page_table_default_page_addr; 991 }; 992 993 struct dc_virtual_addr_space_config { 994 uint64_t page_table_base_addr; 995 uint64_t page_table_start_addr; 996 uint64_t page_table_end_addr; 997 uint32_t page_table_block_size_in_bytes; 998 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 999 }; 1000 1001 struct dc_bounding_box_overrides { 1002 unsigned int sr_exit_time_ns; 1003 unsigned int sr_enter_plus_exit_time_ns; 1004 unsigned int sr_exit_z8_time_ns; 1005 unsigned int sr_enter_plus_exit_z8_time_ns; 1006 unsigned int urgent_latency_ns; 1007 unsigned int percent_of_ideal_drambw; 1008 unsigned int dram_clock_change_latency_ns; 1009 unsigned int dummy_clock_change_latency_ns; 1010 unsigned int fclk_clock_change_latency_ns; 1011 /* This forces a hard min on the DCFCLK we use 1012 * for DML. Unlike the debug option for forcing 1013 * DCFCLK, this override affects watermark calculations 1014 */ 1015 unsigned int min_dcfclk_mhz; 1016 }; 1017 1018 struct dc_qos_info { 1019 uint32_t actual_peak_bw_in_mbps; 1020 uint32_t qos_bandwidth_lb_in_mbps; 1021 uint32_t actual_avg_bw_in_mbps; 1022 uint32_t calculated_avg_bw_in_mbps; 1023 uint32_t actual_max_latency_in_ns; 1024 uint32_t actual_min_latency_in_ns; 1025 uint32_t qos_max_latency_ub_in_ns; 1026 uint32_t actual_avg_latency_in_ns; 1027 uint32_t qos_avg_latency_ub_in_ns; 1028 uint32_t dcn_bandwidth_ub_in_mbps; 1029 uint32_t qos_max_bw_budget_in_mbps; 1030 }; 1031 1032 struct dc_state; 1033 struct resource_pool; 1034 struct dce_hwseq; 1035 struct link_service; 1036 1037 /* 1038 * struct dc_debug_options - DC debug struct 1039 * 1040 * This struct provides a simple mechanism for developers to change some 1041 * configurations, enable/disable features, and activate extra debug options. 1042 * This can be very handy to narrow down whether some specific feature is 1043 * causing an issue or not. 1044 */ 1045 struct dc_debug_options { 1046 bool disable_dsc; 1047 enum visual_confirm visual_confirm; 1048 unsigned int visual_confirm_rect_height; 1049 1050 bool sanity_checks; 1051 bool max_disp_clk; 1052 bool surface_trace; 1053 bool clock_trace; 1054 bool validation_trace; 1055 bool bandwidth_calcs_trace; 1056 int max_downscale_src_width; 1057 1058 /* stutter efficiency related */ 1059 bool disable_stutter; 1060 bool use_max_lb; 1061 enum dcc_option disable_dcc; 1062 1063 /* 1064 * @pipe_split_policy: Define which pipe split policy is used by the 1065 * display core. 1066 */ 1067 enum pipe_split_policy pipe_split_policy; 1068 bool force_single_disp_pipe_split; 1069 bool voltage_align_fclk; 1070 bool disable_min_fclk; 1071 1072 bool hdcp_lc_force_fw_enable; 1073 bool hdcp_lc_enable_sw_fallback; 1074 1075 bool disable_dfs_bypass; 1076 bool disable_dpp_power_gate; 1077 bool disable_hubp_power_gate; 1078 bool disable_dsc_power_gate; 1079 bool disable_optc_power_gate; 1080 bool disable_hpo_power_gate; 1081 bool disable_io_clk_power_gate; 1082 bool disable_mem_power_gate; 1083 bool disable_dio_power_gate; 1084 unsigned int dsc_min_slice_height_override; 1085 unsigned int dsc_bpp_increment_div; 1086 bool disable_pplib_wm_range; 1087 enum wm_report_mode pplib_wm_report_mode; 1088 unsigned int min_disp_clk_khz; 1089 unsigned int min_dpp_clk_khz; 1090 unsigned int min_dram_clk_khz; 1091 unsigned int sr_exit_time_dpm0_ns; 1092 unsigned int sr_enter_plus_exit_time_dpm0_ns; 1093 unsigned int sr_exit_time_ns; 1094 unsigned int sr_enter_plus_exit_time_ns; 1095 unsigned int sr_exit_z8_time_ns; 1096 unsigned int sr_enter_plus_exit_z8_time_ns; 1097 unsigned int urgent_latency_ns; 1098 uint32_t underflow_assert_delay_us; 1099 unsigned int percent_of_ideal_drambw; 1100 unsigned int dram_clock_change_latency_ns; 1101 bool optimized_watermark; 1102 int always_scale; 1103 bool disable_pplib_clock_request; 1104 bool disable_clock_gate; 1105 bool disable_mem_low_power; 1106 bool pstate_enabled; 1107 bool disable_dmcu; 1108 bool force_abm_enable; 1109 bool disable_stereo_support; 1110 bool vsr_support; 1111 bool performance_trace; 1112 bool az_endpoint_mute_only; 1113 bool always_use_regamma; 1114 bool recovery_enabled; 1115 bool avoid_vbios_exec_table; 1116 bool scl_reset_length10; 1117 bool hdmi20_disable; 1118 bool skip_detection_link_training; 1119 uint32_t edid_read_retry_times; 1120 1121 uint8_t force_odm_combine; //bit vector based on otg inst 1122 uint8_t seamless_boot_odm_combine; 1123 uint8_t force_odm_combine_4to1; //bit vector based on otg inst 1124 1125 unsigned int minimum_z8_residency_time; 1126 unsigned int minimum_z10_residency_time; 1127 bool disable_z9_mpc; 1128 unsigned int force_fclk_khz; 1129 bool enable_tri_buf; 1130 bool ips_disallow_entry; 1131 bool disable_idle_power_optimizations; 1132 unsigned int mall_size_override; 1133 unsigned int mall_additional_timer_percent; 1134 bool mall_error_as_fatal; 1135 bool dmub_command_table; /* for testing only */ 1136 struct dc_bw_validation_profile bw_val_profile; 1137 bool disable_fec; 1138 bool disable_48mhz_pwrdwn; 1139 /* This forces a hard min on the DCFCLK requested to SMU/PP 1140 * watermarks are not affected. 1141 */ 1142 unsigned int force_min_dcfclk_mhz; 1143 int dwb_fi_phase; 1144 bool disable_timing_sync; 1145 bool cm_in_bypass; 1146 int force_clock_mode;/*every mode change.*/ 1147 1148 bool disable_dram_clock_change_vactive_support; 1149 bool validate_dml_output; 1150 bool enable_dmcub_surface_flip; 1151 bool usbc_combo_phy_reset_wa; 1152 bool force_fva; 1153 int max_frl_rate; 1154 unsigned int force_frl_rate; 1155 bool ignore_ffe; 1156 unsigned int select_ffe; 1157 unsigned int limit_ffe; 1158 bool force_frl_always; 1159 bool force_frl_dsc; 1160 bool force_frl_max; 1161 bool apply_vsdb_rcc_wa; 1162 bool enable_hdmi_idcc; 1163 1164 bool enable_dram_clock_change_one_display_vactive; 1165 /* TODO - remove once tested */ 1166 bool legacy_dp2_lt; 1167 bool set_mst_en_for_sst; 1168 bool disable_uhbr; 1169 bool force_dp2_lt_fallback_method; 1170 bool ignore_cable_id; 1171 union mem_low_power_enable_options enable_mem_low_power; 1172 union root_clock_optimization_options root_clock_optimization; 1173 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1174 bool hpo_optimization; 1175 bool force_vblank_alignment; 1176 1177 /* Enable dmub aux for legacy ddc */ 1178 bool enable_dmub_aux_for_legacy_ddc; 1179 bool disable_fams; 1180 enum in_game_fams_config disable_fams_gaming; 1181 /* FEC/PSR1 sequence enable delay in 100us */ 1182 uint8_t fec_enable_delay_in100us; 1183 bool enable_driver_sequence_debug; 1184 enum det_size crb_alloc_policy; 1185 unsigned int crb_alloc_policy_min_disp_count; 1186 bool disable_z10; 1187 bool enable_z9_disable_interface; 1188 bool psr_skip_crtc_disable; 1189 uint32_t ips_skip_crtc_disable_mask; 1190 union dpia_debug_options dpia_debug; 1191 bool disable_fixed_vs_aux_timeout_wa; 1192 uint32_t fixed_vs_aux_delay_config_wa; 1193 bool force_disable_subvp; 1194 bool force_subvp_mclk_switch; 1195 bool allow_sw_cursor_fallback; 1196 unsigned int force_subvp_num_ways; 1197 unsigned int force_mall_ss_num_ways; 1198 bool alloc_extra_way_for_cursor; 1199 uint32_t subvp_extra_lines; 1200 bool disable_force_pstate_allow_on_hw_release; 1201 bool force_usr_allow; 1202 /* uses value at boot and disables switch */ 1203 bool disable_dtb_ref_clk_switch; 1204 bool extended_blank_optimization; 1205 union aux_wake_wa_options aux_wake_wa; 1206 uint32_t mst_start_top_delay; 1207 uint8_t psr_power_use_phy_fsm; 1208 enum dml_hostvm_override_opts dml_hostvm_override; 1209 bool dml_disallow_alternate_prefetch_modes; 1210 bool use_legacy_soc_bb_mechanism; 1211 bool exit_idle_opt_for_cursor_updates; 1212 bool using_dml2; 1213 bool enable_single_display_2to1_odm_policy; 1214 bool enable_double_buffered_dsc_pg_support; 1215 bool enable_dp_dig_pixel_rate_div_policy; 1216 bool using_dml21; 1217 enum lttpr_mode lttpr_mode_override; 1218 unsigned int dsc_delay_factor_wa_x1000; 1219 unsigned int min_prefetch_in_strobe_ns; 1220 bool disable_unbounded_requesting; 1221 bool dig_fifo_off_in_blank; 1222 bool override_dispclk_programming; 1223 bool otg_crc_db; 1224 bool disallow_dispclk_dppclk_ds; 1225 bool disable_fpo_optimizations; 1226 bool support_eDP1_5; 1227 uint32_t fpo_vactive_margin_us; 1228 bool disable_fpo_vactive; 1229 bool disable_boot_optimizations; 1230 bool override_odm_optimization; 1231 bool minimize_dispclk_using_odm; 1232 bool disable_subvp_high_refresh; 1233 bool disable_dp_plus_plus_wa; 1234 uint32_t fpo_vactive_min_active_margin_us; 1235 uint32_t fpo_vactive_max_blank_us; 1236 bool enable_hpo_pg_support; 1237 bool disable_dc_mode_overwrite; 1238 bool replay_skip_crtc_disabled; 1239 bool ignore_pg;/*do nothing, let pmfw control it*/ 1240 bool psp_disabled_wa; 1241 unsigned int ips2_eval_delay_us; 1242 unsigned int ips2_entry_delay_us; 1243 bool optimize_ips_handshake; 1244 bool disable_dmub_reallow_idle; 1245 bool disable_timeout; 1246 bool disable_extblankadj; 1247 bool enable_idle_reg_checks; 1248 unsigned int static_screen_wait_frames; 1249 uint32_t pwm_freq; 1250 bool force_chroma_subsampling_1tap; 1251 unsigned int dcc_meta_propagation_delay_us; 1252 bool disable_422_left_edge_pixel; 1253 bool dml21_force_pstate_method; 1254 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1255 uint32_t dml21_disable_pstate_method_mask; 1256 union fw_assisted_mclk_switch_version fams_version; 1257 union dmub_fams2_global_feature_config fams2_config; 1258 unsigned int force_cositing; 1259 unsigned int disable_spl; 1260 unsigned int force_easf; 1261 unsigned int force_sharpness; 1262 unsigned int force_sharpness_level; 1263 unsigned int force_lls; 1264 bool notify_dpia_hr_bw; 1265 bool enable_ips_visual_confirm; 1266 unsigned int sharpen_policy; 1267 unsigned int scale_to_sharpness_policy; 1268 unsigned int enable_oled_edp_power_up_opt; 1269 bool enable_hblank_borrow; 1270 bool force_subvp_df_throttle; 1271 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1272 bool enable_pg_cntl_debug_logs; 1273 unsigned int auxless_alpm_lfps_setup_ns; 1274 unsigned int auxless_alpm_lfps_period_ns; 1275 unsigned int auxless_alpm_lfps_silence_ns; 1276 unsigned int auxless_alpm_lfps_t1t2_us; 1277 short auxless_alpm_lfps_t1t2_offset_us; 1278 bool disable_stutter_for_wm_program; 1279 bool enable_block_sequence_programming; 1280 uint32_t custom_psp_footer_size; 1281 bool disable_deferred_minimal_transitions; 1282 unsigned int num_fast_flips_to_steady_state_override; 1283 bool enable_dmu_recovery; 1284 unsigned int force_vmin_threshold; 1285 bool enable_otg_frame_sync_pwa; 1286 unsigned int min_deep_sleep_dcfclk_khz; 1287 unsigned int force_odm2to1_for_edp_pixclk_mhz; 1288 bool enable_replay_esd_recovery; 1289 uint8_t iommu_mismatch_temp_wka; 1290 bool disable_dynamic_expansion_for_test_pattern; 1291 }; 1292 1293 1294 /* Generic structure that can be used to query properties of DC. More fields 1295 * can be added as required. 1296 */ 1297 struct dc_current_properties { 1298 unsigned int cursor_size_limit; 1299 }; 1300 1301 enum frame_buffer_mode { 1302 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1303 FRAME_BUFFER_MODE_ZFB_ONLY, 1304 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1305 } ; 1306 1307 struct dchub_init_data { 1308 int64_t zfb_phys_addr_base; 1309 int64_t zfb_mc_base_addr; 1310 uint64_t zfb_size_in_byte; 1311 enum frame_buffer_mode fb_mode; 1312 bool dchub_initialzied; 1313 bool dchub_info_valid; 1314 }; 1315 1316 struct dml2_soc_bb; 1317 1318 struct dc_init_data { 1319 struct hw_asic_id asic_id; 1320 void *driver; /* ctx */ 1321 struct cgs_device *cgs_device; 1322 struct dc_bounding_box_overrides bb_overrides; 1323 1324 int num_virtual_links; 1325 /* 1326 * If 'vbios_override' not NULL, it will be called instead 1327 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1328 */ 1329 struct dc_bios *vbios_override; 1330 enum dce_environment dce_environment; 1331 1332 struct dmub_offload_funcs *dmub_if; 1333 1334 struct dc_config flags; 1335 uint64_t log_mask; 1336 1337 struct dpcd_vendor_signature vendor_signature; 1338 bool force_smu_not_present; 1339 /* 1340 * IP offset for run time initializaion of register addresses 1341 * 1342 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1343 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1344 * before them. 1345 */ 1346 uint32_t *dcn_reg_offsets; 1347 uint32_t *nbio_reg_offsets; 1348 uint32_t *clk_reg_offsets; 1349 void *bb_from_dmub; 1350 }; 1351 1352 struct dc_callback_init { 1353 struct cp_psp cp_psp; 1354 }; 1355 1356 struct dc *dc_create(const struct dc_init_data *init_params); 1357 void dc_hardware_init(struct dc *dc); 1358 1359 int dc_get_vmid_use_vector(struct dc *dc); 1360 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1361 /* Returns the number of vmids supported */ 1362 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1363 void dc_init_callbacks(struct dc *dc, 1364 const struct dc_callback_init *init_params); 1365 void dc_deinit_callbacks(struct dc *dc); 1366 void dc_destroy(struct dc **dc); 1367 1368 /* Surface Interfaces */ 1369 1370 enum { 1371 TRANSFER_FUNC_POINTS = 1025 1372 }; 1373 1374 struct dc_hdr_static_metadata { 1375 /* display chromaticities and white point in units of 0.00001 */ 1376 unsigned int chromaticity_green_x; 1377 unsigned int chromaticity_green_y; 1378 unsigned int chromaticity_blue_x; 1379 unsigned int chromaticity_blue_y; 1380 unsigned int chromaticity_red_x; 1381 unsigned int chromaticity_red_y; 1382 unsigned int chromaticity_white_point_x; 1383 unsigned int chromaticity_white_point_y; 1384 1385 uint32_t min_luminance; 1386 uint32_t max_luminance; 1387 uint32_t maximum_content_light_level; 1388 uint32_t maximum_frame_average_light_level; 1389 }; 1390 1391 enum dc_transfer_func_type { 1392 TF_TYPE_PREDEFINED, 1393 TF_TYPE_DISTRIBUTED_POINTS, 1394 TF_TYPE_BYPASS, 1395 TF_TYPE_HWPWL 1396 }; 1397 1398 struct dc_transfer_func_distributed_points { 1399 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1400 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1401 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1402 1403 uint16_t end_exponent; 1404 uint16_t x_point_at_y1_red; 1405 uint16_t x_point_at_y1_green; 1406 uint16_t x_point_at_y1_blue; 1407 }; 1408 1409 enum dc_transfer_func_predefined { 1410 TRANSFER_FUNCTION_SRGB, 1411 TRANSFER_FUNCTION_BT709, 1412 TRANSFER_FUNCTION_PQ, 1413 TRANSFER_FUNCTION_LINEAR, 1414 TRANSFER_FUNCTION_UNITY, 1415 TRANSFER_FUNCTION_HLG, 1416 TRANSFER_FUNCTION_HLG12, 1417 TRANSFER_FUNCTION_GAMMA22, 1418 TRANSFER_FUNCTION_GAMMA24, 1419 TRANSFER_FUNCTION_GAMMA26 1420 }; 1421 1422 1423 struct dc_transfer_func { 1424 struct kref refcount; 1425 enum dc_transfer_func_type type; 1426 enum dc_transfer_func_predefined tf; 1427 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1428 uint32_t sdr_ref_white_level; 1429 union { 1430 struct pwl_params pwl; 1431 struct dc_transfer_func_distributed_points tf_pts; 1432 }; 1433 }; 1434 1435 1436 union dc_3dlut_state { 1437 struct { 1438 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1439 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1440 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1441 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1442 uint32_t mpc_rmu1_mux:4; 1443 uint32_t mpc_rmu2_mux:4; 1444 uint32_t reserved:15; 1445 } bits; 1446 uint32_t raw; 1447 }; 1448 1449 1450 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1451 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1452 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1453 1454 struct lut_rgb { 1455 uint16_t b; 1456 uint16_t g; 1457 uint16_t r; 1458 uint16_t padding; 1459 }; 1460 1461 //this structure maps directly to how the lut will read it from memory 1462 struct lut_mem_mapping { 1463 union { 1464 //NATIVE MODE 1, 2 1465 //RGB layout [b][g][r] //red is 128 byte aligned 1466 //BGR layout [r][g][b] //blue is 128 byte aligned 1467 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1468 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1469 1470 //TRANSFORMED 1471 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1472 }; 1473 uint16_t size; 1474 }; 1475 1476 struct dc_rmcm_3dlut { 1477 bool isInUse; 1478 const struct dc_stream_state *stream; 1479 uint8_t protection_bits; 1480 }; 1481 1482 struct dc_3dlut { 1483 struct kref refcount; 1484 struct tetrahedral_params lut_3d; 1485 struct fixed31_32 hdr_multiplier; 1486 union dc_3dlut_state state; 1487 }; 1488 1489 /* 3DLUT DMA (Fast Load) params */ 1490 struct dc_3dlut_dma { 1491 struct dc_plane_address addr; 1492 enum dc_cm_lut_swizzle swizzle; 1493 enum dc_cm_lut_pixel_format format; 1494 uint16_t bias; /* FP1.5.10 */ 1495 uint16_t scale; /* FP1.5.10 */ 1496 enum dc_cm_lut_size size; 1497 }; 1498 1499 /* color manager */ 1500 union dc_plane_cm_flags { 1501 unsigned int all; 1502 struct { 1503 unsigned int shaper_enable : 1; 1504 unsigned int lut3d_enable : 1; 1505 unsigned int blend_enable : 1; 1506 /* whether legacy (lut3d_func) or DMA is valid */ 1507 unsigned int lut3d_dma_enable : 1; 1508 #if defined(CONFIG_DRM_AMD_DC_DCN4_2) 1509 /* RMCM lut to be used instead of MCM */ 1510 unsigned int rmcm_enable : 1; 1511 unsigned int reserved: 27; 1512 #else 1513 unsigned int reserved: 28; 1514 #endif 1515 } bits; 1516 }; 1517 1518 struct dc_plane_cm { 1519 struct kref refcount; 1520 struct dc_transfer_func shaper_func; 1521 union { 1522 struct dc_3dlut lut3d_func; 1523 struct dc_3dlut_dma lut3d_dma; 1524 }; 1525 struct dc_transfer_func blend_func; 1526 union dc_plane_cm_flags flags; 1527 }; 1528 1529 /* 1530 * This structure is filled in by dc_surface_get_status and contains 1531 * the last requested address and the currently active address so the called 1532 * can determine if there are any outstanding flips 1533 */ 1534 struct dc_plane_status { 1535 struct dc_plane_address requested_address; 1536 struct dc_plane_address current_address; 1537 bool is_flip_pending; 1538 bool is_right_eye; 1539 struct cm_hist cm_hist; 1540 }; 1541 1542 struct pipe_update_bits { 1543 uint32_t addr_update:1; 1544 uint32_t dcc_change:1; 1545 uint32_t color_space_change:1; 1546 uint32_t horizontal_mirror_change:1; 1547 uint32_t per_pixel_alpha_change:1; 1548 uint32_t global_alpha_change:1; 1549 uint32_t hdr_mult:1; 1550 uint32_t rotation_change:1; 1551 uint32_t swizzle_change:1; 1552 uint32_t scaling_change:1; 1553 uint32_t position_change:1; 1554 uint32_t in_transfer_func_change:1; 1555 uint32_t input_csc_change:1; 1556 uint32_t coeff_reduction_change:1; 1557 uint32_t pixel_format_change:1; 1558 uint32_t plane_size_change:1; 1559 uint32_t gamut_remap_change:1; 1560 uint32_t cursor_csc_color_matrix_change:1; 1561 uint32_t new_plane:1; 1562 uint32_t bpp_change:1; 1563 uint32_t gamma_change:1; 1564 uint32_t bandwidth_change:1; 1565 uint32_t clock_change:1; 1566 uint32_t stereo_format_change:1; 1567 uint32_t lut_3d:1; 1568 uint32_t tmz_changed:1; 1569 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1570 uint32_t full_update:1; 1571 uint32_t sdr_white_level_nits:1; 1572 uint32_t cm_hist_change:1; 1573 /* NOTE: When adding a new field, also update: 1574 * - dc_pipe_update_bits_set_full() 1575 * - dc_pipe_update_bits_is_any_set() 1576 */ 1577 }; 1578 1579 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags) 1580 { 1581 /* memset ensures padding bits are zeroed */ 1582 memset(flags, 0, sizeof(*flags)); 1583 } 1584 1585 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags) 1586 { 1587 dc_pipe_update_bits_clear(flags); 1588 flags->addr_update = 1; 1589 flags->dcc_change = 1; 1590 flags->color_space_change = 1; 1591 flags->horizontal_mirror_change = 1; 1592 flags->per_pixel_alpha_change = 1; 1593 flags->global_alpha_change = 1; 1594 flags->hdr_mult = 1; 1595 flags->rotation_change = 1; 1596 flags->swizzle_change = 1; 1597 flags->scaling_change = 1; 1598 flags->position_change = 1; 1599 flags->in_transfer_func_change = 1; 1600 flags->input_csc_change = 1; 1601 flags->coeff_reduction_change = 1; 1602 flags->pixel_format_change = 1; 1603 flags->plane_size_change = 1; 1604 flags->gamut_remap_change = 1; 1605 flags->cursor_csc_color_matrix_change = 1; 1606 flags->new_plane = 1; 1607 flags->bpp_change = 1; 1608 flags->gamma_change = 1; 1609 flags->bandwidth_change = 1; 1610 flags->clock_change = 1; 1611 flags->stereo_format_change = 1; 1612 flags->lut_3d = 1; 1613 flags->tmz_changed = 1; 1614 flags->mcm_transfer_function_enable_change = 1; 1615 flags->full_update = 1; 1616 flags->sdr_white_level_nits = 1; 1617 flags->cm_hist_change = 1; 1618 } 1619 1620 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags) 1621 { 1622 return flags->addr_update || 1623 flags->dcc_change || 1624 flags->color_space_change || 1625 flags->horizontal_mirror_change || 1626 flags->per_pixel_alpha_change || 1627 flags->global_alpha_change || 1628 flags->hdr_mult || 1629 flags->rotation_change || 1630 flags->swizzle_change || 1631 flags->scaling_change || 1632 flags->position_change || 1633 flags->in_transfer_func_change || 1634 flags->input_csc_change || 1635 flags->coeff_reduction_change || 1636 flags->pixel_format_change || 1637 flags->plane_size_change || 1638 flags->gamut_remap_change || 1639 flags->cursor_csc_color_matrix_change || 1640 flags->new_plane || 1641 flags->bpp_change || 1642 flags->gamma_change || 1643 flags->bandwidth_change || 1644 flags->clock_change || 1645 flags->stereo_format_change || 1646 flags->lut_3d || 1647 flags->tmz_changed || 1648 flags->mcm_transfer_function_enable_change || 1649 flags->full_update || 1650 flags->sdr_white_level_nits || 1651 flags->cm_hist_change; 1652 } 1653 1654 bool dc_check_address_only_update(struct pipe_update_bits update_bits); 1655 1656 #define DC_REMOVE_PLANE_POINTERS 1 1657 1658 struct dc_plane_state { 1659 struct dc_plane_address address; 1660 struct dc_plane_flip_time time; 1661 bool triplebuffer_flips; 1662 struct scaling_taps scaling_quality; 1663 struct rect src_rect; 1664 struct rect dst_rect; 1665 struct rect clip_rect; 1666 1667 struct plane_size plane_size; 1668 struct dc_tiling_info tiling_info; 1669 1670 struct dc_plane_dcc_param dcc; 1671 1672 struct dc_gamma gamma_correction; 1673 struct dc_transfer_func in_transfer_func; 1674 struct dc_bias_and_scale bias_and_scale; 1675 struct dc_csc_transform input_csc_color_matrix; 1676 struct fixed31_32 coeff_reduction_factor; 1677 struct fixed31_32 hdr_mult; 1678 struct colorspace_transform gamut_remap_matrix; 1679 1680 enum dc_color_space color_space; 1681 1682 #ifndef TRIM_CM2 1683 // TODO: No longer used, remove 1684 struct dc_hdr_static_metadata hdr_static_ctx; 1685 1686 struct dc_3dlut lut3d_func; 1687 struct dc_transfer_func in_shaper_func; 1688 struct dc_transfer_func blend_tf; 1689 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1690 bool mcm_lut1d_enable; 1691 struct dc_cm2_func_luts mcm_luts; 1692 #endif /* TRIM_CM2 */ 1693 bool lut_bank_a; 1694 enum mpcc_movable_cm_location mcm_location; 1695 struct dc_plane_cm cm; 1696 1697 struct dc_transfer_func *gamcor_tf; 1698 enum surface_pixel_format format; 1699 enum dc_rotation_angle rotation; 1700 enum plane_stereo_format stereo_format; 1701 1702 bool is_tiling_rotated; 1703 bool per_pixel_alpha; 1704 bool pre_multiplied_alpha; 1705 bool global_alpha; 1706 int global_alpha_value; 1707 bool visible; 1708 bool flip_immediate; 1709 bool horizontal_mirror; 1710 unsigned int layer_index; 1711 1712 struct pipe_update_bits update_bits; 1713 bool flip_int_enabled; 1714 bool skip_manual_trigger; 1715 1716 /* private to DC core */ 1717 struct dc_plane_status status; 1718 struct dc_context *ctx; 1719 1720 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1721 bool force_full_update; 1722 1723 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1724 1725 /* private to dc_surface.c */ 1726 enum dc_irq_source irq_source; 1727 struct kref refcount; 1728 struct tg_color visual_confirm_color; 1729 1730 bool is_statically_allocated; 1731 enum chroma_cositing cositing; 1732 struct dc_csc_transform cursor_csc_color_matrix; 1733 bool adaptive_sharpness_en; 1734 int adaptive_sharpness_policy; 1735 unsigned int sharpness_level; 1736 enum linear_light_scaling linear_light_scaling; 1737 unsigned int sdr_white_level_nits; 1738 struct cm_hist_control cm_hist_control; 1739 struct spl_sharpness_range sharpness_range; 1740 enum sharpness_range_source sharpness_source; 1741 }; 1742 1743 struct dc_plane_info { 1744 struct plane_size plane_size; 1745 struct dc_tiling_info tiling_info; 1746 struct dc_plane_dcc_param dcc; 1747 enum surface_pixel_format format; 1748 enum dc_rotation_angle rotation; 1749 enum plane_stereo_format stereo_format; 1750 enum dc_color_space color_space; 1751 bool horizontal_mirror; 1752 bool visible; 1753 bool per_pixel_alpha; 1754 bool pre_multiplied_alpha; 1755 bool global_alpha; 1756 int global_alpha_value; 1757 bool input_csc_enabled; 1758 unsigned int layer_index; 1759 enum chroma_cositing cositing; 1760 }; 1761 1762 #include "dc_stream.h" 1763 1764 struct dc_scratch_space { 1765 /* used to temporarily backup plane states of a stream during 1766 * dc update. The reason is that plane states are overwritten 1767 * with surface updates in dc update. Once they are overwritten 1768 * current state is no longer valid. We want to temporarily 1769 * store current value in plane states so we can still recover 1770 * a valid current state during dc update. 1771 */ 1772 struct dc_plane_state plane_states[MAX_SURFACES]; 1773 1774 struct dc_stream_state stream_state; 1775 }; 1776 1777 /* 1778 * A link contains one or more sinks and their connected status. 1779 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1780 */ 1781 struct dc_link { 1782 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1783 unsigned int sink_count; 1784 struct dc_sink *local_sink; 1785 unsigned int link_index; 1786 enum dc_connection_type type; 1787 enum signal_type connector_signal; 1788 enum dc_irq_source irq_source_hpd; 1789 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1790 enum dc_irq_source irq_source_read_request;/* Read Request */ 1791 1792 bool is_hpd_filter_disabled; 1793 bool dp_ss_off; 1794 1795 /** 1796 * @link_state_valid: 1797 * 1798 * If there is no link and local sink, this variable should be set to 1799 * false. Otherwise, it should be set to true; usually, the function 1800 * core_link_enable_stream sets this field to true. 1801 */ 1802 bool link_state_valid; 1803 bool aux_access_disabled; 1804 bool sync_lt_in_progress; 1805 bool skip_stream_reenable; 1806 bool is_internal_display; 1807 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1808 bool is_dig_mapping_flexible; 1809 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1810 bool is_hpd_pending; /* Indicates a new received hpd */ 1811 1812 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1813 * for every link training. This is incompatible with DP LL compliance automation, 1814 * which expects the same link settings to be used every retry on a link loss. 1815 * This flag is used to skip the fallback when link loss occurs during automation. 1816 */ 1817 bool skip_fallback_on_link_loss; 1818 1819 bool edp_sink_present; 1820 1821 struct dp_trace dp_trace; 1822 volatile bool is_link_locked; 1823 1824 /* caps is the same as reported_link_cap. link_traing use 1825 * reported_link_cap. Will clean up. TODO 1826 */ 1827 struct dc_link_settings reported_link_cap; 1828 struct dc_link_settings verified_link_cap; 1829 struct dc_link_settings cur_link_settings; 1830 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1831 struct dc_link_settings preferred_link_setting; 1832 /* preferred_training_settings are override values that 1833 * come from DM. DM is responsible for the memory 1834 * management of the override pointers. 1835 */ 1836 struct dc_link_training_overrides preferred_training_settings; 1837 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings; 1838 struct dp_audio_test_data audio_test_data; 1839 1840 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap 1841 * set by IFWI, link aux_hw_inst is used in aux layer functions instead 1842 * of ddc_pin to know which aux instance is associated with link. 1843 */ 1844 bool no_ddc_pin; 1845 /** When set, forces all native I2C communication on this DP connector 1846 * to use the I2C-over-AUX protocol instead of native I2C signaling. 1847 */ 1848 bool force_to_use_aux; 1849 enum gpio_ddc_line aux_hw_inst; 1850 1851 enum gpio_ddc_line ddc_hw_inst; 1852 1853 uint8_t hpd_src; 1854 1855 uint8_t link_enc_hw_inst; 1856 /* DIG link encoder ID. Used as index in link encoder resource pool. 1857 * For links with fixed mapping to DIG, this is not changed after dc_link 1858 * object creation. 1859 */ 1860 enum engine_id eng_id; 1861 enum engine_id dpia_preferred_eng_id; 1862 1863 bool test_pattern_enabled; 1864 /* Pending/Current test pattern are only used to perform and track 1865 * FIXED_VS retimer test pattern/lane adjustment override state. 1866 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1867 * to perform specific lane adjust overrides before setting certain 1868 * PHY test patterns. In cases when lane adjust and set test pattern 1869 * calls are not performed atomically (i.e. performing link training), 1870 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1871 * and current_test_pattern will contain required context for any future 1872 * set pattern/set lane adjust to transition between override state(s). 1873 * */ 1874 enum dp_test_pattern current_test_pattern; 1875 enum dp_test_pattern pending_test_pattern; 1876 1877 union compliance_test_state compliance_test_state; 1878 1879 void *priv; 1880 1881 struct ddc_service *ddc; 1882 1883 enum dp_panel_mode panel_mode; 1884 bool aux_mode; 1885 1886 /* Private to DC core */ 1887 1888 const struct dc *dc; 1889 1890 struct dc_context *ctx; 1891 1892 struct panel_cntl *panel_cntl; 1893 struct link_encoder *link_enc; 1894 struct hpo_frl_link_encoder *hpo_frl_link_enc; 1895 struct dc_hdmi_frl_link_settings frl_reported_link_cap; 1896 struct dc_hdmi_frl_link_settings frl_verified_link_cap; 1897 struct dc_hdmi_frl_link_settings frl_link_settings; 1898 struct dc_hdmi_frl_flags frl_flags; 1899 union hdmi_idcc_cable_id hdmi_cable_id; 1900 struct graphics_object_id link_id; 1901 1902 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1903 struct graphics_object_id ext_enc_id; 1904 1905 /* Endpoint type distinguishes display endpoints which do not have entries 1906 * in the BIOS connector table from those that do. Helps when tracking link 1907 * encoder to display endpoint assignments. 1908 */ 1909 enum display_endpoint_type ep_type; 1910 union ddi_channel_mapping ddi_channel_mapping; 1911 struct connector_device_tag_info device_tag; 1912 struct dpcd_caps dpcd_caps; 1913 uint32_t dongle_max_pix_clk; 1914 unsigned short chip_caps; 1915 unsigned int dpcd_sink_count; 1916 struct hdcp_caps hdcp_caps; 1917 enum edp_revision edp_revision; 1918 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1919 1920 struct psr_settings psr_settings; 1921 struct replay_settings replay_settings; 1922 1923 /* Drive settings read from integrated info table */ 1924 struct dc_lane_settings bios_forced_drive_settings; 1925 1926 /* Vendor specific LTTPR workaround variables */ 1927 uint8_t vendor_specific_lttpr_link_rate_wa; 1928 bool apply_vendor_specific_lttpr_link_rate_wa; 1929 1930 /* MST record stream using this link */ 1931 struct link_flags { 1932 bool dp_keep_receiver_powered; 1933 bool dp_skip_DID2; 1934 bool dp_skip_reset_segment; 1935 bool dp_skip_fs_144hz; 1936 bool dp_mot_reset_segment; 1937 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1938 bool dpia_mst_dsc_always_on; 1939 /* Forced DPIA into TBT3 compatibility mode. */ 1940 bool dpia_forced_tbt3_mode; 1941 bool dongle_mode_timing_override; 1942 bool blank_stream_on_ocs_change; 1943 bool read_dpcd204h_on_irq_hpd; 1944 bool force_dp_ffe_preset; 1945 bool skip_phy_ssc_reduction; 1946 } wa_flags; 1947 union dc_dp_ffe_preset forced_dp_ffe_preset; 1948 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1949 1950 struct dc_link_status link_status; 1951 struct dprx_states dprx_states; 1952 1953 enum dc_link_fec_state fec_state; 1954 bool is_dds; 1955 bool is_display_mux_present; 1956 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1957 1958 struct dc_panel_config panel_config; 1959 enum dc_panel_type panel_type; 1960 struct phy_state phy_state; 1961 uint32_t phy_transition_bitmask; 1962 // BW ALLOCATON USB4 ONLY 1963 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1964 bool skip_implict_edp_power_control; 1965 enum backlight_control_type backlight_control_type; 1966 }; 1967 1968 struct dc { 1969 struct dc_debug_options debug; 1970 struct dc_versions versions; 1971 struct dc_caps caps; 1972 struct dc_check_config check_config; 1973 struct dc_cap_funcs cap_funcs; 1974 struct dc_config config; 1975 struct dc_bounding_box_overrides bb_overrides; 1976 struct dc_bug_wa work_arounds; 1977 struct dc_context *ctx; 1978 struct dc_phy_addr_space_config vm_pa_config; 1979 1980 uint8_t link_count; 1981 struct dc_link *links[MAX_LINKS]; 1982 uint8_t lowest_dpia_link_index; 1983 struct link_service *link_srv; 1984 1985 struct dc_state *current_state; 1986 struct resource_pool *res_pool; 1987 1988 struct clk_mgr *clk_mgr; 1989 1990 /* Display Engine Clock levels */ 1991 struct dm_pp_clock_levels sclk_lvls; 1992 1993 /* Inputs into BW and WM calculations. */ 1994 struct bw_calcs_dceip *bw_dceip; 1995 struct bw_calcs_vbios *bw_vbios; 1996 struct dcn_soc_bounding_box *dcn_soc; 1997 struct dcn_ip_params *dcn_ip; 1998 struct display_mode_lib dml; 1999 2000 /* HW functions */ 2001 struct hw_sequencer_funcs hwss; 2002 struct dce_hwseq *hwseq; 2003 2004 /* Require to optimize clocks and bandwidth for added/removed planes */ 2005 bool optimized_required; 2006 bool idle_optimizations_allowed; 2007 bool enable_c20_dtm_b0; 2008 2009 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 2010 2011 /* For eDP to know the switching state of SmartMux */ 2012 bool is_switch_in_progress_orig; 2013 bool is_switch_in_progress_dest; 2014 2015 /* FBC compressor */ 2016 struct compressor *fbc_compressor; 2017 2018 struct dc_debug_data debug_data; 2019 struct dpcd_vendor_signature vendor_signature; 2020 2021 const char *build_id; 2022 struct vm_helper *vm_helper; 2023 2024 uint32_t *dcn_reg_offsets; 2025 uint32_t *nbio_reg_offsets; 2026 uint32_t *clk_reg_offsets; 2027 2028 /* Scratch memory */ 2029 struct { 2030 struct { 2031 /* 2032 * For matching clock_limits table in driver with table 2033 * from PMFW. 2034 */ 2035 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2036 } update_bw_bounding_box; 2037 struct dc_scratch_space current_state; 2038 struct dc_scratch_space new_state; 2039 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 2040 struct dc_link temp_link; 2041 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 2042 } scratch; 2043 2044 struct dml2_configuration_options dml2_options; 2045 struct dml2_configuration_options dml2_dc_power_options; 2046 enum dc_acpi_cm_power_state power_state; 2047 struct soc_and_ip_translator *soc_and_ip_translator; 2048 }; 2049 2050 struct dc_scaling_info { 2051 struct rect src_rect; 2052 struct rect dst_rect; 2053 struct rect clip_rect; 2054 struct scaling_taps scaling_quality; 2055 }; 2056 2057 struct dc_fast_update { 2058 const struct dc_flip_addrs *flip_addr; 2059 const struct dc_gamma *gamma; 2060 const struct colorspace_transform *gamut_remap_matrix; 2061 const struct dc_csc_transform *input_csc_color_matrix; 2062 const struct fixed31_32 *coeff_reduction_factor; 2063 struct dc_transfer_func *out_transfer_func; 2064 struct dc_csc_transform *output_csc_transform; 2065 const struct dc_csc_transform *cursor_csc_color_matrix; 2066 struct cm_hist_control *cm_hist_control; 2067 /* stream-level fast updates */ 2068 const struct colorspace_transform *gamut_remap; 2069 const struct dc_cursor_attributes *cursor_attributes; 2070 const struct dc_cursor_position *cursor_position; 2071 const struct periodic_interrupt_config *periodic_interrupt; 2072 const enum dc_dither_option *dither_option; 2073 struct dc_info_packet *vrr_infopacket; 2074 struct dc_info_packet *vsc_infopacket; 2075 struct dc_info_packet *vsp_infopacket; 2076 struct dc_info_packet *hfvsif_infopacket; 2077 struct dc_info_packet *vtem_infopacket; 2078 struct dc_info_packet *adaptive_sync_infopacket; 2079 struct dc_info_packet *avi_infopacket; 2080 struct dc_info_packet *hdr_static_metadata; 2081 }; 2082 2083 struct dc_surface_update { 2084 struct dc_plane_state *surface; 2085 2086 /* isr safe update parameters. null means no updates */ 2087 const struct dc_flip_addrs *flip_addr; 2088 const struct dc_plane_info *plane_info; 2089 const struct dc_scaling_info *scaling_info; 2090 struct fixed31_32 hdr_mult; 2091 /* following updates require alloc/sleep/spin that is not isr safe, 2092 * null means no updates 2093 */ 2094 const struct dc_gamma *gamma; 2095 const struct dc_transfer_func *in_transfer_func; 2096 2097 const struct dc_csc_transform *input_csc_color_matrix; 2098 const struct fixed31_32 *coeff_reduction_factor; 2099 const struct colorspace_transform *gamut_remap_matrix; 2100 const struct dc_plane_cm *cm; 2101 const struct dc_csc_transform *cursor_csc_color_matrix; 2102 unsigned int sdr_white_level_nits; 2103 struct dc_bias_and_scale bias_and_scale; 2104 struct cm_hist_control *cm_hist_control; 2105 }; 2106 2107 struct dc_underflow_debug_data { 2108 struct dcn_hubbub_reg_state *hubbub_reg_state; 2109 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 2110 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 2111 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 2112 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 2113 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 2114 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 2115 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 2116 }; 2117 2118 struct power_features { 2119 bool ips; 2120 bool rcg; 2121 bool replay; 2122 bool dds; 2123 bool sprs; 2124 bool psr; 2125 bool fams; 2126 bool mpo; 2127 bool uclk_p_state; 2128 }; 2129 2130 /* 2131 * Create a new surface with default parameters; 2132 */ 2133 void dc_gamma_retain(struct dc_gamma *dc_gamma); 2134 void dc_gamma_release(struct dc_gamma **dc_gamma); 2135 struct dc_gamma *dc_create_gamma(void); 2136 2137 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 2138 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 2139 struct dc_transfer_func *dc_create_transfer_func(void); 2140 2141 struct dc_3dlut *dc_create_3dlut_func(void); 2142 void dc_3dlut_func_release(struct dc_3dlut *lut); 2143 void dc_3dlut_func_retain(struct dc_3dlut *lut); 2144 2145 struct dc_plane_cm *dc_plane_cm_create(void); 2146 void dc_plane_cm_release(struct dc_plane_cm *cm); 2147 void dc_plane_cm_retain(struct dc_plane_cm *cm); 2148 2149 void dc_post_update_surfaces_to_stream( 2150 struct dc *dc); 2151 2152 /* 2153 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling 2154 * description for (typically) linear surfaces. 2155 * 2156 * This is used by OS/DM paths that need a valid, fully-initialized tiling 2157 * description without hardcoding gfx-version specifics in the caller. 2158 */ 2159 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); 2160 2161 /** 2162 * struct dc_validation_set - Struct to store surface/stream associations for validation 2163 */ 2164 struct dc_validation_set { 2165 /** 2166 * @stream: Stream state properties 2167 */ 2168 struct dc_stream_state *stream; 2169 2170 /** 2171 * @plane_states: Surface state 2172 */ 2173 struct dc_plane_state *plane_states[MAX_SURFACES]; 2174 2175 /** 2176 * @plane_count: Total of active planes 2177 */ 2178 uint8_t plane_count; 2179 }; 2180 2181 bool dc_validate_boot_timing(const struct dc *dc, 2182 const struct dc_sink *sink, 2183 struct dc_crtc_timing *crtc_timing); 2184 2185 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 2186 2187 enum dc_status dc_validate_with_context(struct dc *dc, 2188 const struct dc_validation_set set[], 2189 unsigned int set_count, 2190 struct dc_state *context, 2191 enum dc_validate_mode validate_mode); 2192 2193 bool dc_set_generic_gpio_for_stereo(bool enable, 2194 struct gpio_service *gpio_service); 2195 2196 enum dc_status dc_validate_global_state( 2197 struct dc *dc, 2198 struct dc_state *new_ctx, 2199 enum dc_validate_mode validate_mode); 2200 2201 bool dc_acquire_release_mpc_3dlut( 2202 struct dc *dc, bool acquire, 2203 struct dc_stream_state *stream, 2204 struct dc_3dlut **lut, 2205 struct dc_transfer_func **shaper); 2206 2207 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 2208 void get_audio_check(struct audio_info *aud_modes, 2209 struct audio_check *aud_chk); 2210 2211 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 2212 void populate_fast_updates(struct dc_fast_update *fast_update, 2213 struct dc_surface_update *srf_updates, 2214 int surface_count, 2215 struct dc_stream_update *stream_update); 2216 /* 2217 * Set up streams and links associated to drive sinks 2218 * The streams parameter is an absolute set of all active streams. 2219 * 2220 * After this call: 2221 * Phy, Encoder, Timing Generator are programmed and enabled. 2222 * New streams are enabled with blank stream; no memory read. 2223 */ 2224 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 2225 2226 2227 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2228 struct dc_stream_state *stream, 2229 int mpcc_inst); 2230 2231 2232 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2233 bool dc_set_fva_vrr_adjust(struct dc *dc, 2234 struct dc_stream_state *stream, 2235 struct fva_adj *fva_adj, 2236 struct dc_crtc_timing_adjust *vrr_adj); 2237 2238 int dc_get_hw_max_fva_factor(struct dc *dc, 2239 struct dc_stream_state *stream, 2240 unsigned int max_pixel_clock); 2241 2242 void dc_set_vstartup_start(struct dc *dc, 2243 struct dc_stream_state *stream); 2244 2245 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2246 2247 /* The function returns minimum bandwidth required to drive a given timing 2248 * return - minimum required timing bandwidth in kbps. 2249 */ 2250 uint32_t dc_bandwidth_in_kbps_from_timing( 2251 const struct dc_crtc_timing *timing, 2252 const enum dc_link_encoding_format link_encoding); 2253 2254 /* Link Interfaces */ 2255 /* Return an enumerated dc_link. 2256 * dc_link order is constant and determined at 2257 * boot time. They cannot be created or destroyed. 2258 * Use dc_get_caps() to get number of links. 2259 */ 2260 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2261 2262 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2263 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2264 const struct dc_link *link, 2265 unsigned int *inst_out); 2266 2267 /* Return an array of link pointers to edp links. */ 2268 void dc_get_edp_links(const struct dc *dc, 2269 struct dc_link **edp_links, 2270 unsigned int *edp_num); 2271 2272 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2273 bool powerOn); 2274 2275 /* The function initiates detection handshake over the given link. It first 2276 * determines if there are display connections over the link. If so it initiates 2277 * detection protocols supported by the connected receiver device. The function 2278 * contains protocol specific handshake sequences which are sometimes mandatory 2279 * to establish a proper connection between TX and RX. So it is always 2280 * recommended to call this function as the first link operation upon HPD event 2281 * or power up event. Upon completion, the function will update link structure 2282 * in place based on latest RX capabilities. The function may also cause dpms 2283 * to be reset to off for all currently enabled streams to the link. It is DM's 2284 * responsibility to serialize detection and DPMS updates. 2285 * 2286 * @reason - Indicate which event triggers this detection. dc may customize 2287 * detection flow depending on the triggering events. 2288 * return false - if detection is not fully completed. This could happen when 2289 * there is an unrecoverable error during detection or detection is partially 2290 * completed (detection has been delegated to dm mst manager ie. 2291 * link->connection_type == dc_connection_mst_branch when returning false). 2292 * return true - detection is completed, link has been fully updated with latest 2293 * detection result. 2294 */ 2295 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2296 2297 struct dc_sink_init_data; 2298 2299 /* When link connection type is dc_connection_mst_branch, remote sink can be 2300 * added to the link. The interface creates a remote sink and associates it with 2301 * current link. The sink will be retained by link until remove remote sink is 2302 * called. 2303 * 2304 * @dc_link - link the remote sink will be added to. 2305 * @edid - byte array of EDID raw data. 2306 * @len - size of the edid in byte 2307 * @init_data - 2308 */ 2309 struct dc_sink *dc_link_add_remote_sink( 2310 struct dc_link *dc_link, 2311 const uint8_t *edid, 2312 unsigned int len, 2313 struct dc_sink_init_data *init_data); 2314 2315 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2316 * @link - link the sink should be removed from 2317 * @sink - sink to be removed. 2318 */ 2319 void dc_link_remove_remote_sink( 2320 struct dc_link *link, 2321 struct dc_sink *sink); 2322 2323 /* Enable HPD interrupt handler for a given link */ 2324 void dc_link_enable_hpd(const struct dc_link *link); 2325 2326 /* Disable HPD interrupt handler for a given link */ 2327 void dc_link_disable_hpd(const struct dc_link *link); 2328 2329 /* determine if there is a sink connected to the link 2330 * 2331 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2332 * return - false if an unexpected error occurs, true otherwise. 2333 * 2334 * NOTE: This function doesn't detect downstream sink connections i.e 2335 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2336 * return dc_connection_single if the branch device is connected despite of 2337 * downstream sink's connection status. 2338 */ 2339 bool dc_link_detect_connection_type(struct dc_link *link, 2340 enum dc_connection_type *type); 2341 2342 /* query current hpd pin value 2343 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2344 * 2345 */ 2346 bool dc_link_get_hpd_state(struct dc_link *link); 2347 2348 /* Getter for cached link status from given link */ 2349 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2350 2351 /* enable/disable hardware HPD filter. 2352 * 2353 * @link - The link the HPD pin is associated with. 2354 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2355 * handler once after no HPD change has been detected within dc default HPD 2356 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2357 * pulses within default HPD interval, no HPD event will be received until HPD 2358 * toggles have stopped. Then HPD event will be queued to irq handler once after 2359 * dc default HPD filtering interval since last HPD event. 2360 * 2361 * @enable = false - disable hardware HPD filter. HPD event will be queued 2362 * immediately to irq handler after no HPD change has been detected within 2363 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2364 */ 2365 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2366 2367 /* submit i2c read/write payloads through ddc channel 2368 * @link_index - index to a link with ddc in i2c mode 2369 * @cmd - i2c command structure 2370 * return - true if success, false otherwise. 2371 */ 2372 bool dc_submit_i2c( 2373 struct dc *dc, 2374 uint32_t link_index, 2375 struct i2c_command *cmd); 2376 2377 /* submit i2c read/write payloads through oem channel 2378 * @link_index - index to a link with ddc in i2c mode 2379 * @cmd - i2c command structure 2380 * return - true if success, false otherwise. 2381 */ 2382 bool dc_submit_i2c_oem( 2383 struct dc *dc, 2384 struct i2c_command *cmd); 2385 2386 enum aux_return_code_type; 2387 /* Attempt to transfer the given aux payload. This function does not perform 2388 * retries or handle error states. The reply is returned in the payload->reply 2389 * and the result through operation_result. Returns the number of bytes 2390 * transferred,or -1 on a failure. 2391 */ 2392 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2393 struct aux_payload *payload, 2394 enum aux_return_code_type *operation_result); 2395 2396 struct ddc_service * 2397 dc_get_oem_i2c_device(struct dc *dc); 2398 2399 bool dc_is_oem_i2c_device_present( 2400 struct dc *dc, 2401 size_t slave_address 2402 ); 2403 2404 /* return true if the connected receiver supports the hdcp version */ 2405 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2406 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2407 2408 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2409 * 2410 * TODO - When defer_handling is true the function will have a different purpose. 2411 * It no longer does complete hpd rx irq handling. We should create a separate 2412 * interface specifically for this case. 2413 * 2414 * Return: 2415 * true - Downstream port status changed. DM should call DC to do the 2416 * detection. 2417 * false - no change in Downstream port status. No further action required 2418 * from DM. 2419 */ 2420 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2421 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2422 bool defer_handling, bool *has_left_work); 2423 /* handle DP specs define test automation sequence*/ 2424 void dc_link_dp_handle_automated_test(struct dc_link *link); 2425 2426 /* handle DP Link loss sequence and try to recover RX link loss with best 2427 * effort 2428 */ 2429 void dc_link_dp_handle_link_loss(struct dc_link *link); 2430 2431 /* Determine if hpd rx irq should be handled or ignored 2432 * return true - hpd rx irq should be handled. 2433 * return false - it is safe to ignore hpd rx irq event 2434 */ 2435 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2436 2437 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2438 * @link - link the hpd irq data associated with 2439 * @hpd_irq_dpcd_data - input hpd irq data 2440 * return - true if hpd irq data indicates a link lost 2441 */ 2442 bool dc_link_check_link_loss_status(struct dc_link *link, 2443 union hpd_irq_data *hpd_irq_dpcd_data); 2444 2445 /* Read hpd rx irq data from a given link 2446 * @link - link where the hpd irq data should be read from 2447 * @irq_data - output hpd irq data 2448 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2449 * read has failed. 2450 */ 2451 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2452 struct dc_link *link, 2453 union hpd_irq_data *irq_data); 2454 2455 bool dc_link_frl_poll_status_flag(struct dc_link *link); 2456 bool dc_link_frl_margin_check_uncompressed_video( 2457 const struct dc_link *link, 2458 struct frl_cap_chk_params_fixed31_32 *params, 2459 struct frl_cap_chk_intermediates_fixed31_32 *inter); 2460 2461 /* The function clears recorded DP RX states in the link. DM should call this 2462 * function when it is resuming from S3 power state to previously connected links. 2463 * 2464 * TODO - in the future we should consider to expand link resume interface to 2465 * support clearing previous rx states. So we don't have to rely on dm to call 2466 * this interface explicitly. 2467 */ 2468 void dc_link_clear_dprx_states(struct dc_link *link); 2469 2470 /* Destruct the mst topology of the link and reset the allocated payload table 2471 * 2472 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2473 * still wants to reset MST topology on an unplug event */ 2474 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2475 2476 /* The function calculates effective DP link bandwidth when a given link is 2477 * using the given link settings. 2478 * 2479 * return - total effective link bandwidth in kbps. 2480 */ 2481 uint32_t dc_link_bandwidth_kbps( 2482 const struct dc_link *link, 2483 const struct dc_link_settings *link_setting); 2484 2485 /* The function returns effective HDMI FRL bandwidth given link rate. 2486 * return - total effective link bandwidth in kbps. 2487 */ 2488 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link, 2489 enum hdmi_frl_link_rate link_rate); 2490 2491 struct dp_audio_bandwidth_params { 2492 const struct dc_crtc_timing *crtc_timing; 2493 enum dp_link_encoding link_encoding; 2494 uint32_t channel_count; 2495 uint32_t sample_rate_hz; 2496 }; 2497 2498 /* The function calculates the minimum size of hblank (in bytes) needed to 2499 * support the specified channel count and sample rate combination, given the 2500 * link encoding and timing to be used. This calculation is not supported 2501 * for 8b/10b SST. 2502 * 2503 * return - min hblank size in bytes, 0 if 8b/10b SST. 2504 */ 2505 uint32_t dc_link_required_hblank_size_bytes( 2506 const struct dc_link *link, 2507 struct dp_audio_bandwidth_params *audio_params); 2508 2509 /* The function takes a snapshot of current link resource allocation state 2510 * @dc: pointer to dc of the dm calling this 2511 * @map: a dc link resource snapshot defined internally to dc. 2512 * 2513 * DM needs to capture a snapshot of current link resource allocation mapping 2514 * and store it in its persistent storage. 2515 * 2516 * Some of the link resource is using first come first serve policy. 2517 * The allocation mapping depends on original hotplug order. This information 2518 * is lost after driver is loaded next time. The snapshot is used in order to 2519 * restore link resource to its previous state so user will get consistent 2520 * link capability allocation across reboot. 2521 * 2522 */ 2523 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2524 2525 /* This function restores link resource allocation state from a snapshot 2526 * @dc: pointer to dc of the dm calling this 2527 * @map: a dc link resource snapshot defined internally to dc. 2528 * 2529 * DM needs to call this function after initial link detection on boot and 2530 * before first commit streams to restore link resource allocation state 2531 * from previous boot session. 2532 * 2533 * Some of the link resource is using first come first serve policy. 2534 * The allocation mapping depends on original hotplug order. This information 2535 * is lost after driver is loaded next time. The snapshot is used in order to 2536 * restore link resource to its previous state so user will get consistent 2537 * link capability allocation across reboot. 2538 * 2539 */ 2540 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2541 2542 void dc_link_wait_for_unlocked(struct dc_link *link); 2543 2544 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2545 * interface i.e stream_update->dsc_config 2546 */ 2547 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2548 2549 /* translate a raw link rate data to bandwidth in kbps */ 2550 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2551 2552 /* determine the optimal bandwidth given link and required bw. 2553 * @link - current detected link 2554 * @req_bw - requested bandwidth in kbps 2555 * @link_settings - returned most optimal link settings that can fit the 2556 * requested bandwidth 2557 * return - false if link can't support requested bandwidth, true if link 2558 * settings is found. 2559 */ 2560 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2561 struct dc_link_settings *link_settings, 2562 uint32_t req_bw); 2563 2564 /* return the max dp link settings can be driven by the link without considering 2565 * connected RX device and its capability 2566 */ 2567 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2568 struct dc_link_settings *max_link_enc_cap); 2569 2570 /* determine when the link is driving MST mode, what DP link channel coding 2571 * format will be used. The decision will remain unchanged until next HPD event. 2572 * 2573 * @link - a link with DP RX connection 2574 * return - if stream is committed to this link with MST signal type, type of 2575 * channel coding format dc will choose. 2576 */ 2577 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2578 const struct dc_link *link); 2579 2580 /* get max dp link settings the link can enable with all things considered. (i.e 2581 * TX/RX/Cable capabilities and dp override policies. 2582 * 2583 * @link - a link with DP RX connection 2584 * return - max dp link settings the link can enable. 2585 * 2586 */ 2587 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2588 2589 /* Get the highest encoding format that the link supports; highest meaning the 2590 * encoding format which supports the maximum bandwidth. 2591 * 2592 * @link - a link with DP RX connection 2593 * return - highest encoding format link supports. 2594 */ 2595 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2596 2597 /* get max frl link settings the link can enable with all things considered. 2598 * (i.e TX/RX capabilities and link verification result. 2599 * 2600 * @link - a link with FRL RX connection 2601 * return - max frl link settings the link can enable. 2602 * 2603 */ 2604 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap( 2605 struct dc_link *link); 2606 2607 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2608 * to a link with dp connector signal type. 2609 * @link - a link with dp connector signal type 2610 * return - true if connected, false otherwise 2611 */ 2612 bool dc_link_is_dp_sink_present(struct dc_link *link); 2613 2614 /* Force DP lane settings update to main-link video signal and notify the change 2615 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2616 * tuning purpose. The interface assumes link has already been enabled with DP 2617 * signal. 2618 * 2619 * @lt_settings - a container structure with desired hw_lane_settings 2620 */ 2621 void dc_link_set_drive_settings(struct dc *dc, 2622 struct link_training_settings *lt_settings, 2623 struct dc_link *link); 2624 2625 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2626 * test or debugging purpose. The test pattern will remain until next un-plug. 2627 * 2628 * @link - active link with DP signal output enabled. 2629 * @test_pattern - desired test pattern to output. 2630 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2631 * @test_pattern_color_space - for video test pattern choose a desired color 2632 * space. 2633 * @p_link_settings - For PHY pattern choose a desired link settings 2634 * @p_custom_pattern - some test pattern will require a custom input to 2635 * customize some pattern details. Otherwise keep it to NULL. 2636 * @cust_pattern_size - size of the custom pattern input. 2637 * 2638 */ 2639 bool dc_link_dp_set_test_pattern( 2640 struct dc_link *link, 2641 enum dp_test_pattern test_pattern, 2642 enum dp_test_pattern_color_space test_pattern_color_space, 2643 const struct link_training_settings *p_link_settings, 2644 const unsigned char *p_custom_pattern, 2645 unsigned int cust_pattern_size); 2646 2647 /* Force DP link settings to always use a specific value until reboot to a 2648 * specific link. If link has already been enabled, the interface will also 2649 * switch to desired link settings immediately. This is a debug interface to 2650 * generic dp issue trouble shooting. 2651 */ 2652 void dc_link_set_preferred_link_settings(struct dc *dc, 2653 struct dc_link_settings *link_setting, 2654 struct dc_link *link); 2655 2656 /* Force FRL link settings to always use a specific value until reboot to a 2657 * specific link. If link has already been enabled, the interface will also 2658 * switch to desired link settings immediately. This is a debug interface to 2659 * generic FRL issue trouble shooting. 2660 */ 2661 void dc_link_set_preferred_frl_link_settings(struct dc *dc, 2662 struct dc_hdmi_frl_link_settings *link_setting, 2663 struct dc_hdmi_frl_link_training_overrides *lt_overrides, 2664 struct dc_link *link); 2665 2666 /* Force DP link to customize a specific link training behavior by overriding to 2667 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2668 * display specific link training issues or apply some display specific 2669 * workaround in link training. 2670 * 2671 * @link_settings - if not NULL, force preferred link settings to the link. 2672 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2673 * will apply this particular override in future link training. If NULL is 2674 * passed in, dc resets previous overrides. 2675 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2676 * training settings. 2677 */ 2678 void dc_link_set_preferred_training_settings(struct dc *dc, 2679 struct dc_link_settings *link_setting, 2680 struct dc_link_training_overrides *lt_overrides, 2681 struct dc_link *link, 2682 bool skip_immediate_retrain); 2683 2684 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2685 bool dc_link_is_fec_supported(const struct dc_link *link); 2686 2687 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2688 * link enablement. 2689 * return - true if FEC should be enabled, false otherwise. 2690 */ 2691 bool dc_link_should_enable_fec(const struct dc_link *link); 2692 2693 /* determine lttpr mode the current link should be enabled with a specific link 2694 * settings. 2695 */ 2696 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2697 struct dc_link_settings *link_setting); 2698 2699 /* Force DP RX to update its power state. 2700 * NOTE: this interface doesn't update dp main-link. Calling this function will 2701 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2702 * RX power state back upon finish DM specific execution requiring DP RX in a 2703 * specific power state. 2704 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2705 * state. 2706 */ 2707 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2708 2709 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2710 * current value read from extended receiver cap from 02200h - 0220Fh. 2711 * Some DP RX has problems of providing accurate DP receiver caps from extended 2712 * field, this interface is a workaround to revert link back to use base caps. 2713 */ 2714 void dc_link_overwrite_extended_receiver_cap( 2715 struct dc_link *link); 2716 2717 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2718 bool wait_for_hpd); 2719 2720 /* Set backlight level of an embedded panel (eDP, LVDS). 2721 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2722 * and 16 bit fractional, where 1.0 is max backlight value. 2723 */ 2724 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2725 struct set_backlight_level_params *backlight_level_params); 2726 2727 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2728 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2729 bool isHDR, 2730 uint32_t backlight_millinits, 2731 uint32_t transition_time_in_ms); 2732 2733 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2734 uint32_t *backlight_millinits, 2735 uint32_t *backlight_millinits_peak); 2736 2737 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2738 2739 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2740 2741 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2742 bool wait, bool force_static, const unsigned int *power_opts); 2743 2744 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2745 2746 bool dc_link_setup_psr(struct dc_link *dc_link, 2747 const struct dc_stream_state *stream, struct psr_config *psr_config, 2748 struct psr_context *psr_context); 2749 2750 /* 2751 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2752 * 2753 * @link: pointer to the dc_link struct instance 2754 * @enable: enable(active) or disable(inactive) replay 2755 * @wait: state transition need to wait the active set completed. 2756 * @force_static: force disable(inactive) the replay 2757 * @power_opts: set power optimazation parameters to DMUB. 2758 * 2759 * return: allow Replay active will return true, else will return false. 2760 */ 2761 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2762 bool wait, bool force_static, const unsigned int *power_opts); 2763 2764 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2765 2766 /* 2767 * Enable or disable Panel Replay on the specified link: 2768 * 2769 * @link: pointer to the dc_link struct instance 2770 * @enable: enable or disable Panel Replay 2771 * 2772 * return: true if successful, false otherwise 2773 */ 2774 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2775 2776 /* 2777 * Update Panel Replay state parameters: 2778 * 2779 * @link: pointer to the dc_link struct instance 2780 * @update_state_data: pointer to state update data structure 2781 * 2782 * return: true if successful, false otherwise 2783 */ 2784 bool dc_link_update_pr_state(struct dc_link *link, 2785 struct dmub_cmd_pr_update_state_data *update_state_data); 2786 2787 /* 2788 * Send general command to Panel Replay firmware: 2789 * 2790 * @link: pointer to the dc_link struct instance 2791 * @general_cmd_data: pointer to general command data structure 2792 * 2793 * return: true if successful, false otherwise 2794 */ 2795 bool dc_link_set_pr_general_cmd(struct dc_link *link, 2796 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 2797 2798 /* 2799 * Get Panel Replay state: 2800 * 2801 * @link: pointer to the dc_link struct instance 2802 * @state: pointer to store the Panel Replay state 2803 * 2804 * return: true if successful, false otherwise 2805 */ 2806 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 2807 2808 /* On eDP links this function call will stall until T12 has elapsed. 2809 * If the panel is not in power off state, this function will return 2810 * immediately. 2811 */ 2812 bool dc_link_wait_for_t12(struct dc_link *link); 2813 2814 /* Determine if dp trace has been initialized to reflect upto date result * 2815 * return - true if trace is initialized and has valid data. False dp trace 2816 * doesn't have valid result. 2817 */ 2818 bool dc_dp_trace_is_initialized(struct dc_link *link); 2819 2820 /* Query a dp trace flag to indicate if the current dp trace data has been 2821 * logged before 2822 */ 2823 bool dc_dp_trace_is_logged(struct dc_link *link, 2824 bool in_detection); 2825 2826 /* Set dp trace flag to indicate whether DM has already logged the current dp 2827 * trace data. DM can set is_logged to true upon logging and check 2828 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2829 */ 2830 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2831 bool in_detection, 2832 bool is_logged); 2833 2834 /* Obtain driver time stamp for last dp link training end. The time stamp is 2835 * formatted based on dm_get_timestamp DM function. 2836 * @in_detection - true to get link training end time stamp of last link 2837 * training in detection sequence. false to get link training end time stamp 2838 * of last link training in commit (dpms) sequence 2839 */ 2840 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2841 bool in_detection); 2842 2843 /* Get how many link training attempts dc has done with latest sequence. 2844 * @in_detection - true to get link training count of last link 2845 * training in detection sequence. false to get link training count of last link 2846 * training in commit (dpms) sequence 2847 */ 2848 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2849 bool in_detection); 2850 2851 /* Get how many link loss has happened since last link training attempts */ 2852 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2853 2854 /* 2855 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2856 */ 2857 /* 2858 * Send a request from DP-Tx requesting to allocate BW remotely after 2859 * allocating it locally. This will get processed by CM and a CB function 2860 * will be called. 2861 * 2862 * @link: pointer to the dc_link struct instance 2863 * @req_bw: The requested bw in Kbyte to allocated 2864 * 2865 * return: none 2866 */ 2867 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2868 2869 /* 2870 * Handle the USB4 BW Allocation related functionality here: 2871 * Plug => Try to allocate max bw from timing parameters supported by the sink 2872 * Unplug => de-allocate bw 2873 * 2874 * @link: pointer to the dc_link struct instance 2875 * @peak_bw: Peak bw used by the link/sink 2876 * 2877 */ 2878 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2879 struct dc_link *link, int peak_bw); 2880 2881 /* 2882 * Calculates the DP tunneling bandwidth required for the stream timing 2883 * and aggregates the stream bandwidth for the respective DP tunneling link 2884 * 2885 * return: dc_status 2886 */ 2887 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2888 2889 /* 2890 * Get if ALPM is supported by the link 2891 */ 2892 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 2893 bool *auxwake_support); 2894 2895 /* Sink Interfaces - A sink corresponds to a display output device */ 2896 2897 struct dc_container_id { 2898 // 128bit GUID in binary form 2899 unsigned char guid[16]; 2900 // 8 byte port ID -> ELD.PortID 2901 unsigned int portId[2]; 2902 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2903 unsigned short manufacturerName; 2904 // 2 byte product code -> ELD.ProductCode 2905 unsigned short productCode; 2906 }; 2907 2908 2909 struct dc_sink_dsc_caps { 2910 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2911 // 'false' if they are sink's DSC caps 2912 bool is_virtual_dpcd_dsc; 2913 // 'true' if MST topology supports DSC passthrough for sink 2914 // 'false' if MST topology does not support DSC passthrough 2915 bool is_dsc_passthrough_supported; 2916 struct dsc_dec_dpcd_caps dsc_dec_caps; 2917 }; 2918 2919 struct dc_sink_hblank_expansion_caps { 2920 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2921 // 'false' if they are sink's HBlank expansion caps 2922 bool is_virtual_dpcd_hblank_expansion; 2923 struct hblank_expansion_dpcd_caps dpcd_caps; 2924 }; 2925 2926 struct dc_sink_fec_caps { 2927 bool is_rx_fec_supported; 2928 bool is_topology_fec_supported; 2929 }; 2930 2931 struct scdc_caps { 2932 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2933 union hdmi_scdc_device_id_data device_id; 2934 }; 2935 2936 /* 2937 * The sink structure contains EDID and other display device properties 2938 */ 2939 struct dc_sink { 2940 enum signal_type sink_signal; 2941 struct dc_edid dc_edid; /* raw edid */ 2942 struct dc_edid_caps edid_caps; /* parse display caps */ 2943 struct dc_container_id *dc_container_id; 2944 uint32_t dongle_max_pix_clk; 2945 void *priv; 2946 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2947 bool converter_disable_audio; 2948 2949 struct mccs_caps mccs_caps; 2950 struct scdc_caps scdc_caps; 2951 struct dc_sink_dsc_caps dsc_caps; 2952 struct dc_sink_fec_caps fec_caps; 2953 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2954 2955 bool is_vsc_sdp_colorimetry_supported; 2956 2957 /* private to DC core */ 2958 struct dc_link *link; 2959 struct dc_context *ctx; 2960 2961 uint32_t sink_id; 2962 2963 /* private to dc_sink.c */ 2964 // refcount must be the last member in dc_sink, since we want the 2965 // sink structure to be logically cloneable up to (but not including) 2966 // refcount 2967 struct kref refcount; 2968 }; 2969 2970 void dc_sink_retain(struct dc_sink *sink); 2971 void dc_sink_release(struct dc_sink *sink); 2972 2973 struct dc_sink_init_data { 2974 enum signal_type sink_signal; 2975 struct dc_link *link; 2976 uint32_t dongle_max_pix_clk; 2977 bool converter_disable_audio; 2978 }; 2979 2980 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2981 2982 /* Newer interfaces */ 2983 struct dc_cursor { 2984 struct dc_plane_address address; 2985 struct dc_cursor_attributes attributes; 2986 }; 2987 2988 2989 /* Interrupt interfaces */ 2990 enum dc_irq_source dc_interrupt_to_irq_source( 2991 struct dc *dc, 2992 uint32_t src_id, 2993 uint32_t ext_id); 2994 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2995 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2996 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2997 struct dc *dc, uint32_t link_index); 2998 2999 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 3000 3001 /* Power Interfaces */ 3002 3003 void dc_set_power_state( 3004 struct dc *dc, 3005 enum dc_acpi_cm_power_state power_state); 3006 void dc_resume(struct dc *dc); 3007 3008 void dc_power_down_on_boot(struct dc *dc); 3009 3010 /* 3011 * HDCP Interfaces 3012 */ 3013 enum hdcp_message_status dc_process_hdcp_msg( 3014 enum signal_type signal, 3015 struct dc_link *link, 3016 struct hdcp_protection_message *message_info); 3017 bool dc_is_dmcu_initialized(struct dc *dc); 3018 3019 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 3020 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 3021 3022 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 3023 unsigned int pitch, 3024 unsigned int height, 3025 enum surface_pixel_format format, 3026 struct dc_cursor_attributes *cursor_attr); 3027 3028 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 3029 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 3030 3031 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 3032 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 3033 bool dc_dmub_is_ips_idle_state(struct dc *dc); 3034 3035 /* set min and max memory clock to lowest and highest DPM level, respectively */ 3036 void dc_unlock_memory_clock_frequency(struct dc *dc); 3037 3038 /* set min memory clock to the min required for current mode, max to maxDPM */ 3039 void dc_lock_memory_clock_frequency(struct dc *dc); 3040 3041 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 3042 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 3043 3044 /* cleanup on driver unload */ 3045 void dc_hardware_release(struct dc *dc); 3046 3047 /* disables fw based mclk switch */ 3048 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 3049 3050 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 3051 3052 bool dc_set_replay_allow_active(struct dc *dc, bool active); 3053 3054 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 3055 3056 void dc_z10_restore(const struct dc *dc); 3057 void dc_z10_save_init(struct dc *dc); 3058 3059 bool dc_is_dmub_outbox_supported(struct dc *dc); 3060 bool dc_enable_dmub_notifications(struct dc *dc); 3061 3062 bool dc_abm_save_restore( 3063 struct dc *dc, 3064 struct dc_stream_state *stream, 3065 struct abm_save_restore *pData); 3066 3067 void dc_enable_dmub_outbox(struct dc *dc); 3068 3069 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 3070 uint32_t link_index, 3071 struct aux_payload *payload); 3072 3073 /* 3074 * smart power OLED Interfaces 3075 */ 3076 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 3077 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 3078 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 3079 3080 /* Get dc link index from dpia port index */ 3081 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 3082 uint8_t dpia_port_index); 3083 3084 bool dc_process_dmub_set_config_async(struct dc *dc, 3085 uint32_t link_index, 3086 struct set_config_cmd_payload *payload, 3087 struct dmub_notification *notify); 3088 3089 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 3090 uint32_t link_index, 3091 uint8_t mst_alloc_slots, 3092 uint8_t *mst_slots_in_use); 3093 3094 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 3095 3096 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 3097 uint32_t hpd_int_enable); 3098 3099 void dc_print_dmub_diagnostic_data(const struct dc *dc); 3100 3101 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 3102 3103 struct dc_power_profile { 3104 int power_level; /* Lower is better */ 3105 }; 3106 3107 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 3108 3109 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 3110 3111 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 3112 3113 void dc_log_preos_dmcub_info(const struct dc *dc); 3114 3115 /* DSC Interfaces */ 3116 #include "dc_dsc.h" 3117 3118 void dc_get_visual_confirm_for_stream( 3119 struct dc *dc, 3120 struct dc_stream_state *stream_state, 3121 struct tg_color *color); 3122 3123 /* Disable acc mode Interfaces */ 3124 void dc_disable_accelerated_mode(struct dc *dc); 3125 3126 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 3127 struct dc_stream_state *new_stream); 3128 3129 bool dc_is_cursor_limit_pending(struct dc *dc); 3130 bool dc_can_clear_cursor_limit(const struct dc *dc); 3131 3132 /** 3133 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 3134 * 3135 * @dc: Pointer to the display core context. 3136 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 3137 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 3138 * 3139 * This function collects and logs underflow-related HW states when underflow happens, 3140 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 3141 * The results are stored in the provided out_data structure for further analysis or logging. 3142 */ 3143 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); 3144 3145 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); 3146 3147 /* 3148 * Software state variables used to program register fields across the display pipeline 3149 */ 3150 struct dc_register_software_state { 3151 /* HUBP register programming variables for each pipe */ 3152 struct { 3153 bool valid_plane_state; 3154 bool valid_stream; 3155 bool min_dc_gfx_version9; 3156 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 3157 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 3158 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 3159 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 3160 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 3161 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 3162 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 3163 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 3164 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 3165 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 3166 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 3167 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 3168 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 3169 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 3170 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 3171 3172 /* Additional DCC configuration */ 3173 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 3174 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 3175 3176 /* Surface pitch configuration */ 3177 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 3178 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 3179 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 3180 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 3181 3182 /* Surface addresses */ 3183 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 3184 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 3185 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 3186 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 3187 3188 /* TMZ configuration */ 3189 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 3190 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 3191 3192 /* Tiling configuration */ 3193 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 3194 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 3195 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 3196 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 3197 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 3198 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 3199 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 3200 3201 /* DML Request Size Configuration - Luma */ 3202 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 3203 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 3204 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 3205 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 3206 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 3207 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 3208 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 3209 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 3210 3211 /* DML Request Size Configuration - Chroma */ 3212 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 3213 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 3214 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 3215 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 3216 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 3217 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 3218 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 3219 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 3220 3221 /* DML Expansion Modes */ 3222 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 3223 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 3224 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 3225 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 3226 3227 /* DML DLG parameters - nominal */ 3228 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 3229 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 3230 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 3231 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 3232 3233 /* DML prefetch settings */ 3234 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 3235 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 3236 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 3237 3238 /* TTU parameters */ 3239 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 3240 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 3241 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 3242 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 3243 } hubp[MAX_PIPES]; 3244 3245 /* HUBBUB register programming variables */ 3246 struct { 3247 /* Individual DET buffer control per pipe - software state that programs DET registers */ 3248 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 3249 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 3250 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 3251 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 3252 3253 /* Compression buffer control - software state that programs COMPBUF registers */ 3254 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 3255 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 3256 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 3257 } hubbub; 3258 3259 /* DPP register programming variables for each pipe (simplified for available fields) */ 3260 struct { 3261 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 3262 3263 /* Recout (Rectangle of Interest) configuration */ 3264 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 3265 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 3266 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 3267 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 3268 3269 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 3270 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 3271 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 3272 3273 /* DSCL mode configuration */ 3274 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3275 3276 /* Scaler ratios (simplified to integer parts) */ 3277 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3278 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3279 3280 /* Basic scaler taps */ 3281 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3282 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3283 } dpp[MAX_PIPES]; 3284 3285 /* DCCG register programming variables */ 3286 struct { 3287 /* Core Display Clock Control */ 3288 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3289 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3290 3291 /* DPP Clock Control - 4 fields per pipe */ 3292 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3293 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3294 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3295 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3296 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3297 3298 /* DSC Clock Control - 4 fields per DSC resource */ 3299 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3300 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3301 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3302 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3303 3304 /* Pixel Clock Control - per pipe */ 3305 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3306 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3307 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3308 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3309 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3310 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3311 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3312 3313 /* DTBCLK DTO Control - 4 DTOs */ 3314 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3315 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3316 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3317 3318 /* DP Stream Clock Control - 4 pipes */ 3319 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3320 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3321 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3322 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3323 3324 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3325 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3326 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3327 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3328 3329 /* SYMCLK32 SE Control - 4 instances */ 3330 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3331 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3332 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3333 3334 /* SYMCLK32 LE Control - 2 instances */ 3335 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3336 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3337 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3338 3339 /* HDMI Clock Control */ 3340 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */ 3341 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */ 3342 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */ 3343 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */ 3344 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */ 3345 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */ 3346 3347 /* DPIA Clock Control */ 3348 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3349 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3350 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3351 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3352 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3353 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3354 3355 /* Clock Gating Control */ 3356 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3357 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3358 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3359 3360 /* VSync Control */ 3361 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3362 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3363 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3364 3365 /* Time Base Control */ 3366 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3367 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3368 } dccg; 3369 3370 /* DSC essential configuration for underflow analysis */ 3371 struct { 3372 /* DSC active state - critical for bandwidth analysis */ 3373 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3374 3375 /* DSC configuration affecting bandwidth and timing */ 3376 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3377 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3378 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3379 3380 /* OPP integration - affects pipeline flow */ 3381 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3382 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3383 } dsc[MAX_PIPES]; 3384 3385 /* MPC register programming variables */ 3386 struct { 3387 /* MPCC blending tree and mode control */ 3388 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3389 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3390 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3391 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3392 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3393 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3394 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3395 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3396 3397 /* MPCC blending tree connections */ 3398 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3399 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3400 3401 /* MPCC output gamma control */ 3402 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3403 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3404 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3405 3406 /* MPCC pipe assignment and status */ 3407 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3408 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3409 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3410 3411 /* MPC output processing */ 3412 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3413 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3414 } mpc; 3415 3416 /* OPP register programming variables for each pipe */ 3417 struct { 3418 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3419 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3420 3421 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3422 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3423 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3424 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3425 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3426 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3427 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3428 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3429 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3430 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3431 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3432 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3433 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3434 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3435 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3436 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3437 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3438 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3439 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3440 3441 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3442 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3443 3444 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3445 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3446 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3447 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3448 3449 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3450 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3451 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3452 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3453 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3454 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3455 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3456 3457 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3458 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3459 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3460 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3461 } opp[MAX_PIPES]; 3462 3463 /* OPTC register programming variables for each pipe */ 3464 struct { 3465 uint32_t otg_master_inst; 3466 3467 /* OTG_CONTROL register - 5 fields for OTG control */ 3468 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3469 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3470 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3471 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3472 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3473 3474 /* OTG Horizontal Timing - 7 fields */ 3475 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3476 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3477 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3478 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3479 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3480 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3481 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3482 3483 /* OTG Vertical Timing - 7 fields */ 3484 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3485 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3486 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3487 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3488 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3489 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3490 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3491 3492 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3493 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3494 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3495 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3496 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3497 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3498 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3499 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3500 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3501 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3502 3503 /* OPTC Data Source and ODM - 6 fields */ 3504 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3505 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3506 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3507 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3508 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3509 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3510 3511 /* OPTC Data Format and DSC - 4 fields */ 3512 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3513 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3514 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3515 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3516 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3517 3518 /* OPTC Clock and Underflow Control - 4 fields */ 3519 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3520 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3521 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3522 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3523 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3524 3525 /* OTG Stereo and 3D Control - 6 fields */ 3526 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3527 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3528 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3529 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3530 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3531 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3532 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3533 3534 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3535 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3536 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3537 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3538 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3539 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3540 3541 /* OTG DRR Advanced Control - 4 fields */ 3542 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3543 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3544 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3545 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3546 3547 /* OTG DSC Position Control - 2 fields */ 3548 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3549 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3550 3551 /* OTG Double Buffer Control - 2 fields */ 3552 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3553 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3554 3555 /* OTG Vertical Interrupts - 6 fields */ 3556 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3557 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3558 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3559 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3560 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3561 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3562 3563 /* OTG Global Sync Parameters - 6 fields */ 3564 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3565 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3566 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3567 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3568 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3569 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3570 3571 /* OTG Manual Trigger Control - 11 fields */ 3572 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3573 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3574 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3575 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3576 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3577 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3578 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3579 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3580 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3581 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3582 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3583 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3584 3585 /* OTG Static Screen and Update Control - 6 fields */ 3586 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3587 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3588 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3589 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3590 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3591 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3592 3593 /* VTG Control - 3 fields */ 3594 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3595 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3596 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3597 3598 /* OTG Status (Read-Only) - 12 fields */ 3599 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3600 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3601 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3602 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3603 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3604 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3605 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3606 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3607 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3608 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3609 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3610 } optc[MAX_PIPES]; 3611 3612 /* Metadata */ 3613 uint32_t active_pipe_count; 3614 uint32_t active_stream_count; 3615 bool state_valid; 3616 }; 3617 3618 /** 3619 * dc_capture_register_software_state() - Capture software state for register programming 3620 * @dc: DC context containing current display configuration 3621 * @state: Pointer to dc_register_software_state structure to populate 3622 * 3623 * Extracts all software state variables that are used to program hardware register 3624 * fields across the display driver pipeline. This provides a complete snapshot 3625 * of the software configuration that drives hardware register programming. 3626 * 3627 * The function traverses the DC context and extracts values from: 3628 * - Stream configurations (timing, format, DSC settings) 3629 * - Plane states (surface format, rotation, scaling, cursor) 3630 * - Pipe contexts (resource allocation, blending, viewport) 3631 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3632 * - Resource context (DET buffer allocation, ODM configuration) 3633 * 3634 * This is essential for underflow debugging as it captures the exact software 3635 * state that determines how registers are programmed, allowing analysis of 3636 * whether underflow is caused by incorrect register programming or timing issues. 3637 * 3638 * Return: true if state was successfully captured, false on error 3639 */ 3640 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3641 3642 /** 3643 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3644 * @dc: DC context containing current display configuration 3645 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3646 * 3647 * This function retrieves QoS metrics from the display core that can be used by 3648 * benchmark tools to analyze display system performance. The function may take 3649 * several milliseconds to execute due to hardware measurement requirements. 3650 * 3651 * QoS information includes: 3652 * - Bandwidth bounds (lower limits in Mbps) 3653 * - Latency bounds (upper limits in nanoseconds) 3654 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3655 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3656 * 3657 * The function will populate the provided dc_qos_info structure with current 3658 * QoS measurements. If hardware measurement functions are not available for 3659 * the current DCN version, the function returns false with zero'd info structure. 3660 * 3661 * Return: true if QoS information was successfully retrieved, false if measurement 3662 * functions are unavailable or hardware measurements cannot be performed 3663 */ 3664 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3665 3666 /** 3667 * dc_override_memory_bandwidth_request - Override the DCN nominal memory 3668 * bandwidth request sent to PMFW, independent of the current display mode. 3669 * For debug use only. 3670 * @dc: DC instance 3671 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override 3672 * 3673 * Return: capped bandwidth value actually applied (MB/s) 3674 */ 3675 unsigned int dc_override_memory_bandwidth_request( 3676 struct dc *dc, 3677 unsigned int bw_mbps); 3678 3679 #endif /* DC_INTERFACE_H_ */ 3680