1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2_0/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "dml/dml1_frl_cap_chk.h" 50 51 #include "sspl/dc_spl_types.h" 52 53 struct abm_save_restore; 54 55 /* forward declaration */ 56 struct aux_payload; 57 struct set_config_cmd_payload; 58 struct dmub_notification; 59 struct dcn_hubbub_reg_state; 60 struct dcn_hubp_reg_state; 61 struct dcn_dpp_reg_state; 62 struct dcn_mpc_reg_state; 63 struct dcn_opp_reg_state; 64 struct dcn_dsc_reg_state; 65 struct dcn_optc_reg_state; 66 struct dcn_dccg_reg_state; 67 68 #define DC_VER "3.2.388" 69 70 /** 71 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 72 */ 73 #define MAX_SURFACES 4 74 /** 75 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 76 */ 77 #define MAX_PLANES 6 78 #define MAX_STREAMS 6 79 #define MIN_VIEWPORT_SIZE 12 80 #define MAX_NUM_EDP 2 81 #define MAX_SUPPORTED_FORMATS 7 82 83 #define MAX_HOST_ROUTERS_NUM 3 84 #define MAX_DPIA_PER_HOST_ROUTER 3 85 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 86 87 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 88 89 struct frl_cap_chk_intermediates_fixed31_32 { 90 int c_frl_sb; 91 struct fixed31_32 overhead_sb; 92 struct fixed31_32 overhead_rs; 93 struct fixed31_32 overhead_map; 94 struct fixed31_32 overhead_min; 95 struct fixed31_32 overhead_max; 96 struct fixed31_32 f_pixel_clock_max; 97 struct fixed31_32 t_line; 98 struct fixed31_32 r_bit_min; 99 struct fixed31_32 r_frl_char_min; 100 struct fixed31_32 c_frl_line; 101 struct fixed31_32 ap; 102 struct fixed31_32 r_ap; 103 struct fixed31_32 avg_audio_packets_line; 104 struct fixed31_32 margin; 105 int audio_packets_line; 106 int blank_audio_min; 107 }; 108 109 struct frl_cap_chk_params_fixed31_32 { 110 int lanes; 111 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 112 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ 113 int audio_packet_type; 114 struct fixed31_32 f_audio; /* Audio rate (Hz) */ 115 int h_active; /* Active pixels per line */ 116 int h_blank; /* Blanking pixels per line */ 117 int bpc; /* Bits per component */ 118 int vic; /* Video Identification Code */ 119 120 enum hdmi_frl_pixel_encoding pixel_encoding; 121 122 bool compressed; /* set to true if DSC is enabled */ 123 bool bypass_hc_target_calc; /* debug only */ 124 bool allow_all_bpp; /* dsc_all_bpp */ 125 126 /* DSC parameters */ 127 int slices; 128 int slice_width; 129 struct fixed31_32 bpp_target; 130 int layout; 131 int acat; /* not supported */ 132 133 /* outputs */ 134 struct frl_dml_borrow_params borrow_params; 135 int average_tribyte_rate; 136 }; 137 138 /* Display Core Interfaces */ 139 struct dc_versions { 140 const char *dc_ver; 141 struct dmcu_version dmcu_version; 142 }; 143 144 enum dp_protocol_version { 145 DP_VERSION_1_4 = 0, 146 DP_VERSION_2_1, 147 DP_VERSION_UNKNOWN, 148 }; 149 150 enum dc_plane_type { 151 DC_PLANE_TYPE_INVALID, 152 DC_PLANE_TYPE_DCE_RGB, 153 DC_PLANE_TYPE_DCE_UNDERLAY, 154 DC_PLANE_TYPE_DCN_UNIVERSAL, 155 }; 156 157 // Sizes defined as multiples of 64KB 158 enum det_size { 159 DET_SIZE_DEFAULT = 0, 160 DET_SIZE_192KB = 3, 161 DET_SIZE_256KB = 4, 162 DET_SIZE_320KB = 5, 163 DET_SIZE_384KB = 6 164 }; 165 166 167 struct dc_plane_cap { 168 enum dc_plane_type type; 169 uint32_t per_pixel_alpha : 1; 170 struct { 171 uint32_t argb8888 : 1; 172 uint32_t nv12 : 1; 173 uint32_t fp16 : 1; 174 uint32_t p010 : 1; 175 uint32_t ayuv : 1; 176 } pixel_format_support; 177 // max upscaling factor x1000 178 // upscaling factors are always >= 1 179 // for example, 1080p -> 8K is 4.0, or 4000 raw value 180 struct { 181 uint32_t argb8888; 182 uint32_t nv12; 183 uint32_t fp16; 184 } max_upscale_factor; 185 // max downscale factor x1000 186 // downscale factors are always <= 1 187 // for example, 8K -> 1080p is 0.25, or 250 raw value 188 struct { 189 uint32_t argb8888; 190 uint32_t nv12; 191 uint32_t fp16; 192 } max_downscale_factor; 193 // minimal width/height 194 uint32_t min_width; 195 uint32_t min_height; 196 }; 197 198 /** 199 * DOC: color-management-caps 200 * 201 * **Color management caps (DPP and MPC)** 202 * 203 * Modules/color calculates various color operations which are translated to 204 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 205 * DCN1, every new generation comes with fairly major differences in color 206 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 207 * decide mapping to HW block based on logical capabilities. 208 */ 209 210 /** 211 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 212 * @srgb: RGB color space transfer func 213 * @bt2020: BT.2020 transfer func 214 * @gamma2_2: standard gamma 215 * @pq: perceptual quantizer transfer function 216 * @hlg: hybrid log–gamma transfer function 217 */ 218 struct rom_curve_caps { 219 uint16_t srgb : 1; 220 uint16_t bt2020 : 1; 221 uint16_t gamma2_2 : 1; 222 uint16_t pq : 1; 223 uint16_t hlg : 1; 224 }; 225 226 /** 227 * struct dpp_color_caps - color pipeline capabilities for display pipe and 228 * plane blocks 229 * 230 * @dcn_arch: all DCE generations treated the same 231 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 232 * just plain 256-entry lookup 233 * @icsc: input color space conversion 234 * @dgam_ram: programmable degamma LUT 235 * @post_csc: post color space conversion, before gamut remap 236 * @gamma_corr: degamma correction 237 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 238 * with MPC by setting mpc:shared_3d_lut flag 239 * @ogam_ram: programmable out/blend gamma LUT 240 * @ocsc: output color space conversion 241 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 242 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 243 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 244 * 245 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 246 */ 247 struct dpp_color_caps { 248 uint16_t dcn_arch : 1; 249 uint16_t input_lut_shared : 1; 250 uint16_t icsc : 1; 251 uint16_t dgam_ram : 1; 252 uint16_t post_csc : 1; 253 uint16_t gamma_corr : 1; 254 uint16_t hw_3d_lut : 1; 255 uint16_t ogam_ram : 1; 256 uint16_t ocsc : 1; 257 uint16_t dgam_rom_for_yuv : 1; 258 struct rom_curve_caps dgam_rom_caps; 259 struct rom_curve_caps ogam_rom_caps; 260 }; 261 262 /* Below structure is to describe the HW support for mem layout, extend support 263 range to match what OS could handle in the roadmap */ 264 struct lut3d_caps { 265 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 266 struct { 267 uint32_t swizzle_3d_rgb : 1; 268 uint32_t swizzle_3d_bgr : 1; 269 uint32_t linear_1d : 1; 270 } mem_layout_support; 271 struct { 272 uint32_t unorm_12msb : 1; 273 uint32_t unorm_12lsb : 1; 274 uint32_t float_fp1_5_10 : 1; 275 } mem_format_support; 276 struct { 277 uint32_t order_rgba : 1; 278 uint32_t order_bgra : 1; 279 } mem_pixel_order_support; 280 /*< size options are 9, 17, 33, 45, 65 */ 281 struct { 282 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 283 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 284 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 285 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 286 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 287 } lut_dim_caps; 288 }; 289 290 /** 291 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 292 * plane combined blocks 293 * 294 * @gamut_remap: color transformation matrix 295 * @ogam_ram: programmable out gamma LUT 296 * @ocsc: output color space conversion matrix 297 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 298 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 299 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 300 * instance 301 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 302 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 303 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 304 * @preblend: whether color manager supports preblend with MPC 305 */ 306 struct mpc_color_caps { 307 uint16_t gamut_remap : 1; 308 uint16_t ogam_ram : 1; 309 uint16_t ocsc : 1; 310 uint16_t num_3dluts : 3; 311 uint16_t num_rmcm_3dluts : 3; 312 uint16_t shared_3d_lut:1; 313 struct rom_curve_caps ogam_rom_caps; 314 struct lut3d_caps mcm_3d_lut_caps; 315 struct lut3d_caps rmcm_3d_lut_caps; 316 bool preblend; 317 }; 318 319 /** 320 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 321 * @dpp: color pipes caps for DPP 322 * @mpc: color pipes caps for MPC 323 */ 324 struct dc_color_caps { 325 struct dpp_color_caps dpp; 326 struct mpc_color_caps mpc; 327 }; 328 329 struct dc_dmub_caps { 330 bool psr; 331 bool mclk_sw; 332 bool subvp_psr; 333 bool gecc_enable; 334 uint8_t fams_ver; 335 bool aux_backlight_support; 336 }; 337 338 struct dc_scl_caps { 339 bool sharpener_support; 340 }; 341 342 struct dc_check_config { 343 /** 344 * max video plane width that can be safely assumed to be always 345 * supported by single DPP pipe. 346 */ 347 unsigned int max_optimizable_video_width; 348 bool enable_legacy_fast_update; 349 350 bool deferred_transition_state; 351 unsigned int transition_countdown_to_steady_state; 352 }; 353 354 struct dc_caps { 355 uint32_t max_streams; 356 uint32_t max_links; 357 uint32_t max_audios; 358 uint32_t max_slave_planes; 359 uint32_t max_slave_yuv_planes; 360 uint32_t max_slave_rgb_planes; 361 uint32_t max_planes; 362 uint32_t max_downscale_ratio; 363 uint32_t i2c_speed_in_khz; 364 uint32_t i2c_speed_in_khz_hdcp; 365 uint32_t dmdata_alloc_size; 366 unsigned int max_cursor_size; 367 unsigned int max_buffered_cursor_size; 368 unsigned int max_video_width; 369 unsigned int min_horizontal_blanking_period; 370 int linear_pitch_alignment; 371 bool dcc_const_color; 372 bool dynamic_audio; 373 bool is_apu; 374 bool dual_link_dvi; 375 bool post_blend_color_processing; 376 bool force_dp_tps4_for_cp2520; 377 bool disable_dp_clk_share; 378 bool psp_setup_panel_mode; 379 bool extended_aux_timeout_support; 380 bool dmcub_support; 381 bool zstate_support; 382 bool ips_support; 383 bool ips_v2_support; 384 uint32_t num_of_internal_disp; 385 enum dp_protocol_version max_dp_protocol_version; 386 bool hdmi_hpo; 387 unsigned int mall_size_per_mem_channel; 388 unsigned int mall_size_total; 389 unsigned int cursor_cache_size; 390 struct dc_plane_cap planes[MAX_PLANES]; 391 struct dc_color_caps color; 392 struct dc_dmub_caps dmub_caps; 393 bool dp_hpo; 394 bool dp_hdmi21_pcon_support; 395 bool edp_dsc_support; 396 bool vbios_lttpr_aware; 397 bool vbios_lttpr_enable; 398 bool fused_io_supported; 399 uint32_t max_otg_num; 400 uint32_t max_cab_allocation_bytes; 401 uint32_t cache_line_size; 402 uint32_t cache_num_ways; 403 uint16_t subvp_fw_processing_delay_us; 404 uint8_t subvp_drr_max_vblank_margin_us; 405 uint16_t subvp_prefetch_end_to_mall_start_us; 406 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 407 uint16_t subvp_pstate_allow_width_us; 408 uint16_t subvp_vertical_int_margin_us; 409 bool seamless_odm; 410 uint32_t max_v_total; 411 bool vtotal_limited_by_fp2; 412 uint32_t max_disp_clock_khz_at_vmin; 413 uint8_t subvp_drr_vblank_start_margin_us; 414 bool cursor_not_scaled; 415 bool dcmode_power_limits_present; 416 bool sequential_ono; 417 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 418 uint32_t dcc_plane_width_limit; 419 struct dc_scl_caps scl_caps; 420 uint8_t num_of_host_routers; 421 uint8_t num_of_dpias_per_host_router; 422 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 423 uint8_t max_odm_combine_factor; 424 }; 425 426 struct dc_bug_wa { 427 bool no_connect_phy_config; 428 bool dedcn20_305_wa; 429 bool skip_clock_update; 430 bool lt_early_cr_pattern; 431 struct { 432 uint8_t uclk : 1; 433 uint8_t fclk : 1; 434 uint8_t dcfclk : 1; 435 uint8_t dcfclk_ds: 1; 436 } clock_update_disable_mask; 437 bool skip_psr_ips_crtc_disable; 438 }; 439 struct dc_dcc_surface_param { 440 struct dc_size surface_size; 441 enum surface_pixel_format format; 442 unsigned int plane0_pitch; 443 struct dc_size plane1_size; 444 unsigned int plane1_pitch; 445 union { 446 enum swizzle_mode_values swizzle_mode; 447 enum swizzle_mode_addr3_values swizzle_mode_addr3; 448 }; 449 enum dc_scan_direction scan; 450 }; 451 452 struct dc_dcc_setting { 453 unsigned int max_compressed_blk_size; 454 unsigned int max_uncompressed_blk_size; 455 bool independent_64b_blks; 456 //These bitfields to be used starting with DCN 3.0 457 struct { 458 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 459 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 460 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 461 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 462 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 463 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 464 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 465 } dcc_controls; 466 }; 467 468 struct dc_surface_dcc_cap { 469 union { 470 struct { 471 struct dc_dcc_setting rgb; 472 } grph; 473 474 struct { 475 struct dc_dcc_setting luma; 476 struct dc_dcc_setting chroma; 477 } video; 478 }; 479 480 bool capable; 481 bool const_color_support; 482 }; 483 484 struct dc_static_screen_params { 485 struct { 486 bool force_trigger; 487 bool cursor_update; 488 bool surface_update; 489 bool overlay_update; 490 } triggers; 491 unsigned int num_frames; 492 }; 493 494 495 /* Surface update type is used by dc_update_surfaces_and_stream 496 * The update type is determined at the very beginning of the function based 497 * on parameters passed in and decides how much programming (or updating) is 498 * going to be done during the call. 499 * 500 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 501 * logical calculations or hardware register programming. This update MUST be 502 * ISR safe on windows. Currently fast update will only be used to flip surface 503 * address. 504 * 505 * UPDATE_TYPE_MED is used for slower updates which require significant hw 506 * re-programming however do not affect bandwidth consumption or clock 507 * requirements. At present, this is the level at which front end updates 508 * that do not require us to run bw_calcs happen. These are in/out transfer func 509 * updates, viewport offset changes, recout size changes and pixel depth changes. 510 * This update can be done at ISR, but we want to minimize how often this happens. 511 * 512 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 513 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 514 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 515 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 516 * a full update. This cannot be done at ISR level and should be a rare event. 517 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 518 * underscan we don't expect to see this call at all. 519 */ 520 521 enum surface_update_type { 522 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 523 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 524 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 525 }; 526 527 enum dc_lock_descriptor { 528 LOCK_DESCRIPTOR_NONE = 0x0, 529 LOCK_DESCRIPTOR_STREAM = 0x1, 530 LOCK_DESCRIPTOR_LINK = 0x2, 531 LOCK_DESCRIPTOR_GLOBAL = 0x4, 532 }; 533 534 struct surface_update_descriptor { 535 enum surface_update_type update_type; 536 enum dc_lock_descriptor lock_descriptor; 537 }; 538 539 /* Forward declaration*/ 540 struct dc; 541 struct dc_plane_state; 542 struct dc_state; 543 544 struct dc_cap_funcs { 545 bool (*get_dcc_compression_cap)(const struct dc *dc, 546 const struct dc_dcc_surface_param *input, 547 struct dc_surface_dcc_cap *output); 548 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 549 }; 550 551 struct link_training_settings; 552 553 union allow_lttpr_non_transparent_mode { 554 struct { 555 bool DP1_4A : 1; 556 bool DP2_0 : 1; 557 } bits; 558 unsigned char raw; 559 }; 560 /* Structure to hold configuration flags set by dm at dc creation. */ 561 struct dc_config { 562 bool gpu_vm_support; 563 bool disable_disp_pll_sharing; 564 bool fbc_support; 565 bool disable_fractional_pwm; 566 bool allow_seamless_boot_optimization; 567 bool seamless_boot_edp_requested; 568 bool edp_not_connected; 569 bool edp_no_power_sequencing; 570 bool force_enum_edp; 571 bool forced_clocks; 572 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 573 bool multi_mon_pp_mclk_switch; 574 bool disable_dmcu; 575 bool allow_4to1MPC; 576 bool enable_windowed_mpo_odm; 577 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 578 uint32_t allow_edp_hotplug_detection; 579 bool skip_riommu_prefetch_wa; 580 bool clamp_min_dcfclk; 581 uint64_t vblank_alignment_dto_params; 582 uint8_t vblank_alignment_max_frame_time_diff; 583 bool is_asymmetric_memory; 584 bool is_single_rank_dimm; 585 bool is_vmin_only_asic; 586 bool use_spl; 587 bool prefer_easf; 588 bool use_pipe_ctx_sync_logic; 589 int smart_mux_version; 590 bool ignore_dpref_ss; 591 bool enable_mipi_converter_optimization; 592 bool enable_frl; 593 bool force_hdmi21_frl_enc_enable; 594 bool use_default_clock_table; 595 bool force_bios_enable_lttpr; 596 uint8_t force_bios_fixed_vs; 597 unsigned int sdpif_request_limit_words_per_umc; 598 bool dc_mode_clk_limit_support; 599 bool EnableMinDispClkODM; 600 bool enable_auto_dpm_test_logs; 601 unsigned int disable_ips; 602 unsigned int disable_ips_rcg; 603 unsigned int disable_ips_in_vpb; 604 bool disable_ips_in_dpms_off; 605 bool usb4_bw_alloc_support; 606 bool allow_0_dtb_clk; 607 bool use_assr_psp_message; 608 bool support_edp0_on_dp1; 609 unsigned int enable_fpo_flicker_detection; 610 bool disable_hbr_audio_dp2; 611 bool consolidated_dpia_dp_lt; 612 bool set_pipe_unlock_order; 613 bool enable_dpia_pre_training; 614 bool unify_link_enc_assignment; 615 bool enable_cursor_offload; 616 bool dp_connector_no_native_i2c; 617 bool frame_update_cmd_version2; 618 struct spl_sharpness_range dcn_sharpness_range; 619 struct spl_sharpness_range dcn_override_sharpness_range; 620 bool no_native422_support; 621 }; 622 623 enum visual_confirm { 624 VISUAL_CONFIRM_DISABLE = 0, 625 VISUAL_CONFIRM_SURFACE = 1, 626 VISUAL_CONFIRM_HDR = 2, 627 VISUAL_CONFIRM_MPCTREE = 4, 628 VISUAL_CONFIRM_PSR = 5, 629 VISUAL_CONFIRM_SWAPCHAIN = 6, 630 VISUAL_CONFIRM_FAMS = 7, 631 VISUAL_CONFIRM_SWIZZLE = 9, 632 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 633 VISUAL_CONFIRM_REPLAY = 12, 634 VISUAL_CONFIRM_SUBVP = 14, 635 VISUAL_CONFIRM_ABM = 15, 636 VISUAL_CONFIRM_MCLK_SWITCH = 16, 637 VISUAL_CONFIRM_FAMS2 = 19, 638 VISUAL_CONFIRM_HW_CURSOR = 20, 639 VISUAL_CONFIRM_VABC = 21, 640 VISUAL_CONFIRM_DCC = 22, 641 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, 642 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 643 }; 644 645 enum dc_psr_power_opts { 646 psr_power_opt_invalid = 0x0, 647 psr_power_opt_smu_opt_static_screen = 0x1, 648 psr_power_opt_z10_static_screen = 0x10, 649 psr_power_opt_ds_disable_allow = 0x100, 650 }; 651 652 enum dml_hostvm_override_opts { 653 DML_HOSTVM_NO_OVERRIDE = 0x0, 654 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 655 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 656 }; 657 658 enum dc_replay_power_opts { 659 replay_power_opt_invalid = 0x0, 660 replay_power_opt_smu_opt_static_screen = 0x1, 661 replay_power_opt_z10_static_screen = 0x10, 662 }; 663 664 enum dcc_option { 665 DCC_ENABLE = 0, 666 DCC_DISABLE = 1, 667 DCC_HALF_REQ_DISALBE = 2, 668 }; 669 670 enum in_game_fams_config { 671 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 672 INGAME_FAMS_DISABLE, // disable in-game fams 673 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 674 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 675 }; 676 677 /** 678 * enum pipe_split_policy - Pipe split strategy supported by DCN 679 * 680 * This enum is used to define the pipe split policy supported by DCN. By 681 * default, DC favors MPC_SPLIT_DYNAMIC. 682 */ 683 enum pipe_split_policy { 684 /** 685 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 686 * pipe in order to bring the best trade-off between performance and 687 * power consumption. This is the recommended option. 688 */ 689 MPC_SPLIT_DYNAMIC = 0, 690 691 /** 692 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 693 * try any sort of split optimization. 694 */ 695 MPC_SPLIT_AVOID = 1, 696 697 /** 698 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 699 * optimize the pipe utilization when using a single display; if the 700 * user connects to a second display, DC will avoid pipe split. 701 */ 702 MPC_SPLIT_AVOID_MULT_DISP = 2, 703 }; 704 705 enum wm_report_mode { 706 WM_REPORT_DEFAULT = 0, 707 WM_REPORT_OVERRIDE = 1, 708 }; 709 enum dtm_pstate{ 710 dtm_level_p0 = 0,/*highest voltage*/ 711 dtm_level_p1, 712 dtm_level_p2, 713 dtm_level_p3, 714 dtm_level_p4,/*when active_display_count = 0*/ 715 }; 716 717 enum dcn_pwr_state { 718 DCN_PWR_STATE_UNKNOWN = -1, 719 DCN_PWR_STATE_MISSION_MODE = 0, 720 DCN_PWR_STATE_LOW_POWER = 3, 721 }; 722 723 enum dcn_zstate_support_state { 724 DCN_ZSTATE_SUPPORT_UNKNOWN, 725 DCN_ZSTATE_SUPPORT_ALLOW, 726 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 727 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 728 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 729 DCN_ZSTATE_SUPPORT_DISALLOW, 730 }; 731 732 /* 733 * struct dc_clocks - DC pipe clocks 734 * 735 * For any clocks that may differ per pipe only the max is stored in this 736 * structure 737 */ 738 struct dc_clocks { 739 int dispclk_khz; 740 int actual_dispclk_khz; 741 int dppclk_khz; 742 int actual_dppclk_khz; 743 int disp_dpp_voltage_level_khz; 744 int dcfclk_khz; 745 int socclk_khz; 746 int dcfclk_deep_sleep_khz; 747 int fclk_khz; 748 int phyclk_khz; 749 int dramclk_khz; 750 bool p_state_change_support; 751 enum dcn_zstate_support_state zstate_support; 752 bool dtbclk_en; 753 int ref_dtbclk_khz; 754 bool fclk_p_state_change_support; 755 enum dcn_pwr_state pwr_state; 756 /* 757 * Elements below are not compared for the purposes of 758 * optimization required 759 */ 760 bool prev_p_state_change_support; 761 bool fclk_prev_p_state_change_support; 762 int num_ways; 763 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 764 765 /* 766 * @fw_based_mclk_switching 767 * 768 * DC has a mechanism that leverage the variable refresh rate to switch 769 * memory clock in cases that we have a large latency to achieve the 770 * memory clock change and a short vblank window. DC has some 771 * requirements to enable this feature, and this field describes if the 772 * system support or not such a feature. 773 */ 774 bool fw_based_mclk_switching; 775 bool fw_based_mclk_switching_shut_down; 776 int prev_num_ways; 777 enum dtm_pstate dtm_level; 778 int max_supported_dppclk_khz; 779 int max_supported_dispclk_khz; 780 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 781 int bw_dispclk_khz; 782 int idle_dramclk_khz; 783 int idle_fclk_khz; 784 int subvp_prefetch_dramclk_khz; 785 int subvp_prefetch_fclk_khz; 786 787 /* Stutter efficiency is technically not clock values 788 * but stored here so the values are part of the update_clocks call similar to num_ways 789 * Efficiencies are stored as percentage (0-100) 790 */ 791 struct { 792 uint8_t base_efficiency; //LP1 793 uint8_t low_power_efficiency; //LP2 794 uint8_t z8_stutter_efficiency; 795 int z8_stutter_period; 796 } stutter_efficiency; 797 }; 798 799 struct dc_bw_validation_profile { 800 bool enable; 801 802 unsigned long long total_ticks; 803 unsigned long long voltage_level_ticks; 804 unsigned long long watermark_ticks; 805 unsigned long long rq_dlg_ticks; 806 807 unsigned long long total_count; 808 unsigned long long skip_fast_count; 809 unsigned long long skip_pass_count; 810 unsigned long long skip_fail_count; 811 }; 812 813 #define BW_VAL_TRACE_SETUP() \ 814 unsigned long long end_tick = 0; \ 815 unsigned long long voltage_level_tick = 0; \ 816 unsigned long long watermark_tick = 0; \ 817 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 818 dm_get_timestamp(dc->ctx) : 0 819 820 #define BW_VAL_TRACE_COUNT() \ 821 if (dc->debug.bw_val_profile.enable) \ 822 dc->debug.bw_val_profile.total_count++ 823 824 #define BW_VAL_TRACE_SKIP(status) \ 825 if (dc->debug.bw_val_profile.enable) { \ 826 if (!voltage_level_tick) \ 827 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 828 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 829 } 830 831 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 832 if (dc->debug.bw_val_profile.enable) \ 833 voltage_level_tick = dm_get_timestamp(dc->ctx) 834 835 #define BW_VAL_TRACE_END_WATERMARKS() \ 836 if (dc->debug.bw_val_profile.enable) \ 837 watermark_tick = dm_get_timestamp(dc->ctx) 838 839 #define BW_VAL_TRACE_FINISH() \ 840 if (dc->debug.bw_val_profile.enable) { \ 841 end_tick = dm_get_timestamp(dc->ctx); \ 842 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 843 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 844 if (watermark_tick) { \ 845 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 846 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 847 } \ 848 } 849 850 union mem_low_power_enable_options { 851 struct { 852 bool vga: 1; 853 bool i2c: 1; 854 bool dmcu: 1; 855 bool dscl: 1; 856 bool cm: 1; 857 bool mpc: 1; 858 bool optc: 1; 859 bool vpg: 1; 860 bool afmt: 1; 861 } bits; 862 uint32_t u32All; 863 }; 864 865 union root_clock_optimization_options { 866 struct { 867 bool dpp: 1; 868 bool dsc: 1; 869 bool hdmistream: 1; 870 bool hdmichar: 1; 871 bool dpstream: 1; 872 bool symclk32_se: 1; 873 bool symclk32_le: 1; 874 bool symclk_fe: 1; 875 bool physymclk: 1; 876 bool dpiasymclk: 1; 877 uint32_t reserved: 22; 878 } bits; 879 uint32_t u32All; 880 }; 881 882 union fine_grain_clock_gating_enable_options { 883 struct { 884 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 885 bool dchub : 1; /* Display controller hub */ 886 bool dchubbub : 1; 887 bool dpp : 1; /* Display pipes and planes */ 888 bool opp : 1; /* Output pixel processing */ 889 bool optc : 1; /* Output pipe timing combiner */ 890 bool dio : 1; /* Display output */ 891 bool dwb : 1; /* Display writeback */ 892 bool mmhubbub : 1; /* Multimedia hub */ 893 bool dmu : 1; /* Display core management unit */ 894 bool az : 1; /* Azalia */ 895 bool dchvm : 1; 896 bool dsc : 1; /* Display stream compression */ 897 898 uint32_t reserved : 19; 899 } bits; 900 uint32_t u32All; 901 }; 902 903 enum pg_hw_pipe_resources { 904 PG_HUBP = 0, 905 PG_DPP, 906 PG_DSC, 907 PG_MPCC, 908 PG_OPP, 909 PG_OPTC, 910 PG_DPSTREAM, 911 PG_HDMISTREAM, 912 PG_PHYSYMCLK, 913 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 914 }; 915 916 enum pg_hw_resources { 917 PG_DCCG = 0, 918 PG_DCIO, 919 PG_DIO, 920 PG_DCHUBBUB, 921 PG_DCHVM, 922 PG_DWB, 923 PG_HPO, 924 PG_DCOH, 925 PG_HW_RESOURCES_NUM_ELEMENT 926 }; 927 928 struct pg_block_update { 929 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 930 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 931 }; 932 933 union dpia_debug_options { 934 struct { 935 uint32_t disable_dpia:1; /* bit 0 */ 936 uint32_t force_non_lttpr:1; /* bit 1 */ 937 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 938 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 939 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 940 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 941 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 942 uint32_t reserved:25; 943 } bits; 944 uint32_t raw; 945 }; 946 947 /* AUX wake work around options 948 * 0: enable/disable work around 949 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 950 * 15-2: reserved 951 * 31-16: timeout in ms 952 */ 953 union aux_wake_wa_options { 954 struct { 955 uint32_t enable_wa : 1; 956 uint32_t use_default_timeout : 1; 957 uint32_t rsvd: 14; 958 uint32_t timeout_ms : 16; 959 } bits; 960 uint32_t raw; 961 }; 962 963 struct dc_debug_data { 964 uint32_t ltFailCount; 965 uint32_t i2cErrorCount; 966 uint32_t auxErrorCount; 967 struct pipe_topology_history topology_history; 968 }; 969 970 struct dc_phy_addr_space_config { 971 struct { 972 uint64_t start_addr; 973 uint64_t end_addr; 974 uint64_t fb_top; 975 uint64_t fb_offset; 976 uint64_t fb_base; 977 uint64_t agp_top; 978 uint64_t agp_bot; 979 uint64_t agp_base; 980 } system_aperture; 981 982 struct { 983 uint64_t page_table_start_addr; 984 uint64_t page_table_end_addr; 985 uint64_t page_table_base_addr; 986 bool base_addr_is_mc_addr; 987 } gart_config; 988 989 bool valid; 990 bool is_hvm_enabled; 991 uint64_t page_table_default_page_addr; 992 }; 993 994 struct dc_virtual_addr_space_config { 995 uint64_t page_table_base_addr; 996 uint64_t page_table_start_addr; 997 uint64_t page_table_end_addr; 998 uint32_t page_table_block_size_in_bytes; 999 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 1000 }; 1001 1002 struct dc_bounding_box_overrides { 1003 unsigned int sr_exit_time_ns; 1004 unsigned int sr_enter_plus_exit_time_ns; 1005 unsigned int sr_exit_z8_time_ns; 1006 unsigned int sr_enter_plus_exit_z8_time_ns; 1007 unsigned int urgent_latency_ns; 1008 unsigned int percent_of_ideal_drambw; 1009 unsigned int dram_clock_change_latency_ns; 1010 unsigned int dummy_clock_change_latency_ns; 1011 unsigned int fclk_clock_change_latency_ns; 1012 /* This forces a hard min on the DCFCLK we use 1013 * for DML. Unlike the debug option for forcing 1014 * DCFCLK, this override affects watermark calculations 1015 */ 1016 unsigned int min_dcfclk_mhz; 1017 }; 1018 1019 struct dc_qos_info { 1020 uint32_t actual_peak_bw_in_mbps; 1021 uint32_t qos_bandwidth_lb_in_mbps; 1022 uint32_t actual_avg_bw_in_mbps; 1023 uint32_t calculated_avg_bw_in_mbps; 1024 uint32_t actual_max_latency_in_ns; 1025 uint32_t actual_min_latency_in_ns; 1026 uint32_t qos_max_latency_ub_in_ns; 1027 uint32_t actual_avg_latency_in_ns; 1028 uint32_t qos_avg_latency_ub_in_ns; 1029 uint32_t dcn_bandwidth_ub_in_mbps; 1030 uint32_t qos_max_bw_budget_in_mbps; 1031 }; 1032 1033 struct dc_state; 1034 struct resource_pool; 1035 struct dce_hwseq; 1036 struct link_service; 1037 1038 /* 1039 * struct dc_debug_options - DC debug struct 1040 * 1041 * This struct provides a simple mechanism for developers to change some 1042 * configurations, enable/disable features, and activate extra debug options. 1043 * This can be very handy to narrow down whether some specific feature is 1044 * causing an issue or not. 1045 */ 1046 struct dc_debug_options { 1047 bool disable_dsc; 1048 enum visual_confirm visual_confirm; 1049 unsigned int visual_confirm_rect_height; 1050 1051 bool sanity_checks; 1052 bool max_disp_clk; 1053 bool surface_trace; 1054 bool clock_trace; 1055 bool validation_trace; 1056 bool bandwidth_calcs_trace; 1057 int max_downscale_src_width; 1058 1059 /* stutter efficiency related */ 1060 bool disable_stutter; 1061 bool use_max_lb; 1062 enum dcc_option disable_dcc; 1063 1064 /* 1065 * @pipe_split_policy: Define which pipe split policy is used by the 1066 * display core. 1067 */ 1068 enum pipe_split_policy pipe_split_policy; 1069 bool force_single_disp_pipe_split; 1070 bool voltage_align_fclk; 1071 bool disable_min_fclk; 1072 1073 bool hdcp_lc_force_fw_enable; 1074 bool hdcp_lc_enable_sw_fallback; 1075 1076 bool disable_dfs_bypass; 1077 bool disable_dpp_power_gate; 1078 bool disable_hubp_power_gate; 1079 bool disable_dsc_power_gate; 1080 bool disable_optc_power_gate; 1081 bool disable_hpo_power_gate; 1082 bool disable_io_clk_power_gate; 1083 bool disable_mem_power_gate; 1084 bool disable_dio_power_gate; 1085 unsigned int dsc_min_slice_height_override; 1086 unsigned int dsc_bpp_increment_div; 1087 bool disable_pplib_wm_range; 1088 enum wm_report_mode pplib_wm_report_mode; 1089 unsigned int min_disp_clk_khz; 1090 unsigned int min_dpp_clk_khz; 1091 unsigned int min_dram_clk_khz; 1092 unsigned int sr_exit_time_dpm0_ns; 1093 unsigned int sr_enter_plus_exit_time_dpm0_ns; 1094 unsigned int sr_exit_time_ns; 1095 unsigned int sr_enter_plus_exit_time_ns; 1096 unsigned int sr_exit_z8_time_ns; 1097 unsigned int sr_enter_plus_exit_z8_time_ns; 1098 unsigned int urgent_latency_ns; 1099 uint32_t underflow_assert_delay_us; 1100 unsigned int percent_of_ideal_drambw; 1101 unsigned int dram_clock_change_latency_ns; 1102 bool optimized_watermark; 1103 int always_scale; 1104 bool disable_pplib_clock_request; 1105 bool disable_clock_gate; 1106 bool disable_mem_low_power; 1107 bool pstate_enabled; 1108 bool disable_dmcu; 1109 bool force_abm_enable; 1110 bool disable_stereo_support; 1111 bool vsr_support; 1112 bool performance_trace; 1113 bool az_endpoint_mute_only; 1114 bool always_use_regamma; 1115 bool recovery_enabled; 1116 bool avoid_vbios_exec_table; 1117 bool scl_reset_length10; 1118 bool hdmi20_disable; 1119 bool skip_detection_link_training; 1120 uint32_t edid_read_retry_times; 1121 1122 uint8_t force_odm_combine; //bit vector based on otg inst 1123 uint8_t seamless_boot_odm_combine; 1124 uint8_t force_odm_combine_4to1; //bit vector based on otg inst 1125 1126 unsigned int minimum_z8_residency_time; 1127 unsigned int minimum_z10_residency_time; 1128 bool disable_z9_mpc; 1129 unsigned int force_fclk_khz; 1130 bool enable_tri_buf; 1131 bool ips_disallow_entry; 1132 bool disable_idle_power_optimizations; 1133 unsigned int mall_size_override; 1134 unsigned int mall_additional_timer_percent; 1135 bool mall_error_as_fatal; 1136 bool dmub_command_table; /* for testing only */ 1137 struct dc_bw_validation_profile bw_val_profile; 1138 bool disable_fec; 1139 bool disable_48mhz_pwrdwn; 1140 /* This forces a hard min on the DCFCLK requested to SMU/PP 1141 * watermarks are not affected. 1142 */ 1143 unsigned int force_min_dcfclk_mhz; 1144 int dwb_fi_phase; 1145 bool disable_timing_sync; 1146 bool cm_in_bypass; 1147 int force_clock_mode;/*every mode change.*/ 1148 1149 bool disable_dram_clock_change_vactive_support; 1150 bool validate_dml_output; 1151 bool enable_dmcub_surface_flip; 1152 bool usbc_combo_phy_reset_wa; 1153 bool force_fva; 1154 int max_frl_rate; 1155 unsigned int force_frl_rate; 1156 bool ignore_ffe; 1157 unsigned int select_ffe; 1158 unsigned int limit_ffe; 1159 bool force_frl_always; 1160 bool force_frl_dsc; 1161 bool force_frl_max; 1162 bool apply_vsdb_rcc_wa; 1163 bool enable_hdmi_idcc; 1164 1165 bool enable_dram_clock_change_one_display_vactive; 1166 /* TODO - remove once tested */ 1167 bool legacy_dp2_lt; 1168 bool set_mst_en_for_sst; 1169 bool disable_uhbr; 1170 bool force_dp2_lt_fallback_method; 1171 bool ignore_cable_id; 1172 union mem_low_power_enable_options enable_mem_low_power; 1173 union root_clock_optimization_options root_clock_optimization; 1174 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1175 bool hpo_optimization; 1176 bool force_vblank_alignment; 1177 1178 /* Enable dmub aux for legacy ddc */ 1179 bool enable_dmub_aux_for_legacy_ddc; 1180 bool disable_fams; 1181 enum in_game_fams_config disable_fams_gaming; 1182 /* FEC/PSR1 sequence enable delay in 100us */ 1183 uint8_t fec_enable_delay_in100us; 1184 bool enable_driver_sequence_debug; 1185 enum det_size crb_alloc_policy; 1186 unsigned int crb_alloc_policy_min_disp_count; 1187 bool disable_z10; 1188 bool enable_z9_disable_interface; 1189 bool psr_skip_crtc_disable; 1190 uint32_t ips_skip_crtc_disable_mask; 1191 union dpia_debug_options dpia_debug; 1192 bool disable_fixed_vs_aux_timeout_wa; 1193 uint32_t fixed_vs_aux_delay_config_wa; 1194 bool force_disable_subvp; 1195 bool force_subvp_mclk_switch; 1196 bool allow_sw_cursor_fallback; 1197 unsigned int force_subvp_num_ways; 1198 unsigned int force_mall_ss_num_ways; 1199 bool alloc_extra_way_for_cursor; 1200 uint32_t subvp_extra_lines; 1201 bool disable_force_pstate_allow_on_hw_release; 1202 bool force_usr_allow; 1203 /* uses value at boot and disables switch */ 1204 bool disable_dtb_ref_clk_switch; 1205 bool extended_blank_optimization; 1206 union aux_wake_wa_options aux_wake_wa; 1207 uint32_t mst_start_top_delay; 1208 uint8_t psr_power_use_phy_fsm; 1209 enum dml_hostvm_override_opts dml_hostvm_override; 1210 bool dml_disallow_alternate_prefetch_modes; 1211 bool use_legacy_soc_bb_mechanism; 1212 bool exit_idle_opt_for_cursor_updates; 1213 bool using_dml2; 1214 bool enable_single_display_2to1_odm_policy; 1215 bool enable_double_buffered_dsc_pg_support; 1216 bool enable_dp_dig_pixel_rate_div_policy; 1217 bool using_dml21; 1218 enum lttpr_mode lttpr_mode_override; 1219 unsigned int dsc_delay_factor_wa_x1000; 1220 unsigned int min_prefetch_in_strobe_ns; 1221 bool disable_unbounded_requesting; 1222 bool dig_fifo_off_in_blank; 1223 bool override_dispclk_programming; 1224 bool otg_crc_db; 1225 bool disallow_dispclk_dppclk_ds; 1226 bool disable_fpo_optimizations; 1227 bool support_eDP1_5; 1228 uint32_t fpo_vactive_margin_us; 1229 bool disable_fpo_vactive; 1230 bool disable_boot_optimizations; 1231 bool override_odm_optimization; 1232 bool minimize_dispclk_using_odm; 1233 bool disable_subvp_high_refresh; 1234 bool disable_dp_plus_plus_wa; 1235 uint32_t fpo_vactive_min_active_margin_us; 1236 uint32_t fpo_vactive_max_blank_us; 1237 bool enable_hpo_pg_support; 1238 bool disable_dc_mode_overwrite; 1239 bool replay_skip_crtc_disabled; 1240 bool ignore_pg;/*do nothing, let pmfw control it*/ 1241 bool psp_disabled_wa; 1242 unsigned int ips2_eval_delay_us; 1243 unsigned int ips2_entry_delay_us; 1244 bool optimize_ips_handshake; 1245 bool disable_dmub_reallow_idle; 1246 bool disable_timeout; 1247 bool disable_extblankadj; 1248 bool enable_idle_reg_checks; 1249 unsigned int static_screen_wait_frames; 1250 uint32_t pwm_freq; 1251 bool force_chroma_subsampling_1tap; 1252 unsigned int dcc_meta_propagation_delay_us; 1253 bool disable_422_left_edge_pixel; 1254 bool dml21_force_pstate_method; 1255 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1256 uint32_t dml21_disable_pstate_method_mask; 1257 union fw_assisted_mclk_switch_version fams_version; 1258 union dmub_fams2_global_feature_config fams2_config; 1259 unsigned int force_cositing; 1260 unsigned int disable_spl; 1261 unsigned int force_easf; 1262 unsigned int force_sharpness; 1263 unsigned int force_sharpness_level; 1264 unsigned int force_lls; 1265 bool notify_dpia_hr_bw; 1266 bool enable_ips_visual_confirm; 1267 unsigned int sharpen_policy; 1268 unsigned int scale_to_sharpness_policy; 1269 unsigned int enable_oled_edp_power_up_opt; 1270 bool enable_hblank_borrow; 1271 bool force_subvp_df_throttle; 1272 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1273 bool enable_pg_cntl_debug_logs; 1274 unsigned int auxless_alpm_lfps_setup_ns; 1275 unsigned int auxless_alpm_lfps_period_ns; 1276 unsigned int auxless_alpm_lfps_silence_ns; 1277 unsigned int auxless_alpm_lfps_t1t2_us; 1278 short auxless_alpm_lfps_t1t2_offset_us; 1279 bool disable_stutter_for_wm_program; 1280 bool enable_block_sequence_programming; 1281 uint32_t custom_psp_footer_size; 1282 bool disable_deferred_minimal_transitions; 1283 unsigned int num_fast_flips_to_steady_state_override; 1284 bool enable_dmu_recovery; 1285 unsigned int force_vmin_threshold; 1286 bool enable_otg_frame_sync_pwa; 1287 unsigned int min_deep_sleep_dcfclk_khz; 1288 unsigned int force_odm2to1_for_edp_pixclk_mhz; 1289 bool enable_replay_esd_recovery; 1290 uint8_t iommu_mismatch_temp_wka; 1291 bool disable_dynamic_expansion_for_test_pattern; 1292 uint32_t dml21_custom_derate_num_dpms; 1293 uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL]; 1294 }; 1295 1296 1297 /* Generic structure that can be used to query properties of DC. More fields 1298 * can be added as required. 1299 */ 1300 struct dc_current_properties { 1301 unsigned int cursor_size_limit; 1302 }; 1303 1304 enum frame_buffer_mode { 1305 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1306 FRAME_BUFFER_MODE_ZFB_ONLY, 1307 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1308 } ; 1309 1310 struct dchub_init_data { 1311 int64_t zfb_phys_addr_base; 1312 int64_t zfb_mc_base_addr; 1313 uint64_t zfb_size_in_byte; 1314 enum frame_buffer_mode fb_mode; 1315 bool dchub_initialzied; 1316 bool dchub_info_valid; 1317 }; 1318 1319 struct dml2_soc_bb; 1320 1321 struct dc_init_data { 1322 struct hw_asic_id asic_id; 1323 void *driver; /* ctx */ 1324 struct cgs_device *cgs_device; 1325 struct dc_bounding_box_overrides bb_overrides; 1326 1327 int num_virtual_links; 1328 /* 1329 * If 'vbios_override' not NULL, it will be called instead 1330 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1331 */ 1332 struct dc_bios *vbios_override; 1333 enum dce_environment dce_environment; 1334 1335 struct dmub_offload_funcs *dmub_if; 1336 1337 struct dc_config flags; 1338 uint64_t log_mask; 1339 1340 struct dpcd_vendor_signature vendor_signature; 1341 bool force_smu_not_present; 1342 /* 1343 * IP offset for run time initializaion of register addresses 1344 * 1345 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1346 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1347 * before them. 1348 */ 1349 uint32_t *dcn_reg_offsets; 1350 uint32_t *nbio_reg_offsets; 1351 uint32_t *clk_reg_offsets; 1352 void *bb_from_dmub; 1353 }; 1354 1355 struct dc_callback_init { 1356 struct cp_psp cp_psp; 1357 }; 1358 1359 struct dc *dc_create(const struct dc_init_data *init_params); 1360 void dc_hardware_init(struct dc *dc); 1361 1362 int dc_get_vmid_use_vector(struct dc *dc); 1363 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1364 /* Returns the number of vmids supported */ 1365 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1366 void dc_init_callbacks(struct dc *dc, 1367 const struct dc_callback_init *init_params); 1368 void dc_deinit_callbacks(struct dc *dc); 1369 void dc_destroy(struct dc **dc); 1370 1371 /* Surface Interfaces */ 1372 1373 enum { 1374 TRANSFER_FUNC_POINTS = 1025 1375 }; 1376 1377 struct dc_hdr_static_metadata { 1378 /* display chromaticities and white point in units of 0.00001 */ 1379 unsigned int chromaticity_green_x; 1380 unsigned int chromaticity_green_y; 1381 unsigned int chromaticity_blue_x; 1382 unsigned int chromaticity_blue_y; 1383 unsigned int chromaticity_red_x; 1384 unsigned int chromaticity_red_y; 1385 unsigned int chromaticity_white_point_x; 1386 unsigned int chromaticity_white_point_y; 1387 1388 uint32_t min_luminance; 1389 uint32_t max_luminance; 1390 uint32_t maximum_content_light_level; 1391 uint32_t maximum_frame_average_light_level; 1392 }; 1393 1394 enum dc_transfer_func_type { 1395 TF_TYPE_PREDEFINED, 1396 TF_TYPE_DISTRIBUTED_POINTS, 1397 TF_TYPE_BYPASS, 1398 TF_TYPE_HWPWL 1399 }; 1400 1401 struct dc_transfer_func_distributed_points { 1402 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1403 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1404 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1405 1406 uint16_t end_exponent; 1407 uint16_t x_point_at_y1_red; 1408 uint16_t x_point_at_y1_green; 1409 uint16_t x_point_at_y1_blue; 1410 }; 1411 1412 enum dc_transfer_func_predefined { 1413 TRANSFER_FUNCTION_SRGB, 1414 TRANSFER_FUNCTION_BT709, 1415 TRANSFER_FUNCTION_PQ, 1416 TRANSFER_FUNCTION_LINEAR, 1417 TRANSFER_FUNCTION_UNITY, 1418 TRANSFER_FUNCTION_HLG, 1419 TRANSFER_FUNCTION_HLG12, 1420 TRANSFER_FUNCTION_GAMMA22, 1421 TRANSFER_FUNCTION_GAMMA24, 1422 TRANSFER_FUNCTION_GAMMA26 1423 }; 1424 1425 1426 struct dc_transfer_func { 1427 struct kref refcount; 1428 enum dc_transfer_func_type type; 1429 enum dc_transfer_func_predefined tf; 1430 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1431 uint32_t sdr_ref_white_level; 1432 union { 1433 struct pwl_params pwl; 1434 struct dc_transfer_func_distributed_points tf_pts; 1435 }; 1436 }; 1437 1438 1439 union dc_3dlut_state { 1440 struct { 1441 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1442 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1443 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1444 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1445 uint32_t mpc_rmu1_mux:4; 1446 uint32_t mpc_rmu2_mux:4; 1447 uint32_t reserved:15; 1448 } bits; 1449 uint32_t raw; 1450 }; 1451 1452 1453 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1454 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1455 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1456 1457 struct lut_rgb { 1458 uint16_t b; 1459 uint16_t g; 1460 uint16_t r; 1461 uint16_t padding; 1462 }; 1463 1464 //this structure maps directly to how the lut will read it from memory 1465 struct lut_mem_mapping { 1466 union { 1467 //NATIVE MODE 1, 2 1468 //RGB layout [b][g][r] //red is 128 byte aligned 1469 //BGR layout [r][g][b] //blue is 128 byte aligned 1470 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1471 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1472 1473 //TRANSFORMED 1474 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1475 }; 1476 uint16_t size; 1477 }; 1478 1479 struct dc_rmcm_3dlut { 1480 bool isInUse; 1481 const struct dc_stream_state *stream; 1482 uint8_t protection_bits; 1483 }; 1484 1485 struct dc_3dlut { 1486 struct kref refcount; 1487 struct tetrahedral_params lut_3d; 1488 struct fixed31_32 hdr_multiplier; 1489 union dc_3dlut_state state; 1490 }; 1491 1492 /* 3DLUT DMA (Fast Load) params */ 1493 struct dc_3dlut_dma { 1494 struct dc_plane_address addr; 1495 enum dc_cm_lut_swizzle swizzle; 1496 enum dc_cm_lut_pixel_format format; 1497 uint16_t bias; /* FP1.5.10 */ 1498 uint16_t scale; /* FP1.5.10 */ 1499 enum dc_cm_lut_size size; 1500 }; 1501 1502 /* color manager */ 1503 union dc_plane_cm_flags { 1504 unsigned int all; 1505 struct { 1506 unsigned int shaper_enable : 1; 1507 unsigned int lut3d_enable : 1; 1508 unsigned int blend_enable : 1; 1509 /* whether legacy (lut3d_func) or DMA is valid */ 1510 unsigned int lut3d_dma_enable : 1; 1511 #if defined(CONFIG_DRM_AMD_DC_DCN4_2) 1512 /* RMCM lut to be used instead of MCM */ 1513 unsigned int rmcm_enable : 1; 1514 unsigned int reserved: 27; 1515 #else 1516 unsigned int reserved: 28; 1517 #endif 1518 } bits; 1519 }; 1520 1521 struct dc_plane_cm { 1522 struct kref refcount; 1523 struct dc_transfer_func shaper_func; 1524 union { 1525 struct dc_3dlut lut3d_func; 1526 struct dc_3dlut_dma lut3d_dma; 1527 }; 1528 struct dc_transfer_func blend_func; 1529 union dc_plane_cm_flags flags; 1530 }; 1531 1532 /* 1533 * This structure is filled in by dc_surface_get_status and contains 1534 * the last requested address and the currently active address so the called 1535 * can determine if there are any outstanding flips 1536 */ 1537 struct dc_plane_status { 1538 struct dc_plane_address requested_address; 1539 struct dc_plane_address current_address; 1540 bool is_flip_pending; 1541 bool is_right_eye; 1542 struct cm_hist cm_hist; 1543 }; 1544 1545 struct pipe_update_bits { 1546 uint32_t addr_update:1; 1547 uint32_t dcc_change:1; 1548 uint32_t color_space_change:1; 1549 uint32_t horizontal_mirror_change:1; 1550 uint32_t per_pixel_alpha_change:1; 1551 uint32_t global_alpha_change:1; 1552 uint32_t hdr_mult:1; 1553 uint32_t rotation_change:1; 1554 uint32_t swizzle_change:1; 1555 uint32_t scaling_change:1; 1556 uint32_t position_change:1; 1557 uint32_t in_transfer_func_change:1; 1558 uint32_t input_csc_change:1; 1559 uint32_t coeff_reduction_change:1; 1560 uint32_t pixel_format_change:1; 1561 uint32_t plane_size_change:1; 1562 uint32_t gamut_remap_change:1; 1563 uint32_t cursor_csc_color_matrix_change:1; 1564 uint32_t new_plane:1; 1565 uint32_t bpp_change:1; 1566 uint32_t gamma_change:1; 1567 uint32_t bandwidth_change:1; 1568 uint32_t clock_change:1; 1569 uint32_t stereo_format_change:1; 1570 uint32_t lut_3d:1; 1571 uint32_t tmz_changed:1; 1572 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1573 uint32_t full_update:1; 1574 uint32_t sdr_white_level_nits:1; 1575 uint32_t cm_hist_change:1; 1576 /* NOTE: When adding a new field, also update: 1577 * - dc_pipe_update_bits_set_full() 1578 * - dc_pipe_update_bits_is_any_set() 1579 */ 1580 }; 1581 1582 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags) 1583 { 1584 /* memset ensures padding bits are zeroed */ 1585 memset(flags, 0, sizeof(*flags)); 1586 } 1587 1588 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags) 1589 { 1590 dc_pipe_update_bits_clear(flags); 1591 flags->addr_update = 1; 1592 flags->dcc_change = 1; 1593 flags->color_space_change = 1; 1594 flags->horizontal_mirror_change = 1; 1595 flags->per_pixel_alpha_change = 1; 1596 flags->global_alpha_change = 1; 1597 flags->hdr_mult = 1; 1598 flags->rotation_change = 1; 1599 flags->swizzle_change = 1; 1600 flags->scaling_change = 1; 1601 flags->position_change = 1; 1602 flags->in_transfer_func_change = 1; 1603 flags->input_csc_change = 1; 1604 flags->coeff_reduction_change = 1; 1605 flags->pixel_format_change = 1; 1606 flags->plane_size_change = 1; 1607 flags->gamut_remap_change = 1; 1608 flags->cursor_csc_color_matrix_change = 1; 1609 flags->new_plane = 1; 1610 flags->bpp_change = 1; 1611 flags->gamma_change = 1; 1612 flags->bandwidth_change = 1; 1613 flags->clock_change = 1; 1614 flags->stereo_format_change = 1; 1615 flags->lut_3d = 1; 1616 flags->tmz_changed = 1; 1617 flags->mcm_transfer_function_enable_change = 1; 1618 flags->full_update = 1; 1619 flags->sdr_white_level_nits = 1; 1620 flags->cm_hist_change = 1; 1621 } 1622 1623 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags) 1624 { 1625 return flags->addr_update || 1626 flags->dcc_change || 1627 flags->color_space_change || 1628 flags->horizontal_mirror_change || 1629 flags->per_pixel_alpha_change || 1630 flags->global_alpha_change || 1631 flags->hdr_mult || 1632 flags->rotation_change || 1633 flags->swizzle_change || 1634 flags->scaling_change || 1635 flags->position_change || 1636 flags->in_transfer_func_change || 1637 flags->input_csc_change || 1638 flags->coeff_reduction_change || 1639 flags->pixel_format_change || 1640 flags->plane_size_change || 1641 flags->gamut_remap_change || 1642 flags->cursor_csc_color_matrix_change || 1643 flags->new_plane || 1644 flags->bpp_change || 1645 flags->gamma_change || 1646 flags->bandwidth_change || 1647 flags->clock_change || 1648 flags->stereo_format_change || 1649 flags->lut_3d || 1650 flags->tmz_changed || 1651 flags->mcm_transfer_function_enable_change || 1652 flags->full_update || 1653 flags->sdr_white_level_nits || 1654 flags->cm_hist_change; 1655 } 1656 1657 bool dc_check_address_only_update(struct pipe_update_bits update_bits); 1658 1659 #define DC_REMOVE_PLANE_POINTERS 1 1660 1661 struct dc_plane_state { 1662 struct dc_plane_address address; 1663 struct dc_plane_flip_time time; 1664 bool triplebuffer_flips; 1665 struct scaling_taps scaling_quality; 1666 struct rect src_rect; 1667 struct rect dst_rect; 1668 struct rect clip_rect; 1669 1670 struct plane_size plane_size; 1671 struct dc_tiling_info tiling_info; 1672 1673 struct dc_plane_dcc_param dcc; 1674 1675 struct dc_gamma gamma_correction; 1676 struct dc_transfer_func in_transfer_func; 1677 struct dc_bias_and_scale bias_and_scale; 1678 struct dc_csc_transform input_csc_color_matrix; 1679 struct fixed31_32 coeff_reduction_factor; 1680 struct fixed31_32 hdr_mult; 1681 struct colorspace_transform gamut_remap_matrix; 1682 1683 enum dc_color_space color_space; 1684 1685 #ifndef TRIM_CM2 1686 // TODO: No longer used, remove 1687 struct dc_hdr_static_metadata hdr_static_ctx; 1688 1689 struct dc_3dlut lut3d_func; 1690 struct dc_transfer_func in_shaper_func; 1691 struct dc_transfer_func blend_tf; 1692 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1693 bool mcm_lut1d_enable; 1694 struct dc_cm2_func_luts mcm_luts; 1695 #endif /* TRIM_CM2 */ 1696 bool lut_bank_a; 1697 enum mpcc_movable_cm_location mcm_location; 1698 struct dc_plane_cm cm; 1699 1700 struct dc_transfer_func *gamcor_tf; 1701 enum surface_pixel_format format; 1702 enum dc_rotation_angle rotation; 1703 enum plane_stereo_format stereo_format; 1704 1705 bool is_tiling_rotated; 1706 bool per_pixel_alpha; 1707 bool pre_multiplied_alpha; 1708 bool global_alpha; 1709 int global_alpha_value; 1710 bool visible; 1711 bool flip_immediate; 1712 bool horizontal_mirror; 1713 unsigned int layer_index; 1714 1715 struct pipe_update_bits update_bits; 1716 bool flip_int_enabled; 1717 bool skip_manual_trigger; 1718 1719 /* private to DC core */ 1720 struct dc_plane_status status; 1721 struct dc_context *ctx; 1722 1723 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1724 bool force_full_update; 1725 1726 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1727 1728 /* private to dc_surface.c */ 1729 enum dc_irq_source irq_source; 1730 struct kref refcount; 1731 struct tg_color visual_confirm_color; 1732 1733 bool is_statically_allocated; 1734 enum chroma_cositing cositing; 1735 struct dc_csc_transform cursor_csc_color_matrix; 1736 bool adaptive_sharpness_en; 1737 int adaptive_sharpness_policy; 1738 unsigned int sharpness_level; 1739 enum linear_light_scaling linear_light_scaling; 1740 unsigned int sdr_white_level_nits; 1741 struct cm_hist_control cm_hist_control; 1742 struct spl_sharpness_range sharpness_range; 1743 enum sharpness_range_source sharpness_source; 1744 }; 1745 1746 struct dc_plane_info { 1747 struct plane_size plane_size; 1748 struct dc_tiling_info tiling_info; 1749 struct dc_plane_dcc_param dcc; 1750 enum surface_pixel_format format; 1751 enum dc_rotation_angle rotation; 1752 enum plane_stereo_format stereo_format; 1753 enum dc_color_space color_space; 1754 bool horizontal_mirror; 1755 bool visible; 1756 bool per_pixel_alpha; 1757 bool pre_multiplied_alpha; 1758 bool global_alpha; 1759 int global_alpha_value; 1760 bool input_csc_enabled; 1761 unsigned int layer_index; 1762 enum chroma_cositing cositing; 1763 }; 1764 1765 #include "dc_stream.h" 1766 1767 struct dc_scratch_space { 1768 /* used to temporarily backup plane states of a stream during 1769 * dc update. The reason is that plane states are overwritten 1770 * with surface updates in dc update. Once they are overwritten 1771 * current state is no longer valid. We want to temporarily 1772 * store current value in plane states so we can still recover 1773 * a valid current state during dc update. 1774 */ 1775 struct dc_plane_state plane_states[MAX_SURFACES]; 1776 1777 struct dc_stream_state stream_state; 1778 }; 1779 1780 /* 1781 * A link contains one or more sinks and their connected status. 1782 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1783 */ 1784 struct dc_link { 1785 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1786 unsigned int sink_count; 1787 struct dc_sink *local_sink; 1788 unsigned int link_index; 1789 enum dc_connection_type type; 1790 enum signal_type connector_signal; 1791 enum dc_irq_source irq_source_hpd; 1792 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1793 enum dc_irq_source irq_source_read_request;/* Read Request */ 1794 1795 bool is_hpd_filter_disabled; 1796 bool dp_ss_off; 1797 1798 /** 1799 * @link_state_valid: 1800 * 1801 * If there is no link and local sink, this variable should be set to 1802 * false. Otherwise, it should be set to true; usually, the function 1803 * core_link_enable_stream sets this field to true. 1804 */ 1805 bool link_state_valid; 1806 bool aux_access_disabled; 1807 bool sync_lt_in_progress; 1808 bool skip_stream_reenable; 1809 bool is_internal_display; 1810 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1811 bool is_dig_mapping_flexible; 1812 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1813 bool is_hpd_pending; /* Indicates a new received hpd */ 1814 1815 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1816 * for every link training. This is incompatible with DP LL compliance automation, 1817 * which expects the same link settings to be used every retry on a link loss. 1818 * This flag is used to skip the fallback when link loss occurs during automation. 1819 */ 1820 bool skip_fallback_on_link_loss; 1821 1822 bool edp_sink_present; 1823 1824 struct dp_trace dp_trace; 1825 volatile bool is_link_locked; 1826 1827 /* caps is the same as reported_link_cap. link_traing use 1828 * reported_link_cap. Will clean up. TODO 1829 */ 1830 struct dc_link_settings reported_link_cap; 1831 struct dc_link_settings verified_link_cap; 1832 struct dc_link_settings cur_link_settings; 1833 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1834 struct dc_link_settings preferred_link_setting; 1835 /* preferred_training_settings are override values that 1836 * come from DM. DM is responsible for the memory 1837 * management of the override pointers. 1838 */ 1839 struct dc_link_training_overrides preferred_training_settings; 1840 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings; 1841 struct dp_audio_test_data audio_test_data; 1842 1843 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap 1844 * set by IFWI, link aux_hw_inst is used in aux layer functions instead 1845 * of ddc_pin to know which aux instance is associated with link. 1846 */ 1847 bool no_ddc_pin; 1848 /** When set, forces all native I2C communication on this DP connector 1849 * to use the I2C-over-AUX protocol instead of native I2C signaling. 1850 */ 1851 bool force_to_use_aux; 1852 enum gpio_ddc_line aux_hw_inst; 1853 1854 enum gpio_ddc_line ddc_hw_inst; 1855 1856 uint8_t hpd_src; 1857 1858 uint8_t link_enc_hw_inst; 1859 /* DIG link encoder ID. Used as index in link encoder resource pool. 1860 * For links with fixed mapping to DIG, this is not changed after dc_link 1861 * object creation. 1862 */ 1863 enum engine_id eng_id; 1864 enum engine_id dpia_preferred_eng_id; 1865 1866 bool test_pattern_enabled; 1867 /* Pending/Current test pattern are only used to perform and track 1868 * FIXED_VS retimer test pattern/lane adjustment override state. 1869 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1870 * to perform specific lane adjust overrides before setting certain 1871 * PHY test patterns. In cases when lane adjust and set test pattern 1872 * calls are not performed atomically (i.e. performing link training), 1873 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1874 * and current_test_pattern will contain required context for any future 1875 * set pattern/set lane adjust to transition between override state(s). 1876 * */ 1877 enum dp_test_pattern current_test_pattern; 1878 enum dp_test_pattern pending_test_pattern; 1879 1880 union compliance_test_state compliance_test_state; 1881 1882 void *priv; 1883 1884 struct ddc_service *ddc; 1885 1886 enum dp_panel_mode panel_mode; 1887 bool aux_mode; 1888 1889 /* Private to DC core */ 1890 1891 const struct dc *dc; 1892 1893 struct dc_context *ctx; 1894 1895 struct panel_cntl *panel_cntl; 1896 struct link_encoder *link_enc; 1897 struct hpo_frl_link_encoder *hpo_frl_link_enc; 1898 struct dc_hdmi_frl_link_settings frl_reported_link_cap; 1899 struct dc_hdmi_frl_link_settings frl_verified_link_cap; 1900 struct dc_hdmi_frl_link_settings frl_link_settings; 1901 struct dc_hdmi_frl_flags frl_flags; 1902 union hdmi_idcc_cable_id hdmi_cable_id; 1903 struct graphics_object_id link_id; 1904 1905 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1906 struct graphics_object_id ext_enc_id; 1907 1908 /* Endpoint type distinguishes display endpoints which do not have entries 1909 * in the BIOS connector table from those that do. Helps when tracking link 1910 * encoder to display endpoint assignments. 1911 */ 1912 enum display_endpoint_type ep_type; 1913 union ddi_channel_mapping ddi_channel_mapping; 1914 struct connector_device_tag_info device_tag; 1915 struct dpcd_caps dpcd_caps; 1916 uint32_t dongle_max_pix_clk; 1917 unsigned short chip_caps; 1918 unsigned int dpcd_sink_count; 1919 struct hdcp_caps hdcp_caps; 1920 enum edp_revision edp_revision; 1921 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1922 1923 struct psr_settings psr_settings; 1924 struct replay_settings replay_settings; 1925 1926 /* Drive settings read from integrated info table */ 1927 struct dc_lane_settings bios_forced_drive_settings; 1928 1929 /* Vendor specific LTTPR workaround variables */ 1930 uint8_t vendor_specific_lttpr_link_rate_wa; 1931 bool apply_vendor_specific_lttpr_link_rate_wa; 1932 1933 /* MST record stream using this link */ 1934 struct link_flags { 1935 bool dp_keep_receiver_powered; 1936 bool dp_skip_DID2; 1937 bool dp_skip_reset_segment; 1938 bool dp_skip_fs_144hz; 1939 bool dp_mot_reset_segment; 1940 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1941 bool dpia_mst_dsc_always_on; 1942 /* Forced DPIA into TBT3 compatibility mode. */ 1943 bool dpia_forced_tbt3_mode; 1944 bool dongle_mode_timing_override; 1945 bool blank_stream_on_ocs_change; 1946 bool read_dpcd204h_on_irq_hpd; 1947 bool force_dp_ffe_preset; 1948 bool skip_phy_ssc_reduction; 1949 } wa_flags; 1950 union dc_dp_ffe_preset forced_dp_ffe_preset; 1951 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1952 1953 struct dc_link_status link_status; 1954 struct dprx_states dprx_states; 1955 1956 enum dc_link_fec_state fec_state; 1957 bool is_dds; 1958 bool is_display_mux_present; 1959 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1960 1961 struct dc_panel_config panel_config; 1962 enum dc_panel_type panel_type; 1963 struct phy_state phy_state; 1964 uint32_t phy_transition_bitmask; 1965 // BW ALLOCATON USB4 ONLY 1966 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1967 bool skip_implict_edp_power_control; 1968 enum backlight_control_type backlight_control_type; 1969 }; 1970 1971 struct dc { 1972 struct dc_debug_options debug; 1973 struct dc_versions versions; 1974 struct dc_caps caps; 1975 struct dc_check_config check_config; 1976 struct dc_cap_funcs cap_funcs; 1977 struct dc_config config; 1978 struct dc_bounding_box_overrides bb_overrides; 1979 struct dc_bug_wa work_arounds; 1980 struct dc_context *ctx; 1981 struct dc_phy_addr_space_config vm_pa_config; 1982 1983 uint8_t link_count; 1984 struct dc_link *links[MAX_LINKS]; 1985 uint8_t lowest_dpia_link_index; 1986 struct link_service *link_srv; 1987 1988 struct dc_state *current_state; 1989 struct resource_pool *res_pool; 1990 1991 struct clk_mgr *clk_mgr; 1992 1993 /* Display Engine Clock levels */ 1994 struct dm_pp_clock_levels sclk_lvls; 1995 1996 /* Inputs into BW and WM calculations. */ 1997 struct bw_calcs_dceip *bw_dceip; 1998 struct bw_calcs_vbios *bw_vbios; 1999 struct dcn_soc_bounding_box *dcn_soc; 2000 struct dcn_ip_params *dcn_ip; 2001 struct display_mode_lib dml; 2002 2003 /* HW functions */ 2004 struct hw_sequencer_funcs hwss; 2005 struct dce_hwseq *hwseq; 2006 2007 /* Require to optimize clocks and bandwidth for added/removed planes */ 2008 bool optimized_required; 2009 bool idle_optimizations_allowed; 2010 bool enable_c20_dtm_b0; 2011 2012 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 2013 2014 /* For eDP to know the switching state of SmartMux */ 2015 bool is_switch_in_progress_orig; 2016 bool is_switch_in_progress_dest; 2017 2018 /* FBC compressor */ 2019 struct compressor *fbc_compressor; 2020 2021 struct dc_debug_data debug_data; 2022 struct dpcd_vendor_signature vendor_signature; 2023 2024 const char *build_id; 2025 struct vm_helper *vm_helper; 2026 2027 uint32_t *dcn_reg_offsets; 2028 uint32_t *nbio_reg_offsets; 2029 uint32_t *clk_reg_offsets; 2030 2031 /* Scratch memory */ 2032 struct { 2033 struct { 2034 /* 2035 * For matching clock_limits table in driver with table 2036 * from PMFW. 2037 */ 2038 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2039 } update_bw_bounding_box; 2040 struct dc_scratch_space current_state; 2041 struct dc_scratch_space new_state; 2042 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 2043 struct dc_link temp_link; 2044 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 2045 } scratch; 2046 2047 struct dml2_configuration_options dml2_options; 2048 struct dml2_configuration_options dml2_dc_power_options; 2049 enum dc_acpi_cm_power_state power_state; 2050 struct soc_and_ip_translator *soc_and_ip_translator; 2051 }; 2052 2053 struct dc_scaling_info { 2054 struct rect src_rect; 2055 struct rect dst_rect; 2056 struct rect clip_rect; 2057 struct scaling_taps scaling_quality; 2058 }; 2059 2060 struct dc_fast_update { 2061 const struct dc_flip_addrs *flip_addr; 2062 const struct dc_gamma *gamma; 2063 const struct colorspace_transform *gamut_remap_matrix; 2064 const struct dc_csc_transform *input_csc_color_matrix; 2065 const struct fixed31_32 *coeff_reduction_factor; 2066 struct dc_transfer_func *out_transfer_func; 2067 struct dc_csc_transform *output_csc_transform; 2068 const struct dc_csc_transform *cursor_csc_color_matrix; 2069 struct cm_hist_control *cm_hist_control; 2070 /* stream-level fast updates */ 2071 const struct colorspace_transform *gamut_remap; 2072 const struct dc_cursor_attributes *cursor_attributes; 2073 const struct dc_cursor_position *cursor_position; 2074 const struct periodic_interrupt_config *periodic_interrupt; 2075 const enum dc_dither_option *dither_option; 2076 struct dc_info_packet *vrr_infopacket; 2077 struct dc_info_packet *vsc_infopacket; 2078 struct dc_info_packet *vsp_infopacket; 2079 struct dc_info_packet *hfvsif_infopacket; 2080 struct dc_info_packet *vtem_infopacket; 2081 struct dc_info_packet *adaptive_sync_infopacket; 2082 struct dc_info_packet *avi_infopacket; 2083 struct dc_info_packet *hdr_static_metadata; 2084 }; 2085 2086 struct dc_surface_update { 2087 struct dc_plane_state *surface; 2088 2089 /* isr safe update parameters. null means no updates */ 2090 const struct dc_flip_addrs *flip_addr; 2091 const struct dc_plane_info *plane_info; 2092 const struct dc_scaling_info *scaling_info; 2093 struct fixed31_32 hdr_mult; 2094 /* following updates require alloc/sleep/spin that is not isr safe, 2095 * null means no updates 2096 */ 2097 const struct dc_gamma *gamma; 2098 const struct dc_transfer_func *in_transfer_func; 2099 2100 const struct dc_csc_transform *input_csc_color_matrix; 2101 const struct fixed31_32 *coeff_reduction_factor; 2102 const struct colorspace_transform *gamut_remap_matrix; 2103 const struct dc_plane_cm *cm; 2104 const struct dc_csc_transform *cursor_csc_color_matrix; 2105 unsigned int sdr_white_level_nits; 2106 struct dc_bias_and_scale bias_and_scale; 2107 struct cm_hist_control *cm_hist_control; 2108 }; 2109 2110 struct dc_underflow_debug_data { 2111 struct dcn_hubbub_reg_state *hubbub_reg_state; 2112 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 2113 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 2114 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 2115 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 2116 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 2117 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 2118 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 2119 }; 2120 2121 struct power_features { 2122 bool ips; 2123 bool rcg; 2124 bool replay; 2125 bool dds; 2126 bool sprs; 2127 bool psr; 2128 bool fams; 2129 bool mpo; 2130 bool uclk_p_state; 2131 }; 2132 2133 /* 2134 * Create a new surface with default parameters; 2135 */ 2136 void dc_gamma_retain(struct dc_gamma *dc_gamma); 2137 void dc_gamma_release(struct dc_gamma **dc_gamma); 2138 struct dc_gamma *dc_create_gamma(void); 2139 2140 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 2141 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 2142 struct dc_transfer_func *dc_create_transfer_func(void); 2143 2144 struct dc_3dlut *dc_create_3dlut_func(void); 2145 void dc_3dlut_func_release(struct dc_3dlut *lut); 2146 void dc_3dlut_func_retain(struct dc_3dlut *lut); 2147 2148 struct dc_plane_cm *dc_plane_cm_create(void); 2149 void dc_plane_cm_release(struct dc_plane_cm *cm); 2150 void dc_plane_cm_retain(struct dc_plane_cm *cm); 2151 2152 void dc_post_update_surfaces_to_stream( 2153 struct dc *dc); 2154 2155 /* 2156 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling 2157 * description for (typically) linear surfaces. 2158 * 2159 * This is used by OS/DM paths that need a valid, fully-initialized tiling 2160 * description without hardcoding gfx-version specifics in the caller. 2161 */ 2162 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); 2163 2164 /** 2165 * struct dc_validation_set - Struct to store surface/stream associations for validation 2166 */ 2167 struct dc_validation_set { 2168 /** 2169 * @stream: Stream state properties 2170 */ 2171 struct dc_stream_state *stream; 2172 2173 /** 2174 * @plane_states: Surface state 2175 */ 2176 struct dc_plane_state *plane_states[MAX_SURFACES]; 2177 2178 /** 2179 * @plane_count: Total of active planes 2180 */ 2181 uint8_t plane_count; 2182 }; 2183 2184 bool dc_validate_boot_timing(const struct dc *dc, 2185 const struct dc_sink *sink, 2186 struct dc_crtc_timing *crtc_timing); 2187 2188 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 2189 2190 enum dc_status dc_validate_with_context(struct dc *dc, 2191 const struct dc_validation_set set[], 2192 unsigned int set_count, 2193 struct dc_state *context, 2194 enum dc_validate_mode validate_mode); 2195 2196 bool dc_set_generic_gpio_for_stereo(bool enable, 2197 struct gpio_service *gpio_service); 2198 2199 enum dc_status dc_validate_global_state( 2200 struct dc *dc, 2201 struct dc_state *new_ctx, 2202 enum dc_validate_mode validate_mode); 2203 2204 bool dc_acquire_release_mpc_3dlut( 2205 struct dc *dc, bool acquire, 2206 struct dc_stream_state *stream, 2207 struct dc_3dlut **lut, 2208 struct dc_transfer_func **shaper); 2209 2210 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 2211 void get_audio_check(struct audio_info *aud_modes, 2212 struct audio_check *aud_chk); 2213 2214 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 2215 void populate_fast_updates(struct dc_fast_update *fast_update, 2216 struct dc_surface_update *srf_updates, 2217 int surface_count, 2218 struct dc_stream_update *stream_update); 2219 /* 2220 * Set up streams and links associated to drive sinks 2221 * The streams parameter is an absolute set of all active streams. 2222 * 2223 * After this call: 2224 * Phy, Encoder, Timing Generator are programmed and enabled. 2225 * New streams are enabled with blank stream; no memory read. 2226 */ 2227 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 2228 2229 2230 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2231 struct dc_stream_state *stream, 2232 int mpcc_inst); 2233 2234 2235 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2236 bool dc_set_fva_vrr_adjust(struct dc *dc, 2237 struct dc_stream_state *stream, 2238 struct fva_adj *fva_adj, 2239 struct dc_crtc_timing_adjust *vrr_adj); 2240 2241 int dc_get_hw_max_fva_factor(struct dc *dc, 2242 struct dc_stream_state *stream, 2243 unsigned int max_pixel_clock); 2244 2245 void dc_set_vstartup_start(struct dc *dc, 2246 struct dc_stream_state *stream); 2247 2248 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2249 2250 /* The function returns minimum bandwidth required to drive a given timing 2251 * return - minimum required timing bandwidth in kbps. 2252 */ 2253 uint32_t dc_bandwidth_in_kbps_from_timing( 2254 const struct dc_crtc_timing *timing, 2255 const enum dc_link_encoding_format link_encoding); 2256 2257 /* Link Interfaces */ 2258 /* Return an enumerated dc_link. 2259 * dc_link order is constant and determined at 2260 * boot time. They cannot be created or destroyed. 2261 * Use dc_get_caps() to get number of links. 2262 */ 2263 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2264 2265 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2266 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2267 const struct dc_link *link, 2268 unsigned int *inst_out); 2269 2270 /* Return an array of link pointers to edp links. */ 2271 void dc_get_edp_links(const struct dc *dc, 2272 struct dc_link **edp_links, 2273 unsigned int *edp_num); 2274 2275 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2276 bool powerOn); 2277 2278 /* The function initiates detection handshake over the given link. It first 2279 * determines if there are display connections over the link. If so it initiates 2280 * detection protocols supported by the connected receiver device. The function 2281 * contains protocol specific handshake sequences which are sometimes mandatory 2282 * to establish a proper connection between TX and RX. So it is always 2283 * recommended to call this function as the first link operation upon HPD event 2284 * or power up event. Upon completion, the function will update link structure 2285 * in place based on latest RX capabilities. The function may also cause dpms 2286 * to be reset to off for all currently enabled streams to the link. It is DM's 2287 * responsibility to serialize detection and DPMS updates. 2288 * 2289 * @reason - Indicate which event triggers this detection. dc may customize 2290 * detection flow depending on the triggering events. 2291 * return false - if detection is not fully completed. This could happen when 2292 * there is an unrecoverable error during detection or detection is partially 2293 * completed (detection has been delegated to dm mst manager ie. 2294 * link->connection_type == dc_connection_mst_branch when returning false). 2295 * return true - detection is completed, link has been fully updated with latest 2296 * detection result. 2297 */ 2298 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2299 2300 struct dc_sink_init_data; 2301 2302 /* When link connection type is dc_connection_mst_branch, remote sink can be 2303 * added to the link. The interface creates a remote sink and associates it with 2304 * current link. The sink will be retained by link until remove remote sink is 2305 * called. 2306 * 2307 * @dc_link - link the remote sink will be added to. 2308 * @edid - byte array of EDID raw data. 2309 * @len - size of the edid in byte 2310 * @init_data - 2311 */ 2312 struct dc_sink *dc_link_add_remote_sink( 2313 struct dc_link *dc_link, 2314 const uint8_t *edid, 2315 unsigned int len, 2316 struct dc_sink_init_data *init_data); 2317 2318 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2319 * @link - link the sink should be removed from 2320 * @sink - sink to be removed. 2321 */ 2322 void dc_link_remove_remote_sink( 2323 struct dc_link *link, 2324 struct dc_sink *sink); 2325 2326 /* Enable HPD interrupt handler for a given link */ 2327 void dc_link_enable_hpd(const struct dc_link *link); 2328 2329 /* Disable HPD interrupt handler for a given link */ 2330 void dc_link_disable_hpd(const struct dc_link *link); 2331 2332 /* determine if there is a sink connected to the link 2333 * 2334 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2335 * return - false if an unexpected error occurs, true otherwise. 2336 * 2337 * NOTE: This function doesn't detect downstream sink connections i.e 2338 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2339 * return dc_connection_single if the branch device is connected despite of 2340 * downstream sink's connection status. 2341 */ 2342 bool dc_link_detect_connection_type(struct dc_link *link, 2343 enum dc_connection_type *type); 2344 2345 /* query current hpd pin value 2346 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2347 * 2348 */ 2349 bool dc_link_get_hpd_state(struct dc_link *link); 2350 2351 /* Getter for cached link status from given link */ 2352 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2353 2354 /* enable/disable hardware HPD filter. 2355 * 2356 * @link - The link the HPD pin is associated with. 2357 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2358 * handler once after no HPD change has been detected within dc default HPD 2359 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2360 * pulses within default HPD interval, no HPD event will be received until HPD 2361 * toggles have stopped. Then HPD event will be queued to irq handler once after 2362 * dc default HPD filtering interval since last HPD event. 2363 * 2364 * @enable = false - disable hardware HPD filter. HPD event will be queued 2365 * immediately to irq handler after no HPD change has been detected within 2366 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2367 */ 2368 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2369 2370 /* submit i2c read/write payloads through ddc channel 2371 * @link_index - index to a link with ddc in i2c mode 2372 * @cmd - i2c command structure 2373 * return - true if success, false otherwise. 2374 */ 2375 bool dc_submit_i2c( 2376 struct dc *dc, 2377 uint32_t link_index, 2378 struct i2c_command *cmd); 2379 2380 /* submit i2c read/write payloads through oem channel 2381 * @link_index - index to a link with ddc in i2c mode 2382 * @cmd - i2c command structure 2383 * return - true if success, false otherwise. 2384 */ 2385 bool dc_submit_i2c_oem( 2386 struct dc *dc, 2387 struct i2c_command *cmd); 2388 2389 enum aux_return_code_type; 2390 /* Attempt to transfer the given aux payload. This function does not perform 2391 * retries or handle error states. The reply is returned in the payload->reply 2392 * and the result through operation_result. Returns the number of bytes 2393 * transferred,or -1 on a failure. 2394 */ 2395 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2396 struct aux_payload *payload, 2397 enum aux_return_code_type *operation_result); 2398 2399 struct ddc_service * 2400 dc_get_oem_i2c_device(struct dc *dc); 2401 2402 bool dc_is_oem_i2c_device_present( 2403 struct dc *dc, 2404 size_t slave_address 2405 ); 2406 2407 /* return true if the connected receiver supports the hdcp version */ 2408 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2409 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2410 2411 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2412 * 2413 * TODO - When defer_handling is true the function will have a different purpose. 2414 * It no longer does complete hpd rx irq handling. We should create a separate 2415 * interface specifically for this case. 2416 * 2417 * Return: 2418 * true - Downstream port status changed. DM should call DC to do the 2419 * detection. 2420 * false - no change in Downstream port status. No further action required 2421 * from DM. 2422 */ 2423 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2424 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2425 bool defer_handling, bool *has_left_work); 2426 /* handle DP specs define test automation sequence*/ 2427 void dc_link_dp_handle_automated_test(struct dc_link *link); 2428 2429 /* handle DP Link loss sequence and try to recover RX link loss with best 2430 * effort 2431 */ 2432 void dc_link_dp_handle_link_loss(struct dc_link *link); 2433 2434 /* Determine if hpd rx irq should be handled or ignored 2435 * return true - hpd rx irq should be handled. 2436 * return false - it is safe to ignore hpd rx irq event 2437 */ 2438 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2439 2440 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2441 * @link - link the hpd irq data associated with 2442 * @hpd_irq_dpcd_data - input hpd irq data 2443 * return - true if hpd irq data indicates a link lost 2444 */ 2445 bool dc_link_check_link_loss_status(struct dc_link *link, 2446 union hpd_irq_data *hpd_irq_dpcd_data); 2447 2448 /* Read hpd rx irq data from a given link 2449 * @link - link where the hpd irq data should be read from 2450 * @irq_data - output hpd irq data 2451 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2452 * read has failed. 2453 */ 2454 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2455 struct dc_link *link, 2456 union hpd_irq_data *irq_data); 2457 2458 bool dc_link_frl_poll_status_flag(struct dc_link *link); 2459 bool dc_link_frl_margin_check_uncompressed_video( 2460 const struct dc_link *link, 2461 struct frl_cap_chk_params_fixed31_32 *params, 2462 struct frl_cap_chk_intermediates_fixed31_32 *inter); 2463 2464 /* The function clears recorded DP RX states in the link. DM should call this 2465 * function when it is resuming from S3 power state to previously connected links. 2466 * 2467 * TODO - in the future we should consider to expand link resume interface to 2468 * support clearing previous rx states. So we don't have to rely on dm to call 2469 * this interface explicitly. 2470 */ 2471 void dc_link_clear_dprx_states(struct dc_link *link); 2472 2473 /* Destruct the mst topology of the link and reset the allocated payload table 2474 * 2475 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2476 * still wants to reset MST topology on an unplug event */ 2477 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2478 2479 /* The function calculates effective DP link bandwidth when a given link is 2480 * using the given link settings. 2481 * 2482 * return - total effective link bandwidth in kbps. 2483 */ 2484 uint32_t dc_link_bandwidth_kbps( 2485 const struct dc_link *link, 2486 const struct dc_link_settings *link_setting); 2487 2488 /* The function returns effective HDMI FRL bandwidth given link rate. 2489 * return - total effective link bandwidth in kbps. 2490 */ 2491 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link, 2492 enum hdmi_frl_link_rate link_rate); 2493 2494 struct dp_audio_bandwidth_params { 2495 const struct dc_crtc_timing *crtc_timing; 2496 enum dp_link_encoding link_encoding; 2497 uint32_t channel_count; 2498 uint32_t sample_rate_hz; 2499 }; 2500 2501 /* The function calculates the minimum size of hblank (in bytes) needed to 2502 * support the specified channel count and sample rate combination, given the 2503 * link encoding and timing to be used. This calculation is not supported 2504 * for 8b/10b SST. 2505 * 2506 * return - min hblank size in bytes, 0 if 8b/10b SST. 2507 */ 2508 uint32_t dc_link_required_hblank_size_bytes( 2509 const struct dc_link *link, 2510 struct dp_audio_bandwidth_params *audio_params); 2511 2512 /* The function takes a snapshot of current link resource allocation state 2513 * @dc: pointer to dc of the dm calling this 2514 * @map: a dc link resource snapshot defined internally to dc. 2515 * 2516 * DM needs to capture a snapshot of current link resource allocation mapping 2517 * and store it in its persistent storage. 2518 * 2519 * Some of the link resource is using first come first serve policy. 2520 * The allocation mapping depends on original hotplug order. This information 2521 * is lost after driver is loaded next time. The snapshot is used in order to 2522 * restore link resource to its previous state so user will get consistent 2523 * link capability allocation across reboot. 2524 * 2525 */ 2526 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2527 2528 /* This function restores link resource allocation state from a snapshot 2529 * @dc: pointer to dc of the dm calling this 2530 * @map: a dc link resource snapshot defined internally to dc. 2531 * 2532 * DM needs to call this function after initial link detection on boot and 2533 * before first commit streams to restore link resource allocation state 2534 * from previous boot session. 2535 * 2536 * Some of the link resource is using first come first serve policy. 2537 * The allocation mapping depends on original hotplug order. This information 2538 * is lost after driver is loaded next time. The snapshot is used in order to 2539 * restore link resource to its previous state so user will get consistent 2540 * link capability allocation across reboot. 2541 * 2542 */ 2543 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2544 2545 void dc_link_wait_for_unlocked(struct dc_link *link); 2546 2547 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2548 * interface i.e stream_update->dsc_config 2549 */ 2550 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2551 2552 /* translate a raw link rate data to bandwidth in kbps */ 2553 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2554 2555 /* determine the optimal bandwidth given link and required bw. 2556 * @link - current detected link 2557 * @req_bw - requested bandwidth in kbps 2558 * @link_settings - returned most optimal link settings that can fit the 2559 * requested bandwidth 2560 * return - false if link can't support requested bandwidth, true if link 2561 * settings is found. 2562 */ 2563 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2564 struct dc_link_settings *link_settings, 2565 uint32_t req_bw); 2566 2567 /* return the max dp link settings can be driven by the link without considering 2568 * connected RX device and its capability 2569 */ 2570 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2571 struct dc_link_settings *max_link_enc_cap); 2572 2573 /* determine when the link is driving MST mode, what DP link channel coding 2574 * format will be used. The decision will remain unchanged until next HPD event. 2575 * 2576 * @link - a link with DP RX connection 2577 * return - if stream is committed to this link with MST signal type, type of 2578 * channel coding format dc will choose. 2579 */ 2580 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2581 const struct dc_link *link); 2582 2583 /* get max dp link settings the link can enable with all things considered. (i.e 2584 * TX/RX/Cable capabilities and dp override policies. 2585 * 2586 * @link - a link with DP RX connection 2587 * return - max dp link settings the link can enable. 2588 * 2589 */ 2590 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2591 2592 /* Get the highest encoding format that the link supports; highest meaning the 2593 * encoding format which supports the maximum bandwidth. 2594 * 2595 * @link - a link with DP RX connection 2596 * return - highest encoding format link supports. 2597 */ 2598 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2599 2600 /* get max frl link settings the link can enable with all things considered. 2601 * (i.e TX/RX capabilities and link verification result. 2602 * 2603 * @link - a link with FRL RX connection 2604 * return - max frl link settings the link can enable. 2605 * 2606 */ 2607 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap( 2608 struct dc_link *link); 2609 2610 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2611 * to a link with dp connector signal type. 2612 * @link - a link with dp connector signal type 2613 * return - true if connected, false otherwise 2614 */ 2615 bool dc_link_is_dp_sink_present(struct dc_link *link); 2616 2617 /* Force DP lane settings update to main-link video signal and notify the change 2618 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2619 * tuning purpose. The interface assumes link has already been enabled with DP 2620 * signal. 2621 * 2622 * @lt_settings - a container structure with desired hw_lane_settings 2623 */ 2624 void dc_link_set_drive_settings(struct dc *dc, 2625 struct link_training_settings *lt_settings, 2626 struct dc_link *link); 2627 2628 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2629 * test or debugging purpose. The test pattern will remain until next un-plug. 2630 * 2631 * @link - active link with DP signal output enabled. 2632 * @test_pattern - desired test pattern to output. 2633 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2634 * @test_pattern_color_space - for video test pattern choose a desired color 2635 * space. 2636 * @p_link_settings - For PHY pattern choose a desired link settings 2637 * @p_custom_pattern - some test pattern will require a custom input to 2638 * customize some pattern details. Otherwise keep it to NULL. 2639 * @cust_pattern_size - size of the custom pattern input. 2640 * 2641 */ 2642 bool dc_link_dp_set_test_pattern( 2643 struct dc_link *link, 2644 enum dp_test_pattern test_pattern, 2645 enum dp_test_pattern_color_space test_pattern_color_space, 2646 const struct link_training_settings *p_link_settings, 2647 const unsigned char *p_custom_pattern, 2648 unsigned int cust_pattern_size); 2649 2650 /* Force DP link settings to always use a specific value until reboot to a 2651 * specific link. If link has already been enabled, the interface will also 2652 * switch to desired link settings immediately. This is a debug interface to 2653 * generic dp issue trouble shooting. 2654 */ 2655 void dc_link_set_preferred_link_settings(struct dc *dc, 2656 struct dc_link_settings *link_setting, 2657 struct dc_link *link); 2658 2659 /* Force FRL link settings to always use a specific value until reboot to a 2660 * specific link. If link has already been enabled, the interface will also 2661 * switch to desired link settings immediately. This is a debug interface to 2662 * generic FRL issue trouble shooting. 2663 */ 2664 void dc_link_set_preferred_frl_link_settings(struct dc *dc, 2665 struct dc_hdmi_frl_link_settings *link_setting, 2666 struct dc_hdmi_frl_link_training_overrides *lt_overrides, 2667 struct dc_link *link); 2668 2669 /* Force DP link to customize a specific link training behavior by overriding to 2670 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2671 * display specific link training issues or apply some display specific 2672 * workaround in link training. 2673 * 2674 * @link_settings - if not NULL, force preferred link settings to the link. 2675 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2676 * will apply this particular override in future link training. If NULL is 2677 * passed in, dc resets previous overrides. 2678 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2679 * training settings. 2680 */ 2681 void dc_link_set_preferred_training_settings(struct dc *dc, 2682 struct dc_link_settings *link_setting, 2683 struct dc_link_training_overrides *lt_overrides, 2684 struct dc_link *link, 2685 bool skip_immediate_retrain); 2686 2687 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2688 bool dc_link_is_fec_supported(const struct dc_link *link); 2689 2690 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2691 * link enablement. 2692 * return - true if FEC should be enabled, false otherwise. 2693 */ 2694 bool dc_link_should_enable_fec(const struct dc_link *link); 2695 2696 /* determine lttpr mode the current link should be enabled with a specific link 2697 * settings. 2698 */ 2699 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2700 struct dc_link_settings *link_setting); 2701 2702 /* Force DP RX to update its power state. 2703 * NOTE: this interface doesn't update dp main-link. Calling this function will 2704 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2705 * RX power state back upon finish DM specific execution requiring DP RX in a 2706 * specific power state. 2707 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2708 * state. 2709 */ 2710 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2711 2712 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2713 * current value read from extended receiver cap from 02200h - 0220Fh. 2714 * Some DP RX has problems of providing accurate DP receiver caps from extended 2715 * field, this interface is a workaround to revert link back to use base caps. 2716 */ 2717 void dc_link_overwrite_extended_receiver_cap( 2718 struct dc_link *link); 2719 2720 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2721 bool wait_for_hpd); 2722 2723 /* Set backlight level of an embedded panel (eDP, LVDS). 2724 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2725 * and 16 bit fractional, where 1.0 is max backlight value. 2726 */ 2727 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2728 struct set_backlight_level_params *backlight_level_params); 2729 2730 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2731 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2732 bool isHDR, 2733 uint32_t backlight_millinits, 2734 uint32_t transition_time_in_ms); 2735 2736 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2737 uint32_t *backlight_millinits, 2738 uint32_t *backlight_millinits_peak); 2739 2740 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2741 2742 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2743 2744 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2745 bool wait, bool force_static, const unsigned int *power_opts); 2746 2747 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2748 2749 bool dc_link_setup_psr(struct dc_link *dc_link, 2750 const struct dc_stream_state *stream, struct psr_config *psr_config, 2751 struct psr_context *psr_context); 2752 2753 /* 2754 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2755 * 2756 * @link: pointer to the dc_link struct instance 2757 * @enable: enable(active) or disable(inactive) replay 2758 * @wait: state transition need to wait the active set completed. 2759 * @force_static: force disable(inactive) the replay 2760 * @power_opts: set power optimazation parameters to DMUB. 2761 * 2762 * return: allow Replay active will return true, else will return false. 2763 */ 2764 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2765 bool wait, bool force_static, const unsigned int *power_opts); 2766 2767 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2768 2769 /* 2770 * Enable or disable Panel Replay on the specified link: 2771 * 2772 * @link: pointer to the dc_link struct instance 2773 * @enable: enable or disable Panel Replay 2774 * 2775 * return: true if successful, false otherwise 2776 */ 2777 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2778 2779 /* 2780 * Update Panel Replay state parameters: 2781 * 2782 * @link: pointer to the dc_link struct instance 2783 * @update_state_data: pointer to state update data structure 2784 * 2785 * return: true if successful, false otherwise 2786 */ 2787 bool dc_link_update_pr_state(struct dc_link *link, 2788 struct dmub_cmd_pr_update_state_data *update_state_data); 2789 2790 /* 2791 * Send general command to Panel Replay firmware: 2792 * 2793 * @link: pointer to the dc_link struct instance 2794 * @general_cmd_data: pointer to general command data structure 2795 * 2796 * return: true if successful, false otherwise 2797 */ 2798 bool dc_link_set_pr_general_cmd(struct dc_link *link, 2799 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 2800 2801 /* 2802 * Get Panel Replay state: 2803 * 2804 * @link: pointer to the dc_link struct instance 2805 * @state: pointer to store the Panel Replay state 2806 * 2807 * return: true if successful, false otherwise 2808 */ 2809 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 2810 2811 /* On eDP links this function call will stall until T12 has elapsed. 2812 * If the panel is not in power off state, this function will return 2813 * immediately. 2814 */ 2815 bool dc_link_wait_for_t12(struct dc_link *link); 2816 2817 /* Determine if dp trace has been initialized to reflect upto date result * 2818 * return - true if trace is initialized and has valid data. False dp trace 2819 * doesn't have valid result. 2820 */ 2821 bool dc_dp_trace_is_initialized(struct dc_link *link); 2822 2823 /* Query a dp trace flag to indicate if the current dp trace data has been 2824 * logged before 2825 */ 2826 bool dc_dp_trace_is_logged(struct dc_link *link, 2827 bool in_detection); 2828 2829 /* Set dp trace flag to indicate whether DM has already logged the current dp 2830 * trace data. DM can set is_logged to true upon logging and check 2831 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2832 */ 2833 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2834 bool in_detection, 2835 bool is_logged); 2836 2837 /* Obtain driver time stamp for last dp link training end. The time stamp is 2838 * formatted based on dm_get_timestamp DM function. 2839 * @in_detection - true to get link training end time stamp of last link 2840 * training in detection sequence. false to get link training end time stamp 2841 * of last link training in commit (dpms) sequence 2842 */ 2843 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2844 bool in_detection); 2845 2846 /* Get how many link training attempts dc has done with latest sequence. 2847 * @in_detection - true to get link training count of last link 2848 * training in detection sequence. false to get link training count of last link 2849 * training in commit (dpms) sequence 2850 */ 2851 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2852 bool in_detection); 2853 2854 /* Get how many link loss has happened since last link training attempts */ 2855 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2856 2857 /* 2858 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2859 */ 2860 /* 2861 * Send a request from DP-Tx requesting to allocate BW remotely after 2862 * allocating it locally. This will get processed by CM and a CB function 2863 * will be called. 2864 * 2865 * @link: pointer to the dc_link struct instance 2866 * @req_bw: The requested bw in Kbyte to allocated 2867 * 2868 * return: none 2869 */ 2870 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2871 2872 /* 2873 * Handle the USB4 BW Allocation related functionality here: 2874 * Plug => Try to allocate max bw from timing parameters supported by the sink 2875 * Unplug => de-allocate bw 2876 * 2877 * @link: pointer to the dc_link struct instance 2878 * @peak_bw: Peak bw used by the link/sink 2879 * 2880 */ 2881 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2882 struct dc_link *link, int peak_bw); 2883 2884 /* 2885 * Calculates the DP tunneling bandwidth required for the stream timing 2886 * and aggregates the stream bandwidth for the respective DP tunneling link 2887 * 2888 * return: dc_status 2889 */ 2890 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2891 2892 /* 2893 * Get if ALPM is supported by the link 2894 */ 2895 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 2896 bool *auxwake_support); 2897 2898 /* Sink Interfaces - A sink corresponds to a display output device */ 2899 2900 struct dc_container_id { 2901 // 128bit GUID in binary form 2902 unsigned char guid[16]; 2903 // 8 byte port ID -> ELD.PortID 2904 unsigned int portId[2]; 2905 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2906 unsigned short manufacturerName; 2907 // 2 byte product code -> ELD.ProductCode 2908 unsigned short productCode; 2909 }; 2910 2911 2912 struct dc_sink_dsc_caps { 2913 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2914 // 'false' if they are sink's DSC caps 2915 bool is_virtual_dpcd_dsc; 2916 // 'true' if MST topology supports DSC passthrough for sink 2917 // 'false' if MST topology does not support DSC passthrough 2918 bool is_dsc_passthrough_supported; 2919 struct dsc_dec_dpcd_caps dsc_dec_caps; 2920 }; 2921 2922 struct dc_sink_hblank_expansion_caps { 2923 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2924 // 'false' if they are sink's HBlank expansion caps 2925 bool is_virtual_dpcd_hblank_expansion; 2926 struct hblank_expansion_dpcd_caps dpcd_caps; 2927 }; 2928 2929 struct dc_sink_fec_caps { 2930 bool is_rx_fec_supported; 2931 bool is_topology_fec_supported; 2932 }; 2933 2934 struct scdc_caps { 2935 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2936 union hdmi_scdc_device_id_data device_id; 2937 }; 2938 2939 /* 2940 * The sink structure contains EDID and other display device properties 2941 */ 2942 struct dc_sink { 2943 enum signal_type sink_signal; 2944 struct dc_edid dc_edid; /* raw edid */ 2945 struct dc_edid_caps edid_caps; /* parse display caps */ 2946 struct dc_container_id *dc_container_id; 2947 uint32_t dongle_max_pix_clk; 2948 void *priv; 2949 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2950 bool converter_disable_audio; 2951 2952 struct mccs_caps mccs_caps; 2953 struct scdc_caps scdc_caps; 2954 struct dc_sink_dsc_caps dsc_caps; 2955 struct dc_sink_fec_caps fec_caps; 2956 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2957 2958 bool is_vsc_sdp_colorimetry_supported; 2959 2960 /* private to DC core */ 2961 struct dc_link *link; 2962 struct dc_context *ctx; 2963 2964 uint32_t sink_id; 2965 2966 /* private to dc_sink.c */ 2967 // refcount must be the last member in dc_sink, since we want the 2968 // sink structure to be logically cloneable up to (but not including) 2969 // refcount 2970 struct kref refcount; 2971 }; 2972 2973 void dc_sink_retain(struct dc_sink *sink); 2974 void dc_sink_release(struct dc_sink *sink); 2975 2976 struct dc_sink_init_data { 2977 enum signal_type sink_signal; 2978 struct dc_link *link; 2979 uint32_t dongle_max_pix_clk; 2980 bool converter_disable_audio; 2981 }; 2982 2983 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2984 2985 /* Newer interfaces */ 2986 struct dc_cursor { 2987 struct dc_plane_address address; 2988 struct dc_cursor_attributes attributes; 2989 }; 2990 2991 2992 /* Interrupt interfaces */ 2993 enum dc_irq_source dc_interrupt_to_irq_source( 2994 struct dc *dc, 2995 uint32_t src_id, 2996 uint32_t ext_id); 2997 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2998 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2999 enum dc_irq_source dc_get_hpd_irq_source_at_index( 3000 struct dc *dc, uint32_t link_index); 3001 3002 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 3003 3004 /* Power Interfaces */ 3005 3006 void dc_set_power_state( 3007 struct dc *dc, 3008 enum dc_acpi_cm_power_state power_state); 3009 void dc_resume(struct dc *dc); 3010 3011 void dc_power_down_on_boot(struct dc *dc); 3012 3013 /* 3014 * HDCP Interfaces 3015 */ 3016 enum hdcp_message_status dc_process_hdcp_msg( 3017 enum signal_type signal, 3018 struct dc_link *link, 3019 struct hdcp_protection_message *message_info); 3020 bool dc_is_dmcu_initialized(struct dc *dc); 3021 3022 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 3023 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 3024 3025 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 3026 unsigned int pitch, 3027 unsigned int height, 3028 enum surface_pixel_format format, 3029 struct dc_cursor_attributes *cursor_attr); 3030 3031 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 3032 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 3033 3034 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 3035 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 3036 bool dc_dmub_is_ips_idle_state(struct dc *dc); 3037 3038 /* set min and max memory clock to lowest and highest DPM level, respectively */ 3039 void dc_unlock_memory_clock_frequency(struct dc *dc); 3040 3041 /* set min memory clock to the min required for current mode, max to maxDPM */ 3042 void dc_lock_memory_clock_frequency(struct dc *dc); 3043 3044 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 3045 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 3046 3047 /* cleanup on driver unload */ 3048 void dc_hardware_release(struct dc *dc); 3049 3050 /* disables fw based mclk switch */ 3051 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 3052 3053 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 3054 3055 bool dc_set_replay_allow_active(struct dc *dc, bool active); 3056 3057 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 3058 3059 void dc_z10_restore(const struct dc *dc); 3060 void dc_z10_save_init(struct dc *dc); 3061 3062 bool dc_is_dmub_outbox_supported(struct dc *dc); 3063 bool dc_enable_dmub_notifications(struct dc *dc); 3064 3065 bool dc_abm_save_restore( 3066 struct dc *dc, 3067 struct dc_stream_state *stream, 3068 struct abm_save_restore *pData); 3069 3070 void dc_enable_dmub_outbox(struct dc *dc); 3071 3072 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 3073 uint32_t link_index, 3074 struct aux_payload *payload); 3075 3076 /* 3077 * smart power OLED Interfaces 3078 */ 3079 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 3080 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 3081 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 3082 3083 /* Get dc link index from dpia port index */ 3084 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 3085 uint8_t dpia_port_index); 3086 3087 bool dc_process_dmub_set_config_async(struct dc *dc, 3088 uint32_t link_index, 3089 struct set_config_cmd_payload *payload, 3090 struct dmub_notification *notify); 3091 3092 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 3093 uint32_t link_index, 3094 uint8_t mst_alloc_slots, 3095 uint8_t *mst_slots_in_use); 3096 3097 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 3098 3099 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 3100 uint32_t hpd_int_enable); 3101 3102 void dc_print_dmub_diagnostic_data(const struct dc *dc); 3103 3104 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 3105 3106 struct dc_power_profile { 3107 int power_level; /* Lower is better */ 3108 }; 3109 3110 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 3111 3112 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 3113 3114 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 3115 3116 void dc_log_preos_dmcub_info(const struct dc *dc); 3117 3118 /* DSC Interfaces */ 3119 #include "dc_dsc.h" 3120 3121 void dc_get_visual_confirm_for_stream( 3122 struct dc *dc, 3123 struct dc_stream_state *stream_state, 3124 struct tg_color *color); 3125 3126 /* Disable acc mode Interfaces */ 3127 void dc_disable_accelerated_mode(struct dc *dc); 3128 3129 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 3130 struct dc_stream_state *new_stream); 3131 3132 bool dc_is_cursor_limit_pending(struct dc *dc); 3133 bool dc_can_clear_cursor_limit(const struct dc *dc); 3134 3135 /** 3136 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 3137 * 3138 * @dc: Pointer to the display core context. 3139 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 3140 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 3141 * 3142 * This function collects and logs underflow-related HW states when underflow happens, 3143 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 3144 * The results are stored in the provided out_data structure for further analysis or logging. 3145 */ 3146 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); 3147 3148 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); 3149 3150 /* 3151 * Software state variables used to program register fields across the display pipeline 3152 */ 3153 struct dc_register_software_state { 3154 /* HUBP register programming variables for each pipe */ 3155 struct { 3156 bool valid_plane_state; 3157 bool valid_stream; 3158 bool min_dc_gfx_version9; 3159 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 3160 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 3161 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 3162 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 3163 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 3164 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 3165 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 3166 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 3167 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 3168 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 3169 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 3170 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 3171 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 3172 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 3173 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 3174 3175 /* Additional DCC configuration */ 3176 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 3177 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 3178 3179 /* Surface pitch configuration */ 3180 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 3181 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 3182 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 3183 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 3184 3185 /* Surface addresses */ 3186 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 3187 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 3188 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 3189 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 3190 3191 /* TMZ configuration */ 3192 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 3193 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 3194 3195 /* Tiling configuration */ 3196 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 3197 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 3198 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 3199 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 3200 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 3201 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 3202 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 3203 3204 /* DML Request Size Configuration - Luma */ 3205 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 3206 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 3207 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 3208 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 3209 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 3210 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 3211 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 3212 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 3213 3214 /* DML Request Size Configuration - Chroma */ 3215 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 3216 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 3217 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 3218 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 3219 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 3220 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 3221 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 3222 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 3223 3224 /* DML Expansion Modes */ 3225 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 3226 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 3227 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 3228 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 3229 3230 /* DML DLG parameters - nominal */ 3231 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 3232 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 3233 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 3234 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 3235 3236 /* DML prefetch settings */ 3237 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 3238 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 3239 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 3240 3241 /* TTU parameters */ 3242 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 3243 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 3244 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 3245 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 3246 } hubp[MAX_PIPES]; 3247 3248 /* HUBBUB register programming variables */ 3249 struct { 3250 /* Individual DET buffer control per pipe - software state that programs DET registers */ 3251 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 3252 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 3253 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 3254 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 3255 3256 /* Compression buffer control - software state that programs COMPBUF registers */ 3257 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 3258 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 3259 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 3260 } hubbub; 3261 3262 /* DPP register programming variables for each pipe (simplified for available fields) */ 3263 struct { 3264 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 3265 3266 /* Recout (Rectangle of Interest) configuration */ 3267 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 3268 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 3269 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 3270 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 3271 3272 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 3273 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 3274 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 3275 3276 /* DSCL mode configuration */ 3277 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3278 3279 /* Scaler ratios (simplified to integer parts) */ 3280 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3281 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3282 3283 /* Basic scaler taps */ 3284 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3285 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3286 } dpp[MAX_PIPES]; 3287 3288 /* DCCG register programming variables */ 3289 struct { 3290 /* Core Display Clock Control */ 3291 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3292 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3293 3294 /* DPP Clock Control - 4 fields per pipe */ 3295 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3296 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3297 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3298 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3299 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3300 3301 /* DSC Clock Control - 4 fields per DSC resource */ 3302 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3303 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3304 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3305 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3306 3307 /* Pixel Clock Control - per pipe */ 3308 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3309 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3310 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3311 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3312 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3313 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3314 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3315 3316 /* DTBCLK DTO Control - 4 DTOs */ 3317 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3318 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3319 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3320 3321 /* DP Stream Clock Control - 4 pipes */ 3322 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3323 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3324 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3325 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3326 3327 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3328 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3329 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3330 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3331 3332 /* SYMCLK32 SE Control - 4 instances */ 3333 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3334 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3335 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3336 3337 /* SYMCLK32 LE Control - 2 instances */ 3338 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3339 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3340 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3341 3342 /* HDMI Clock Control */ 3343 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */ 3344 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */ 3345 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */ 3346 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */ 3347 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */ 3348 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */ 3349 3350 /* DPIA Clock Control */ 3351 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3352 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3353 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3354 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3355 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3356 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3357 3358 /* Clock Gating Control */ 3359 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3360 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3361 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3362 3363 /* VSync Control */ 3364 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3365 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3366 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3367 3368 /* Time Base Control */ 3369 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3370 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3371 } dccg; 3372 3373 /* DSC essential configuration for underflow analysis */ 3374 struct { 3375 /* DSC active state - critical for bandwidth analysis */ 3376 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3377 3378 /* DSC configuration affecting bandwidth and timing */ 3379 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3380 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3381 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3382 3383 /* OPP integration - affects pipeline flow */ 3384 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3385 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3386 } dsc[MAX_PIPES]; 3387 3388 /* MPC register programming variables */ 3389 struct { 3390 /* MPCC blending tree and mode control */ 3391 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3392 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3393 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3394 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3395 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3396 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3397 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3398 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3399 3400 /* MPCC blending tree connections */ 3401 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3402 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3403 3404 /* MPCC output gamma control */ 3405 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3406 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3407 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3408 3409 /* MPCC pipe assignment and status */ 3410 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3411 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3412 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3413 3414 /* MPC output processing */ 3415 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3416 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3417 } mpc; 3418 3419 /* OPP register programming variables for each pipe */ 3420 struct { 3421 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3422 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3423 3424 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3425 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3426 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3427 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3428 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3429 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3430 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3431 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3432 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3433 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3434 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3435 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3436 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3437 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3438 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3439 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3440 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3441 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3442 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3443 3444 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3445 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3446 3447 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3448 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3449 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3450 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3451 3452 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3453 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3454 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3455 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3456 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3457 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3458 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3459 3460 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3461 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3462 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3463 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3464 } opp[MAX_PIPES]; 3465 3466 /* OPTC register programming variables for each pipe */ 3467 struct { 3468 uint32_t otg_master_inst; 3469 3470 /* OTG_CONTROL register - 5 fields for OTG control */ 3471 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3472 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3473 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3474 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3475 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3476 3477 /* OTG Horizontal Timing - 7 fields */ 3478 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3479 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3480 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3481 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3482 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3483 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3484 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3485 3486 /* OTG Vertical Timing - 7 fields */ 3487 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3488 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3489 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3490 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3491 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3492 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3493 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3494 3495 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3496 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3497 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3498 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3499 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3500 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3501 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3502 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3503 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3504 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3505 3506 /* OPTC Data Source and ODM - 6 fields */ 3507 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3508 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3509 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3510 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3511 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3512 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3513 3514 /* OPTC Data Format and DSC - 4 fields */ 3515 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3516 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3517 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3518 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3519 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3520 3521 /* OPTC Clock and Underflow Control - 4 fields */ 3522 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3523 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3524 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3525 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3526 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3527 3528 /* OTG Stereo and 3D Control - 6 fields */ 3529 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3530 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3531 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3532 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3533 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3534 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3535 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3536 3537 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3538 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3539 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3540 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3541 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3542 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3543 3544 /* OTG DRR Advanced Control - 4 fields */ 3545 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3546 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3547 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3548 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3549 3550 /* OTG DSC Position Control - 2 fields */ 3551 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3552 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3553 3554 /* OTG Double Buffer Control - 2 fields */ 3555 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3556 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3557 3558 /* OTG Vertical Interrupts - 6 fields */ 3559 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3560 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3561 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3562 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3563 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3564 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3565 3566 /* OTG Global Sync Parameters - 6 fields */ 3567 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3568 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3569 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3570 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3571 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3572 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3573 3574 /* OTG Manual Trigger Control - 11 fields */ 3575 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3576 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3577 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3578 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3579 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3580 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3581 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3582 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3583 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3584 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3585 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3586 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3587 3588 /* OTG Static Screen and Update Control - 6 fields */ 3589 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3590 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3591 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3592 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3593 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3594 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3595 3596 /* VTG Control - 3 fields */ 3597 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3598 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3599 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3600 3601 /* OTG Status (Read-Only) - 12 fields */ 3602 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3603 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3604 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3605 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3606 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3607 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3608 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3609 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3610 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3611 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3612 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3613 } optc[MAX_PIPES]; 3614 3615 /* Metadata */ 3616 uint32_t active_pipe_count; 3617 uint32_t active_stream_count; 3618 bool state_valid; 3619 }; 3620 3621 /** 3622 * dc_capture_register_software_state() - Capture software state for register programming 3623 * @dc: DC context containing current display configuration 3624 * @state: Pointer to dc_register_software_state structure to populate 3625 * 3626 * Extracts all software state variables that are used to program hardware register 3627 * fields across the display driver pipeline. This provides a complete snapshot 3628 * of the software configuration that drives hardware register programming. 3629 * 3630 * The function traverses the DC context and extracts values from: 3631 * - Stream configurations (timing, format, DSC settings) 3632 * - Plane states (surface format, rotation, scaling, cursor) 3633 * - Pipe contexts (resource allocation, blending, viewport) 3634 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3635 * - Resource context (DET buffer allocation, ODM configuration) 3636 * 3637 * This is essential for underflow debugging as it captures the exact software 3638 * state that determines how registers are programmed, allowing analysis of 3639 * whether underflow is caused by incorrect register programming or timing issues. 3640 * 3641 * Return: true if state was successfully captured, false on error 3642 */ 3643 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3644 3645 /** 3646 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3647 * @dc: DC context containing current display configuration 3648 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3649 * 3650 * This function retrieves QoS metrics from the display core that can be used by 3651 * benchmark tools to analyze display system performance. The function may take 3652 * several milliseconds to execute due to hardware measurement requirements. 3653 * 3654 * QoS information includes: 3655 * - Bandwidth bounds (lower limits in Mbps) 3656 * - Latency bounds (upper limits in nanoseconds) 3657 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3658 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3659 * 3660 * The function will populate the provided dc_qos_info structure with current 3661 * QoS measurements. If hardware measurement functions are not available for 3662 * the current DCN version, the function returns false with zero'd info structure. 3663 * 3664 * Return: true if QoS information was successfully retrieved, false if measurement 3665 * functions are unavailable or hardware measurements cannot be performed 3666 */ 3667 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3668 3669 /** 3670 * dc_override_memory_bandwidth_request - Override the DCN nominal memory 3671 * bandwidth request sent to PMFW, independent of the current display mode. 3672 * For debug use only. 3673 * @dc: DC instance 3674 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override 3675 * 3676 * Return: capped bandwidth value actually applied (MB/s) 3677 */ 3678 unsigned int dc_override_memory_bandwidth_request( 3679 struct dc *dc, 3680 unsigned int bw_mbps); 3681 3682 #endif /* DC_INTERFACE_H_ */ 3683