1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.94" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 }; 100 101 // Color management caps (DPP and MPC) 102 struct rom_curve_caps { 103 uint16_t srgb : 1; 104 uint16_t bt2020 : 1; 105 uint16_t gamma2_2 : 1; 106 uint16_t pq : 1; 107 uint16_t hlg : 1; 108 }; 109 110 struct dpp_color_caps { 111 uint16_t dcn_arch : 1; // all DCE generations treated the same 112 // input lut is different than most LUTs, just plain 256-entry lookup 113 uint16_t input_lut_shared : 1; // shared with DGAM 114 uint16_t icsc : 1; 115 uint16_t dgam_ram : 1; 116 uint16_t post_csc : 1; // before gamut remap 117 uint16_t gamma_corr : 1; 118 119 // hdr_mult and gamut remap always available in DPP (in that order) 120 // 3d lut implies shaper LUT, 121 // it may be shared with MPC - check MPC:shared_3d_lut flag 122 uint16_t hw_3d_lut : 1; 123 uint16_t ogam_ram : 1; // blnd gam 124 uint16_t ocsc : 1; 125 struct rom_curve_caps dgam_rom_caps; 126 struct rom_curve_caps ogam_rom_caps; 127 }; 128 129 struct mpc_color_caps { 130 uint16_t gamut_remap : 1; 131 uint16_t ogam_ram : 1; 132 uint16_t ocsc : 1; 133 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 134 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 135 136 struct rom_curve_caps ogam_rom_caps; 137 }; 138 139 struct dc_color_caps { 140 struct dpp_color_caps dpp; 141 struct mpc_color_caps mpc; 142 }; 143 144 struct dc_caps { 145 uint32_t max_streams; 146 uint32_t max_links; 147 uint32_t max_audios; 148 uint32_t max_slave_planes; 149 uint32_t max_planes; 150 uint32_t max_downscale_ratio; 151 uint32_t i2c_speed_in_khz; 152 uint32_t dmdata_alloc_size; 153 unsigned int max_cursor_size; 154 unsigned int max_video_width; 155 int linear_pitch_alignment; 156 bool dcc_const_color; 157 bool dynamic_audio; 158 bool is_apu; 159 bool dual_link_dvi; 160 bool post_blend_color_processing; 161 bool force_dp_tps4_for_cp2520; 162 bool disable_dp_clk_share; 163 bool psp_setup_panel_mode; 164 bool extended_aux_timeout_support; 165 bool dmcub_support; 166 enum dp_protocol_version max_dp_protocol_version; 167 struct dc_plane_cap planes[MAX_PLANES]; 168 struct dc_color_caps color; 169 }; 170 171 struct dc_bug_wa { 172 bool no_connect_phy_config; 173 bool dedcn20_305_wa; 174 bool skip_clock_update; 175 bool lt_early_cr_pattern; 176 }; 177 178 struct dc_dcc_surface_param { 179 struct dc_size surface_size; 180 enum surface_pixel_format format; 181 enum swizzle_mode_values swizzle_mode; 182 enum dc_scan_direction scan; 183 }; 184 185 struct dc_dcc_setting { 186 unsigned int max_compressed_blk_size; 187 unsigned int max_uncompressed_blk_size; 188 bool independent_64b_blks; 189 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 190 //These bitfields to be used starting with DCN 3.0 191 struct { 192 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 193 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 194 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 195 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 196 } dcc_controls; 197 #endif 198 }; 199 200 struct dc_surface_dcc_cap { 201 union { 202 struct { 203 struct dc_dcc_setting rgb; 204 } grph; 205 206 struct { 207 struct dc_dcc_setting luma; 208 struct dc_dcc_setting chroma; 209 } video; 210 }; 211 212 bool capable; 213 bool const_color_support; 214 }; 215 216 struct dc_static_screen_params { 217 struct { 218 bool force_trigger; 219 bool cursor_update; 220 bool surface_update; 221 bool overlay_update; 222 } triggers; 223 unsigned int num_frames; 224 }; 225 226 227 /* Surface update type is used by dc_update_surfaces_and_stream 228 * The update type is determined at the very beginning of the function based 229 * on parameters passed in and decides how much programming (or updating) is 230 * going to be done during the call. 231 * 232 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 233 * logical calculations or hardware register programming. This update MUST be 234 * ISR safe on windows. Currently fast update will only be used to flip surface 235 * address. 236 * 237 * UPDATE_TYPE_MED is used for slower updates which require significant hw 238 * re-programming however do not affect bandwidth consumption or clock 239 * requirements. At present, this is the level at which front end updates 240 * that do not require us to run bw_calcs happen. These are in/out transfer func 241 * updates, viewport offset changes, recout size changes and pixel depth changes. 242 * This update can be done at ISR, but we want to minimize how often this happens. 243 * 244 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 245 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 246 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 247 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 248 * a full update. This cannot be done at ISR level and should be a rare event. 249 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 250 * underscan we don't expect to see this call at all. 251 */ 252 253 enum surface_update_type { 254 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 255 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 256 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 257 }; 258 259 /* Forward declaration*/ 260 struct dc; 261 struct dc_plane_state; 262 struct dc_state; 263 264 265 struct dc_cap_funcs { 266 bool (*get_dcc_compression_cap)(const struct dc *dc, 267 const struct dc_dcc_surface_param *input, 268 struct dc_surface_dcc_cap *output); 269 }; 270 271 struct link_training_settings; 272 273 274 /* Structure to hold configuration flags set by dm at dc creation. */ 275 struct dc_config { 276 bool gpu_vm_support; 277 bool disable_disp_pll_sharing; 278 bool fbc_support; 279 bool optimize_edp_link_rate; 280 bool disable_fractional_pwm; 281 bool allow_seamless_boot_optimization; 282 bool power_down_display_on_boot; 283 bool edp_not_connected; 284 bool force_enum_edp; 285 bool forced_clocks; 286 bool allow_lttpr_non_transparent_mode; 287 bool multi_mon_pp_mclk_switch; 288 bool disable_dmcu; 289 bool enable_4to1MPC; 290 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 291 bool clamp_min_dcfclk; 292 #endif 293 }; 294 295 enum visual_confirm { 296 VISUAL_CONFIRM_DISABLE = 0, 297 VISUAL_CONFIRM_SURFACE = 1, 298 VISUAL_CONFIRM_HDR = 2, 299 VISUAL_CONFIRM_MPCTREE = 4, 300 VISUAL_CONFIRM_PSR = 5, 301 }; 302 303 enum dcc_option { 304 DCC_ENABLE = 0, 305 DCC_DISABLE = 1, 306 DCC_HALF_REQ_DISALBE = 2, 307 }; 308 309 enum pipe_split_policy { 310 MPC_SPLIT_DYNAMIC = 0, 311 MPC_SPLIT_AVOID = 1, 312 MPC_SPLIT_AVOID_MULT_DISP = 2, 313 }; 314 315 enum wm_report_mode { 316 WM_REPORT_DEFAULT = 0, 317 WM_REPORT_OVERRIDE = 1, 318 }; 319 enum dtm_pstate{ 320 dtm_level_p0 = 0,/*highest voltage*/ 321 dtm_level_p1, 322 dtm_level_p2, 323 dtm_level_p3, 324 dtm_level_p4,/*when active_display_count = 0*/ 325 }; 326 327 enum dcn_pwr_state { 328 DCN_PWR_STATE_UNKNOWN = -1, 329 DCN_PWR_STATE_MISSION_MODE = 0, 330 DCN_PWR_STATE_LOW_POWER = 3, 331 }; 332 333 /* 334 * For any clocks that may differ per pipe 335 * only the max is stored in this structure 336 */ 337 struct dc_clocks { 338 int dispclk_khz; 339 int dppclk_khz; 340 int disp_dpp_voltage_level_khz; 341 int dcfclk_khz; 342 int socclk_khz; 343 int dcfclk_deep_sleep_khz; 344 int fclk_khz; 345 int phyclk_khz; 346 int dramclk_khz; 347 bool p_state_change_support; 348 enum dcn_pwr_state pwr_state; 349 /* 350 * Elements below are not compared for the purposes of 351 * optimization required 352 */ 353 bool prev_p_state_change_support; 354 enum dtm_pstate dtm_level; 355 int max_supported_dppclk_khz; 356 int max_supported_dispclk_khz; 357 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 358 int bw_dispclk_khz; 359 }; 360 361 struct dc_bw_validation_profile { 362 bool enable; 363 364 unsigned long long total_ticks; 365 unsigned long long voltage_level_ticks; 366 unsigned long long watermark_ticks; 367 unsigned long long rq_dlg_ticks; 368 369 unsigned long long total_count; 370 unsigned long long skip_fast_count; 371 unsigned long long skip_pass_count; 372 unsigned long long skip_fail_count; 373 }; 374 375 #define BW_VAL_TRACE_SETUP() \ 376 unsigned long long end_tick = 0; \ 377 unsigned long long voltage_level_tick = 0; \ 378 unsigned long long watermark_tick = 0; \ 379 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 380 dm_get_timestamp(dc->ctx) : 0 381 382 #define BW_VAL_TRACE_COUNT() \ 383 if (dc->debug.bw_val_profile.enable) \ 384 dc->debug.bw_val_profile.total_count++ 385 386 #define BW_VAL_TRACE_SKIP(status) \ 387 if (dc->debug.bw_val_profile.enable) { \ 388 if (!voltage_level_tick) \ 389 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 390 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 391 } 392 393 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 394 if (dc->debug.bw_val_profile.enable) \ 395 voltage_level_tick = dm_get_timestamp(dc->ctx) 396 397 #define BW_VAL_TRACE_END_WATERMARKS() \ 398 if (dc->debug.bw_val_profile.enable) \ 399 watermark_tick = dm_get_timestamp(dc->ctx) 400 401 #define BW_VAL_TRACE_FINISH() \ 402 if (dc->debug.bw_val_profile.enable) { \ 403 end_tick = dm_get_timestamp(dc->ctx); \ 404 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 405 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 406 if (watermark_tick) { \ 407 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 408 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 409 } \ 410 } 411 412 struct dc_debug_options { 413 enum visual_confirm visual_confirm; 414 bool sanity_checks; 415 bool max_disp_clk; 416 bool surface_trace; 417 bool timing_trace; 418 bool clock_trace; 419 bool validation_trace; 420 bool bandwidth_calcs_trace; 421 int max_downscale_src_width; 422 423 /* stutter efficiency related */ 424 bool disable_stutter; 425 bool use_max_lb; 426 enum dcc_option disable_dcc; 427 enum pipe_split_policy pipe_split_policy; 428 bool force_single_disp_pipe_split; 429 bool voltage_align_fclk; 430 431 bool disable_dfs_bypass; 432 bool disable_dpp_power_gate; 433 bool disable_hubp_power_gate; 434 bool disable_dsc_power_gate; 435 int dsc_min_slice_height_override; 436 int dsc_bpp_increment_div; 437 bool native422_support; 438 bool disable_pplib_wm_range; 439 enum wm_report_mode pplib_wm_report_mode; 440 unsigned int min_disp_clk_khz; 441 unsigned int min_dpp_clk_khz; 442 int sr_exit_time_dpm0_ns; 443 int sr_enter_plus_exit_time_dpm0_ns; 444 int sr_exit_time_ns; 445 int sr_enter_plus_exit_time_ns; 446 int urgent_latency_ns; 447 uint32_t underflow_assert_delay_us; 448 int percent_of_ideal_drambw; 449 int dram_clock_change_latency_ns; 450 bool optimized_watermark; 451 int always_scale; 452 bool disable_pplib_clock_request; 453 bool disable_clock_gate; 454 bool disable_mem_low_power; 455 bool disable_dmcu; 456 bool disable_psr; 457 bool force_abm_enable; 458 bool disable_stereo_support; 459 bool vsr_support; 460 bool performance_trace; 461 bool az_endpoint_mute_only; 462 bool always_use_regamma; 463 bool p010_mpo_support; 464 bool recovery_enabled; 465 bool avoid_vbios_exec_table; 466 bool scl_reset_length10; 467 bool hdmi20_disable; 468 bool skip_detection_link_training; 469 bool edid_read_retry_times; 470 bool remove_disconnect_edp; 471 unsigned int force_odm_combine; //bit vector based on otg inst 472 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 473 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 474 #endif 475 unsigned int force_fclk_khz; 476 bool disable_tri_buf; 477 bool dmub_offload_enabled; 478 bool dmcub_emulation; 479 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 480 bool disable_idle_power_optimizations; 481 #endif 482 bool dmub_command_table; /* for testing only */ 483 struct dc_bw_validation_profile bw_val_profile; 484 bool disable_fec; 485 bool disable_48mhz_pwrdwn; 486 /* This forces a hard min on the DCFCLK requested to SMU/PP 487 * watermarks are not affected. 488 */ 489 unsigned int force_min_dcfclk_mhz; 490 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 491 int dwb_fi_phase; 492 #endif 493 bool disable_timing_sync; 494 bool cm_in_bypass; 495 int force_clock_mode;/*every mode change.*/ 496 497 bool disable_dram_clock_change_vactive_support; 498 bool validate_dml_output; 499 bool enable_dmcub_surface_flip; 500 bool usbc_combo_phy_reset_wa; 501 bool disable_dsc; 502 bool enable_dram_clock_change_one_display_vactive; 503 }; 504 505 struct dc_debug_data { 506 uint32_t ltFailCount; 507 uint32_t i2cErrorCount; 508 uint32_t auxErrorCount; 509 }; 510 511 struct dc_phy_addr_space_config { 512 struct { 513 uint64_t start_addr; 514 uint64_t end_addr; 515 uint64_t fb_top; 516 uint64_t fb_offset; 517 uint64_t fb_base; 518 uint64_t agp_top; 519 uint64_t agp_bot; 520 uint64_t agp_base; 521 } system_aperture; 522 523 struct { 524 uint64_t page_table_start_addr; 525 uint64_t page_table_end_addr; 526 uint64_t page_table_base_addr; 527 } gart_config; 528 529 bool valid; 530 bool is_hvm_enabled; 531 uint64_t page_table_default_page_addr; 532 }; 533 534 struct dc_virtual_addr_space_config { 535 uint64_t page_table_base_addr; 536 uint64_t page_table_start_addr; 537 uint64_t page_table_end_addr; 538 uint32_t page_table_block_size_in_bytes; 539 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 540 }; 541 542 struct dc_bounding_box_overrides { 543 int sr_exit_time_ns; 544 int sr_enter_plus_exit_time_ns; 545 int urgent_latency_ns; 546 int percent_of_ideal_drambw; 547 int dram_clock_change_latency_ns; 548 int dummy_clock_change_latency_ns; 549 /* This forces a hard min on the DCFCLK we use 550 * for DML. Unlike the debug option for forcing 551 * DCFCLK, this override affects watermark calculations 552 */ 553 int min_dcfclk_mhz; 554 }; 555 556 struct dc_state; 557 struct resource_pool; 558 struct dce_hwseq; 559 struct gpu_info_soc_bounding_box_v1_0; 560 struct dc { 561 struct dc_versions versions; 562 struct dc_caps caps; 563 struct dc_cap_funcs cap_funcs; 564 struct dc_config config; 565 struct dc_debug_options debug; 566 struct dc_bounding_box_overrides bb_overrides; 567 struct dc_bug_wa work_arounds; 568 struct dc_context *ctx; 569 struct dc_phy_addr_space_config vm_pa_config; 570 571 uint8_t link_count; 572 struct dc_link *links[MAX_PIPES * 2]; 573 574 struct dc_state *current_state; 575 struct resource_pool *res_pool; 576 577 struct clk_mgr *clk_mgr; 578 579 /* Display Engine Clock levels */ 580 struct dm_pp_clock_levels sclk_lvls; 581 582 /* Inputs into BW and WM calculations. */ 583 struct bw_calcs_dceip *bw_dceip; 584 struct bw_calcs_vbios *bw_vbios; 585 #ifdef CONFIG_DRM_AMD_DC_DCN 586 struct dcn_soc_bounding_box *dcn_soc; 587 struct dcn_ip_params *dcn_ip; 588 struct display_mode_lib dml; 589 #endif 590 591 /* HW functions */ 592 struct hw_sequencer_funcs hwss; 593 struct dce_hwseq *hwseq; 594 595 /* Require to optimize clocks and bandwidth for added/removed planes */ 596 bool optimized_required; 597 bool wm_optimized_required; 598 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 599 bool idle_optimizations_allowed; 600 #endif 601 602 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 603 int optimize_seamless_boot_streams; 604 605 /* FBC compressor */ 606 struct compressor *fbc_compressor; 607 608 struct dc_debug_data debug_data; 609 struct dpcd_vendor_signature vendor_signature; 610 611 const char *build_id; 612 struct vm_helper *vm_helper; 613 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 614 }; 615 616 enum frame_buffer_mode { 617 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 618 FRAME_BUFFER_MODE_ZFB_ONLY, 619 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 620 } ; 621 622 struct dchub_init_data { 623 int64_t zfb_phys_addr_base; 624 int64_t zfb_mc_base_addr; 625 uint64_t zfb_size_in_byte; 626 enum frame_buffer_mode fb_mode; 627 bool dchub_initialzied; 628 bool dchub_info_valid; 629 }; 630 631 struct dc_init_data { 632 struct hw_asic_id asic_id; 633 void *driver; /* ctx */ 634 struct cgs_device *cgs_device; 635 struct dc_bounding_box_overrides bb_overrides; 636 637 int num_virtual_links; 638 /* 639 * If 'vbios_override' not NULL, it will be called instead 640 * of the real VBIOS. Intended use is Diagnostics on FPGA. 641 */ 642 struct dc_bios *vbios_override; 643 enum dce_environment dce_environment; 644 645 struct dmub_offload_funcs *dmub_if; 646 struct dc_reg_helper_state *dmub_offload; 647 648 struct dc_config flags; 649 uint64_t log_mask; 650 651 /** 652 * gpu_info FW provided soc bounding box struct or 0 if not 653 * available in FW 654 */ 655 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 656 struct dpcd_vendor_signature vendor_signature; 657 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 658 bool force_smu_not_present; 659 #endif 660 }; 661 662 struct dc_callback_init { 663 #ifdef CONFIG_DRM_AMD_DC_HDCP 664 struct cp_psp cp_psp; 665 #else 666 uint8_t reserved; 667 #endif 668 }; 669 670 struct dc *dc_create(const struct dc_init_data *init_params); 671 void dc_hardware_init(struct dc *dc); 672 673 int dc_get_vmid_use_vector(struct dc *dc); 674 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 675 /* Returns the number of vmids supported */ 676 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 677 void dc_init_callbacks(struct dc *dc, 678 const struct dc_callback_init *init_params); 679 void dc_deinit_callbacks(struct dc *dc); 680 void dc_destroy(struct dc **dc); 681 682 /******************************************************************************* 683 * Surface Interfaces 684 ******************************************************************************/ 685 686 enum { 687 TRANSFER_FUNC_POINTS = 1025 688 }; 689 690 struct dc_hdr_static_metadata { 691 /* display chromaticities and white point in units of 0.00001 */ 692 unsigned int chromaticity_green_x; 693 unsigned int chromaticity_green_y; 694 unsigned int chromaticity_blue_x; 695 unsigned int chromaticity_blue_y; 696 unsigned int chromaticity_red_x; 697 unsigned int chromaticity_red_y; 698 unsigned int chromaticity_white_point_x; 699 unsigned int chromaticity_white_point_y; 700 701 uint32_t min_luminance; 702 uint32_t max_luminance; 703 uint32_t maximum_content_light_level; 704 uint32_t maximum_frame_average_light_level; 705 }; 706 707 enum dc_transfer_func_type { 708 TF_TYPE_PREDEFINED, 709 TF_TYPE_DISTRIBUTED_POINTS, 710 TF_TYPE_BYPASS, 711 TF_TYPE_HWPWL 712 }; 713 714 struct dc_transfer_func_distributed_points { 715 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 716 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 717 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 718 719 uint16_t end_exponent; 720 uint16_t x_point_at_y1_red; 721 uint16_t x_point_at_y1_green; 722 uint16_t x_point_at_y1_blue; 723 }; 724 725 enum dc_transfer_func_predefined { 726 TRANSFER_FUNCTION_SRGB, 727 TRANSFER_FUNCTION_BT709, 728 TRANSFER_FUNCTION_PQ, 729 TRANSFER_FUNCTION_LINEAR, 730 TRANSFER_FUNCTION_UNITY, 731 TRANSFER_FUNCTION_HLG, 732 TRANSFER_FUNCTION_HLG12, 733 TRANSFER_FUNCTION_GAMMA22, 734 TRANSFER_FUNCTION_GAMMA24, 735 TRANSFER_FUNCTION_GAMMA26 736 }; 737 738 739 struct dc_transfer_func { 740 struct kref refcount; 741 enum dc_transfer_func_type type; 742 enum dc_transfer_func_predefined tf; 743 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 744 uint32_t sdr_ref_white_level; 745 struct dc_context *ctx; 746 union { 747 struct pwl_params pwl; 748 struct dc_transfer_func_distributed_points tf_pts; 749 }; 750 }; 751 752 753 union dc_3dlut_state { 754 struct { 755 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 756 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 757 uint32_t rmu_mux_num:3; /*index of mux to use*/ 758 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 759 uint32_t mpc_rmu1_mux:4; 760 uint32_t mpc_rmu2_mux:4; 761 uint32_t reserved:15; 762 } bits; 763 uint32_t raw; 764 }; 765 766 767 struct dc_3dlut { 768 struct kref refcount; 769 struct tetrahedral_params lut_3d; 770 struct fixed31_32 hdr_multiplier; 771 union dc_3dlut_state state; 772 struct dc_context *ctx; 773 }; 774 /* 775 * This structure is filled in by dc_surface_get_status and contains 776 * the last requested address and the currently active address so the called 777 * can determine if there are any outstanding flips 778 */ 779 struct dc_plane_status { 780 struct dc_plane_address requested_address; 781 struct dc_plane_address current_address; 782 bool is_flip_pending; 783 bool is_right_eye; 784 }; 785 786 union surface_update_flags { 787 788 struct { 789 uint32_t addr_update:1; 790 /* Medium updates */ 791 uint32_t dcc_change:1; 792 uint32_t color_space_change:1; 793 uint32_t horizontal_mirror_change:1; 794 uint32_t per_pixel_alpha_change:1; 795 uint32_t global_alpha_change:1; 796 uint32_t hdr_mult:1; 797 uint32_t rotation_change:1; 798 uint32_t swizzle_change:1; 799 uint32_t scaling_change:1; 800 uint32_t position_change:1; 801 uint32_t in_transfer_func_change:1; 802 uint32_t input_csc_change:1; 803 uint32_t coeff_reduction_change:1; 804 uint32_t output_tf_change:1; 805 uint32_t pixel_format_change:1; 806 uint32_t plane_size_change:1; 807 uint32_t gamut_remap_change:1; 808 809 /* Full updates */ 810 uint32_t new_plane:1; 811 uint32_t bpp_change:1; 812 uint32_t gamma_change:1; 813 uint32_t bandwidth_change:1; 814 uint32_t clock_change:1; 815 uint32_t stereo_format_change:1; 816 uint32_t full_update:1; 817 } bits; 818 819 uint32_t raw; 820 }; 821 822 struct dc_plane_state { 823 struct dc_plane_address address; 824 struct dc_plane_flip_time time; 825 bool triplebuffer_flips; 826 struct scaling_taps scaling_quality; 827 struct rect src_rect; 828 struct rect dst_rect; 829 struct rect clip_rect; 830 831 struct plane_size plane_size; 832 union dc_tiling_info tiling_info; 833 834 struct dc_plane_dcc_param dcc; 835 836 struct dc_gamma *gamma_correction; 837 struct dc_transfer_func *in_transfer_func; 838 struct dc_bias_and_scale *bias_and_scale; 839 struct dc_csc_transform input_csc_color_matrix; 840 struct fixed31_32 coeff_reduction_factor; 841 struct fixed31_32 hdr_mult; 842 struct colorspace_transform gamut_remap_matrix; 843 844 // TODO: No longer used, remove 845 struct dc_hdr_static_metadata hdr_static_ctx; 846 847 enum dc_color_space color_space; 848 849 struct dc_3dlut *lut3d_func; 850 struct dc_transfer_func *in_shaper_func; 851 struct dc_transfer_func *blend_tf; 852 853 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 854 struct dc_transfer_func *gamcor_tf; 855 #endif 856 enum surface_pixel_format format; 857 enum dc_rotation_angle rotation; 858 enum plane_stereo_format stereo_format; 859 860 bool is_tiling_rotated; 861 bool per_pixel_alpha; 862 bool global_alpha; 863 int global_alpha_value; 864 bool visible; 865 bool flip_immediate; 866 bool horizontal_mirror; 867 int layer_index; 868 869 union surface_update_flags update_flags; 870 /* private to DC core */ 871 struct dc_plane_status status; 872 struct dc_context *ctx; 873 874 /* HACK: Workaround for forcing full reprogramming under some conditions */ 875 bool force_full_update; 876 877 /* private to dc_surface.c */ 878 enum dc_irq_source irq_source; 879 struct kref refcount; 880 }; 881 882 struct dc_plane_info { 883 struct plane_size plane_size; 884 union dc_tiling_info tiling_info; 885 struct dc_plane_dcc_param dcc; 886 enum surface_pixel_format format; 887 enum dc_rotation_angle rotation; 888 enum plane_stereo_format stereo_format; 889 enum dc_color_space color_space; 890 bool horizontal_mirror; 891 bool visible; 892 bool per_pixel_alpha; 893 bool global_alpha; 894 int global_alpha_value; 895 bool input_csc_enabled; 896 int layer_index; 897 }; 898 899 struct dc_scaling_info { 900 struct rect src_rect; 901 struct rect dst_rect; 902 struct rect clip_rect; 903 struct scaling_taps scaling_quality; 904 }; 905 906 struct dc_surface_update { 907 struct dc_plane_state *surface; 908 909 /* isr safe update parameters. null means no updates */ 910 const struct dc_flip_addrs *flip_addr; 911 const struct dc_plane_info *plane_info; 912 const struct dc_scaling_info *scaling_info; 913 struct fixed31_32 hdr_mult; 914 /* following updates require alloc/sleep/spin that is not isr safe, 915 * null means no updates 916 */ 917 const struct dc_gamma *gamma; 918 const struct dc_transfer_func *in_transfer_func; 919 920 const struct dc_csc_transform *input_csc_color_matrix; 921 const struct fixed31_32 *coeff_reduction_factor; 922 const struct dc_transfer_func *func_shaper; 923 const struct dc_3dlut *lut3d_func; 924 const struct dc_transfer_func *blend_tf; 925 const struct colorspace_transform *gamut_remap_matrix; 926 }; 927 928 /* 929 * Create a new surface with default parameters; 930 */ 931 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 932 const struct dc_plane_status *dc_plane_get_status( 933 const struct dc_plane_state *plane_state); 934 935 void dc_plane_state_retain(struct dc_plane_state *plane_state); 936 void dc_plane_state_release(struct dc_plane_state *plane_state); 937 938 void dc_gamma_retain(struct dc_gamma *dc_gamma); 939 void dc_gamma_release(struct dc_gamma **dc_gamma); 940 struct dc_gamma *dc_create_gamma(void); 941 942 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 943 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 944 struct dc_transfer_func *dc_create_transfer_func(void); 945 946 struct dc_3dlut *dc_create_3dlut_func(void); 947 void dc_3dlut_func_release(struct dc_3dlut *lut); 948 void dc_3dlut_func_retain(struct dc_3dlut *lut); 949 /* 950 * This structure holds a surface address. There could be multiple addresses 951 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 952 * as frame durations and DCC format can also be set. 953 */ 954 struct dc_flip_addrs { 955 struct dc_plane_address address; 956 unsigned int flip_timestamp_in_us; 957 bool flip_immediate; 958 /* TODO: add flip duration for FreeSync */ 959 bool triplebuffer_flips; 960 }; 961 962 bool dc_post_update_surfaces_to_stream( 963 struct dc *dc); 964 965 #include "dc_stream.h" 966 967 /* 968 * Structure to store surface/stream associations for validation 969 */ 970 struct dc_validation_set { 971 struct dc_stream_state *stream; 972 struct dc_plane_state *plane_states[MAX_SURFACES]; 973 uint8_t plane_count; 974 }; 975 976 bool dc_validate_seamless_boot_timing(const struct dc *dc, 977 const struct dc_sink *sink, 978 struct dc_crtc_timing *crtc_timing); 979 980 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 981 982 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 983 984 bool dc_set_generic_gpio_for_stereo(bool enable, 985 struct gpio_service *gpio_service); 986 987 /* 988 * fast_validate: we return after determining if we can support the new state, 989 * but before we populate the programming info 990 */ 991 enum dc_status dc_validate_global_state( 992 struct dc *dc, 993 struct dc_state *new_ctx, 994 bool fast_validate); 995 996 997 void dc_resource_state_construct( 998 const struct dc *dc, 999 struct dc_state *dst_ctx); 1000 1001 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1002 bool dc_acquire_release_mpc_3dlut( 1003 struct dc *dc, bool acquire, 1004 struct dc_stream_state *stream, 1005 struct dc_3dlut **lut, 1006 struct dc_transfer_func **shaper); 1007 #endif 1008 1009 void dc_resource_state_copy_construct( 1010 const struct dc_state *src_ctx, 1011 struct dc_state *dst_ctx); 1012 1013 void dc_resource_state_copy_construct_current( 1014 const struct dc *dc, 1015 struct dc_state *dst_ctx); 1016 1017 void dc_resource_state_destruct(struct dc_state *context); 1018 1019 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1020 1021 /* 1022 * TODO update to make it about validation sets 1023 * Set up streams and links associated to drive sinks 1024 * The streams parameter is an absolute set of all active streams. 1025 * 1026 * After this call: 1027 * Phy, Encoder, Timing Generator are programmed and enabled. 1028 * New streams are enabled with blank stream; no memory read. 1029 */ 1030 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1031 1032 void dc_power_down_on_boot(struct dc *dc); 1033 1034 struct dc_state *dc_create_state(struct dc *dc); 1035 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1036 void dc_retain_state(struct dc_state *context); 1037 void dc_release_state(struct dc_state *context); 1038 1039 /******************************************************************************* 1040 * Link Interfaces 1041 ******************************************************************************/ 1042 1043 struct dpcd_caps { 1044 union dpcd_rev dpcd_rev; 1045 union max_lane_count max_ln_count; 1046 union max_down_spread max_down_spread; 1047 union dprx_feature dprx_feature; 1048 1049 /* valid only for eDP v1.4 or higher*/ 1050 uint8_t edp_supported_link_rates_count; 1051 enum dc_link_rate edp_supported_link_rates[8]; 1052 1053 /* dongle type (DP converter, CV smart dongle) */ 1054 enum display_dongle_type dongle_type; 1055 /* branch device or sink device */ 1056 bool is_branch_dev; 1057 /* Dongle's downstream count. */ 1058 union sink_count sink_count; 1059 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1060 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1061 struct dc_dongle_caps dongle_caps; 1062 1063 uint32_t sink_dev_id; 1064 int8_t sink_dev_id_str[6]; 1065 int8_t sink_hw_revision; 1066 int8_t sink_fw_revision[2]; 1067 1068 uint32_t branch_dev_id; 1069 int8_t branch_dev_name[6]; 1070 int8_t branch_hw_revision; 1071 int8_t branch_fw_revision[2]; 1072 1073 bool allow_invalid_MSA_timing_param; 1074 bool panel_mode_edp; 1075 bool dpcd_display_control_capable; 1076 bool ext_receiver_cap_field_present; 1077 union dpcd_fec_capability fec_cap; 1078 struct dpcd_dsc_capabilities dsc_caps; 1079 struct dc_lttpr_caps lttpr_caps; 1080 struct psr_caps psr_caps; 1081 1082 }; 1083 1084 union dpcd_sink_ext_caps { 1085 struct { 1086 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1087 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1088 */ 1089 uint8_t sdr_aux_backlight_control : 1; 1090 uint8_t hdr_aux_backlight_control : 1; 1091 uint8_t reserved_1 : 2; 1092 uint8_t oled : 1; 1093 uint8_t reserved : 3; 1094 } bits; 1095 uint8_t raw; 1096 }; 1097 1098 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1099 union hdcp_rx_caps { 1100 struct { 1101 uint8_t version; 1102 uint8_t reserved; 1103 struct { 1104 uint8_t repeater : 1; 1105 uint8_t hdcp_capable : 1; 1106 uint8_t reserved : 6; 1107 } byte0; 1108 } fields; 1109 uint8_t raw[3]; 1110 }; 1111 1112 union hdcp_bcaps { 1113 struct { 1114 uint8_t HDCP_CAPABLE:1; 1115 uint8_t REPEATER:1; 1116 uint8_t RESERVED:6; 1117 } bits; 1118 uint8_t raw; 1119 }; 1120 1121 struct hdcp_caps { 1122 union hdcp_rx_caps rx_caps; 1123 union hdcp_bcaps bcaps; 1124 }; 1125 #endif 1126 1127 #include "dc_link.h" 1128 1129 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1130 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1131 1132 #endif 1133 /******************************************************************************* 1134 * Sink Interfaces - A sink corresponds to a display output device 1135 ******************************************************************************/ 1136 1137 struct dc_container_id { 1138 // 128bit GUID in binary form 1139 unsigned char guid[16]; 1140 // 8 byte port ID -> ELD.PortID 1141 unsigned int portId[2]; 1142 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1143 unsigned short manufacturerName; 1144 // 2 byte product code -> ELD.ProductCode 1145 unsigned short productCode; 1146 }; 1147 1148 1149 struct dc_sink_dsc_caps { 1150 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1151 // 'false' if they are sink's DSC caps 1152 bool is_virtual_dpcd_dsc; 1153 struct dsc_dec_dpcd_caps dsc_dec_caps; 1154 }; 1155 1156 struct dc_sink_fec_caps { 1157 bool is_rx_fec_supported; 1158 bool is_topology_fec_supported; 1159 }; 1160 1161 /* 1162 * The sink structure contains EDID and other display device properties 1163 */ 1164 struct dc_sink { 1165 enum signal_type sink_signal; 1166 struct dc_edid dc_edid; /* raw edid */ 1167 struct dc_edid_caps edid_caps; /* parse display caps */ 1168 struct dc_container_id *dc_container_id; 1169 uint32_t dongle_max_pix_clk; 1170 void *priv; 1171 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1172 bool converter_disable_audio; 1173 bool is_mst_legacy; 1174 struct dc_sink_dsc_caps dsc_caps; 1175 struct dc_sink_fec_caps fec_caps; 1176 1177 bool is_vsc_sdp_colorimetry_supported; 1178 1179 /* private to DC core */ 1180 struct dc_link *link; 1181 struct dc_context *ctx; 1182 1183 uint32_t sink_id; 1184 1185 /* private to dc_sink.c */ 1186 // refcount must be the last member in dc_sink, since we want the 1187 // sink structure to be logically cloneable up to (but not including) 1188 // refcount 1189 struct kref refcount; 1190 }; 1191 1192 void dc_sink_retain(struct dc_sink *sink); 1193 void dc_sink_release(struct dc_sink *sink); 1194 1195 struct dc_sink_init_data { 1196 enum signal_type sink_signal; 1197 struct dc_link *link; 1198 uint32_t dongle_max_pix_clk; 1199 bool converter_disable_audio; 1200 bool sink_is_legacy; 1201 }; 1202 1203 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1204 1205 /* Newer interfaces */ 1206 struct dc_cursor { 1207 struct dc_plane_address address; 1208 struct dc_cursor_attributes attributes; 1209 }; 1210 1211 1212 /******************************************************************************* 1213 * Interrupt interfaces 1214 ******************************************************************************/ 1215 enum dc_irq_source dc_interrupt_to_irq_source( 1216 struct dc *dc, 1217 uint32_t src_id, 1218 uint32_t ext_id); 1219 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1220 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1221 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1222 struct dc *dc, uint32_t link_index); 1223 1224 /******************************************************************************* 1225 * Power Interfaces 1226 ******************************************************************************/ 1227 1228 void dc_set_power_state( 1229 struct dc *dc, 1230 enum dc_acpi_cm_power_state power_state); 1231 void dc_resume(struct dc *dc); 1232 1233 void dc_power_down_on_boot(struct dc *dc); 1234 1235 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1236 /* 1237 * HDCP Interfaces 1238 */ 1239 enum hdcp_message_status dc_process_hdcp_msg( 1240 enum signal_type signal, 1241 struct dc_link *link, 1242 struct hdcp_protection_message *message_info); 1243 #endif 1244 bool dc_is_dmcu_initialized(struct dc *dc); 1245 1246 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1247 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1248 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1249 1250 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1251 1252 /* 1253 * blank all streams, and set min and max memory clock to 1254 * lowest and highest DPM level, respectively 1255 */ 1256 void dc_unlock_memory_clock_frequency(struct dc *dc); 1257 1258 /* 1259 * set min memory clock to the min required for current mode, 1260 * max to maxDPM, and unblank streams 1261 */ 1262 void dc_lock_memory_clock_frequency(struct dc *dc); 1263 1264 #endif 1265 /******************************************************************************* 1266 * DSC Interfaces 1267 ******************************************************************************/ 1268 #include "dc_dsc.h" 1269 #endif /* DC_INTERFACE_H_ */ 1270