1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "sspl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 58 #define DC_VER "3.2.349" 59 60 /** 61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 62 */ 63 #define MAX_SURFACES 4 64 /** 65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 66 */ 67 #define MAX_PLANES 6 68 #define MAX_STREAMS 6 69 #define MIN_VIEWPORT_SIZE 12 70 #define MAX_NUM_EDP 2 71 #define MAX_SUPPORTED_FORMATS 7 72 73 #define MAX_HOST_ROUTERS_NUM 3 74 #define MAX_DPIA_PER_HOST_ROUTER 3 75 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 76 77 /* Display Core Interfaces */ 78 struct dc_versions { 79 const char *dc_ver; 80 struct dmcu_version dmcu_version; 81 }; 82 83 enum dp_protocol_version { 84 DP_VERSION_1_4 = 0, 85 DP_VERSION_2_1, 86 DP_VERSION_UNKNOWN, 87 }; 88 89 enum dc_plane_type { 90 DC_PLANE_TYPE_INVALID, 91 DC_PLANE_TYPE_DCE_RGB, 92 DC_PLANE_TYPE_DCE_UNDERLAY, 93 DC_PLANE_TYPE_DCN_UNIVERSAL, 94 }; 95 96 // Sizes defined as multiples of 64KB 97 enum det_size { 98 DET_SIZE_DEFAULT = 0, 99 DET_SIZE_192KB = 3, 100 DET_SIZE_256KB = 4, 101 DET_SIZE_320KB = 5, 102 DET_SIZE_384KB = 6 103 }; 104 105 106 struct dc_plane_cap { 107 enum dc_plane_type type; 108 uint32_t per_pixel_alpha : 1; 109 struct { 110 uint32_t argb8888 : 1; 111 uint32_t nv12 : 1; 112 uint32_t fp16 : 1; 113 uint32_t p010 : 1; 114 uint32_t ayuv : 1; 115 } pixel_format_support; 116 // max upscaling factor x1000 117 // upscaling factors are always >= 1 118 // for example, 1080p -> 8K is 4.0, or 4000 raw value 119 struct { 120 uint32_t argb8888; 121 uint32_t nv12; 122 uint32_t fp16; 123 } max_upscale_factor; 124 // max downscale factor x1000 125 // downscale factors are always <= 1 126 // for example, 8K -> 1080p is 0.25, or 250 raw value 127 struct { 128 uint32_t argb8888; 129 uint32_t nv12; 130 uint32_t fp16; 131 } max_downscale_factor; 132 // minimal width/height 133 uint32_t min_width; 134 uint32_t min_height; 135 }; 136 137 /** 138 * DOC: color-management-caps 139 * 140 * **Color management caps (DPP and MPC)** 141 * 142 * Modules/color calculates various color operations which are translated to 143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 144 * DCN1, every new generation comes with fairly major differences in color 145 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 146 * decide mapping to HW block based on logical capabilities. 147 */ 148 149 /** 150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 151 * @srgb: RGB color space transfer func 152 * @bt2020: BT.2020 transfer func 153 * @gamma2_2: standard gamma 154 * @pq: perceptual quantizer transfer function 155 * @hlg: hybrid log–gamma transfer function 156 */ 157 struct rom_curve_caps { 158 uint16_t srgb : 1; 159 uint16_t bt2020 : 1; 160 uint16_t gamma2_2 : 1; 161 uint16_t pq : 1; 162 uint16_t hlg : 1; 163 }; 164 165 /** 166 * struct dpp_color_caps - color pipeline capabilities for display pipe and 167 * plane blocks 168 * 169 * @dcn_arch: all DCE generations treated the same 170 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 171 * just plain 256-entry lookup 172 * @icsc: input color space conversion 173 * @dgam_ram: programmable degamma LUT 174 * @post_csc: post color space conversion, before gamut remap 175 * @gamma_corr: degamma correction 176 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 177 * with MPC by setting mpc:shared_3d_lut flag 178 * @ogam_ram: programmable out/blend gamma LUT 179 * @ocsc: output color space conversion 180 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 181 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 182 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 183 * 184 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 185 */ 186 struct dpp_color_caps { 187 uint16_t dcn_arch : 1; 188 uint16_t input_lut_shared : 1; 189 uint16_t icsc : 1; 190 uint16_t dgam_ram : 1; 191 uint16_t post_csc : 1; 192 uint16_t gamma_corr : 1; 193 uint16_t hw_3d_lut : 1; 194 uint16_t ogam_ram : 1; 195 uint16_t ocsc : 1; 196 uint16_t dgam_rom_for_yuv : 1; 197 struct rom_curve_caps dgam_rom_caps; 198 struct rom_curve_caps ogam_rom_caps; 199 }; 200 201 /* Below structure is to describe the HW support for mem layout, extend support 202 range to match what OS could handle in the roadmap */ 203 struct lut3d_caps { 204 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 205 struct { 206 uint32_t swizzle_3d_rgb : 1; 207 uint32_t swizzle_3d_bgr : 1; 208 uint32_t linear_1d : 1; 209 } mem_layout_support; 210 struct { 211 uint32_t unorm_12msb : 1; 212 uint32_t unorm_12lsb : 1; 213 uint32_t float_fp1_5_10 : 1; 214 } mem_format_support; 215 struct { 216 uint32_t order_rgba : 1; 217 uint32_t order_bgra : 1; 218 } mem_pixel_order_support; 219 /*< size options are 9, 17, 33, 45, 65 */ 220 struct { 221 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 222 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 223 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 224 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 225 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 226 } lut_dim_caps; 227 }; 228 229 /** 230 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 231 * plane combined blocks 232 * 233 * @gamut_remap: color transformation matrix 234 * @ogam_ram: programmable out gamma LUT 235 * @ocsc: output color space conversion matrix 236 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 237 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 238 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 239 * instance 240 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 241 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 242 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 243 * @preblend: whether color manager supports preblend with MPC 244 */ 245 struct mpc_color_caps { 246 uint16_t gamut_remap : 1; 247 uint16_t ogam_ram : 1; 248 uint16_t ocsc : 1; 249 uint16_t num_3dluts : 3; 250 uint16_t num_rmcm_3dluts : 3; 251 uint16_t shared_3d_lut:1; 252 struct rom_curve_caps ogam_rom_caps; 253 struct lut3d_caps mcm_3d_lut_caps; 254 struct lut3d_caps rmcm_3d_lut_caps; 255 bool preblend; 256 }; 257 258 /** 259 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 260 * @dpp: color pipes caps for DPP 261 * @mpc: color pipes caps for MPC 262 */ 263 struct dc_color_caps { 264 struct dpp_color_caps dpp; 265 struct mpc_color_caps mpc; 266 }; 267 268 struct dc_dmub_caps { 269 bool psr; 270 bool mclk_sw; 271 bool subvp_psr; 272 bool gecc_enable; 273 uint8_t fams_ver; 274 bool aux_backlight_support; 275 }; 276 277 struct dc_scl_caps { 278 bool sharpener_support; 279 }; 280 281 struct dc_caps { 282 uint32_t max_streams; 283 uint32_t max_links; 284 uint32_t max_audios; 285 uint32_t max_slave_planes; 286 uint32_t max_slave_yuv_planes; 287 uint32_t max_slave_rgb_planes; 288 uint32_t max_planes; 289 uint32_t max_downscale_ratio; 290 uint32_t i2c_speed_in_khz; 291 uint32_t i2c_speed_in_khz_hdcp; 292 uint32_t dmdata_alloc_size; 293 unsigned int max_cursor_size; 294 unsigned int max_buffered_cursor_size; 295 unsigned int max_video_width; 296 /* 297 * max video plane width that can be safely assumed to be always 298 * supported by single DPP pipe. 299 */ 300 unsigned int max_optimizable_video_width; 301 unsigned int min_horizontal_blanking_period; 302 int linear_pitch_alignment; 303 bool dcc_const_color; 304 bool dynamic_audio; 305 bool is_apu; 306 bool dual_link_dvi; 307 bool post_blend_color_processing; 308 bool force_dp_tps4_for_cp2520; 309 bool disable_dp_clk_share; 310 bool psp_setup_panel_mode; 311 bool extended_aux_timeout_support; 312 bool dmcub_support; 313 bool zstate_support; 314 bool ips_support; 315 bool ips_v2_support; 316 uint32_t num_of_internal_disp; 317 enum dp_protocol_version max_dp_protocol_version; 318 unsigned int mall_size_per_mem_channel; 319 unsigned int mall_size_total; 320 unsigned int cursor_cache_size; 321 struct dc_plane_cap planes[MAX_PLANES]; 322 struct dc_color_caps color; 323 struct dc_dmub_caps dmub_caps; 324 bool dp_hpo; 325 bool dp_hdmi21_pcon_support; 326 bool edp_dsc_support; 327 bool vbios_lttpr_aware; 328 bool vbios_lttpr_enable; 329 bool fused_io_supported; 330 uint32_t max_otg_num; 331 uint32_t max_cab_allocation_bytes; 332 uint32_t cache_line_size; 333 uint32_t cache_num_ways; 334 uint16_t subvp_fw_processing_delay_us; 335 uint8_t subvp_drr_max_vblank_margin_us; 336 uint16_t subvp_prefetch_end_to_mall_start_us; 337 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 338 uint16_t subvp_pstate_allow_width_us; 339 uint16_t subvp_vertical_int_margin_us; 340 bool seamless_odm; 341 uint32_t max_v_total; 342 bool vtotal_limited_by_fp2; 343 uint32_t max_disp_clock_khz_at_vmin; 344 uint8_t subvp_drr_vblank_start_margin_us; 345 bool cursor_not_scaled; 346 bool dcmode_power_limits_present; 347 bool sequential_ono; 348 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 349 uint32_t dcc_plane_width_limit; 350 struct dc_scl_caps scl_caps; 351 uint8_t num_of_host_routers; 352 uint8_t num_of_dpias_per_host_router; 353 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 354 uint8_t max_odm_combine_factor; 355 }; 356 357 struct dc_bug_wa { 358 bool no_connect_phy_config; 359 bool dedcn20_305_wa; 360 bool skip_clock_update; 361 bool lt_early_cr_pattern; 362 struct { 363 uint8_t uclk : 1; 364 uint8_t fclk : 1; 365 uint8_t dcfclk : 1; 366 uint8_t dcfclk_ds: 1; 367 } clock_update_disable_mask; 368 bool skip_psr_ips_crtc_disable; 369 }; 370 struct dc_dcc_surface_param { 371 struct dc_size surface_size; 372 enum surface_pixel_format format; 373 unsigned int plane0_pitch; 374 struct dc_size plane1_size; 375 unsigned int plane1_pitch; 376 union { 377 enum swizzle_mode_values swizzle_mode; 378 enum swizzle_mode_addr3_values swizzle_mode_addr3; 379 }; 380 enum dc_scan_direction scan; 381 }; 382 383 struct dc_dcc_setting { 384 unsigned int max_compressed_blk_size; 385 unsigned int max_uncompressed_blk_size; 386 bool independent_64b_blks; 387 //These bitfields to be used starting with DCN 3.0 388 struct { 389 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 390 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 391 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 392 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 393 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 394 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 395 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 396 } dcc_controls; 397 }; 398 399 struct dc_surface_dcc_cap { 400 union { 401 struct { 402 struct dc_dcc_setting rgb; 403 } grph; 404 405 struct { 406 struct dc_dcc_setting luma; 407 struct dc_dcc_setting chroma; 408 } video; 409 }; 410 411 bool capable; 412 bool const_color_support; 413 }; 414 415 struct dc_static_screen_params { 416 struct { 417 bool force_trigger; 418 bool cursor_update; 419 bool surface_update; 420 bool overlay_update; 421 } triggers; 422 unsigned int num_frames; 423 }; 424 425 426 /* Surface update type is used by dc_update_surfaces_and_stream 427 * The update type is determined at the very beginning of the function based 428 * on parameters passed in and decides how much programming (or updating) is 429 * going to be done during the call. 430 * 431 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 432 * logical calculations or hardware register programming. This update MUST be 433 * ISR safe on windows. Currently fast update will only be used to flip surface 434 * address. 435 * 436 * UPDATE_TYPE_MED is used for slower updates which require significant hw 437 * re-programming however do not affect bandwidth consumption or clock 438 * requirements. At present, this is the level at which front end updates 439 * that do not require us to run bw_calcs happen. These are in/out transfer func 440 * updates, viewport offset changes, recout size changes and pixel depth changes. 441 * This update can be done at ISR, but we want to minimize how often this happens. 442 * 443 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 444 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 445 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 446 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 447 * a full update. This cannot be done at ISR level and should be a rare event. 448 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 449 * underscan we don't expect to see this call at all. 450 */ 451 452 enum surface_update_type { 453 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 454 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 455 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 456 }; 457 458 /* Forward declaration*/ 459 struct dc; 460 struct dc_plane_state; 461 struct dc_state; 462 463 struct dc_cap_funcs { 464 bool (*get_dcc_compression_cap)(const struct dc *dc, 465 const struct dc_dcc_surface_param *input, 466 struct dc_surface_dcc_cap *output); 467 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 468 }; 469 470 struct link_training_settings; 471 472 union allow_lttpr_non_transparent_mode { 473 struct { 474 bool DP1_4A : 1; 475 bool DP2_0 : 1; 476 } bits; 477 unsigned char raw; 478 }; 479 480 /* Structure to hold configuration flags set by dm at dc creation. */ 481 struct dc_config { 482 bool gpu_vm_support; 483 bool disable_disp_pll_sharing; 484 bool fbc_support; 485 bool disable_fractional_pwm; 486 bool allow_seamless_boot_optimization; 487 bool seamless_boot_edp_requested; 488 bool edp_not_connected; 489 bool edp_no_power_sequencing; 490 bool force_enum_edp; 491 bool forced_clocks; 492 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 493 bool multi_mon_pp_mclk_switch; 494 bool disable_dmcu; 495 bool enable_4to1MPC; 496 bool enable_windowed_mpo_odm; 497 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 498 uint32_t allow_edp_hotplug_detection; 499 bool skip_riommu_prefetch_wa; 500 bool clamp_min_dcfclk; 501 uint64_t vblank_alignment_dto_params; 502 uint8_t vblank_alignment_max_frame_time_diff; 503 bool is_asymmetric_memory; 504 bool is_single_rank_dimm; 505 bool is_vmin_only_asic; 506 bool use_spl; 507 bool prefer_easf; 508 bool use_pipe_ctx_sync_logic; 509 int smart_mux_version; 510 bool ignore_dpref_ss; 511 bool enable_mipi_converter_optimization; 512 bool use_default_clock_table; 513 bool force_bios_enable_lttpr; 514 uint8_t force_bios_fixed_vs; 515 int sdpif_request_limit_words_per_umc; 516 bool dc_mode_clk_limit_support; 517 bool EnableMinDispClkODM; 518 bool enable_auto_dpm_test_logs; 519 unsigned int disable_ips; 520 unsigned int disable_ips_rcg; 521 unsigned int disable_ips_in_vpb; 522 bool disable_ips_in_dpms_off; 523 bool usb4_bw_alloc_support; 524 bool allow_0_dtb_clk; 525 bool use_assr_psp_message; 526 bool support_edp0_on_dp1; 527 unsigned int enable_fpo_flicker_detection; 528 bool disable_hbr_audio_dp2; 529 bool consolidated_dpia_dp_lt; 530 bool set_pipe_unlock_order; 531 bool enable_dpia_pre_training; 532 bool unify_link_enc_assignment; 533 struct spl_sharpness_range dcn_sharpness_range; 534 struct spl_sharpness_range dcn_override_sharpness_range; 535 }; 536 537 enum visual_confirm { 538 VISUAL_CONFIRM_DISABLE = 0, 539 VISUAL_CONFIRM_SURFACE = 1, 540 VISUAL_CONFIRM_HDR = 2, 541 VISUAL_CONFIRM_MPCTREE = 4, 542 VISUAL_CONFIRM_PSR = 5, 543 VISUAL_CONFIRM_SWAPCHAIN = 6, 544 VISUAL_CONFIRM_FAMS = 7, 545 VISUAL_CONFIRM_SWIZZLE = 9, 546 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 547 VISUAL_CONFIRM_REPLAY = 12, 548 VISUAL_CONFIRM_SUBVP = 14, 549 VISUAL_CONFIRM_MCLK_SWITCH = 16, 550 VISUAL_CONFIRM_FAMS2 = 19, 551 VISUAL_CONFIRM_HW_CURSOR = 20, 552 VISUAL_CONFIRM_VABC = 21, 553 VISUAL_CONFIRM_DCC = 22, 554 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 555 }; 556 557 enum dc_psr_power_opts { 558 psr_power_opt_invalid = 0x0, 559 psr_power_opt_smu_opt_static_screen = 0x1, 560 psr_power_opt_z10_static_screen = 0x10, 561 psr_power_opt_ds_disable_allow = 0x100, 562 }; 563 564 enum dml_hostvm_override_opts { 565 DML_HOSTVM_NO_OVERRIDE = 0x0, 566 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 567 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 568 }; 569 570 enum dc_replay_power_opts { 571 replay_power_opt_invalid = 0x0, 572 replay_power_opt_smu_opt_static_screen = 0x1, 573 replay_power_opt_z10_static_screen = 0x10, 574 }; 575 576 enum dcc_option { 577 DCC_ENABLE = 0, 578 DCC_DISABLE = 1, 579 DCC_HALF_REQ_DISALBE = 2, 580 }; 581 582 enum in_game_fams_config { 583 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 584 INGAME_FAMS_DISABLE, // disable in-game fams 585 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 586 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 587 }; 588 589 /** 590 * enum pipe_split_policy - Pipe split strategy supported by DCN 591 * 592 * This enum is used to define the pipe split policy supported by DCN. By 593 * default, DC favors MPC_SPLIT_DYNAMIC. 594 */ 595 enum pipe_split_policy { 596 /** 597 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 598 * pipe in order to bring the best trade-off between performance and 599 * power consumption. This is the recommended option. 600 */ 601 MPC_SPLIT_DYNAMIC = 0, 602 603 /** 604 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 605 * try any sort of split optimization. 606 */ 607 MPC_SPLIT_AVOID = 1, 608 609 /** 610 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 611 * optimize the pipe utilization when using a single display; if the 612 * user connects to a second display, DC will avoid pipe split. 613 */ 614 MPC_SPLIT_AVOID_MULT_DISP = 2, 615 }; 616 617 enum wm_report_mode { 618 WM_REPORT_DEFAULT = 0, 619 WM_REPORT_OVERRIDE = 1, 620 }; 621 enum dtm_pstate{ 622 dtm_level_p0 = 0,/*highest voltage*/ 623 dtm_level_p1, 624 dtm_level_p2, 625 dtm_level_p3, 626 dtm_level_p4,/*when active_display_count = 0*/ 627 }; 628 629 enum dcn_pwr_state { 630 DCN_PWR_STATE_UNKNOWN = -1, 631 DCN_PWR_STATE_MISSION_MODE = 0, 632 DCN_PWR_STATE_LOW_POWER = 3, 633 }; 634 635 enum dcn_zstate_support_state { 636 DCN_ZSTATE_SUPPORT_UNKNOWN, 637 DCN_ZSTATE_SUPPORT_ALLOW, 638 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 639 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 640 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 641 DCN_ZSTATE_SUPPORT_DISALLOW, 642 }; 643 644 /* 645 * struct dc_clocks - DC pipe clocks 646 * 647 * For any clocks that may differ per pipe only the max is stored in this 648 * structure 649 */ 650 struct dc_clocks { 651 int dispclk_khz; 652 int actual_dispclk_khz; 653 int dppclk_khz; 654 int actual_dppclk_khz; 655 int disp_dpp_voltage_level_khz; 656 int dcfclk_khz; 657 int socclk_khz; 658 int dcfclk_deep_sleep_khz; 659 int fclk_khz; 660 int phyclk_khz; 661 int dramclk_khz; 662 bool p_state_change_support; 663 enum dcn_zstate_support_state zstate_support; 664 bool dtbclk_en; 665 int ref_dtbclk_khz; 666 bool fclk_p_state_change_support; 667 enum dcn_pwr_state pwr_state; 668 /* 669 * Elements below are not compared for the purposes of 670 * optimization required 671 */ 672 bool prev_p_state_change_support; 673 bool fclk_prev_p_state_change_support; 674 int num_ways; 675 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 676 677 /* 678 * @fw_based_mclk_switching 679 * 680 * DC has a mechanism that leverage the variable refresh rate to switch 681 * memory clock in cases that we have a large latency to achieve the 682 * memory clock change and a short vblank window. DC has some 683 * requirements to enable this feature, and this field describes if the 684 * system support or not such a feature. 685 */ 686 bool fw_based_mclk_switching; 687 bool fw_based_mclk_switching_shut_down; 688 int prev_num_ways; 689 enum dtm_pstate dtm_level; 690 int max_supported_dppclk_khz; 691 int max_supported_dispclk_khz; 692 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 693 int bw_dispclk_khz; 694 int idle_dramclk_khz; 695 int idle_fclk_khz; 696 int subvp_prefetch_dramclk_khz; 697 int subvp_prefetch_fclk_khz; 698 699 /* Stutter efficiency is technically not clock values 700 * but stored here so the values are part of the update_clocks call similar to num_ways 701 * Efficiencies are stored as percentage (0-100) 702 */ 703 struct { 704 uint8_t base_efficiency; //LP1 705 uint8_t low_power_efficiency; //LP2 706 } stutter_efficiency; 707 }; 708 709 struct dc_bw_validation_profile { 710 bool enable; 711 712 unsigned long long total_ticks; 713 unsigned long long voltage_level_ticks; 714 unsigned long long watermark_ticks; 715 unsigned long long rq_dlg_ticks; 716 717 unsigned long long total_count; 718 unsigned long long skip_fast_count; 719 unsigned long long skip_pass_count; 720 unsigned long long skip_fail_count; 721 }; 722 723 #define BW_VAL_TRACE_SETUP() \ 724 unsigned long long end_tick = 0; \ 725 unsigned long long voltage_level_tick = 0; \ 726 unsigned long long watermark_tick = 0; \ 727 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 728 dm_get_timestamp(dc->ctx) : 0 729 730 #define BW_VAL_TRACE_COUNT() \ 731 if (dc->debug.bw_val_profile.enable) \ 732 dc->debug.bw_val_profile.total_count++ 733 734 #define BW_VAL_TRACE_SKIP(status) \ 735 if (dc->debug.bw_val_profile.enable) { \ 736 if (!voltage_level_tick) \ 737 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 738 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 739 } 740 741 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 742 if (dc->debug.bw_val_profile.enable) \ 743 voltage_level_tick = dm_get_timestamp(dc->ctx) 744 745 #define BW_VAL_TRACE_END_WATERMARKS() \ 746 if (dc->debug.bw_val_profile.enable) \ 747 watermark_tick = dm_get_timestamp(dc->ctx) 748 749 #define BW_VAL_TRACE_FINISH() \ 750 if (dc->debug.bw_val_profile.enable) { \ 751 end_tick = dm_get_timestamp(dc->ctx); \ 752 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 753 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 754 if (watermark_tick) { \ 755 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 756 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 757 } \ 758 } 759 760 union mem_low_power_enable_options { 761 struct { 762 bool vga: 1; 763 bool i2c: 1; 764 bool dmcu: 1; 765 bool dscl: 1; 766 bool cm: 1; 767 bool mpc: 1; 768 bool optc: 1; 769 bool vpg: 1; 770 bool afmt: 1; 771 } bits; 772 uint32_t u32All; 773 }; 774 775 union root_clock_optimization_options { 776 struct { 777 bool dpp: 1; 778 bool dsc: 1; 779 bool hdmistream: 1; 780 bool hdmichar: 1; 781 bool dpstream: 1; 782 bool symclk32_se: 1; 783 bool symclk32_le: 1; 784 bool symclk_fe: 1; 785 bool physymclk: 1; 786 bool dpiasymclk: 1; 787 uint32_t reserved: 22; 788 } bits; 789 uint32_t u32All; 790 }; 791 792 union fine_grain_clock_gating_enable_options { 793 struct { 794 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 795 bool dchub : 1; /* Display controller hub */ 796 bool dchubbub : 1; 797 bool dpp : 1; /* Display pipes and planes */ 798 bool opp : 1; /* Output pixel processing */ 799 bool optc : 1; /* Output pipe timing combiner */ 800 bool dio : 1; /* Display output */ 801 bool dwb : 1; /* Display writeback */ 802 bool mmhubbub : 1; /* Multimedia hub */ 803 bool dmu : 1; /* Display core management unit */ 804 bool az : 1; /* Azalia */ 805 bool dchvm : 1; 806 bool dsc : 1; /* Display stream compression */ 807 808 uint32_t reserved : 19; 809 } bits; 810 uint32_t u32All; 811 }; 812 813 enum pg_hw_pipe_resources { 814 PG_HUBP = 0, 815 PG_DPP, 816 PG_DSC, 817 PG_MPCC, 818 PG_OPP, 819 PG_OPTC, 820 PG_DPSTREAM, 821 PG_HDMISTREAM, 822 PG_PHYSYMCLK, 823 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 824 }; 825 826 enum pg_hw_resources { 827 PG_DCCG = 0, 828 PG_DCIO, 829 PG_DIO, 830 PG_DCHUBBUB, 831 PG_DCHVM, 832 PG_DWB, 833 PG_HPO, 834 PG_DCOH, 835 PG_HW_RESOURCES_NUM_ELEMENT 836 }; 837 838 struct pg_block_update { 839 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 840 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 841 }; 842 843 union dpia_debug_options { 844 struct { 845 uint32_t disable_dpia:1; /* bit 0 */ 846 uint32_t force_non_lttpr:1; /* bit 1 */ 847 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 848 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 849 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 850 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 851 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 852 uint32_t enable_bw_allocation_mode:1; /* bit 7 */ 853 uint32_t reserved:24; 854 } bits; 855 uint32_t raw; 856 }; 857 858 /* AUX wake work around options 859 * 0: enable/disable work around 860 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 861 * 15-2: reserved 862 * 31-16: timeout in ms 863 */ 864 union aux_wake_wa_options { 865 struct { 866 uint32_t enable_wa : 1; 867 uint32_t use_default_timeout : 1; 868 uint32_t rsvd: 14; 869 uint32_t timeout_ms : 16; 870 } bits; 871 uint32_t raw; 872 }; 873 874 struct dc_debug_data { 875 uint32_t ltFailCount; 876 uint32_t i2cErrorCount; 877 uint32_t auxErrorCount; 878 }; 879 880 struct dc_phy_addr_space_config { 881 struct { 882 uint64_t start_addr; 883 uint64_t end_addr; 884 uint64_t fb_top; 885 uint64_t fb_offset; 886 uint64_t fb_base; 887 uint64_t agp_top; 888 uint64_t agp_bot; 889 uint64_t agp_base; 890 } system_aperture; 891 892 struct { 893 uint64_t page_table_start_addr; 894 uint64_t page_table_end_addr; 895 uint64_t page_table_base_addr; 896 bool base_addr_is_mc_addr; 897 } gart_config; 898 899 bool valid; 900 bool is_hvm_enabled; 901 uint64_t page_table_default_page_addr; 902 }; 903 904 struct dc_virtual_addr_space_config { 905 uint64_t page_table_base_addr; 906 uint64_t page_table_start_addr; 907 uint64_t page_table_end_addr; 908 uint32_t page_table_block_size_in_bytes; 909 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 910 }; 911 912 struct dc_bounding_box_overrides { 913 int sr_exit_time_ns; 914 int sr_enter_plus_exit_time_ns; 915 int sr_exit_z8_time_ns; 916 int sr_enter_plus_exit_z8_time_ns; 917 int urgent_latency_ns; 918 int percent_of_ideal_drambw; 919 int dram_clock_change_latency_ns; 920 int dummy_clock_change_latency_ns; 921 int fclk_clock_change_latency_ns; 922 /* This forces a hard min on the DCFCLK we use 923 * for DML. Unlike the debug option for forcing 924 * DCFCLK, this override affects watermark calculations 925 */ 926 int min_dcfclk_mhz; 927 }; 928 929 struct dc_state; 930 struct resource_pool; 931 struct dce_hwseq; 932 struct link_service; 933 934 /* 935 * struct dc_debug_options - DC debug struct 936 * 937 * This struct provides a simple mechanism for developers to change some 938 * configurations, enable/disable features, and activate extra debug options. 939 * This can be very handy to narrow down whether some specific feature is 940 * causing an issue or not. 941 */ 942 struct dc_debug_options { 943 bool native422_support; 944 bool disable_dsc; 945 enum visual_confirm visual_confirm; 946 int visual_confirm_rect_height; 947 948 bool sanity_checks; 949 bool max_disp_clk; 950 bool surface_trace; 951 bool clock_trace; 952 bool validation_trace; 953 bool bandwidth_calcs_trace; 954 int max_downscale_src_width; 955 956 /* stutter efficiency related */ 957 bool disable_stutter; 958 bool use_max_lb; 959 enum dcc_option disable_dcc; 960 961 /* 962 * @pipe_split_policy: Define which pipe split policy is used by the 963 * display core. 964 */ 965 enum pipe_split_policy pipe_split_policy; 966 bool force_single_disp_pipe_split; 967 bool voltage_align_fclk; 968 bool disable_min_fclk; 969 970 bool hdcp_lc_force_fw_enable; 971 bool hdcp_lc_enable_sw_fallback; 972 973 bool disable_dfs_bypass; 974 bool disable_dpp_power_gate; 975 bool disable_hubp_power_gate; 976 bool disable_dsc_power_gate; 977 bool disable_optc_power_gate; 978 bool disable_hpo_power_gate; 979 bool disable_io_clk_power_gate; 980 bool disable_mem_power_gate; 981 bool disable_dio_power_gate; 982 int dsc_min_slice_height_override; 983 int dsc_bpp_increment_div; 984 bool disable_pplib_wm_range; 985 enum wm_report_mode pplib_wm_report_mode; 986 unsigned int min_disp_clk_khz; 987 unsigned int min_dpp_clk_khz; 988 unsigned int min_dram_clk_khz; 989 int sr_exit_time_dpm0_ns; 990 int sr_enter_plus_exit_time_dpm0_ns; 991 int sr_exit_time_ns; 992 int sr_enter_plus_exit_time_ns; 993 int sr_exit_z8_time_ns; 994 int sr_enter_plus_exit_z8_time_ns; 995 int urgent_latency_ns; 996 uint32_t underflow_assert_delay_us; 997 int percent_of_ideal_drambw; 998 int dram_clock_change_latency_ns; 999 bool optimized_watermark; 1000 int always_scale; 1001 bool disable_pplib_clock_request; 1002 bool disable_clock_gate; 1003 bool disable_mem_low_power; 1004 bool pstate_enabled; 1005 bool disable_dmcu; 1006 bool force_abm_enable; 1007 bool disable_stereo_support; 1008 bool vsr_support; 1009 bool performance_trace; 1010 bool az_endpoint_mute_only; 1011 bool always_use_regamma; 1012 bool recovery_enabled; 1013 bool avoid_vbios_exec_table; 1014 bool scl_reset_length10; 1015 bool hdmi20_disable; 1016 bool skip_detection_link_training; 1017 uint32_t edid_read_retry_times; 1018 unsigned int force_odm_combine; //bit vector based on otg inst 1019 unsigned int seamless_boot_odm_combine; 1020 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 1021 int minimum_z8_residency_time; 1022 int minimum_z10_residency_time; 1023 bool disable_z9_mpc; 1024 unsigned int force_fclk_khz; 1025 bool enable_tri_buf; 1026 bool ips_disallow_entry; 1027 bool dmub_offload_enabled; 1028 bool dmcub_emulation; 1029 bool disable_idle_power_optimizations; 1030 unsigned int mall_size_override; 1031 unsigned int mall_additional_timer_percent; 1032 bool mall_error_as_fatal; 1033 bool dmub_command_table; /* for testing only */ 1034 struct dc_bw_validation_profile bw_val_profile; 1035 bool disable_fec; 1036 bool disable_48mhz_pwrdwn; 1037 /* This forces a hard min on the DCFCLK requested to SMU/PP 1038 * watermarks are not affected. 1039 */ 1040 unsigned int force_min_dcfclk_mhz; 1041 int dwb_fi_phase; 1042 bool disable_timing_sync; 1043 bool cm_in_bypass; 1044 int force_clock_mode;/*every mode change.*/ 1045 1046 bool disable_dram_clock_change_vactive_support; 1047 bool validate_dml_output; 1048 bool enable_dmcub_surface_flip; 1049 bool usbc_combo_phy_reset_wa; 1050 bool enable_dram_clock_change_one_display_vactive; 1051 /* TODO - remove once tested */ 1052 bool legacy_dp2_lt; 1053 bool set_mst_en_for_sst; 1054 bool disable_uhbr; 1055 bool force_dp2_lt_fallback_method; 1056 bool ignore_cable_id; 1057 union mem_low_power_enable_options enable_mem_low_power; 1058 union root_clock_optimization_options root_clock_optimization; 1059 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1060 bool hpo_optimization; 1061 bool force_vblank_alignment; 1062 1063 /* Enable dmub aux for legacy ddc */ 1064 bool enable_dmub_aux_for_legacy_ddc; 1065 bool disable_fams; 1066 enum in_game_fams_config disable_fams_gaming; 1067 /* FEC/PSR1 sequence enable delay in 100us */ 1068 uint8_t fec_enable_delay_in100us; 1069 bool enable_driver_sequence_debug; 1070 enum det_size crb_alloc_policy; 1071 int crb_alloc_policy_min_disp_count; 1072 bool disable_z10; 1073 bool enable_z9_disable_interface; 1074 bool psr_skip_crtc_disable; 1075 uint32_t ips_skip_crtc_disable_mask; 1076 union dpia_debug_options dpia_debug; 1077 bool disable_fixed_vs_aux_timeout_wa; 1078 uint32_t fixed_vs_aux_delay_config_wa; 1079 bool force_disable_subvp; 1080 bool force_subvp_mclk_switch; 1081 bool allow_sw_cursor_fallback; 1082 unsigned int force_subvp_num_ways; 1083 unsigned int force_mall_ss_num_ways; 1084 bool alloc_extra_way_for_cursor; 1085 uint32_t subvp_extra_lines; 1086 bool disable_force_pstate_allow_on_hw_release; 1087 bool force_usr_allow; 1088 /* uses value at boot and disables switch */ 1089 bool disable_dtb_ref_clk_switch; 1090 bool extended_blank_optimization; 1091 union aux_wake_wa_options aux_wake_wa; 1092 uint32_t mst_start_top_delay; 1093 uint8_t psr_power_use_phy_fsm; 1094 enum dml_hostvm_override_opts dml_hostvm_override; 1095 bool dml_disallow_alternate_prefetch_modes; 1096 bool use_legacy_soc_bb_mechanism; 1097 bool exit_idle_opt_for_cursor_updates; 1098 bool using_dml2; 1099 bool enable_single_display_2to1_odm_policy; 1100 bool enable_double_buffered_dsc_pg_support; 1101 bool enable_dp_dig_pixel_rate_div_policy; 1102 bool using_dml21; 1103 enum lttpr_mode lttpr_mode_override; 1104 unsigned int dsc_delay_factor_wa_x1000; 1105 unsigned int min_prefetch_in_strobe_ns; 1106 bool disable_unbounded_requesting; 1107 bool dig_fifo_off_in_blank; 1108 bool override_dispclk_programming; 1109 bool otg_crc_db; 1110 bool disallow_dispclk_dppclk_ds; 1111 bool disable_fpo_optimizations; 1112 bool support_eDP1_5; 1113 uint32_t fpo_vactive_margin_us; 1114 bool disable_fpo_vactive; 1115 bool disable_boot_optimizations; 1116 bool override_odm_optimization; 1117 bool minimize_dispclk_using_odm; 1118 bool disable_subvp_high_refresh; 1119 bool disable_dp_plus_plus_wa; 1120 uint32_t fpo_vactive_min_active_margin_us; 1121 uint32_t fpo_vactive_max_blank_us; 1122 bool enable_hpo_pg_support; 1123 bool enable_legacy_fast_update; 1124 bool disable_dc_mode_overwrite; 1125 bool replay_skip_crtc_disabled; 1126 bool ignore_pg;/*do nothing, let pmfw control it*/ 1127 bool psp_disabled_wa; 1128 unsigned int ips2_eval_delay_us; 1129 unsigned int ips2_entry_delay_us; 1130 bool optimize_ips_handshake; 1131 bool disable_dmub_reallow_idle; 1132 bool disable_timeout; 1133 bool disable_extblankadj; 1134 bool enable_idle_reg_checks; 1135 unsigned int static_screen_wait_frames; 1136 uint32_t pwm_freq; 1137 bool force_chroma_subsampling_1tap; 1138 unsigned int dcc_meta_propagation_delay_us; 1139 bool disable_422_left_edge_pixel; 1140 bool dml21_force_pstate_method; 1141 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1142 uint32_t dml21_disable_pstate_method_mask; 1143 union fw_assisted_mclk_switch_version fams_version; 1144 union dmub_fams2_global_feature_config fams2_config; 1145 unsigned int force_cositing; 1146 unsigned int disable_spl; 1147 unsigned int force_easf; 1148 unsigned int force_sharpness; 1149 unsigned int force_sharpness_level; 1150 unsigned int force_lls; 1151 bool notify_dpia_hr_bw; 1152 bool enable_ips_visual_confirm; 1153 unsigned int sharpen_policy; 1154 unsigned int scale_to_sharpness_policy; 1155 bool skip_full_updated_if_possible; 1156 unsigned int enable_oled_edp_power_up_opt; 1157 bool enable_hblank_borrow; 1158 bool force_subvp_df_throttle; 1159 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1160 unsigned int auxless_alpm_lfps_setup_ns; 1161 unsigned int auxless_alpm_lfps_period_ns; 1162 unsigned int auxless_alpm_lfps_silence_ns; 1163 unsigned int auxless_alpm_lfps_t1t2_us; 1164 short auxless_alpm_lfps_t1t2_offset_us; 1165 bool enable_pg_cntl_debug_logs; 1166 }; 1167 1168 1169 /* Generic structure that can be used to query properties of DC. More fields 1170 * can be added as required. 1171 */ 1172 struct dc_current_properties { 1173 unsigned int cursor_size_limit; 1174 }; 1175 1176 enum frame_buffer_mode { 1177 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1178 FRAME_BUFFER_MODE_ZFB_ONLY, 1179 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1180 } ; 1181 1182 struct dchub_init_data { 1183 int64_t zfb_phys_addr_base; 1184 int64_t zfb_mc_base_addr; 1185 uint64_t zfb_size_in_byte; 1186 enum frame_buffer_mode fb_mode; 1187 bool dchub_initialzied; 1188 bool dchub_info_valid; 1189 }; 1190 1191 struct dml2_soc_bb; 1192 1193 struct dc_init_data { 1194 struct hw_asic_id asic_id; 1195 void *driver; /* ctx */ 1196 struct cgs_device *cgs_device; 1197 struct dc_bounding_box_overrides bb_overrides; 1198 1199 int num_virtual_links; 1200 /* 1201 * If 'vbios_override' not NULL, it will be called instead 1202 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1203 */ 1204 struct dc_bios *vbios_override; 1205 enum dce_environment dce_environment; 1206 1207 struct dmub_offload_funcs *dmub_if; 1208 struct dc_reg_helper_state *dmub_offload; 1209 1210 struct dc_config flags; 1211 uint64_t log_mask; 1212 1213 struct dpcd_vendor_signature vendor_signature; 1214 bool force_smu_not_present; 1215 /* 1216 * IP offset for run time initializaion of register addresses 1217 * 1218 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1219 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1220 * before them. 1221 */ 1222 uint32_t *dcn_reg_offsets; 1223 uint32_t *nbio_reg_offsets; 1224 uint32_t *clk_reg_offsets; 1225 void *bb_from_dmub; 1226 }; 1227 1228 struct dc_callback_init { 1229 struct cp_psp cp_psp; 1230 }; 1231 1232 struct dc *dc_create(const struct dc_init_data *init_params); 1233 void dc_hardware_init(struct dc *dc); 1234 1235 int dc_get_vmid_use_vector(struct dc *dc); 1236 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1237 /* Returns the number of vmids supported */ 1238 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1239 void dc_init_callbacks(struct dc *dc, 1240 const struct dc_callback_init *init_params); 1241 void dc_deinit_callbacks(struct dc *dc); 1242 void dc_destroy(struct dc **dc); 1243 1244 /* Surface Interfaces */ 1245 1246 enum { 1247 TRANSFER_FUNC_POINTS = 1025 1248 }; 1249 1250 struct dc_hdr_static_metadata { 1251 /* display chromaticities and white point in units of 0.00001 */ 1252 unsigned int chromaticity_green_x; 1253 unsigned int chromaticity_green_y; 1254 unsigned int chromaticity_blue_x; 1255 unsigned int chromaticity_blue_y; 1256 unsigned int chromaticity_red_x; 1257 unsigned int chromaticity_red_y; 1258 unsigned int chromaticity_white_point_x; 1259 unsigned int chromaticity_white_point_y; 1260 1261 uint32_t min_luminance; 1262 uint32_t max_luminance; 1263 uint32_t maximum_content_light_level; 1264 uint32_t maximum_frame_average_light_level; 1265 }; 1266 1267 enum dc_transfer_func_type { 1268 TF_TYPE_PREDEFINED, 1269 TF_TYPE_DISTRIBUTED_POINTS, 1270 TF_TYPE_BYPASS, 1271 TF_TYPE_HWPWL 1272 }; 1273 1274 struct dc_transfer_func_distributed_points { 1275 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1276 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1277 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1278 1279 uint16_t end_exponent; 1280 uint16_t x_point_at_y1_red; 1281 uint16_t x_point_at_y1_green; 1282 uint16_t x_point_at_y1_blue; 1283 }; 1284 1285 enum dc_transfer_func_predefined { 1286 TRANSFER_FUNCTION_SRGB, 1287 TRANSFER_FUNCTION_BT709, 1288 TRANSFER_FUNCTION_PQ, 1289 TRANSFER_FUNCTION_LINEAR, 1290 TRANSFER_FUNCTION_UNITY, 1291 TRANSFER_FUNCTION_HLG, 1292 TRANSFER_FUNCTION_HLG12, 1293 TRANSFER_FUNCTION_GAMMA22, 1294 TRANSFER_FUNCTION_GAMMA24, 1295 TRANSFER_FUNCTION_GAMMA26 1296 }; 1297 1298 1299 struct dc_transfer_func { 1300 struct kref refcount; 1301 enum dc_transfer_func_type type; 1302 enum dc_transfer_func_predefined tf; 1303 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1304 uint32_t sdr_ref_white_level; 1305 union { 1306 struct pwl_params pwl; 1307 struct dc_transfer_func_distributed_points tf_pts; 1308 }; 1309 }; 1310 1311 1312 union dc_3dlut_state { 1313 struct { 1314 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1315 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1316 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1317 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1318 uint32_t mpc_rmu1_mux:4; 1319 uint32_t mpc_rmu2_mux:4; 1320 uint32_t reserved:15; 1321 } bits; 1322 uint32_t raw; 1323 }; 1324 1325 1326 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1327 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1328 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1329 1330 struct lut_rgb { 1331 uint16_t b; 1332 uint16_t g; 1333 uint16_t r; 1334 uint16_t padding; 1335 }; 1336 1337 //this structure maps directly to how the lut will read it from memory 1338 struct lut_mem_mapping { 1339 union { 1340 //NATIVE MODE 1, 2 1341 //RGB layout [b][g][r] //red is 128 byte aligned 1342 //BGR layout [r][g][b] //blue is 128 byte aligned 1343 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1344 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1345 1346 //TRANSFORMED 1347 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1348 }; 1349 uint16_t size; 1350 }; 1351 1352 struct dc_rmcm_3dlut { 1353 bool isInUse; 1354 const struct dc_stream_state *stream; 1355 uint8_t protection_bits; 1356 }; 1357 1358 struct dc_3dlut { 1359 struct kref refcount; 1360 struct tetrahedral_params lut_3d; 1361 struct fixed31_32 hdr_multiplier; 1362 union dc_3dlut_state state; 1363 }; 1364 /* 1365 * This structure is filled in by dc_surface_get_status and contains 1366 * the last requested address and the currently active address so the called 1367 * can determine if there are any outstanding flips 1368 */ 1369 struct dc_plane_status { 1370 struct dc_plane_address requested_address; 1371 struct dc_plane_address current_address; 1372 bool is_flip_pending; 1373 bool is_right_eye; 1374 }; 1375 1376 union surface_update_flags { 1377 1378 struct { 1379 uint32_t addr_update:1; 1380 /* Medium updates */ 1381 uint32_t dcc_change:1; 1382 uint32_t color_space_change:1; 1383 uint32_t horizontal_mirror_change:1; 1384 uint32_t per_pixel_alpha_change:1; 1385 uint32_t global_alpha_change:1; 1386 uint32_t hdr_mult:1; 1387 uint32_t rotation_change:1; 1388 uint32_t swizzle_change:1; 1389 uint32_t scaling_change:1; 1390 uint32_t position_change:1; 1391 uint32_t in_transfer_func_change:1; 1392 uint32_t input_csc_change:1; 1393 uint32_t coeff_reduction_change:1; 1394 uint32_t output_tf_change:1; 1395 uint32_t pixel_format_change:1; 1396 uint32_t plane_size_change:1; 1397 uint32_t gamut_remap_change:1; 1398 1399 /* Full updates */ 1400 uint32_t new_plane:1; 1401 uint32_t bpp_change:1; 1402 uint32_t gamma_change:1; 1403 uint32_t bandwidth_change:1; 1404 uint32_t clock_change:1; 1405 uint32_t stereo_format_change:1; 1406 uint32_t lut_3d:1; 1407 uint32_t tmz_changed:1; 1408 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1409 uint32_t full_update:1; 1410 uint32_t sdr_white_level_nits:1; 1411 } bits; 1412 1413 uint32_t raw; 1414 }; 1415 1416 #define DC_REMOVE_PLANE_POINTERS 1 1417 1418 struct dc_plane_state { 1419 struct dc_plane_address address; 1420 struct dc_plane_flip_time time; 1421 bool triplebuffer_flips; 1422 struct scaling_taps scaling_quality; 1423 struct rect src_rect; 1424 struct rect dst_rect; 1425 struct rect clip_rect; 1426 1427 struct plane_size plane_size; 1428 struct dc_tiling_info tiling_info; 1429 1430 struct dc_plane_dcc_param dcc; 1431 1432 struct dc_gamma gamma_correction; 1433 struct dc_transfer_func in_transfer_func; 1434 struct dc_bias_and_scale bias_and_scale; 1435 struct dc_csc_transform input_csc_color_matrix; 1436 struct fixed31_32 coeff_reduction_factor; 1437 struct fixed31_32 hdr_mult; 1438 struct colorspace_transform gamut_remap_matrix; 1439 1440 // TODO: No longer used, remove 1441 struct dc_hdr_static_metadata hdr_static_ctx; 1442 1443 enum dc_color_space color_space; 1444 1445 struct dc_3dlut lut3d_func; 1446 struct dc_transfer_func in_shaper_func; 1447 struct dc_transfer_func blend_tf; 1448 1449 struct dc_transfer_func *gamcor_tf; 1450 enum surface_pixel_format format; 1451 enum dc_rotation_angle rotation; 1452 enum plane_stereo_format stereo_format; 1453 1454 bool is_tiling_rotated; 1455 bool per_pixel_alpha; 1456 bool pre_multiplied_alpha; 1457 bool global_alpha; 1458 int global_alpha_value; 1459 bool visible; 1460 bool flip_immediate; 1461 bool horizontal_mirror; 1462 int layer_index; 1463 1464 union surface_update_flags update_flags; 1465 bool flip_int_enabled; 1466 bool skip_manual_trigger; 1467 1468 /* private to DC core */ 1469 struct dc_plane_status status; 1470 struct dc_context *ctx; 1471 1472 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1473 bool force_full_update; 1474 1475 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1476 1477 /* private to dc_surface.c */ 1478 enum dc_irq_source irq_source; 1479 struct kref refcount; 1480 struct tg_color visual_confirm_color; 1481 1482 bool is_statically_allocated; 1483 enum chroma_cositing cositing; 1484 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1485 bool mcm_lut1d_enable; 1486 struct dc_cm2_func_luts mcm_luts; 1487 bool lut_bank_a; 1488 enum mpcc_movable_cm_location mcm_location; 1489 struct dc_csc_transform cursor_csc_color_matrix; 1490 bool adaptive_sharpness_en; 1491 int adaptive_sharpness_policy; 1492 int sharpness_level; 1493 enum linear_light_scaling linear_light_scaling; 1494 unsigned int sdr_white_level_nits; 1495 struct spl_sharpness_range sharpness_range; 1496 enum sharpness_range_source sharpness_source; 1497 }; 1498 1499 struct dc_plane_info { 1500 struct plane_size plane_size; 1501 struct dc_tiling_info tiling_info; 1502 struct dc_plane_dcc_param dcc; 1503 enum surface_pixel_format format; 1504 enum dc_rotation_angle rotation; 1505 enum plane_stereo_format stereo_format; 1506 enum dc_color_space color_space; 1507 bool horizontal_mirror; 1508 bool visible; 1509 bool per_pixel_alpha; 1510 bool pre_multiplied_alpha; 1511 bool global_alpha; 1512 int global_alpha_value; 1513 bool input_csc_enabled; 1514 int layer_index; 1515 enum chroma_cositing cositing; 1516 }; 1517 1518 #include "dc_stream.h" 1519 1520 struct dc_scratch_space { 1521 /* used to temporarily backup plane states of a stream during 1522 * dc update. The reason is that plane states are overwritten 1523 * with surface updates in dc update. Once they are overwritten 1524 * current state is no longer valid. We want to temporarily 1525 * store current value in plane states so we can still recover 1526 * a valid current state during dc update. 1527 */ 1528 struct dc_plane_state plane_states[MAX_SURFACES]; 1529 1530 struct dc_stream_state stream_state; 1531 }; 1532 1533 /* 1534 * A link contains one or more sinks and their connected status. 1535 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1536 */ 1537 struct dc_link { 1538 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1539 unsigned int sink_count; 1540 struct dc_sink *local_sink; 1541 unsigned int link_index; 1542 enum dc_connection_type type; 1543 enum signal_type connector_signal; 1544 enum dc_irq_source irq_source_hpd; 1545 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1546 enum dc_irq_source irq_source_read_request;/* Read Request */ 1547 1548 bool is_hpd_filter_disabled; 1549 bool dp_ss_off; 1550 1551 /** 1552 * @link_state_valid: 1553 * 1554 * If there is no link and local sink, this variable should be set to 1555 * false. Otherwise, it should be set to true; usually, the function 1556 * core_link_enable_stream sets this field to true. 1557 */ 1558 bool link_state_valid; 1559 bool aux_access_disabled; 1560 bool sync_lt_in_progress; 1561 bool skip_stream_reenable; 1562 bool is_internal_display; 1563 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1564 bool is_dig_mapping_flexible; 1565 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1566 bool is_hpd_pending; /* Indicates a new received hpd */ 1567 1568 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1569 * for every link training. This is incompatible with DP LL compliance automation, 1570 * which expects the same link settings to be used every retry on a link loss. 1571 * This flag is used to skip the fallback when link loss occurs during automation. 1572 */ 1573 bool skip_fallback_on_link_loss; 1574 1575 bool edp_sink_present; 1576 1577 struct dp_trace dp_trace; 1578 1579 /* caps is the same as reported_link_cap. link_traing use 1580 * reported_link_cap. Will clean up. TODO 1581 */ 1582 struct dc_link_settings reported_link_cap; 1583 struct dc_link_settings verified_link_cap; 1584 struct dc_link_settings cur_link_settings; 1585 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1586 struct dc_link_settings preferred_link_setting; 1587 /* preferred_training_settings are override values that 1588 * come from DM. DM is responsible for the memory 1589 * management of the override pointers. 1590 */ 1591 struct dc_link_training_overrides preferred_training_settings; 1592 struct dp_audio_test_data audio_test_data; 1593 1594 uint8_t ddc_hw_inst; 1595 1596 uint8_t hpd_src; 1597 1598 uint8_t link_enc_hw_inst; 1599 /* DIG link encoder ID. Used as index in link encoder resource pool. 1600 * For links with fixed mapping to DIG, this is not changed after dc_link 1601 * object creation. 1602 */ 1603 enum engine_id eng_id; 1604 enum engine_id dpia_preferred_eng_id; 1605 1606 bool test_pattern_enabled; 1607 /* Pending/Current test pattern are only used to perform and track 1608 * FIXED_VS retimer test pattern/lane adjustment override state. 1609 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1610 * to perform specific lane adjust overrides before setting certain 1611 * PHY test patterns. In cases when lane adjust and set test pattern 1612 * calls are not performed atomically (i.e. performing link training), 1613 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1614 * and current_test_pattern will contain required context for any future 1615 * set pattern/set lane adjust to transition between override state(s). 1616 * */ 1617 enum dp_test_pattern current_test_pattern; 1618 enum dp_test_pattern pending_test_pattern; 1619 1620 union compliance_test_state compliance_test_state; 1621 1622 void *priv; 1623 1624 struct ddc_service *ddc; 1625 1626 enum dp_panel_mode panel_mode; 1627 bool aux_mode; 1628 1629 /* Private to DC core */ 1630 1631 const struct dc *dc; 1632 1633 struct dc_context *ctx; 1634 1635 struct panel_cntl *panel_cntl; 1636 struct link_encoder *link_enc; 1637 struct graphics_object_id link_id; 1638 /* Endpoint type distinguishes display endpoints which do not have entries 1639 * in the BIOS connector table from those that do. Helps when tracking link 1640 * encoder to display endpoint assignments. 1641 */ 1642 enum display_endpoint_type ep_type; 1643 union ddi_channel_mapping ddi_channel_mapping; 1644 struct connector_device_tag_info device_tag; 1645 struct dpcd_caps dpcd_caps; 1646 uint32_t dongle_max_pix_clk; 1647 unsigned short chip_caps; 1648 unsigned int dpcd_sink_count; 1649 struct hdcp_caps hdcp_caps; 1650 enum edp_revision edp_revision; 1651 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1652 1653 struct psr_settings psr_settings; 1654 struct replay_settings replay_settings; 1655 1656 /* Drive settings read from integrated info table */ 1657 struct dc_lane_settings bios_forced_drive_settings; 1658 1659 /* Vendor specific LTTPR workaround variables */ 1660 uint8_t vendor_specific_lttpr_link_rate_wa; 1661 bool apply_vendor_specific_lttpr_link_rate_wa; 1662 1663 /* MST record stream using this link */ 1664 struct link_flags { 1665 bool dp_keep_receiver_powered; 1666 bool dp_skip_DID2; 1667 bool dp_skip_reset_segment; 1668 bool dp_skip_fs_144hz; 1669 bool dp_mot_reset_segment; 1670 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1671 bool dpia_mst_dsc_always_on; 1672 /* Forced DPIA into TBT3 compatibility mode. */ 1673 bool dpia_forced_tbt3_mode; 1674 bool dongle_mode_timing_override; 1675 bool blank_stream_on_ocs_change; 1676 bool read_dpcd204h_on_irq_hpd; 1677 bool force_dp_ffe_preset; 1678 bool skip_phy_ssc_reduction; 1679 } wa_flags; 1680 union dc_dp_ffe_preset forced_dp_ffe_preset; 1681 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1682 1683 struct dc_link_status link_status; 1684 struct dprx_states dprx_states; 1685 1686 struct gpio *hpd_gpio; 1687 enum dc_link_fec_state fec_state; 1688 bool is_dds; 1689 bool is_display_mux_present; 1690 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1691 1692 struct dc_panel_config panel_config; 1693 struct phy_state phy_state; 1694 uint32_t phy_transition_bitmask; 1695 // BW ALLOCATON USB4 ONLY 1696 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1697 bool skip_implict_edp_power_control; 1698 enum backlight_control_type backlight_control_type; 1699 }; 1700 1701 struct dc { 1702 struct dc_debug_options debug; 1703 struct dc_versions versions; 1704 struct dc_caps caps; 1705 struct dc_cap_funcs cap_funcs; 1706 struct dc_config config; 1707 struct dc_bounding_box_overrides bb_overrides; 1708 struct dc_bug_wa work_arounds; 1709 struct dc_context *ctx; 1710 struct dc_phy_addr_space_config vm_pa_config; 1711 1712 uint8_t link_count; 1713 struct dc_link *links[MAX_LINKS]; 1714 uint8_t lowest_dpia_link_index; 1715 struct link_service *link_srv; 1716 1717 struct dc_state *current_state; 1718 struct resource_pool *res_pool; 1719 1720 struct clk_mgr *clk_mgr; 1721 1722 /* Display Engine Clock levels */ 1723 struct dm_pp_clock_levels sclk_lvls; 1724 1725 /* Inputs into BW and WM calculations. */ 1726 struct bw_calcs_dceip *bw_dceip; 1727 struct bw_calcs_vbios *bw_vbios; 1728 struct dcn_soc_bounding_box *dcn_soc; 1729 struct dcn_ip_params *dcn_ip; 1730 struct display_mode_lib dml; 1731 1732 /* HW functions */ 1733 struct hw_sequencer_funcs hwss; 1734 struct dce_hwseq *hwseq; 1735 1736 /* Require to optimize clocks and bandwidth for added/removed planes */ 1737 bool optimized_required; 1738 bool wm_optimized_required; 1739 bool idle_optimizations_allowed; 1740 bool enable_c20_dtm_b0; 1741 1742 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1743 1744 /* For eDP to know the switching state of SmartMux */ 1745 bool is_switch_in_progress_orig; 1746 bool is_switch_in_progress_dest; 1747 1748 /* FBC compressor */ 1749 struct compressor *fbc_compressor; 1750 1751 struct dc_debug_data debug_data; 1752 struct dpcd_vendor_signature vendor_signature; 1753 1754 const char *build_id; 1755 struct vm_helper *vm_helper; 1756 1757 uint32_t *dcn_reg_offsets; 1758 uint32_t *nbio_reg_offsets; 1759 uint32_t *clk_reg_offsets; 1760 1761 /* Scratch memory */ 1762 struct { 1763 struct { 1764 /* 1765 * For matching clock_limits table in driver with table 1766 * from PMFW. 1767 */ 1768 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1769 } update_bw_bounding_box; 1770 struct dc_scratch_space current_state; 1771 struct dc_scratch_space new_state; 1772 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1773 struct dc_link temp_link; 1774 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1775 } scratch; 1776 1777 struct dml2_configuration_options dml2_options; 1778 struct dml2_configuration_options dml2_dc_power_options; 1779 enum dc_acpi_cm_power_state power_state; 1780 struct soc_and_ip_translator *soc_and_ip_translator; 1781 }; 1782 1783 struct dc_scaling_info { 1784 struct rect src_rect; 1785 struct rect dst_rect; 1786 struct rect clip_rect; 1787 struct scaling_taps scaling_quality; 1788 }; 1789 1790 struct dc_fast_update { 1791 const struct dc_flip_addrs *flip_addr; 1792 const struct dc_gamma *gamma; 1793 const struct colorspace_transform *gamut_remap_matrix; 1794 const struct dc_csc_transform *input_csc_color_matrix; 1795 const struct fixed31_32 *coeff_reduction_factor; 1796 struct dc_transfer_func *out_transfer_func; 1797 struct dc_csc_transform *output_csc_transform; 1798 const struct dc_csc_transform *cursor_csc_color_matrix; 1799 }; 1800 1801 struct dc_surface_update { 1802 struct dc_plane_state *surface; 1803 1804 /* isr safe update parameters. null means no updates */ 1805 const struct dc_flip_addrs *flip_addr; 1806 const struct dc_plane_info *plane_info; 1807 const struct dc_scaling_info *scaling_info; 1808 struct fixed31_32 hdr_mult; 1809 /* following updates require alloc/sleep/spin that is not isr safe, 1810 * null means no updates 1811 */ 1812 const struct dc_gamma *gamma; 1813 const struct dc_transfer_func *in_transfer_func; 1814 1815 const struct dc_csc_transform *input_csc_color_matrix; 1816 const struct fixed31_32 *coeff_reduction_factor; 1817 const struct dc_transfer_func *func_shaper; 1818 const struct dc_3dlut *lut3d_func; 1819 const struct dc_transfer_func *blend_tf; 1820 const struct colorspace_transform *gamut_remap_matrix; 1821 /* 1822 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1823 * 1824 * change cm2_params.component_settings: Full update 1825 * change cm2_params.cm2_luts: Fast update 1826 */ 1827 const struct dc_cm2_parameters *cm2_params; 1828 const struct dc_csc_transform *cursor_csc_color_matrix; 1829 unsigned int sdr_white_level_nits; 1830 struct dc_bias_and_scale bias_and_scale; 1831 }; 1832 1833 struct dc_underflow_debug_data { 1834 uint32_t otg_inst; 1835 uint32_t otg_underflow; 1836 uint32_t h_position; 1837 uint32_t v_position; 1838 uint32_t otg_frame_count; 1839 struct dc_underflow_per_hubp_debug_data { 1840 uint32_t hubp_underflow; 1841 uint32_t hubp_in_blank; 1842 uint32_t hubp_readline; 1843 uint32_t det_config_error; 1844 } hubps[MAX_PIPES]; 1845 uint32_t curr_det_sizes[MAX_PIPES]; 1846 uint32_t target_det_sizes[MAX_PIPES]; 1847 uint32_t compbuf_config_error; 1848 }; 1849 1850 /* 1851 * Create a new surface with default parameters; 1852 */ 1853 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1854 void dc_gamma_release(struct dc_gamma **dc_gamma); 1855 struct dc_gamma *dc_create_gamma(void); 1856 1857 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1858 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1859 struct dc_transfer_func *dc_create_transfer_func(void); 1860 1861 struct dc_3dlut *dc_create_3dlut_func(void); 1862 void dc_3dlut_func_release(struct dc_3dlut *lut); 1863 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1864 1865 void dc_post_update_surfaces_to_stream( 1866 struct dc *dc); 1867 1868 /** 1869 * struct dc_validation_set - Struct to store surface/stream associations for validation 1870 */ 1871 struct dc_validation_set { 1872 /** 1873 * @stream: Stream state properties 1874 */ 1875 struct dc_stream_state *stream; 1876 1877 /** 1878 * @plane_states: Surface state 1879 */ 1880 struct dc_plane_state *plane_states[MAX_SURFACES]; 1881 1882 /** 1883 * @plane_count: Total of active planes 1884 */ 1885 uint8_t plane_count; 1886 }; 1887 1888 bool dc_validate_boot_timing(const struct dc *dc, 1889 const struct dc_sink *sink, 1890 struct dc_crtc_timing *crtc_timing); 1891 1892 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1893 1894 enum dc_status dc_validate_with_context(struct dc *dc, 1895 const struct dc_validation_set set[], 1896 int set_count, 1897 struct dc_state *context, 1898 enum dc_validate_mode validate_mode); 1899 1900 bool dc_set_generic_gpio_for_stereo(bool enable, 1901 struct gpio_service *gpio_service); 1902 1903 enum dc_status dc_validate_global_state( 1904 struct dc *dc, 1905 struct dc_state *new_ctx, 1906 enum dc_validate_mode validate_mode); 1907 1908 bool dc_acquire_release_mpc_3dlut( 1909 struct dc *dc, bool acquire, 1910 struct dc_stream_state *stream, 1911 struct dc_3dlut **lut, 1912 struct dc_transfer_func **shaper); 1913 1914 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1915 void get_audio_check(struct audio_info *aud_modes, 1916 struct audio_check *aud_chk); 1917 1918 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1919 void populate_fast_updates(struct dc_fast_update *fast_update, 1920 struct dc_surface_update *srf_updates, 1921 int surface_count, 1922 struct dc_stream_update *stream_update); 1923 /* 1924 * Set up streams and links associated to drive sinks 1925 * The streams parameter is an absolute set of all active streams. 1926 * 1927 * After this call: 1928 * Phy, Encoder, Timing Generator are programmed and enabled. 1929 * New streams are enabled with blank stream; no memory read. 1930 */ 1931 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1932 1933 1934 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1935 struct dc_stream_state *stream, 1936 int mpcc_inst); 1937 1938 1939 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1940 1941 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1942 1943 /* The function returns minimum bandwidth required to drive a given timing 1944 * return - minimum required timing bandwidth in kbps. 1945 */ 1946 uint32_t dc_bandwidth_in_kbps_from_timing( 1947 const struct dc_crtc_timing *timing, 1948 const enum dc_link_encoding_format link_encoding); 1949 1950 /* Link Interfaces */ 1951 /* Return an enumerated dc_link. 1952 * dc_link order is constant and determined at 1953 * boot time. They cannot be created or destroyed. 1954 * Use dc_get_caps() to get number of links. 1955 */ 1956 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1957 1958 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1959 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1960 const struct dc_link *link, 1961 unsigned int *inst_out); 1962 1963 /* Return an array of link pointers to edp links. */ 1964 void dc_get_edp_links(const struct dc *dc, 1965 struct dc_link **edp_links, 1966 int *edp_num); 1967 1968 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1969 bool powerOn); 1970 1971 /* The function initiates detection handshake over the given link. It first 1972 * determines if there are display connections over the link. If so it initiates 1973 * detection protocols supported by the connected receiver device. The function 1974 * contains protocol specific handshake sequences which are sometimes mandatory 1975 * to establish a proper connection between TX and RX. So it is always 1976 * recommended to call this function as the first link operation upon HPD event 1977 * or power up event. Upon completion, the function will update link structure 1978 * in place based on latest RX capabilities. The function may also cause dpms 1979 * to be reset to off for all currently enabled streams to the link. It is DM's 1980 * responsibility to serialize detection and DPMS updates. 1981 * 1982 * @reason - Indicate which event triggers this detection. dc may customize 1983 * detection flow depending on the triggering events. 1984 * return false - if detection is not fully completed. This could happen when 1985 * there is an unrecoverable error during detection or detection is partially 1986 * completed (detection has been delegated to dm mst manager ie. 1987 * link->connection_type == dc_connection_mst_branch when returning false). 1988 * return true - detection is completed, link has been fully updated with latest 1989 * detection result. 1990 */ 1991 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1992 1993 struct dc_sink_init_data; 1994 1995 /* When link connection type is dc_connection_mst_branch, remote sink can be 1996 * added to the link. The interface creates a remote sink and associates it with 1997 * current link. The sink will be retained by link until remove remote sink is 1998 * called. 1999 * 2000 * @dc_link - link the remote sink will be added to. 2001 * @edid - byte array of EDID raw data. 2002 * @len - size of the edid in byte 2003 * @init_data - 2004 */ 2005 struct dc_sink *dc_link_add_remote_sink( 2006 struct dc_link *dc_link, 2007 const uint8_t *edid, 2008 int len, 2009 struct dc_sink_init_data *init_data); 2010 2011 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2012 * @link - link the sink should be removed from 2013 * @sink - sink to be removed. 2014 */ 2015 void dc_link_remove_remote_sink( 2016 struct dc_link *link, 2017 struct dc_sink *sink); 2018 2019 /* Enable HPD interrupt handler for a given link */ 2020 void dc_link_enable_hpd(const struct dc_link *link); 2021 2022 /* Disable HPD interrupt handler for a given link */ 2023 void dc_link_disable_hpd(const struct dc_link *link); 2024 2025 /* determine if there is a sink connected to the link 2026 * 2027 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2028 * return - false if an unexpected error occurs, true otherwise. 2029 * 2030 * NOTE: This function doesn't detect downstream sink connections i.e 2031 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2032 * return dc_connection_single if the branch device is connected despite of 2033 * downstream sink's connection status. 2034 */ 2035 bool dc_link_detect_connection_type(struct dc_link *link, 2036 enum dc_connection_type *type); 2037 2038 /* query current hpd pin value 2039 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2040 * 2041 */ 2042 bool dc_link_get_hpd_state(struct dc_link *link); 2043 2044 /* Getter for cached link status from given link */ 2045 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2046 2047 /* enable/disable hardware HPD filter. 2048 * 2049 * @link - The link the HPD pin is associated with. 2050 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2051 * handler once after no HPD change has been detected within dc default HPD 2052 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2053 * pulses within default HPD interval, no HPD event will be received until HPD 2054 * toggles have stopped. Then HPD event will be queued to irq handler once after 2055 * dc default HPD filtering interval since last HPD event. 2056 * 2057 * @enable = false - disable hardware HPD filter. HPD event will be queued 2058 * immediately to irq handler after no HPD change has been detected within 2059 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2060 */ 2061 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2062 2063 /* submit i2c read/write payloads through ddc channel 2064 * @link_index - index to a link with ddc in i2c mode 2065 * @cmd - i2c command structure 2066 * return - true if success, false otherwise. 2067 */ 2068 bool dc_submit_i2c( 2069 struct dc *dc, 2070 uint32_t link_index, 2071 struct i2c_command *cmd); 2072 2073 /* submit i2c read/write payloads through oem channel 2074 * @link_index - index to a link with ddc in i2c mode 2075 * @cmd - i2c command structure 2076 * return - true if success, false otherwise. 2077 */ 2078 bool dc_submit_i2c_oem( 2079 struct dc *dc, 2080 struct i2c_command *cmd); 2081 2082 enum aux_return_code_type; 2083 /* Attempt to transfer the given aux payload. This function does not perform 2084 * retries or handle error states. The reply is returned in the payload->reply 2085 * and the result through operation_result. Returns the number of bytes 2086 * transferred,or -1 on a failure. 2087 */ 2088 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2089 struct aux_payload *payload, 2090 enum aux_return_code_type *operation_result); 2091 2092 struct ddc_service * 2093 dc_get_oem_i2c_device(struct dc *dc); 2094 2095 bool dc_is_oem_i2c_device_present( 2096 struct dc *dc, 2097 size_t slave_address 2098 ); 2099 2100 /* return true if the connected receiver supports the hdcp version */ 2101 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2102 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2103 2104 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2105 * 2106 * TODO - When defer_handling is true the function will have a different purpose. 2107 * It no longer does complete hpd rx irq handling. We should create a separate 2108 * interface specifically for this case. 2109 * 2110 * Return: 2111 * true - Downstream port status changed. DM should call DC to do the 2112 * detection. 2113 * false - no change in Downstream port status. No further action required 2114 * from DM. 2115 */ 2116 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2117 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2118 bool defer_handling, bool *has_left_work); 2119 /* handle DP specs define test automation sequence*/ 2120 void dc_link_dp_handle_automated_test(struct dc_link *link); 2121 2122 /* handle DP Link loss sequence and try to recover RX link loss with best 2123 * effort 2124 */ 2125 void dc_link_dp_handle_link_loss(struct dc_link *link); 2126 2127 /* Determine if hpd rx irq should be handled or ignored 2128 * return true - hpd rx irq should be handled. 2129 * return false - it is safe to ignore hpd rx irq event 2130 */ 2131 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2132 2133 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2134 * @link - link the hpd irq data associated with 2135 * @hpd_irq_dpcd_data - input hpd irq data 2136 * return - true if hpd irq data indicates a link lost 2137 */ 2138 bool dc_link_check_link_loss_status(struct dc_link *link, 2139 union hpd_irq_data *hpd_irq_dpcd_data); 2140 2141 /* Read hpd rx irq data from a given link 2142 * @link - link where the hpd irq data should be read from 2143 * @irq_data - output hpd irq data 2144 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2145 * read has failed. 2146 */ 2147 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2148 struct dc_link *link, 2149 union hpd_irq_data *irq_data); 2150 2151 /* The function clears recorded DP RX states in the link. DM should call this 2152 * function when it is resuming from S3 power state to previously connected links. 2153 * 2154 * TODO - in the future we should consider to expand link resume interface to 2155 * support clearing previous rx states. So we don't have to rely on dm to call 2156 * this interface explicitly. 2157 */ 2158 void dc_link_clear_dprx_states(struct dc_link *link); 2159 2160 /* Destruct the mst topology of the link and reset the allocated payload table 2161 * 2162 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2163 * still wants to reset MST topology on an unplug event */ 2164 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2165 2166 /* The function calculates effective DP link bandwidth when a given link is 2167 * using the given link settings. 2168 * 2169 * return - total effective link bandwidth in kbps. 2170 */ 2171 uint32_t dc_link_bandwidth_kbps( 2172 const struct dc_link *link, 2173 const struct dc_link_settings *link_setting); 2174 2175 struct dp_audio_bandwidth_params { 2176 const struct dc_crtc_timing *crtc_timing; 2177 enum dp_link_encoding link_encoding; 2178 uint32_t channel_count; 2179 uint32_t sample_rate_hz; 2180 }; 2181 2182 /* The function calculates the minimum size of hblank (in bytes) needed to 2183 * support the specified channel count and sample rate combination, given the 2184 * link encoding and timing to be used. This calculation is not supported 2185 * for 8b/10b SST. 2186 * 2187 * return - min hblank size in bytes, 0 if 8b/10b SST. 2188 */ 2189 uint32_t dc_link_required_hblank_size_bytes( 2190 const struct dc_link *link, 2191 struct dp_audio_bandwidth_params *audio_params); 2192 2193 /* The function takes a snapshot of current link resource allocation state 2194 * @dc: pointer to dc of the dm calling this 2195 * @map: a dc link resource snapshot defined internally to dc. 2196 * 2197 * DM needs to capture a snapshot of current link resource allocation mapping 2198 * and store it in its persistent storage. 2199 * 2200 * Some of the link resource is using first come first serve policy. 2201 * The allocation mapping depends on original hotplug order. This information 2202 * is lost after driver is loaded next time. The snapshot is used in order to 2203 * restore link resource to its previous state so user will get consistent 2204 * link capability allocation across reboot. 2205 * 2206 */ 2207 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2208 2209 /* This function restores link resource allocation state from a snapshot 2210 * @dc: pointer to dc of the dm calling this 2211 * @map: a dc link resource snapshot defined internally to dc. 2212 * 2213 * DM needs to call this function after initial link detection on boot and 2214 * before first commit streams to restore link resource allocation state 2215 * from previous boot session. 2216 * 2217 * Some of the link resource is using first come first serve policy. 2218 * The allocation mapping depends on original hotplug order. This information 2219 * is lost after driver is loaded next time. The snapshot is used in order to 2220 * restore link resource to its previous state so user will get consistent 2221 * link capability allocation across reboot. 2222 * 2223 */ 2224 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2225 2226 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2227 * interface i.e stream_update->dsc_config 2228 */ 2229 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2230 2231 /* translate a raw link rate data to bandwidth in kbps */ 2232 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2233 2234 /* determine the optimal bandwidth given link and required bw. 2235 * @link - current detected link 2236 * @req_bw - requested bandwidth in kbps 2237 * @link_settings - returned most optimal link settings that can fit the 2238 * requested bandwidth 2239 * return - false if link can't support requested bandwidth, true if link 2240 * settings is found. 2241 */ 2242 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2243 struct dc_link_settings *link_settings, 2244 uint32_t req_bw); 2245 2246 /* return the max dp link settings can be driven by the link without considering 2247 * connected RX device and its capability 2248 */ 2249 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2250 struct dc_link_settings *max_link_enc_cap); 2251 2252 /* determine when the link is driving MST mode, what DP link channel coding 2253 * format will be used. The decision will remain unchanged until next HPD event. 2254 * 2255 * @link - a link with DP RX connection 2256 * return - if stream is committed to this link with MST signal type, type of 2257 * channel coding format dc will choose. 2258 */ 2259 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2260 const struct dc_link *link); 2261 2262 /* get max dp link settings the link can enable with all things considered. (i.e 2263 * TX/RX/Cable capabilities and dp override policies. 2264 * 2265 * @link - a link with DP RX connection 2266 * return - max dp link settings the link can enable. 2267 * 2268 */ 2269 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2270 2271 /* Get the highest encoding format that the link supports; highest meaning the 2272 * encoding format which supports the maximum bandwidth. 2273 * 2274 * @link - a link with DP RX connection 2275 * return - highest encoding format link supports. 2276 */ 2277 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2278 2279 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2280 * to a link with dp connector signal type. 2281 * @link - a link with dp connector signal type 2282 * return - true if connected, false otherwise 2283 */ 2284 bool dc_link_is_dp_sink_present(struct dc_link *link); 2285 2286 /* Force DP lane settings update to main-link video signal and notify the change 2287 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2288 * tuning purpose. The interface assumes link has already been enabled with DP 2289 * signal. 2290 * 2291 * @lt_settings - a container structure with desired hw_lane_settings 2292 */ 2293 void dc_link_set_drive_settings(struct dc *dc, 2294 struct link_training_settings *lt_settings, 2295 struct dc_link *link); 2296 2297 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2298 * test or debugging purpose. The test pattern will remain until next un-plug. 2299 * 2300 * @link - active link with DP signal output enabled. 2301 * @test_pattern - desired test pattern to output. 2302 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2303 * @test_pattern_color_space - for video test pattern choose a desired color 2304 * space. 2305 * @p_link_settings - For PHY pattern choose a desired link settings 2306 * @p_custom_pattern - some test pattern will require a custom input to 2307 * customize some pattern details. Otherwise keep it to NULL. 2308 * @cust_pattern_size - size of the custom pattern input. 2309 * 2310 */ 2311 bool dc_link_dp_set_test_pattern( 2312 struct dc_link *link, 2313 enum dp_test_pattern test_pattern, 2314 enum dp_test_pattern_color_space test_pattern_color_space, 2315 const struct link_training_settings *p_link_settings, 2316 const unsigned char *p_custom_pattern, 2317 unsigned int cust_pattern_size); 2318 2319 /* Force DP link settings to always use a specific value until reboot to a 2320 * specific link. If link has already been enabled, the interface will also 2321 * switch to desired link settings immediately. This is a debug interface to 2322 * generic dp issue trouble shooting. 2323 */ 2324 void dc_link_set_preferred_link_settings(struct dc *dc, 2325 struct dc_link_settings *link_setting, 2326 struct dc_link *link); 2327 2328 /* Force DP link to customize a specific link training behavior by overriding to 2329 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2330 * display specific link training issues or apply some display specific 2331 * workaround in link training. 2332 * 2333 * @link_settings - if not NULL, force preferred link settings to the link. 2334 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2335 * will apply this particular override in future link training. If NULL is 2336 * passed in, dc resets previous overrides. 2337 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2338 * training settings. 2339 */ 2340 void dc_link_set_preferred_training_settings(struct dc *dc, 2341 struct dc_link_settings *link_setting, 2342 struct dc_link_training_overrides *lt_overrides, 2343 struct dc_link *link, 2344 bool skip_immediate_retrain); 2345 2346 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2347 bool dc_link_is_fec_supported(const struct dc_link *link); 2348 2349 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2350 * link enablement. 2351 * return - true if FEC should be enabled, false otherwise. 2352 */ 2353 bool dc_link_should_enable_fec(const struct dc_link *link); 2354 2355 /* determine lttpr mode the current link should be enabled with a specific link 2356 * settings. 2357 */ 2358 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2359 struct dc_link_settings *link_setting); 2360 2361 /* Force DP RX to update its power state. 2362 * NOTE: this interface doesn't update dp main-link. Calling this function will 2363 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2364 * RX power state back upon finish DM specific execution requiring DP RX in a 2365 * specific power state. 2366 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2367 * state. 2368 */ 2369 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2370 2371 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2372 * current value read from extended receiver cap from 02200h - 0220Fh. 2373 * Some DP RX has problems of providing accurate DP receiver caps from extended 2374 * field, this interface is a workaround to revert link back to use base caps. 2375 */ 2376 void dc_link_overwrite_extended_receiver_cap( 2377 struct dc_link *link); 2378 2379 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2380 bool wait_for_hpd); 2381 2382 /* Set backlight level of an embedded panel (eDP, LVDS). 2383 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2384 * and 16 bit fractional, where 1.0 is max backlight value. 2385 */ 2386 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2387 struct set_backlight_level_params *backlight_level_params); 2388 2389 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2390 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2391 bool isHDR, 2392 uint32_t backlight_millinits, 2393 uint32_t transition_time_in_ms); 2394 2395 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2396 uint32_t *backlight_millinits, 2397 uint32_t *backlight_millinits_peak); 2398 2399 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2400 2401 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2402 2403 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2404 bool wait, bool force_static, const unsigned int *power_opts); 2405 2406 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2407 2408 bool dc_link_setup_psr(struct dc_link *dc_link, 2409 const struct dc_stream_state *stream, struct psr_config *psr_config, 2410 struct psr_context *psr_context); 2411 2412 /* 2413 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2414 * 2415 * @link: pointer to the dc_link struct instance 2416 * @enable: enable(active) or disable(inactive) replay 2417 * @wait: state transition need to wait the active set completed. 2418 * @force_static: force disable(inactive) the replay 2419 * @power_opts: set power optimazation parameters to DMUB. 2420 * 2421 * return: allow Replay active will return true, else will return false. 2422 */ 2423 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2424 bool wait, bool force_static, const unsigned int *power_opts); 2425 2426 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2427 2428 /* On eDP links this function call will stall until T12 has elapsed. 2429 * If the panel is not in power off state, this function will return 2430 * immediately. 2431 */ 2432 bool dc_link_wait_for_t12(struct dc_link *link); 2433 2434 /* Determine if dp trace has been initialized to reflect upto date result * 2435 * return - true if trace is initialized and has valid data. False dp trace 2436 * doesn't have valid result. 2437 */ 2438 bool dc_dp_trace_is_initialized(struct dc_link *link); 2439 2440 /* Query a dp trace flag to indicate if the current dp trace data has been 2441 * logged before 2442 */ 2443 bool dc_dp_trace_is_logged(struct dc_link *link, 2444 bool in_detection); 2445 2446 /* Set dp trace flag to indicate whether DM has already logged the current dp 2447 * trace data. DM can set is_logged to true upon logging and check 2448 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2449 */ 2450 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2451 bool in_detection, 2452 bool is_logged); 2453 2454 /* Obtain driver time stamp for last dp link training end. The time stamp is 2455 * formatted based on dm_get_timestamp DM function. 2456 * @in_detection - true to get link training end time stamp of last link 2457 * training in detection sequence. false to get link training end time stamp 2458 * of last link training in commit (dpms) sequence 2459 */ 2460 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2461 bool in_detection); 2462 2463 /* Get how many link training attempts dc has done with latest sequence. 2464 * @in_detection - true to get link training count of last link 2465 * training in detection sequence. false to get link training count of last link 2466 * training in commit (dpms) sequence 2467 */ 2468 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2469 bool in_detection); 2470 2471 /* Get how many link loss has happened since last link training attempts */ 2472 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2473 2474 /* 2475 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2476 */ 2477 /* 2478 * Send a request from DP-Tx requesting to allocate BW remotely after 2479 * allocating it locally. This will get processed by CM and a CB function 2480 * will be called. 2481 * 2482 * @link: pointer to the dc_link struct instance 2483 * @req_bw: The requested bw in Kbyte to allocated 2484 * 2485 * return: none 2486 */ 2487 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2488 2489 /* 2490 * Handle the USB4 BW Allocation related functionality here: 2491 * Plug => Try to allocate max bw from timing parameters supported by the sink 2492 * Unplug => de-allocate bw 2493 * 2494 * @link: pointer to the dc_link struct instance 2495 * @peak_bw: Peak bw used by the link/sink 2496 * 2497 */ 2498 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2499 struct dc_link *link, int peak_bw); 2500 2501 /* 2502 * Calculates the DP tunneling bandwidth required for the stream timing 2503 * and aggregates the stream bandwidth for the respective DP tunneling link 2504 * 2505 * return: dc_status 2506 */ 2507 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2508 2509 /* 2510 * Get if ALPM is supported by the link 2511 */ 2512 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 2513 bool *auxwake_support); 2514 2515 /* Sink Interfaces - A sink corresponds to a display output device */ 2516 2517 struct dc_container_id { 2518 // 128bit GUID in binary form 2519 unsigned char guid[16]; 2520 // 8 byte port ID -> ELD.PortID 2521 unsigned int portId[2]; 2522 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2523 unsigned short manufacturerName; 2524 // 2 byte product code -> ELD.ProductCode 2525 unsigned short productCode; 2526 }; 2527 2528 2529 struct dc_sink_dsc_caps { 2530 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2531 // 'false' if they are sink's DSC caps 2532 bool is_virtual_dpcd_dsc; 2533 // 'true' if MST topology supports DSC passthrough for sink 2534 // 'false' if MST topology does not support DSC passthrough 2535 bool is_dsc_passthrough_supported; 2536 struct dsc_dec_dpcd_caps dsc_dec_caps; 2537 }; 2538 2539 struct dc_sink_hblank_expansion_caps { 2540 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2541 // 'false' if they are sink's HBlank expansion caps 2542 bool is_virtual_dpcd_hblank_expansion; 2543 struct hblank_expansion_dpcd_caps dpcd_caps; 2544 }; 2545 2546 struct dc_sink_fec_caps { 2547 bool is_rx_fec_supported; 2548 bool is_topology_fec_supported; 2549 }; 2550 2551 struct scdc_caps { 2552 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2553 union hdmi_scdc_device_id_data device_id; 2554 }; 2555 2556 /* 2557 * The sink structure contains EDID and other display device properties 2558 */ 2559 struct dc_sink { 2560 enum signal_type sink_signal; 2561 struct dc_edid dc_edid; /* raw edid */ 2562 struct dc_edid_caps edid_caps; /* parse display caps */ 2563 struct dc_container_id *dc_container_id; 2564 uint32_t dongle_max_pix_clk; 2565 void *priv; 2566 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2567 bool converter_disable_audio; 2568 2569 struct scdc_caps scdc_caps; 2570 struct dc_sink_dsc_caps dsc_caps; 2571 struct dc_sink_fec_caps fec_caps; 2572 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2573 2574 bool is_vsc_sdp_colorimetry_supported; 2575 2576 /* private to DC core */ 2577 struct dc_link *link; 2578 struct dc_context *ctx; 2579 2580 uint32_t sink_id; 2581 2582 /* private to dc_sink.c */ 2583 // refcount must be the last member in dc_sink, since we want the 2584 // sink structure to be logically cloneable up to (but not including) 2585 // refcount 2586 struct kref refcount; 2587 }; 2588 2589 void dc_sink_retain(struct dc_sink *sink); 2590 void dc_sink_release(struct dc_sink *sink); 2591 2592 struct dc_sink_init_data { 2593 enum signal_type sink_signal; 2594 struct dc_link *link; 2595 uint32_t dongle_max_pix_clk; 2596 bool converter_disable_audio; 2597 }; 2598 2599 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2600 2601 /* Newer interfaces */ 2602 struct dc_cursor { 2603 struct dc_plane_address address; 2604 struct dc_cursor_attributes attributes; 2605 }; 2606 2607 2608 /* Interrupt interfaces */ 2609 enum dc_irq_source dc_interrupt_to_irq_source( 2610 struct dc *dc, 2611 uint32_t src_id, 2612 uint32_t ext_id); 2613 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2614 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2615 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2616 struct dc *dc, uint32_t link_index); 2617 2618 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2619 2620 /* Power Interfaces */ 2621 2622 void dc_set_power_state( 2623 struct dc *dc, 2624 enum dc_acpi_cm_power_state power_state); 2625 void dc_resume(struct dc *dc); 2626 2627 void dc_power_down_on_boot(struct dc *dc); 2628 2629 /* 2630 * HDCP Interfaces 2631 */ 2632 enum hdcp_message_status dc_process_hdcp_msg( 2633 enum signal_type signal, 2634 struct dc_link *link, 2635 struct hdcp_protection_message *message_info); 2636 bool dc_is_dmcu_initialized(struct dc *dc); 2637 2638 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2639 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2640 2641 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2642 unsigned int pitch, 2643 unsigned int height, 2644 enum surface_pixel_format format, 2645 struct dc_cursor_attributes *cursor_attr); 2646 2647 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2648 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2649 2650 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2651 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2652 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2653 2654 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2655 void dc_unlock_memory_clock_frequency(struct dc *dc); 2656 2657 /* set min memory clock to the min required for current mode, max to maxDPM */ 2658 void dc_lock_memory_clock_frequency(struct dc *dc); 2659 2660 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2661 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2662 2663 /* cleanup on driver unload */ 2664 void dc_hardware_release(struct dc *dc); 2665 2666 /* disables fw based mclk switch */ 2667 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2668 2669 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2670 2671 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2672 2673 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2674 2675 void dc_z10_restore(const struct dc *dc); 2676 void dc_z10_save_init(struct dc *dc); 2677 2678 bool dc_is_dmub_outbox_supported(struct dc *dc); 2679 bool dc_enable_dmub_notifications(struct dc *dc); 2680 2681 bool dc_abm_save_restore( 2682 struct dc *dc, 2683 struct dc_stream_state *stream, 2684 struct abm_save_restore *pData); 2685 2686 void dc_enable_dmub_outbox(struct dc *dc); 2687 2688 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2689 uint32_t link_index, 2690 struct aux_payload *payload); 2691 2692 /* Get dc link index from dpia port index */ 2693 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2694 uint8_t dpia_port_index); 2695 2696 bool dc_process_dmub_set_config_async(struct dc *dc, 2697 uint32_t link_index, 2698 struct set_config_cmd_payload *payload, 2699 struct dmub_notification *notify); 2700 2701 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2702 uint32_t link_index, 2703 uint8_t mst_alloc_slots, 2704 uint8_t *mst_slots_in_use); 2705 2706 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2707 2708 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2709 uint32_t hpd_int_enable); 2710 2711 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2712 2713 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2714 2715 struct dc_power_profile { 2716 int power_level; /* Lower is better */ 2717 }; 2718 2719 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2720 2721 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2722 2723 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2724 2725 /* DSC Interfaces */ 2726 #include "dc_dsc.h" 2727 2728 void dc_get_visual_confirm_for_stream( 2729 struct dc *dc, 2730 struct dc_stream_state *stream_state, 2731 struct tg_color *color); 2732 2733 /* Disable acc mode Interfaces */ 2734 void dc_disable_accelerated_mode(struct dc *dc); 2735 2736 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2737 struct dc_stream_state *new_stream); 2738 2739 bool dc_is_cursor_limit_pending(struct dc *dc); 2740 bool dc_can_clear_cursor_limit(struct dc *dc); 2741 2742 /** 2743 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 2744 * 2745 * @dc: Pointer to the display core context. 2746 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 2747 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 2748 * 2749 * This function collects and logs underflow-related HW states when underflow happens, 2750 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 2751 * The results are stored in the provided out_data structure for further analysis or logging. 2752 */ 2753 void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); 2754 2755 #endif /* DC_INTERFACE_H_ */ 2756