1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 struct abm_save_restore; 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.249" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MIN_VIEWPORT_SIZE 12 56 #define MAX_NUM_EDP 2 57 58 /* Display Core Interfaces */ 59 struct dc_versions { 60 const char *dc_ver; 61 struct dmcu_version dmcu_version; 62 }; 63 64 enum dp_protocol_version { 65 DP_VERSION_1_4 = 0, 66 DP_VERSION_2_1, 67 DP_VERSION_UNKNOWN, 68 }; 69 70 enum dc_plane_type { 71 DC_PLANE_TYPE_INVALID, 72 DC_PLANE_TYPE_DCE_RGB, 73 DC_PLANE_TYPE_DCE_UNDERLAY, 74 DC_PLANE_TYPE_DCN_UNIVERSAL, 75 }; 76 77 // Sizes defined as multiples of 64KB 78 enum det_size { 79 DET_SIZE_DEFAULT = 0, 80 DET_SIZE_192KB = 3, 81 DET_SIZE_256KB = 4, 82 DET_SIZE_320KB = 5, 83 DET_SIZE_384KB = 6 84 }; 85 86 87 struct dc_plane_cap { 88 enum dc_plane_type type; 89 uint32_t per_pixel_alpha : 1; 90 struct { 91 uint32_t argb8888 : 1; 92 uint32_t nv12 : 1; 93 uint32_t fp16 : 1; 94 uint32_t p010 : 1; 95 uint32_t ayuv : 1; 96 } pixel_format_support; 97 // max upscaling factor x1000 98 // upscaling factors are always >= 1 99 // for example, 1080p -> 8K is 4.0, or 4000 raw value 100 struct { 101 uint32_t argb8888; 102 uint32_t nv12; 103 uint32_t fp16; 104 } max_upscale_factor; 105 // max downscale factor x1000 106 // downscale factors are always <= 1 107 // for example, 8K -> 1080p is 0.25, or 250 raw value 108 struct { 109 uint32_t argb8888; 110 uint32_t nv12; 111 uint32_t fp16; 112 } max_downscale_factor; 113 // minimal width/height 114 uint32_t min_width; 115 uint32_t min_height; 116 }; 117 118 /** 119 * DOC: color-management-caps 120 * 121 * **Color management caps (DPP and MPC)** 122 * 123 * Modules/color calculates various color operations which are translated to 124 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 125 * DCN1, every new generation comes with fairly major differences in color 126 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 127 * decide mapping to HW block based on logical capabilities. 128 */ 129 130 /** 131 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 132 * @srgb: RGB color space transfer func 133 * @bt2020: BT.2020 transfer func 134 * @gamma2_2: standard gamma 135 * @pq: perceptual quantizer transfer function 136 * @hlg: hybrid log–gamma transfer function 137 */ 138 struct rom_curve_caps { 139 uint16_t srgb : 1; 140 uint16_t bt2020 : 1; 141 uint16_t gamma2_2 : 1; 142 uint16_t pq : 1; 143 uint16_t hlg : 1; 144 }; 145 146 /** 147 * struct dpp_color_caps - color pipeline capabilities for display pipe and 148 * plane blocks 149 * 150 * @dcn_arch: all DCE generations treated the same 151 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 152 * just plain 256-entry lookup 153 * @icsc: input color space conversion 154 * @dgam_ram: programmable degamma LUT 155 * @post_csc: post color space conversion, before gamut remap 156 * @gamma_corr: degamma correction 157 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 158 * with MPC by setting mpc:shared_3d_lut flag 159 * @ogam_ram: programmable out/blend gamma LUT 160 * @ocsc: output color space conversion 161 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 162 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 163 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 164 * 165 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 166 */ 167 struct dpp_color_caps { 168 uint16_t dcn_arch : 1; 169 uint16_t input_lut_shared : 1; 170 uint16_t icsc : 1; 171 uint16_t dgam_ram : 1; 172 uint16_t post_csc : 1; 173 uint16_t gamma_corr : 1; 174 uint16_t hw_3d_lut : 1; 175 uint16_t ogam_ram : 1; 176 uint16_t ocsc : 1; 177 uint16_t dgam_rom_for_yuv : 1; 178 struct rom_curve_caps dgam_rom_caps; 179 struct rom_curve_caps ogam_rom_caps; 180 }; 181 182 /** 183 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 184 * plane combined blocks 185 * 186 * @gamut_remap: color transformation matrix 187 * @ogam_ram: programmable out gamma LUT 188 * @ocsc: output color space conversion matrix 189 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 190 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 191 * instance 192 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 193 */ 194 struct mpc_color_caps { 195 uint16_t gamut_remap : 1; 196 uint16_t ogam_ram : 1; 197 uint16_t ocsc : 1; 198 uint16_t num_3dluts : 3; 199 uint16_t shared_3d_lut:1; 200 struct rom_curve_caps ogam_rom_caps; 201 }; 202 203 /** 204 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 205 * @dpp: color pipes caps for DPP 206 * @mpc: color pipes caps for MPC 207 */ 208 struct dc_color_caps { 209 struct dpp_color_caps dpp; 210 struct mpc_color_caps mpc; 211 }; 212 213 struct dc_dmub_caps { 214 bool psr; 215 bool mclk_sw; 216 bool subvp_psr; 217 bool gecc_enable; 218 }; 219 220 struct dc_caps { 221 uint32_t max_streams; 222 uint32_t max_links; 223 uint32_t max_audios; 224 uint32_t max_slave_planes; 225 uint32_t max_slave_yuv_planes; 226 uint32_t max_slave_rgb_planes; 227 uint32_t max_planes; 228 uint32_t max_downscale_ratio; 229 uint32_t i2c_speed_in_khz; 230 uint32_t i2c_speed_in_khz_hdcp; 231 uint32_t dmdata_alloc_size; 232 unsigned int max_cursor_size; 233 unsigned int max_video_width; 234 unsigned int min_horizontal_blanking_period; 235 int linear_pitch_alignment; 236 bool dcc_const_color; 237 bool dynamic_audio; 238 bool is_apu; 239 bool dual_link_dvi; 240 bool post_blend_color_processing; 241 bool force_dp_tps4_for_cp2520; 242 bool disable_dp_clk_share; 243 bool psp_setup_panel_mode; 244 bool extended_aux_timeout_support; 245 bool dmcub_support; 246 bool zstate_support; 247 bool ips_support; 248 uint32_t num_of_internal_disp; 249 enum dp_protocol_version max_dp_protocol_version; 250 unsigned int mall_size_per_mem_channel; 251 unsigned int mall_size_total; 252 unsigned int cursor_cache_size; 253 struct dc_plane_cap planes[MAX_PLANES]; 254 struct dc_color_caps color; 255 struct dc_dmub_caps dmub_caps; 256 bool dp_hpo; 257 bool dp_hdmi21_pcon_support; 258 bool edp_dsc_support; 259 bool vbios_lttpr_aware; 260 bool vbios_lttpr_enable; 261 uint32_t max_otg_num; 262 uint32_t max_cab_allocation_bytes; 263 uint32_t cache_line_size; 264 uint32_t cache_num_ways; 265 uint16_t subvp_fw_processing_delay_us; 266 uint8_t subvp_drr_max_vblank_margin_us; 267 uint16_t subvp_prefetch_end_to_mall_start_us; 268 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 269 uint16_t subvp_pstate_allow_width_us; 270 uint16_t subvp_vertical_int_margin_us; 271 bool seamless_odm; 272 uint32_t max_v_total; 273 uint8_t subvp_drr_vblank_start_margin_us; 274 }; 275 276 struct dc_bug_wa { 277 bool no_connect_phy_config; 278 bool dedcn20_305_wa; 279 bool skip_clock_update; 280 bool lt_early_cr_pattern; 281 struct { 282 uint8_t uclk : 1; 283 uint8_t fclk : 1; 284 uint8_t dcfclk : 1; 285 uint8_t dcfclk_ds: 1; 286 } clock_update_disable_mask; 287 }; 288 struct dc_dcc_surface_param { 289 struct dc_size surface_size; 290 enum surface_pixel_format format; 291 enum swizzle_mode_values swizzle_mode; 292 enum dc_scan_direction scan; 293 }; 294 295 struct dc_dcc_setting { 296 unsigned int max_compressed_blk_size; 297 unsigned int max_uncompressed_blk_size; 298 bool independent_64b_blks; 299 //These bitfields to be used starting with DCN 300 struct { 301 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 302 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 303 uint32_t dcc_256_128_128 : 1; //available starting with DCN 304 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 305 } dcc_controls; 306 }; 307 308 struct dc_surface_dcc_cap { 309 union { 310 struct { 311 struct dc_dcc_setting rgb; 312 } grph; 313 314 struct { 315 struct dc_dcc_setting luma; 316 struct dc_dcc_setting chroma; 317 } video; 318 }; 319 320 bool capable; 321 bool const_color_support; 322 }; 323 324 struct dc_static_screen_params { 325 struct { 326 bool force_trigger; 327 bool cursor_update; 328 bool surface_update; 329 bool overlay_update; 330 } triggers; 331 unsigned int num_frames; 332 }; 333 334 335 /* Surface update type is used by dc_update_surfaces_and_stream 336 * The update type is determined at the very beginning of the function based 337 * on parameters passed in and decides how much programming (or updating) is 338 * going to be done during the call. 339 * 340 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 341 * logical calculations or hardware register programming. This update MUST be 342 * ISR safe on windows. Currently fast update will only be used to flip surface 343 * address. 344 * 345 * UPDATE_TYPE_MED is used for slower updates which require significant hw 346 * re-programming however do not affect bandwidth consumption or clock 347 * requirements. At present, this is the level at which front end updates 348 * that do not require us to run bw_calcs happen. These are in/out transfer func 349 * updates, viewport offset changes, recout size changes and pixel depth changes. 350 * This update can be done at ISR, but we want to minimize how often this happens. 351 * 352 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 353 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 354 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 355 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 356 * a full update. This cannot be done at ISR level and should be a rare event. 357 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 358 * underscan we don't expect to see this call at all. 359 */ 360 361 enum surface_update_type { 362 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 363 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 364 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 365 }; 366 367 /* Forward declaration*/ 368 struct dc; 369 struct dc_plane_state; 370 struct dc_state; 371 372 373 struct dc_cap_funcs { 374 bool (*get_dcc_compression_cap)(const struct dc *dc, 375 const struct dc_dcc_surface_param *input, 376 struct dc_surface_dcc_cap *output); 377 }; 378 379 struct link_training_settings; 380 381 union allow_lttpr_non_transparent_mode { 382 struct { 383 bool DP1_4A : 1; 384 bool DP2_0 : 1; 385 } bits; 386 unsigned char raw; 387 }; 388 389 /* Structure to hold configuration flags set by dm at dc creation. */ 390 struct dc_config { 391 bool gpu_vm_support; 392 bool disable_disp_pll_sharing; 393 bool fbc_support; 394 bool disable_fractional_pwm; 395 bool allow_seamless_boot_optimization; 396 bool seamless_boot_edp_requested; 397 bool edp_not_connected; 398 bool edp_no_power_sequencing; 399 bool force_enum_edp; 400 bool forced_clocks; 401 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 402 bool multi_mon_pp_mclk_switch; 403 bool disable_dmcu; 404 bool enable_4to1MPC; 405 bool enable_windowed_mpo_odm; 406 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 407 uint32_t allow_edp_hotplug_detection; 408 bool clamp_min_dcfclk; 409 uint64_t vblank_alignment_dto_params; 410 uint8_t vblank_alignment_max_frame_time_diff; 411 bool is_asymmetric_memory; 412 bool is_single_rank_dimm; 413 bool is_vmin_only_asic; 414 bool use_pipe_ctx_sync_logic; 415 bool ignore_dpref_ss; 416 bool enable_mipi_converter_optimization; 417 bool use_default_clock_table; 418 bool force_bios_enable_lttpr; 419 uint8_t force_bios_fixed_vs; 420 int sdpif_request_limit_words_per_umc; 421 bool use_old_fixed_vs_sequence; 422 bool dc_mode_clk_limit_support; 423 }; 424 425 enum visual_confirm { 426 VISUAL_CONFIRM_DISABLE = 0, 427 VISUAL_CONFIRM_SURFACE = 1, 428 VISUAL_CONFIRM_HDR = 2, 429 VISUAL_CONFIRM_MPCTREE = 4, 430 VISUAL_CONFIRM_PSR = 5, 431 VISUAL_CONFIRM_SWAPCHAIN = 6, 432 VISUAL_CONFIRM_FAMS = 7, 433 VISUAL_CONFIRM_SWIZZLE = 9, 434 VISUAL_CONFIRM_REPLAY = 12, 435 VISUAL_CONFIRM_SUBVP = 14, 436 VISUAL_CONFIRM_MCLK_SWITCH = 16, 437 }; 438 439 enum dc_psr_power_opts { 440 psr_power_opt_invalid = 0x0, 441 psr_power_opt_smu_opt_static_screen = 0x1, 442 psr_power_opt_z10_static_screen = 0x10, 443 psr_power_opt_ds_disable_allow = 0x100, 444 }; 445 446 enum dml_hostvm_override_opts { 447 DML_HOSTVM_NO_OVERRIDE = 0x0, 448 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 449 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 450 }; 451 452 enum dcc_option { 453 DCC_ENABLE = 0, 454 DCC_DISABLE = 1, 455 DCC_HALF_REQ_DISALBE = 2, 456 }; 457 458 /** 459 * enum pipe_split_policy - Pipe split strategy supported by DCN 460 * 461 * This enum is used to define the pipe split policy supported by DCN. By 462 * default, DC favors MPC_SPLIT_DYNAMIC. 463 */ 464 enum pipe_split_policy { 465 /** 466 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 467 * pipe in order to bring the best trade-off between performance and 468 * power consumption. This is the recommended option. 469 */ 470 MPC_SPLIT_DYNAMIC = 0, 471 472 /** 473 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 474 * try any sort of split optimization. 475 */ 476 MPC_SPLIT_AVOID = 1, 477 478 /** 479 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 480 * optimize the pipe utilization when using a single display; if the 481 * user connects to a second display, DC will avoid pipe split. 482 */ 483 MPC_SPLIT_AVOID_MULT_DISP = 2, 484 }; 485 486 enum wm_report_mode { 487 WM_REPORT_DEFAULT = 0, 488 WM_REPORT_OVERRIDE = 1, 489 }; 490 enum dtm_pstate{ 491 dtm_level_p0 = 0,/*highest voltage*/ 492 dtm_level_p1, 493 dtm_level_p2, 494 dtm_level_p3, 495 dtm_level_p4,/*when active_display_count = 0*/ 496 }; 497 498 enum dcn_pwr_state { 499 DCN_PWR_STATE_UNKNOWN = -1, 500 DCN_PWR_STATE_MISSION_MODE = 0, 501 DCN_PWR_STATE_LOW_POWER = 3, 502 }; 503 504 enum dcn_zstate_support_state { 505 DCN_ZSTATE_SUPPORT_UNKNOWN, 506 DCN_ZSTATE_SUPPORT_ALLOW, 507 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 508 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 509 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 510 DCN_ZSTATE_SUPPORT_DISALLOW, 511 }; 512 513 /* 514 * struct dc_clocks - DC pipe clocks 515 * 516 * For any clocks that may differ per pipe only the max is stored in this 517 * structure 518 */ 519 struct dc_clocks { 520 int dispclk_khz; 521 int actual_dispclk_khz; 522 int dppclk_khz; 523 int actual_dppclk_khz; 524 int disp_dpp_voltage_level_khz; 525 int dcfclk_khz; 526 int socclk_khz; 527 int dcfclk_deep_sleep_khz; 528 int fclk_khz; 529 int phyclk_khz; 530 int dramclk_khz; 531 bool p_state_change_support; 532 enum dcn_zstate_support_state zstate_support; 533 bool dtbclk_en; 534 int ref_dtbclk_khz; 535 bool fclk_p_state_change_support; 536 enum dcn_pwr_state pwr_state; 537 /* 538 * Elements below are not compared for the purposes of 539 * optimization required 540 */ 541 bool prev_p_state_change_support; 542 bool fclk_prev_p_state_change_support; 543 int num_ways; 544 545 /* 546 * @fw_based_mclk_switching 547 * 548 * DC has a mechanism that leverage the variable refresh rate to switch 549 * memory clock in cases that we have a large latency to achieve the 550 * memory clock change and a short vblank window. DC has some 551 * requirements to enable this feature, and this field describes if the 552 * system support or not such a feature. 553 */ 554 bool fw_based_mclk_switching; 555 bool fw_based_mclk_switching_shut_down; 556 int prev_num_ways; 557 enum dtm_pstate dtm_level; 558 int max_supported_dppclk_khz; 559 int max_supported_dispclk_khz; 560 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 561 int bw_dispclk_khz; 562 }; 563 564 struct dc_bw_validation_profile { 565 bool enable; 566 567 unsigned long long total_ticks; 568 unsigned long long voltage_level_ticks; 569 unsigned long long watermark_ticks; 570 unsigned long long rq_dlg_ticks; 571 572 unsigned long long total_count; 573 unsigned long long skip_fast_count; 574 unsigned long long skip_pass_count; 575 unsigned long long skip_fail_count; 576 }; 577 578 #define BW_VAL_TRACE_SETUP() \ 579 unsigned long long end_tick = 0; \ 580 unsigned long long voltage_level_tick = 0; \ 581 unsigned long long watermark_tick = 0; \ 582 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 583 dm_get_timestamp(dc->ctx) : 0 584 585 #define BW_VAL_TRACE_COUNT() \ 586 if (dc->debug.bw_val_profile.enable) \ 587 dc->debug.bw_val_profile.total_count++ 588 589 #define BW_VAL_TRACE_SKIP(status) \ 590 if (dc->debug.bw_val_profile.enable) { \ 591 if (!voltage_level_tick) \ 592 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 593 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 594 } 595 596 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 597 if (dc->debug.bw_val_profile.enable) \ 598 voltage_level_tick = dm_get_timestamp(dc->ctx) 599 600 #define BW_VAL_TRACE_END_WATERMARKS() \ 601 if (dc->debug.bw_val_profile.enable) \ 602 watermark_tick = dm_get_timestamp(dc->ctx) 603 604 #define BW_VAL_TRACE_FINISH() \ 605 if (dc->debug.bw_val_profile.enable) { \ 606 end_tick = dm_get_timestamp(dc->ctx); \ 607 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 608 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 609 if (watermark_tick) { \ 610 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 611 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 612 } \ 613 } 614 615 union mem_low_power_enable_options { 616 struct { 617 bool vga: 1; 618 bool i2c: 1; 619 bool dmcu: 1; 620 bool dscl: 1; 621 bool cm: 1; 622 bool mpc: 1; 623 bool optc: 1; 624 bool vpg: 1; 625 bool afmt: 1; 626 } bits; 627 uint32_t u32All; 628 }; 629 630 union root_clock_optimization_options { 631 struct { 632 bool dpp: 1; 633 bool dsc: 1; 634 bool hdmistream: 1; 635 bool hdmichar: 1; 636 bool dpstream: 1; 637 bool symclk32_se: 1; 638 bool symclk32_le: 1; 639 bool symclk_fe: 1; 640 bool physymclk: 1; 641 bool dpiasymclk: 1; 642 uint32_t reserved: 22; 643 } bits; 644 uint32_t u32All; 645 }; 646 647 union fine_grain_clock_gating_enable_options { 648 struct { 649 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 650 bool dchub : 1; /* Display controller hub */ 651 bool dchubbub : 1; 652 bool dpp : 1; /* Display pipes and planes */ 653 bool opp : 1; /* Output pixel processing */ 654 bool optc : 1; /* Output pipe timing combiner */ 655 bool dio : 1; /* Display output */ 656 bool dwb : 1; /* Display writeback */ 657 bool mmhubbub : 1; /* Multimedia hub */ 658 bool dmu : 1; /* Display core management unit */ 659 bool az : 1; /* Azalia */ 660 bool dchvm : 1; 661 bool dsc : 1; /* Display stream compression */ 662 663 uint32_t reserved : 19; 664 } bits; 665 uint32_t u32All; 666 }; 667 668 enum pg_hw_pipe_resources { 669 PG_HUBP = 0, 670 PG_DPP, 671 PG_DSC, 672 PG_MPCC, 673 PG_OPP, 674 PG_OPTC, 675 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 676 }; 677 678 enum pg_hw_resources { 679 PG_DCCG = 0, 680 PG_DCIO, 681 PG_DIO, 682 PG_DCHUBBUB, 683 PG_DCHVM, 684 PG_DWB, 685 PG_HPO, 686 PG_HW_RESOURCES_NUM_ELEMENT 687 }; 688 689 struct pg_block_update { 690 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 691 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 692 }; 693 694 union dpia_debug_options { 695 struct { 696 uint32_t disable_dpia:1; /* bit 0 */ 697 uint32_t force_non_lttpr:1; /* bit 1 */ 698 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 699 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 700 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 701 uint32_t reserved:27; 702 } bits; 703 uint32_t raw; 704 }; 705 706 /* AUX wake work around options 707 * 0: enable/disable work around 708 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 709 * 15-2: reserved 710 * 31-16: timeout in ms 711 */ 712 union aux_wake_wa_options { 713 struct { 714 uint32_t enable_wa : 1; 715 uint32_t use_default_timeout : 1; 716 uint32_t rsvd: 14; 717 uint32_t timeout_ms : 16; 718 } bits; 719 uint32_t raw; 720 }; 721 722 struct dc_debug_data { 723 uint32_t ltFailCount; 724 uint32_t i2cErrorCount; 725 uint32_t auxErrorCount; 726 }; 727 728 struct dc_phy_addr_space_config { 729 struct { 730 uint64_t start_addr; 731 uint64_t end_addr; 732 uint64_t fb_top; 733 uint64_t fb_offset; 734 uint64_t fb_base; 735 uint64_t agp_top; 736 uint64_t agp_bot; 737 uint64_t agp_base; 738 } system_aperture; 739 740 struct { 741 uint64_t page_table_start_addr; 742 uint64_t page_table_end_addr; 743 uint64_t page_table_base_addr; 744 bool base_addr_is_mc_addr; 745 } gart_config; 746 747 bool valid; 748 bool is_hvm_enabled; 749 uint64_t page_table_default_page_addr; 750 }; 751 752 struct dc_virtual_addr_space_config { 753 uint64_t page_table_base_addr; 754 uint64_t page_table_start_addr; 755 uint64_t page_table_end_addr; 756 uint32_t page_table_block_size_in_bytes; 757 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 758 }; 759 760 struct dc_bounding_box_overrides { 761 int sr_exit_time_ns; 762 int sr_enter_plus_exit_time_ns; 763 int sr_exit_z8_time_ns; 764 int sr_enter_plus_exit_z8_time_ns; 765 int urgent_latency_ns; 766 int percent_of_ideal_drambw; 767 int dram_clock_change_latency_ns; 768 int dummy_clock_change_latency_ns; 769 int fclk_clock_change_latency_ns; 770 /* This forces a hard min on the DCFCLK we use 771 * for DML. Unlike the debug option for forcing 772 * DCFCLK, this override affects watermark calculations 773 */ 774 int min_dcfclk_mhz; 775 }; 776 777 struct dc_state; 778 struct resource_pool; 779 struct dce_hwseq; 780 struct link_service; 781 782 /* 783 * struct dc_debug_options - DC debug struct 784 * 785 * This struct provides a simple mechanism for developers to change some 786 * configurations, enable/disable features, and activate extra debug options. 787 * This can be very handy to narrow down whether some specific feature is 788 * causing an issue or not. 789 */ 790 struct dc_debug_options { 791 bool native422_support; 792 bool disable_dsc; 793 enum visual_confirm visual_confirm; 794 int visual_confirm_rect_height; 795 796 bool sanity_checks; 797 bool max_disp_clk; 798 bool surface_trace; 799 bool timing_trace; 800 bool clock_trace; 801 bool validation_trace; 802 bool bandwidth_calcs_trace; 803 int max_downscale_src_width; 804 805 /* stutter efficiency related */ 806 bool disable_stutter; 807 bool use_max_lb; 808 enum dcc_option disable_dcc; 809 810 /* 811 * @pipe_split_policy: Define which pipe split policy is used by the 812 * display core. 813 */ 814 enum pipe_split_policy pipe_split_policy; 815 bool force_single_disp_pipe_split; 816 bool voltage_align_fclk; 817 bool disable_min_fclk; 818 819 bool disable_dfs_bypass; 820 bool disable_dpp_power_gate; 821 bool disable_hubp_power_gate; 822 bool disable_dsc_power_gate; 823 bool disable_optc_power_gate; 824 int dsc_min_slice_height_override; 825 int dsc_bpp_increment_div; 826 bool disable_pplib_wm_range; 827 enum wm_report_mode pplib_wm_report_mode; 828 unsigned int min_disp_clk_khz; 829 unsigned int min_dpp_clk_khz; 830 unsigned int min_dram_clk_khz; 831 int sr_exit_time_dpm0_ns; 832 int sr_enter_plus_exit_time_dpm0_ns; 833 int sr_exit_time_ns; 834 int sr_enter_plus_exit_time_ns; 835 int sr_exit_z8_time_ns; 836 int sr_enter_plus_exit_z8_time_ns; 837 int urgent_latency_ns; 838 uint32_t underflow_assert_delay_us; 839 int percent_of_ideal_drambw; 840 int dram_clock_change_latency_ns; 841 bool optimized_watermark; 842 int always_scale; 843 bool disable_pplib_clock_request; 844 bool disable_clock_gate; 845 bool disable_mem_low_power; 846 bool pstate_enabled; 847 bool disable_dmcu; 848 bool force_abm_enable; 849 bool disable_stereo_support; 850 bool vsr_support; 851 bool performance_trace; 852 bool az_endpoint_mute_only; 853 bool always_use_regamma; 854 bool recovery_enabled; 855 bool avoid_vbios_exec_table; 856 bool scl_reset_length10; 857 bool hdmi20_disable; 858 bool skip_detection_link_training; 859 uint32_t edid_read_retry_times; 860 unsigned int force_odm_combine; //bit vector based on otg inst 861 unsigned int seamless_boot_odm_combine; 862 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 863 int minimum_z8_residency_time; 864 bool disable_z9_mpc; 865 unsigned int force_fclk_khz; 866 bool enable_tri_buf; 867 bool dmub_offload_enabled; 868 bool dmcub_emulation; 869 bool disable_idle_power_optimizations; 870 unsigned int mall_size_override; 871 unsigned int mall_additional_timer_percent; 872 bool mall_error_as_fatal; 873 bool dmub_command_table; /* for testing only */ 874 struct dc_bw_validation_profile bw_val_profile; 875 bool disable_fec; 876 bool disable_48mhz_pwrdwn; 877 /* This forces a hard min on the DCFCLK requested to SMU/PP 878 * watermarks are not affected. 879 */ 880 unsigned int force_min_dcfclk_mhz; 881 int dwb_fi_phase; 882 bool disable_timing_sync; 883 bool cm_in_bypass; 884 int force_clock_mode;/*every mode change.*/ 885 886 bool disable_dram_clock_change_vactive_support; 887 bool validate_dml_output; 888 bool enable_dmcub_surface_flip; 889 bool usbc_combo_phy_reset_wa; 890 bool enable_dram_clock_change_one_display_vactive; 891 /* TODO - remove once tested */ 892 bool legacy_dp2_lt; 893 bool set_mst_en_for_sst; 894 bool disable_uhbr; 895 bool force_dp2_lt_fallback_method; 896 bool ignore_cable_id; 897 union mem_low_power_enable_options enable_mem_low_power; 898 union root_clock_optimization_options root_clock_optimization; 899 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 900 bool hpo_optimization; 901 bool force_vblank_alignment; 902 903 /* Enable dmub aux for legacy ddc */ 904 bool enable_dmub_aux_for_legacy_ddc; 905 bool disable_fams; 906 bool disable_fams_gaming; 907 /* FEC/PSR1 sequence enable delay in 100us */ 908 uint8_t fec_enable_delay_in100us; 909 bool enable_driver_sequence_debug; 910 enum det_size crb_alloc_policy; 911 int crb_alloc_policy_min_disp_count; 912 bool disable_z10; 913 unsigned int disable_ips; 914 bool enable_z9_disable_interface; 915 bool psr_skip_crtc_disable; 916 union dpia_debug_options dpia_debug; 917 bool disable_fixed_vs_aux_timeout_wa; 918 uint32_t fixed_vs_aux_delay_config_wa; 919 bool force_disable_subvp; 920 bool force_subvp_mclk_switch; 921 bool allow_sw_cursor_fallback; 922 unsigned int force_subvp_num_ways; 923 unsigned int force_mall_ss_num_ways; 924 bool alloc_extra_way_for_cursor; 925 uint32_t subvp_extra_lines; 926 bool force_usr_allow; 927 /* uses value at boot and disables switch */ 928 bool disable_dtb_ref_clk_switch; 929 bool extended_blank_optimization; 930 union aux_wake_wa_options aux_wake_wa; 931 uint32_t mst_start_top_delay; 932 uint8_t psr_power_use_phy_fsm; 933 enum dml_hostvm_override_opts dml_hostvm_override; 934 bool dml_disallow_alternate_prefetch_modes; 935 bool use_legacy_soc_bb_mechanism; 936 bool exit_idle_opt_for_cursor_updates; 937 bool enable_single_display_2to1_odm_policy; 938 bool enable_double_buffered_dsc_pg_support; 939 bool enable_dp_dig_pixel_rate_div_policy; 940 enum lttpr_mode lttpr_mode_override; 941 unsigned int dsc_delay_factor_wa_x1000; 942 unsigned int min_prefetch_in_strobe_ns; 943 bool disable_unbounded_requesting; 944 bool dig_fifo_off_in_blank; 945 bool temp_mst_deallocation_sequence; 946 bool override_dispclk_programming; 947 bool otg_crc_db; 948 bool disallow_dispclk_dppclk_ds; 949 bool disable_fpo_optimizations; 950 bool support_eDP1_5; 951 uint32_t fpo_vactive_margin_us; 952 bool disable_fpo_vactive; 953 bool disable_boot_optimizations; 954 bool override_odm_optimization; 955 bool minimize_dispclk_using_odm; 956 bool disable_subvp_high_refresh; 957 bool disable_dp_plus_plus_wa; 958 uint32_t fpo_vactive_min_active_margin_us; 959 uint32_t fpo_vactive_max_blank_us; 960 bool enable_hpo_pg_support; 961 bool enable_legacy_fast_update; 962 bool disable_dc_mode_overwrite; 963 bool replay_skip_crtc_disabled; 964 bool ignore_pg;/*do nothing, let pmfw control it*/ 965 bool psp_disabled_wa; 966 }; 967 968 struct gpu_info_soc_bounding_box_v1_0; 969 970 /* Generic structure that can be used to query properties of DC. More fields 971 * can be added as required. 972 */ 973 struct dc_current_properties { 974 unsigned int cursor_size_limit; 975 }; 976 977 struct dc { 978 struct dc_debug_options debug; 979 struct dc_versions versions; 980 struct dc_caps caps; 981 struct dc_cap_funcs cap_funcs; 982 struct dc_config config; 983 struct dc_bounding_box_overrides bb_overrides; 984 struct dc_bug_wa work_arounds; 985 struct dc_context *ctx; 986 struct dc_phy_addr_space_config vm_pa_config; 987 988 uint8_t link_count; 989 struct dc_link *links[MAX_PIPES * 2]; 990 struct link_service *link_srv; 991 992 struct dc_state *current_state; 993 struct resource_pool *res_pool; 994 995 struct clk_mgr *clk_mgr; 996 997 /* Display Engine Clock levels */ 998 struct dm_pp_clock_levels sclk_lvls; 999 1000 /* Inputs into BW and WM calculations. */ 1001 struct bw_calcs_dceip *bw_dceip; 1002 struct bw_calcs_vbios *bw_vbios; 1003 struct dcn_soc_bounding_box *dcn_soc; 1004 struct dcn_ip_params *dcn_ip; 1005 struct display_mode_lib dml; 1006 1007 /* HW functions */ 1008 struct hw_sequencer_funcs hwss; 1009 struct dce_hwseq *hwseq; 1010 1011 /* Require to optimize clocks and bandwidth for added/removed planes */ 1012 bool optimized_required; 1013 bool wm_optimized_required; 1014 bool idle_optimizations_allowed; 1015 bool enable_c20_dtm_b0; 1016 1017 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1018 1019 /* FBC compressor */ 1020 struct compressor *fbc_compressor; 1021 1022 struct dc_debug_data debug_data; 1023 struct dpcd_vendor_signature vendor_signature; 1024 1025 const char *build_id; 1026 struct vm_helper *vm_helper; 1027 1028 uint32_t *dcn_reg_offsets; 1029 uint32_t *nbio_reg_offsets; 1030 uint32_t *clk_reg_offsets; 1031 1032 /* Scratch memory */ 1033 struct { 1034 struct { 1035 /* 1036 * For matching clock_limits table in driver with table 1037 * from PMFW. 1038 */ 1039 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1040 } update_bw_bounding_box; 1041 } scratch; 1042 }; 1043 1044 enum frame_buffer_mode { 1045 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1046 FRAME_BUFFER_MODE_ZFB_ONLY, 1047 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1048 } ; 1049 1050 struct dchub_init_data { 1051 int64_t zfb_phys_addr_base; 1052 int64_t zfb_mc_base_addr; 1053 uint64_t zfb_size_in_byte; 1054 enum frame_buffer_mode fb_mode; 1055 bool dchub_initialzied; 1056 bool dchub_info_valid; 1057 }; 1058 1059 struct dc_init_data { 1060 struct hw_asic_id asic_id; 1061 void *driver; /* ctx */ 1062 struct cgs_device *cgs_device; 1063 struct dc_bounding_box_overrides bb_overrides; 1064 1065 int num_virtual_links; 1066 /* 1067 * If 'vbios_override' not NULL, it will be called instead 1068 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1069 */ 1070 struct dc_bios *vbios_override; 1071 enum dce_environment dce_environment; 1072 1073 struct dmub_offload_funcs *dmub_if; 1074 struct dc_reg_helper_state *dmub_offload; 1075 1076 struct dc_config flags; 1077 uint64_t log_mask; 1078 1079 struct dpcd_vendor_signature vendor_signature; 1080 bool force_smu_not_present; 1081 /* 1082 * IP offset for run time initializaion of register addresses 1083 * 1084 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1085 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1086 * before them. 1087 */ 1088 uint32_t *dcn_reg_offsets; 1089 uint32_t *nbio_reg_offsets; 1090 uint32_t *clk_reg_offsets; 1091 }; 1092 1093 struct dc_callback_init { 1094 struct cp_psp cp_psp; 1095 }; 1096 1097 struct dc *dc_create(const struct dc_init_data *init_params); 1098 void dc_hardware_init(struct dc *dc); 1099 1100 int dc_get_vmid_use_vector(struct dc *dc); 1101 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1102 /* Returns the number of vmids supported */ 1103 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1104 void dc_init_callbacks(struct dc *dc, 1105 const struct dc_callback_init *init_params); 1106 void dc_deinit_callbacks(struct dc *dc); 1107 void dc_destroy(struct dc **dc); 1108 1109 /* Surface Interfaces */ 1110 1111 enum { 1112 TRANSFER_FUNC_POINTS = 1025 1113 }; 1114 1115 struct dc_hdr_static_metadata { 1116 /* display chromaticities and white point in units of 0.00001 */ 1117 unsigned int chromaticity_green_x; 1118 unsigned int chromaticity_green_y; 1119 unsigned int chromaticity_blue_x; 1120 unsigned int chromaticity_blue_y; 1121 unsigned int chromaticity_red_x; 1122 unsigned int chromaticity_red_y; 1123 unsigned int chromaticity_white_point_x; 1124 unsigned int chromaticity_white_point_y; 1125 1126 uint32_t min_luminance; 1127 uint32_t max_luminance; 1128 uint32_t maximum_content_light_level; 1129 uint32_t maximum_frame_average_light_level; 1130 }; 1131 1132 enum dc_transfer_func_type { 1133 TF_TYPE_PREDEFINED, 1134 TF_TYPE_DISTRIBUTED_POINTS, 1135 TF_TYPE_BYPASS, 1136 TF_TYPE_HWPWL 1137 }; 1138 1139 struct dc_transfer_func_distributed_points { 1140 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1141 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1142 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1143 1144 uint16_t end_exponent; 1145 uint16_t x_point_at_y1_red; 1146 uint16_t x_point_at_y1_green; 1147 uint16_t x_point_at_y1_blue; 1148 }; 1149 1150 enum dc_transfer_func_predefined { 1151 TRANSFER_FUNCTION_SRGB, 1152 TRANSFER_FUNCTION_BT709, 1153 TRANSFER_FUNCTION_PQ, 1154 TRANSFER_FUNCTION_LINEAR, 1155 TRANSFER_FUNCTION_UNITY, 1156 TRANSFER_FUNCTION_HLG, 1157 TRANSFER_FUNCTION_HLG12, 1158 TRANSFER_FUNCTION_GAMMA22, 1159 TRANSFER_FUNCTION_GAMMA24, 1160 TRANSFER_FUNCTION_GAMMA26 1161 }; 1162 1163 1164 struct dc_transfer_func { 1165 struct kref refcount; 1166 enum dc_transfer_func_type type; 1167 enum dc_transfer_func_predefined tf; 1168 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1169 uint32_t sdr_ref_white_level; 1170 union { 1171 struct pwl_params pwl; 1172 struct dc_transfer_func_distributed_points tf_pts; 1173 }; 1174 }; 1175 1176 1177 union dc_3dlut_state { 1178 struct { 1179 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1180 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1181 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1182 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1183 uint32_t mpc_rmu1_mux:4; 1184 uint32_t mpc_rmu2_mux:4; 1185 uint32_t reserved:15; 1186 } bits; 1187 uint32_t raw; 1188 }; 1189 1190 1191 struct dc_3dlut { 1192 struct kref refcount; 1193 struct tetrahedral_params lut_3d; 1194 struct fixed31_32 hdr_multiplier; 1195 union dc_3dlut_state state; 1196 }; 1197 /* 1198 * This structure is filled in by dc_surface_get_status and contains 1199 * the last requested address and the currently active address so the called 1200 * can determine if there are any outstanding flips 1201 */ 1202 struct dc_plane_status { 1203 struct dc_plane_address requested_address; 1204 struct dc_plane_address current_address; 1205 bool is_flip_pending; 1206 bool is_right_eye; 1207 }; 1208 1209 union surface_update_flags { 1210 1211 struct { 1212 uint32_t addr_update:1; 1213 /* Medium updates */ 1214 uint32_t dcc_change:1; 1215 uint32_t color_space_change:1; 1216 uint32_t horizontal_mirror_change:1; 1217 uint32_t per_pixel_alpha_change:1; 1218 uint32_t global_alpha_change:1; 1219 uint32_t hdr_mult:1; 1220 uint32_t rotation_change:1; 1221 uint32_t swizzle_change:1; 1222 uint32_t scaling_change:1; 1223 uint32_t position_change:1; 1224 uint32_t in_transfer_func_change:1; 1225 uint32_t input_csc_change:1; 1226 uint32_t coeff_reduction_change:1; 1227 uint32_t output_tf_change:1; 1228 uint32_t pixel_format_change:1; 1229 uint32_t plane_size_change:1; 1230 uint32_t gamut_remap_change:1; 1231 1232 /* Full updates */ 1233 uint32_t new_plane:1; 1234 uint32_t bpp_change:1; 1235 uint32_t gamma_change:1; 1236 uint32_t bandwidth_change:1; 1237 uint32_t clock_change:1; 1238 uint32_t stereo_format_change:1; 1239 uint32_t lut_3d:1; 1240 uint32_t tmz_changed:1; 1241 uint32_t full_update:1; 1242 } bits; 1243 1244 uint32_t raw; 1245 }; 1246 1247 struct dc_plane_state { 1248 struct dc_plane_address address; 1249 struct dc_plane_flip_time time; 1250 bool triplebuffer_flips; 1251 struct scaling_taps scaling_quality; 1252 struct rect src_rect; 1253 struct rect dst_rect; 1254 struct rect clip_rect; 1255 1256 struct plane_size plane_size; 1257 union dc_tiling_info tiling_info; 1258 1259 struct dc_plane_dcc_param dcc; 1260 1261 struct dc_gamma *gamma_correction; 1262 struct dc_transfer_func *in_transfer_func; 1263 struct dc_bias_and_scale *bias_and_scale; 1264 struct dc_csc_transform input_csc_color_matrix; 1265 struct fixed31_32 coeff_reduction_factor; 1266 struct fixed31_32 hdr_mult; 1267 struct colorspace_transform gamut_remap_matrix; 1268 1269 // TODO: No longer used, remove 1270 struct dc_hdr_static_metadata hdr_static_ctx; 1271 1272 enum dc_color_space color_space; 1273 1274 struct dc_3dlut *lut3d_func; 1275 struct dc_transfer_func *in_shaper_func; 1276 struct dc_transfer_func *blend_tf; 1277 1278 struct dc_transfer_func *gamcor_tf; 1279 enum surface_pixel_format format; 1280 enum dc_rotation_angle rotation; 1281 enum plane_stereo_format stereo_format; 1282 1283 bool is_tiling_rotated; 1284 bool per_pixel_alpha; 1285 bool pre_multiplied_alpha; 1286 bool global_alpha; 1287 int global_alpha_value; 1288 bool visible; 1289 bool flip_immediate; 1290 bool horizontal_mirror; 1291 int layer_index; 1292 1293 union surface_update_flags update_flags; 1294 bool flip_int_enabled; 1295 bool skip_manual_trigger; 1296 1297 /* private to DC core */ 1298 struct dc_plane_status status; 1299 struct dc_context *ctx; 1300 1301 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1302 bool force_full_update; 1303 1304 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1305 1306 /* private to dc_surface.c */ 1307 enum dc_irq_source irq_source; 1308 struct kref refcount; 1309 struct tg_color visual_confirm_color; 1310 1311 bool is_statically_allocated; 1312 }; 1313 1314 struct dc_plane_info { 1315 struct plane_size plane_size; 1316 union dc_tiling_info tiling_info; 1317 struct dc_plane_dcc_param dcc; 1318 enum surface_pixel_format format; 1319 enum dc_rotation_angle rotation; 1320 enum plane_stereo_format stereo_format; 1321 enum dc_color_space color_space; 1322 bool horizontal_mirror; 1323 bool visible; 1324 bool per_pixel_alpha; 1325 bool pre_multiplied_alpha; 1326 bool global_alpha; 1327 int global_alpha_value; 1328 bool input_csc_enabled; 1329 int layer_index; 1330 }; 1331 1332 struct dc_scaling_info { 1333 struct rect src_rect; 1334 struct rect dst_rect; 1335 struct rect clip_rect; 1336 struct scaling_taps scaling_quality; 1337 }; 1338 1339 struct dc_fast_update { 1340 const struct dc_flip_addrs *flip_addr; 1341 const struct dc_gamma *gamma; 1342 const struct colorspace_transform *gamut_remap_matrix; 1343 const struct dc_csc_transform *input_csc_color_matrix; 1344 const struct fixed31_32 *coeff_reduction_factor; 1345 struct dc_transfer_func *out_transfer_func; 1346 struct dc_csc_transform *output_csc_transform; 1347 }; 1348 1349 struct dc_surface_update { 1350 struct dc_plane_state *surface; 1351 1352 /* isr safe update parameters. null means no updates */ 1353 const struct dc_flip_addrs *flip_addr; 1354 const struct dc_plane_info *plane_info; 1355 const struct dc_scaling_info *scaling_info; 1356 struct fixed31_32 hdr_mult; 1357 /* following updates require alloc/sleep/spin that is not isr safe, 1358 * null means no updates 1359 */ 1360 const struct dc_gamma *gamma; 1361 const struct dc_transfer_func *in_transfer_func; 1362 1363 const struct dc_csc_transform *input_csc_color_matrix; 1364 const struct fixed31_32 *coeff_reduction_factor; 1365 const struct dc_transfer_func *func_shaper; 1366 const struct dc_3dlut *lut3d_func; 1367 const struct dc_transfer_func *blend_tf; 1368 const struct colorspace_transform *gamut_remap_matrix; 1369 }; 1370 1371 /* 1372 * Create a new surface with default parameters; 1373 */ 1374 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1375 const struct dc_plane_status *dc_plane_get_status( 1376 const struct dc_plane_state *plane_state); 1377 1378 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1379 void dc_plane_state_release(struct dc_plane_state *plane_state); 1380 1381 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1382 void dc_gamma_release(struct dc_gamma **dc_gamma); 1383 struct dc_gamma *dc_create_gamma(void); 1384 1385 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1386 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1387 struct dc_transfer_func *dc_create_transfer_func(void); 1388 1389 struct dc_3dlut *dc_create_3dlut_func(void); 1390 void dc_3dlut_func_release(struct dc_3dlut *lut); 1391 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1392 1393 void dc_post_update_surfaces_to_stream( 1394 struct dc *dc); 1395 1396 #include "dc_stream.h" 1397 1398 /** 1399 * struct dc_validation_set - Struct to store surface/stream associations for validation 1400 */ 1401 struct dc_validation_set { 1402 /** 1403 * @stream: Stream state properties 1404 */ 1405 struct dc_stream_state *stream; 1406 1407 /** 1408 * @plane_states: Surface state 1409 */ 1410 struct dc_plane_state *plane_states[MAX_SURFACES]; 1411 1412 /** 1413 * @plane_count: Total of active planes 1414 */ 1415 uint8_t plane_count; 1416 }; 1417 1418 bool dc_validate_boot_timing(const struct dc *dc, 1419 const struct dc_sink *sink, 1420 struct dc_crtc_timing *crtc_timing); 1421 1422 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1423 1424 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1425 1426 enum dc_status dc_validate_with_context(struct dc *dc, 1427 const struct dc_validation_set set[], 1428 int set_count, 1429 struct dc_state *context, 1430 bool fast_validate); 1431 1432 bool dc_set_generic_gpio_for_stereo(bool enable, 1433 struct gpio_service *gpio_service); 1434 1435 /* 1436 * fast_validate: we return after determining if we can support the new state, 1437 * but before we populate the programming info 1438 */ 1439 enum dc_status dc_validate_global_state( 1440 struct dc *dc, 1441 struct dc_state *new_ctx, 1442 bool fast_validate); 1443 1444 1445 void dc_resource_state_construct( 1446 const struct dc *dc, 1447 struct dc_state *dst_ctx); 1448 1449 bool dc_acquire_release_mpc_3dlut( 1450 struct dc *dc, bool acquire, 1451 struct dc_stream_state *stream, 1452 struct dc_3dlut **lut, 1453 struct dc_transfer_func **shaper); 1454 1455 void dc_resource_state_copy_construct( 1456 const struct dc_state *src_ctx, 1457 struct dc_state *dst_ctx); 1458 1459 void dc_resource_state_copy_construct_current( 1460 const struct dc *dc, 1461 struct dc_state *dst_ctx); 1462 1463 void dc_resource_state_destruct(struct dc_state *context); 1464 1465 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1466 1467 enum dc_status dc_commit_streams(struct dc *dc, 1468 struct dc_stream_state *streams[], 1469 uint8_t stream_count); 1470 1471 struct dc_state *dc_create_state(struct dc *dc); 1472 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1473 void dc_retain_state(struct dc_state *context); 1474 void dc_release_state(struct dc_state *context); 1475 1476 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1477 struct dc_stream_state *stream, 1478 int mpcc_inst); 1479 1480 1481 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1482 1483 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1484 1485 /* The function returns minimum bandwidth required to drive a given timing 1486 * return - minimum required timing bandwidth in kbps. 1487 */ 1488 uint32_t dc_bandwidth_in_kbps_from_timing( 1489 const struct dc_crtc_timing *timing, 1490 const enum dc_link_encoding_format link_encoding); 1491 1492 /* Link Interfaces */ 1493 /* 1494 * A link contains one or more sinks and their connected status. 1495 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1496 */ 1497 struct dc_link { 1498 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1499 unsigned int sink_count; 1500 struct dc_sink *local_sink; 1501 unsigned int link_index; 1502 enum dc_connection_type type; 1503 enum signal_type connector_signal; 1504 enum dc_irq_source irq_source_hpd; 1505 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1506 1507 bool is_hpd_filter_disabled; 1508 bool dp_ss_off; 1509 1510 /** 1511 * @link_state_valid: 1512 * 1513 * If there is no link and local sink, this variable should be set to 1514 * false. Otherwise, it should be set to true; usually, the function 1515 * core_link_enable_stream sets this field to true. 1516 */ 1517 bool link_state_valid; 1518 bool aux_access_disabled; 1519 bool sync_lt_in_progress; 1520 bool skip_stream_reenable; 1521 bool is_internal_display; 1522 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1523 bool is_dig_mapping_flexible; 1524 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1525 bool is_hpd_pending; /* Indicates a new received hpd */ 1526 bool is_automated; /* Indicates automated testing */ 1527 1528 bool edp_sink_present; 1529 1530 struct dp_trace dp_trace; 1531 1532 /* caps is the same as reported_link_cap. link_traing use 1533 * reported_link_cap. Will clean up. TODO 1534 */ 1535 struct dc_link_settings reported_link_cap; 1536 struct dc_link_settings verified_link_cap; 1537 struct dc_link_settings cur_link_settings; 1538 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1539 struct dc_link_settings preferred_link_setting; 1540 /* preferred_training_settings are override values that 1541 * come from DM. DM is responsible for the memory 1542 * management of the override pointers. 1543 */ 1544 struct dc_link_training_overrides preferred_training_settings; 1545 struct dp_audio_test_data audio_test_data; 1546 1547 uint8_t ddc_hw_inst; 1548 1549 uint8_t hpd_src; 1550 1551 uint8_t link_enc_hw_inst; 1552 /* DIG link encoder ID. Used as index in link encoder resource pool. 1553 * For links with fixed mapping to DIG, this is not changed after dc_link 1554 * object creation. 1555 */ 1556 enum engine_id eng_id; 1557 enum engine_id dpia_preferred_eng_id; 1558 1559 bool test_pattern_enabled; 1560 enum dp_test_pattern current_test_pattern; 1561 union compliance_test_state compliance_test_state; 1562 1563 void *priv; 1564 1565 struct ddc_service *ddc; 1566 1567 enum dp_panel_mode panel_mode; 1568 bool aux_mode; 1569 1570 /* Private to DC core */ 1571 1572 const struct dc *dc; 1573 1574 struct dc_context *ctx; 1575 1576 struct panel_cntl *panel_cntl; 1577 struct link_encoder *link_enc; 1578 struct graphics_object_id link_id; 1579 /* Endpoint type distinguishes display endpoints which do not have entries 1580 * in the BIOS connector table from those that do. Helps when tracking link 1581 * encoder to display endpoint assignments. 1582 */ 1583 enum display_endpoint_type ep_type; 1584 union ddi_channel_mapping ddi_channel_mapping; 1585 struct connector_device_tag_info device_tag; 1586 struct dpcd_caps dpcd_caps; 1587 uint32_t dongle_max_pix_clk; 1588 unsigned short chip_caps; 1589 unsigned int dpcd_sink_count; 1590 struct hdcp_caps hdcp_caps; 1591 enum edp_revision edp_revision; 1592 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1593 1594 struct backlight_settings backlight_settings; 1595 struct psr_settings psr_settings; 1596 1597 struct replay_settings replay_settings; 1598 1599 /* Drive settings read from integrated info table */ 1600 struct dc_lane_settings bios_forced_drive_settings; 1601 1602 /* Vendor specific LTTPR workaround variables */ 1603 uint8_t vendor_specific_lttpr_link_rate_wa; 1604 bool apply_vendor_specific_lttpr_link_rate_wa; 1605 1606 /* MST record stream using this link */ 1607 struct link_flags { 1608 bool dp_keep_receiver_powered; 1609 bool dp_skip_DID2; 1610 bool dp_skip_reset_segment; 1611 bool dp_skip_fs_144hz; 1612 bool dp_mot_reset_segment; 1613 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1614 bool dpia_mst_dsc_always_on; 1615 /* Forced DPIA into TBT3 compatibility mode. */ 1616 bool dpia_forced_tbt3_mode; 1617 bool dongle_mode_timing_override; 1618 bool blank_stream_on_ocs_change; 1619 bool read_dpcd204h_on_irq_hpd; 1620 } wa_flags; 1621 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1622 1623 struct dc_link_status link_status; 1624 struct dprx_states dprx_states; 1625 1626 struct gpio *hpd_gpio; 1627 enum dc_link_fec_state fec_state; 1628 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1629 1630 struct dc_panel_config panel_config; 1631 struct phy_state phy_state; 1632 // BW ALLOCATON USB4 ONLY 1633 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1634 bool skip_implict_edp_power_control; 1635 }; 1636 1637 /* Return an enumerated dc_link. 1638 * dc_link order is constant and determined at 1639 * boot time. They cannot be created or destroyed. 1640 * Use dc_get_caps() to get number of links. 1641 */ 1642 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1643 1644 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1645 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1646 const struct dc_link *link, 1647 unsigned int *inst_out); 1648 1649 /* Return an array of link pointers to edp links. */ 1650 void dc_get_edp_links(const struct dc *dc, 1651 struct dc_link **edp_links, 1652 int *edp_num); 1653 1654 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1655 bool powerOn); 1656 1657 /* The function initiates detection handshake over the given link. It first 1658 * determines if there are display connections over the link. If so it initiates 1659 * detection protocols supported by the connected receiver device. The function 1660 * contains protocol specific handshake sequences which are sometimes mandatory 1661 * to establish a proper connection between TX and RX. So it is always 1662 * recommended to call this function as the first link operation upon HPD event 1663 * or power up event. Upon completion, the function will update link structure 1664 * in place based on latest RX capabilities. The function may also cause dpms 1665 * to be reset to off for all currently enabled streams to the link. It is DM's 1666 * responsibility to serialize detection and DPMS updates. 1667 * 1668 * @reason - Indicate which event triggers this detection. dc may customize 1669 * detection flow depending on the triggering events. 1670 * return false - if detection is not fully completed. This could happen when 1671 * there is an unrecoverable error during detection or detection is partially 1672 * completed (detection has been delegated to dm mst manager ie. 1673 * link->connection_type == dc_connection_mst_branch when returning false). 1674 * return true - detection is completed, link has been fully updated with latest 1675 * detection result. 1676 */ 1677 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1678 1679 struct dc_sink_init_data; 1680 1681 /* When link connection type is dc_connection_mst_branch, remote sink can be 1682 * added to the link. The interface creates a remote sink and associates it with 1683 * current link. The sink will be retained by link until remove remote sink is 1684 * called. 1685 * 1686 * @dc_link - link the remote sink will be added to. 1687 * @edid - byte array of EDID raw data. 1688 * @len - size of the edid in byte 1689 * @init_data - 1690 */ 1691 struct dc_sink *dc_link_add_remote_sink( 1692 struct dc_link *dc_link, 1693 const uint8_t *edid, 1694 int len, 1695 struct dc_sink_init_data *init_data); 1696 1697 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1698 * @link - link the sink should be removed from 1699 * @sink - sink to be removed. 1700 */ 1701 void dc_link_remove_remote_sink( 1702 struct dc_link *link, 1703 struct dc_sink *sink); 1704 1705 /* Enable HPD interrupt handler for a given link */ 1706 void dc_link_enable_hpd(const struct dc_link *link); 1707 1708 /* Disable HPD interrupt handler for a given link */ 1709 void dc_link_disable_hpd(const struct dc_link *link); 1710 1711 /* determine if there is a sink connected to the link 1712 * 1713 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1714 * return - false if an unexpected error occurs, true otherwise. 1715 * 1716 * NOTE: This function doesn't detect downstream sink connections i.e 1717 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1718 * return dc_connection_single if the branch device is connected despite of 1719 * downstream sink's connection status. 1720 */ 1721 bool dc_link_detect_connection_type(struct dc_link *link, 1722 enum dc_connection_type *type); 1723 1724 /* query current hpd pin value 1725 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1726 * 1727 */ 1728 bool dc_link_get_hpd_state(struct dc_link *link); 1729 1730 /* Getter for cached link status from given link */ 1731 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1732 1733 /* enable/disable hardware HPD filter. 1734 * 1735 * @link - The link the HPD pin is associated with. 1736 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1737 * handler once after no HPD change has been detected within dc default HPD 1738 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1739 * pulses within default HPD interval, no HPD event will be received until HPD 1740 * toggles have stopped. Then HPD event will be queued to irq handler once after 1741 * dc default HPD filtering interval since last HPD event. 1742 * 1743 * @enable = false - disable hardware HPD filter. HPD event will be queued 1744 * immediately to irq handler after no HPD change has been detected within 1745 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1746 */ 1747 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1748 1749 /* submit i2c read/write payloads through ddc channel 1750 * @link_index - index to a link with ddc in i2c mode 1751 * @cmd - i2c command structure 1752 * return - true if success, false otherwise. 1753 */ 1754 bool dc_submit_i2c( 1755 struct dc *dc, 1756 uint32_t link_index, 1757 struct i2c_command *cmd); 1758 1759 /* submit i2c read/write payloads through oem channel 1760 * @link_index - index to a link with ddc in i2c mode 1761 * @cmd - i2c command structure 1762 * return - true if success, false otherwise. 1763 */ 1764 bool dc_submit_i2c_oem( 1765 struct dc *dc, 1766 struct i2c_command *cmd); 1767 1768 enum aux_return_code_type; 1769 /* Attempt to transfer the given aux payload. This function does not perform 1770 * retries or handle error states. The reply is returned in the payload->reply 1771 * and the result through operation_result. Returns the number of bytes 1772 * transferred,or -1 on a failure. 1773 */ 1774 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1775 struct aux_payload *payload, 1776 enum aux_return_code_type *operation_result); 1777 1778 bool dc_is_oem_i2c_device_present( 1779 struct dc *dc, 1780 size_t slave_address 1781 ); 1782 1783 /* return true if the connected receiver supports the hdcp version */ 1784 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1785 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1786 1787 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1788 * 1789 * TODO - When defer_handling is true the function will have a different purpose. 1790 * It no longer does complete hpd rx irq handling. We should create a separate 1791 * interface specifically for this case. 1792 * 1793 * Return: 1794 * true - Downstream port status changed. DM should call DC to do the 1795 * detection. 1796 * false - no change in Downstream port status. No further action required 1797 * from DM. 1798 */ 1799 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1800 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1801 bool defer_handling, bool *has_left_work); 1802 /* handle DP specs define test automation sequence*/ 1803 void dc_link_dp_handle_automated_test(struct dc_link *link); 1804 1805 /* handle DP Link loss sequence and try to recover RX link loss with best 1806 * effort 1807 */ 1808 void dc_link_dp_handle_link_loss(struct dc_link *link); 1809 1810 /* Determine if hpd rx irq should be handled or ignored 1811 * return true - hpd rx irq should be handled. 1812 * return false - it is safe to ignore hpd rx irq event 1813 */ 1814 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1815 1816 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1817 * @link - link the hpd irq data associated with 1818 * @hpd_irq_dpcd_data - input hpd irq data 1819 * return - true if hpd irq data indicates a link lost 1820 */ 1821 bool dc_link_check_link_loss_status(struct dc_link *link, 1822 union hpd_irq_data *hpd_irq_dpcd_data); 1823 1824 /* Read hpd rx irq data from a given link 1825 * @link - link where the hpd irq data should be read from 1826 * @irq_data - output hpd irq data 1827 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1828 * read has failed. 1829 */ 1830 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1831 struct dc_link *link, 1832 union hpd_irq_data *irq_data); 1833 1834 /* The function clears recorded DP RX states in the link. DM should call this 1835 * function when it is resuming from S3 power state to previously connected links. 1836 * 1837 * TODO - in the future we should consider to expand link resume interface to 1838 * support clearing previous rx states. So we don't have to rely on dm to call 1839 * this interface explicitly. 1840 */ 1841 void dc_link_clear_dprx_states(struct dc_link *link); 1842 1843 /* Destruct the mst topology of the link and reset the allocated payload table 1844 * 1845 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1846 * still wants to reset MST topology on an unplug event */ 1847 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1848 1849 /* The function calculates effective DP link bandwidth when a given link is 1850 * using the given link settings. 1851 * 1852 * return - total effective link bandwidth in kbps. 1853 */ 1854 uint32_t dc_link_bandwidth_kbps( 1855 const struct dc_link *link, 1856 const struct dc_link_settings *link_setting); 1857 1858 /* The function takes a snapshot of current link resource allocation state 1859 * @dc: pointer to dc of the dm calling this 1860 * @map: a dc link resource snapshot defined internally to dc. 1861 * 1862 * DM needs to capture a snapshot of current link resource allocation mapping 1863 * and store it in its persistent storage. 1864 * 1865 * Some of the link resource is using first come first serve policy. 1866 * The allocation mapping depends on original hotplug order. This information 1867 * is lost after driver is loaded next time. The snapshot is used in order to 1868 * restore link resource to its previous state so user will get consistent 1869 * link capability allocation across reboot. 1870 * 1871 */ 1872 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1873 1874 /* This function restores link resource allocation state from a snapshot 1875 * @dc: pointer to dc of the dm calling this 1876 * @map: a dc link resource snapshot defined internally to dc. 1877 * 1878 * DM needs to call this function after initial link detection on boot and 1879 * before first commit streams to restore link resource allocation state 1880 * from previous boot session. 1881 * 1882 * Some of the link resource is using first come first serve policy. 1883 * The allocation mapping depends on original hotplug order. This information 1884 * is lost after driver is loaded next time. The snapshot is used in order to 1885 * restore link resource to its previous state so user will get consistent 1886 * link capability allocation across reboot. 1887 * 1888 */ 1889 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1890 1891 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1892 * interface i.e stream_update->dsc_config 1893 */ 1894 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1895 1896 /* translate a raw link rate data to bandwidth in kbps */ 1897 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1898 1899 /* determine the optimal bandwidth given link and required bw. 1900 * @link - current detected link 1901 * @req_bw - requested bandwidth in kbps 1902 * @link_settings - returned most optimal link settings that can fit the 1903 * requested bandwidth 1904 * return - false if link can't support requested bandwidth, true if link 1905 * settings is found. 1906 */ 1907 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1908 struct dc_link_settings *link_settings, 1909 uint32_t req_bw); 1910 1911 /* return the max dp link settings can be driven by the link without considering 1912 * connected RX device and its capability 1913 */ 1914 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1915 struct dc_link_settings *max_link_enc_cap); 1916 1917 /* determine when the link is driving MST mode, what DP link channel coding 1918 * format will be used. The decision will remain unchanged until next HPD event. 1919 * 1920 * @link - a link with DP RX connection 1921 * return - if stream is committed to this link with MST signal type, type of 1922 * channel coding format dc will choose. 1923 */ 1924 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1925 const struct dc_link *link); 1926 1927 /* get max dp link settings the link can enable with all things considered. (i.e 1928 * TX/RX/Cable capabilities and dp override policies. 1929 * 1930 * @link - a link with DP RX connection 1931 * return - max dp link settings the link can enable. 1932 * 1933 */ 1934 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1935 1936 /* Get the highest encoding format that the link supports; highest meaning the 1937 * encoding format which supports the maximum bandwidth. 1938 * 1939 * @link - a link with DP RX connection 1940 * return - highest encoding format link supports. 1941 */ 1942 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 1943 1944 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1945 * to a link with dp connector signal type. 1946 * @link - a link with dp connector signal type 1947 * return - true if connected, false otherwise 1948 */ 1949 bool dc_link_is_dp_sink_present(struct dc_link *link); 1950 1951 /* Force DP lane settings update to main-link video signal and notify the change 1952 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1953 * tuning purpose. The interface assumes link has already been enabled with DP 1954 * signal. 1955 * 1956 * @lt_settings - a container structure with desired hw_lane_settings 1957 */ 1958 void dc_link_set_drive_settings(struct dc *dc, 1959 struct link_training_settings *lt_settings, 1960 struct dc_link *link); 1961 1962 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1963 * test or debugging purpose. The test pattern will remain until next un-plug. 1964 * 1965 * @link - active link with DP signal output enabled. 1966 * @test_pattern - desired test pattern to output. 1967 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1968 * @test_pattern_color_space - for video test pattern choose a desired color 1969 * space. 1970 * @p_link_settings - For PHY pattern choose a desired link settings 1971 * @p_custom_pattern - some test pattern will require a custom input to 1972 * customize some pattern details. Otherwise keep it to NULL. 1973 * @cust_pattern_size - size of the custom pattern input. 1974 * 1975 */ 1976 bool dc_link_dp_set_test_pattern( 1977 struct dc_link *link, 1978 enum dp_test_pattern test_pattern, 1979 enum dp_test_pattern_color_space test_pattern_color_space, 1980 const struct link_training_settings *p_link_settings, 1981 const unsigned char *p_custom_pattern, 1982 unsigned int cust_pattern_size); 1983 1984 /* Force DP link settings to always use a specific value until reboot to a 1985 * specific link. If link has already been enabled, the interface will also 1986 * switch to desired link settings immediately. This is a debug interface to 1987 * generic dp issue trouble shooting. 1988 */ 1989 void dc_link_set_preferred_link_settings(struct dc *dc, 1990 struct dc_link_settings *link_setting, 1991 struct dc_link *link); 1992 1993 /* Force DP link to customize a specific link training behavior by overriding to 1994 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1995 * display specific link training issues or apply some display specific 1996 * workaround in link training. 1997 * 1998 * @link_settings - if not NULL, force preferred link settings to the link. 1999 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2000 * will apply this particular override in future link training. If NULL is 2001 * passed in, dc resets previous overrides. 2002 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2003 * training settings. 2004 */ 2005 void dc_link_set_preferred_training_settings(struct dc *dc, 2006 struct dc_link_settings *link_setting, 2007 struct dc_link_training_overrides *lt_overrides, 2008 struct dc_link *link, 2009 bool skip_immediate_retrain); 2010 2011 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2012 bool dc_link_is_fec_supported(const struct dc_link *link); 2013 2014 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2015 * link enablement. 2016 * return - true if FEC should be enabled, false otherwise. 2017 */ 2018 bool dc_link_should_enable_fec(const struct dc_link *link); 2019 2020 /* determine lttpr mode the current link should be enabled with a specific link 2021 * settings. 2022 */ 2023 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2024 struct dc_link_settings *link_setting); 2025 2026 /* Force DP RX to update its power state. 2027 * NOTE: this interface doesn't update dp main-link. Calling this function will 2028 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2029 * RX power state back upon finish DM specific execution requiring DP RX in a 2030 * specific power state. 2031 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2032 * state. 2033 */ 2034 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2035 2036 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2037 * current value read from extended receiver cap from 02200h - 0220Fh. 2038 * Some DP RX has problems of providing accurate DP receiver caps from extended 2039 * field, this interface is a workaround to revert link back to use base caps. 2040 */ 2041 void dc_link_overwrite_extended_receiver_cap( 2042 struct dc_link *link); 2043 2044 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2045 bool wait_for_hpd); 2046 2047 /* Set backlight level of an embedded panel (eDP, LVDS). 2048 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2049 * and 16 bit fractional, where 1.0 is max backlight value. 2050 */ 2051 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2052 uint32_t backlight_pwm_u16_16, 2053 uint32_t frame_ramp); 2054 2055 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2056 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2057 bool isHDR, 2058 uint32_t backlight_millinits, 2059 uint32_t transition_time_in_ms); 2060 2061 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2062 uint32_t *backlight_millinits, 2063 uint32_t *backlight_millinits_peak); 2064 2065 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2066 2067 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2068 2069 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2070 bool wait, bool force_static, const unsigned int *power_opts); 2071 2072 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2073 2074 bool dc_link_setup_psr(struct dc_link *dc_link, 2075 const struct dc_stream_state *stream, struct psr_config *psr_config, 2076 struct psr_context *psr_context); 2077 2078 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2079 2080 /* On eDP links this function call will stall until T12 has elapsed. 2081 * If the panel is not in power off state, this function will return 2082 * immediately. 2083 */ 2084 bool dc_link_wait_for_t12(struct dc_link *link); 2085 2086 /* Determine if dp trace has been initialized to reflect upto date result * 2087 * return - true if trace is initialized and has valid data. False dp trace 2088 * doesn't have valid result. 2089 */ 2090 bool dc_dp_trace_is_initialized(struct dc_link *link); 2091 2092 /* Query a dp trace flag to indicate if the current dp trace data has been 2093 * logged before 2094 */ 2095 bool dc_dp_trace_is_logged(struct dc_link *link, 2096 bool in_detection); 2097 2098 /* Set dp trace flag to indicate whether DM has already logged the current dp 2099 * trace data. DM can set is_logged to true upon logging and check 2100 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2101 */ 2102 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2103 bool in_detection, 2104 bool is_logged); 2105 2106 /* Obtain driver time stamp for last dp link training end. The time stamp is 2107 * formatted based on dm_get_timestamp DM function. 2108 * @in_detection - true to get link training end time stamp of last link 2109 * training in detection sequence. false to get link training end time stamp 2110 * of last link training in commit (dpms) sequence 2111 */ 2112 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2113 bool in_detection); 2114 2115 /* Get how many link training attempts dc has done with latest sequence. 2116 * @in_detection - true to get link training count of last link 2117 * training in detection sequence. false to get link training count of last link 2118 * training in commit (dpms) sequence 2119 */ 2120 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2121 bool in_detection); 2122 2123 /* Get how many link loss has happened since last link training attempts */ 2124 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2125 2126 /* 2127 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2128 */ 2129 /* 2130 * Send a request from DP-Tx requesting to allocate BW remotely after 2131 * allocating it locally. This will get processed by CM and a CB function 2132 * will be called. 2133 * 2134 * @link: pointer to the dc_link struct instance 2135 * @req_bw: The requested bw in Kbyte to allocated 2136 * 2137 * return: none 2138 */ 2139 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2140 2141 /* 2142 * Handle function for when the status of the Request above is complete. 2143 * We will find out the result of allocating on CM and update structs. 2144 * 2145 * @link: pointer to the dc_link struct instance 2146 * @bw: Allocated or Estimated BW depending on the result 2147 * @result: Response type 2148 * 2149 * return: none 2150 */ 2151 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2152 uint8_t bw, uint8_t result); 2153 2154 /* 2155 * Handle the USB4 BW Allocation related functionality here: 2156 * Plug => Try to allocate max bw from timing parameters supported by the sink 2157 * Unplug => de-allocate bw 2158 * 2159 * @link: pointer to the dc_link struct instance 2160 * @peak_bw: Peak bw used by the link/sink 2161 * 2162 * return: allocated bw else return 0 2163 */ 2164 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2165 struct dc_link *link, int peak_bw); 2166 2167 /* 2168 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2169 * available BW for each host router 2170 * 2171 * @dc: pointer to dc struct 2172 * @stream: pointer to all possible streams 2173 * @num_streams: number of valid DPIA streams 2174 * 2175 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2176 */ 2177 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2178 const unsigned int count); 2179 2180 /* Sink Interfaces - A sink corresponds to a display output device */ 2181 2182 struct dc_container_id { 2183 // 128bit GUID in binary form 2184 unsigned char guid[16]; 2185 // 8 byte port ID -> ELD.PortID 2186 unsigned int portId[2]; 2187 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2188 unsigned short manufacturerName; 2189 // 2 byte product code -> ELD.ProductCode 2190 unsigned short productCode; 2191 }; 2192 2193 2194 struct dc_sink_dsc_caps { 2195 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2196 // 'false' if they are sink's DSC caps 2197 bool is_virtual_dpcd_dsc; 2198 #if defined(CONFIG_DRM_AMD_DC_FP) 2199 // 'true' if MST topology supports DSC passthrough for sink 2200 // 'false' if MST topology does not support DSC passthrough 2201 bool is_dsc_passthrough_supported; 2202 #endif 2203 struct dsc_dec_dpcd_caps dsc_dec_caps; 2204 }; 2205 2206 struct dc_sink_fec_caps { 2207 bool is_rx_fec_supported; 2208 bool is_topology_fec_supported; 2209 }; 2210 2211 struct scdc_caps { 2212 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2213 union hdmi_scdc_device_id_data device_id; 2214 }; 2215 2216 /* 2217 * The sink structure contains EDID and other display device properties 2218 */ 2219 struct dc_sink { 2220 enum signal_type sink_signal; 2221 struct dc_edid dc_edid; /* raw edid */ 2222 struct dc_edid_caps edid_caps; /* parse display caps */ 2223 struct dc_container_id *dc_container_id; 2224 uint32_t dongle_max_pix_clk; 2225 void *priv; 2226 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2227 bool converter_disable_audio; 2228 2229 struct scdc_caps scdc_caps; 2230 struct dc_sink_dsc_caps dsc_caps; 2231 struct dc_sink_fec_caps fec_caps; 2232 2233 bool is_vsc_sdp_colorimetry_supported; 2234 2235 /* private to DC core */ 2236 struct dc_link *link; 2237 struct dc_context *ctx; 2238 2239 uint32_t sink_id; 2240 2241 /* private to dc_sink.c */ 2242 // refcount must be the last member in dc_sink, since we want the 2243 // sink structure to be logically cloneable up to (but not including) 2244 // refcount 2245 struct kref refcount; 2246 }; 2247 2248 void dc_sink_retain(struct dc_sink *sink); 2249 void dc_sink_release(struct dc_sink *sink); 2250 2251 struct dc_sink_init_data { 2252 enum signal_type sink_signal; 2253 struct dc_link *link; 2254 uint32_t dongle_max_pix_clk; 2255 bool converter_disable_audio; 2256 }; 2257 2258 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2259 2260 /* Newer interfaces */ 2261 struct dc_cursor { 2262 struct dc_plane_address address; 2263 struct dc_cursor_attributes attributes; 2264 }; 2265 2266 2267 /* Interrupt interfaces */ 2268 enum dc_irq_source dc_interrupt_to_irq_source( 2269 struct dc *dc, 2270 uint32_t src_id, 2271 uint32_t ext_id); 2272 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2273 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2274 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2275 struct dc *dc, uint32_t link_index); 2276 2277 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2278 2279 /* Power Interfaces */ 2280 2281 void dc_set_power_state( 2282 struct dc *dc, 2283 enum dc_acpi_cm_power_state power_state); 2284 void dc_resume(struct dc *dc); 2285 2286 void dc_power_down_on_boot(struct dc *dc); 2287 2288 /* 2289 * HDCP Interfaces 2290 */ 2291 enum hdcp_message_status dc_process_hdcp_msg( 2292 enum signal_type signal, 2293 struct dc_link *link, 2294 struct hdcp_protection_message *message_info); 2295 bool dc_is_dmcu_initialized(struct dc *dc); 2296 2297 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2298 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2299 2300 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2301 struct dc_cursor_attributes *cursor_attr); 2302 2303 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2304 2305 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2306 void dc_unlock_memory_clock_frequency(struct dc *dc); 2307 2308 /* set min memory clock to the min required for current mode, max to maxDPM */ 2309 void dc_lock_memory_clock_frequency(struct dc *dc); 2310 2311 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2312 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2313 2314 /* cleanup on driver unload */ 2315 void dc_hardware_release(struct dc *dc); 2316 2317 /* disables fw based mclk switch */ 2318 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2319 2320 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2321 void dc_z10_restore(const struct dc *dc); 2322 void dc_z10_save_init(struct dc *dc); 2323 2324 bool dc_is_dmub_outbox_supported(struct dc *dc); 2325 bool dc_enable_dmub_notifications(struct dc *dc); 2326 2327 bool dc_abm_save_restore( 2328 struct dc *dc, 2329 struct dc_stream_state *stream, 2330 struct abm_save_restore *pData); 2331 2332 void dc_enable_dmub_outbox(struct dc *dc); 2333 2334 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2335 uint32_t link_index, 2336 struct aux_payload *payload); 2337 2338 /* Get dc link index from dpia port index */ 2339 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2340 uint8_t dpia_port_index); 2341 2342 bool dc_process_dmub_set_config_async(struct dc *dc, 2343 uint32_t link_index, 2344 struct set_config_cmd_payload *payload, 2345 struct dmub_notification *notify); 2346 2347 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2348 uint32_t link_index, 2349 uint8_t mst_alloc_slots, 2350 uint8_t *mst_slots_in_use); 2351 2352 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2353 uint32_t hpd_int_enable); 2354 2355 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2356 2357 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2358 2359 /* DSC Interfaces */ 2360 #include "dc_dsc.h" 2361 2362 /* Disable acc mode Interfaces */ 2363 void dc_disable_accelerated_mode(struct dc *dc); 2364 2365 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2366 struct dc_stream_state *new_stream); 2367 2368 #endif /* DC_INTERFACE_H_ */ 2369