1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2_0/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "sspl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 struct dcn_hubbub_reg_state; 58 struct dcn_hubp_reg_state; 59 struct dcn_dpp_reg_state; 60 struct dcn_mpc_reg_state; 61 struct dcn_opp_reg_state; 62 struct dcn_dsc_reg_state; 63 struct dcn_optc_reg_state; 64 struct dcn_dccg_reg_state; 65 66 #define DC_VER "3.2.370" 67 68 /** 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 70 */ 71 #define MAX_SURFACES 4 72 /** 73 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 74 */ 75 #define MAX_PLANES 6 76 #define MAX_STREAMS 6 77 #define MIN_VIEWPORT_SIZE 12 78 #define MAX_NUM_EDP 2 79 #define MAX_SUPPORTED_FORMATS 7 80 81 #define MAX_HOST_ROUTERS_NUM 3 82 #define MAX_DPIA_PER_HOST_ROUTER 3 83 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 84 85 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 86 87 /* Display Core Interfaces */ 88 struct dc_versions { 89 const char *dc_ver; 90 struct dmcu_version dmcu_version; 91 }; 92 93 enum dp_protocol_version { 94 DP_VERSION_1_4 = 0, 95 DP_VERSION_2_1, 96 DP_VERSION_UNKNOWN, 97 }; 98 99 enum dc_plane_type { 100 DC_PLANE_TYPE_INVALID, 101 DC_PLANE_TYPE_DCE_RGB, 102 DC_PLANE_TYPE_DCE_UNDERLAY, 103 DC_PLANE_TYPE_DCN_UNIVERSAL, 104 }; 105 106 // Sizes defined as multiples of 64KB 107 enum det_size { 108 DET_SIZE_DEFAULT = 0, 109 DET_SIZE_192KB = 3, 110 DET_SIZE_256KB = 4, 111 DET_SIZE_320KB = 5, 112 DET_SIZE_384KB = 6 113 }; 114 115 116 struct dc_plane_cap { 117 enum dc_plane_type type; 118 uint32_t per_pixel_alpha : 1; 119 struct { 120 uint32_t argb8888 : 1; 121 uint32_t nv12 : 1; 122 uint32_t fp16 : 1; 123 uint32_t p010 : 1; 124 uint32_t ayuv : 1; 125 } pixel_format_support; 126 // max upscaling factor x1000 127 // upscaling factors are always >= 1 128 // for example, 1080p -> 8K is 4.0, or 4000 raw value 129 struct { 130 uint32_t argb8888; 131 uint32_t nv12; 132 uint32_t fp16; 133 } max_upscale_factor; 134 // max downscale factor x1000 135 // downscale factors are always <= 1 136 // for example, 8K -> 1080p is 0.25, or 250 raw value 137 struct { 138 uint32_t argb8888; 139 uint32_t nv12; 140 uint32_t fp16; 141 } max_downscale_factor; 142 // minimal width/height 143 uint32_t min_width; 144 uint32_t min_height; 145 }; 146 147 /** 148 * DOC: color-management-caps 149 * 150 * **Color management caps (DPP and MPC)** 151 * 152 * Modules/color calculates various color operations which are translated to 153 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 154 * DCN1, every new generation comes with fairly major differences in color 155 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 156 * decide mapping to HW block based on logical capabilities. 157 */ 158 159 /** 160 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 161 * @srgb: RGB color space transfer func 162 * @bt2020: BT.2020 transfer func 163 * @gamma2_2: standard gamma 164 * @pq: perceptual quantizer transfer function 165 * @hlg: hybrid log–gamma transfer function 166 */ 167 struct rom_curve_caps { 168 uint16_t srgb : 1; 169 uint16_t bt2020 : 1; 170 uint16_t gamma2_2 : 1; 171 uint16_t pq : 1; 172 uint16_t hlg : 1; 173 }; 174 175 /** 176 * struct dpp_color_caps - color pipeline capabilities for display pipe and 177 * plane blocks 178 * 179 * @dcn_arch: all DCE generations treated the same 180 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 181 * just plain 256-entry lookup 182 * @icsc: input color space conversion 183 * @dgam_ram: programmable degamma LUT 184 * @post_csc: post color space conversion, before gamut remap 185 * @gamma_corr: degamma correction 186 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 187 * with MPC by setting mpc:shared_3d_lut flag 188 * @ogam_ram: programmable out/blend gamma LUT 189 * @ocsc: output color space conversion 190 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 191 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 192 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 193 * 194 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 195 */ 196 struct dpp_color_caps { 197 uint16_t dcn_arch : 1; 198 uint16_t input_lut_shared : 1; 199 uint16_t icsc : 1; 200 uint16_t dgam_ram : 1; 201 uint16_t post_csc : 1; 202 uint16_t gamma_corr : 1; 203 uint16_t hw_3d_lut : 1; 204 uint16_t ogam_ram : 1; 205 uint16_t ocsc : 1; 206 uint16_t dgam_rom_for_yuv : 1; 207 struct rom_curve_caps dgam_rom_caps; 208 struct rom_curve_caps ogam_rom_caps; 209 }; 210 211 /* Below structure is to describe the HW support for mem layout, extend support 212 range to match what OS could handle in the roadmap */ 213 struct lut3d_caps { 214 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 215 struct { 216 uint32_t swizzle_3d_rgb : 1; 217 uint32_t swizzle_3d_bgr : 1; 218 uint32_t linear_1d : 1; 219 } mem_layout_support; 220 struct { 221 uint32_t unorm_12msb : 1; 222 uint32_t unorm_12lsb : 1; 223 uint32_t float_fp1_5_10 : 1; 224 } mem_format_support; 225 struct { 226 uint32_t order_rgba : 1; 227 uint32_t order_bgra : 1; 228 } mem_pixel_order_support; 229 /*< size options are 9, 17, 33, 45, 65 */ 230 struct { 231 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 232 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 233 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 234 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 235 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 236 } lut_dim_caps; 237 }; 238 239 /** 240 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 241 * plane combined blocks 242 * 243 * @gamut_remap: color transformation matrix 244 * @ogam_ram: programmable out gamma LUT 245 * @ocsc: output color space conversion matrix 246 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 247 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 248 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 249 * instance 250 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 251 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 252 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 253 * @preblend: whether color manager supports preblend with MPC 254 */ 255 struct mpc_color_caps { 256 uint16_t gamut_remap : 1; 257 uint16_t ogam_ram : 1; 258 uint16_t ocsc : 1; 259 uint16_t num_3dluts : 3; 260 uint16_t num_rmcm_3dluts : 3; 261 uint16_t shared_3d_lut:1; 262 struct rom_curve_caps ogam_rom_caps; 263 struct lut3d_caps mcm_3d_lut_caps; 264 struct lut3d_caps rmcm_3d_lut_caps; 265 bool preblend; 266 }; 267 268 /** 269 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 270 * @dpp: color pipes caps for DPP 271 * @mpc: color pipes caps for MPC 272 */ 273 struct dc_color_caps { 274 struct dpp_color_caps dpp; 275 struct mpc_color_caps mpc; 276 }; 277 278 struct dc_dmub_caps { 279 bool psr; 280 bool mclk_sw; 281 bool subvp_psr; 282 bool gecc_enable; 283 uint8_t fams_ver; 284 bool aux_backlight_support; 285 }; 286 287 struct dc_scl_caps { 288 bool sharpener_support; 289 }; 290 291 struct dc_check_config { 292 /** 293 * max video plane width that can be safely assumed to be always 294 * supported by single DPP pipe. 295 */ 296 unsigned int max_optimizable_video_width; 297 bool enable_legacy_fast_update; 298 299 bool deferred_transition_state; 300 unsigned int transition_countdown_to_steady_state; 301 }; 302 303 struct dc_caps { 304 uint32_t max_streams; 305 uint32_t max_links; 306 uint32_t max_audios; 307 uint32_t max_slave_planes; 308 uint32_t max_slave_yuv_planes; 309 uint32_t max_slave_rgb_planes; 310 uint32_t max_planes; 311 uint32_t max_downscale_ratio; 312 uint32_t i2c_speed_in_khz; 313 uint32_t i2c_speed_in_khz_hdcp; 314 uint32_t dmdata_alloc_size; 315 unsigned int max_cursor_size; 316 unsigned int max_buffered_cursor_size; 317 unsigned int max_video_width; 318 unsigned int min_horizontal_blanking_period; 319 int linear_pitch_alignment; 320 bool dcc_const_color; 321 bool dynamic_audio; 322 bool is_apu; 323 bool dual_link_dvi; 324 bool post_blend_color_processing; 325 bool force_dp_tps4_for_cp2520; 326 bool disable_dp_clk_share; 327 bool psp_setup_panel_mode; 328 bool extended_aux_timeout_support; 329 bool dmcub_support; 330 bool zstate_support; 331 bool ips_support; 332 bool ips_v2_support; 333 uint32_t num_of_internal_disp; 334 enum dp_protocol_version max_dp_protocol_version; 335 unsigned int mall_size_per_mem_channel; 336 unsigned int mall_size_total; 337 unsigned int cursor_cache_size; 338 struct dc_plane_cap planes[MAX_PLANES]; 339 struct dc_color_caps color; 340 struct dc_dmub_caps dmub_caps; 341 bool dp_hpo; 342 bool dp_hdmi21_pcon_support; 343 bool edp_dsc_support; 344 bool vbios_lttpr_aware; 345 bool vbios_lttpr_enable; 346 bool fused_io_supported; 347 uint32_t max_otg_num; 348 uint32_t max_cab_allocation_bytes; 349 uint32_t cache_line_size; 350 uint32_t cache_num_ways; 351 uint16_t subvp_fw_processing_delay_us; 352 uint8_t subvp_drr_max_vblank_margin_us; 353 uint16_t subvp_prefetch_end_to_mall_start_us; 354 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 355 uint16_t subvp_pstate_allow_width_us; 356 uint16_t subvp_vertical_int_margin_us; 357 bool seamless_odm; 358 uint32_t max_v_total; 359 bool vtotal_limited_by_fp2; 360 uint32_t max_disp_clock_khz_at_vmin; 361 uint8_t subvp_drr_vblank_start_margin_us; 362 bool cursor_not_scaled; 363 bool dcmode_power_limits_present; 364 bool sequential_ono; 365 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 366 uint32_t dcc_plane_width_limit; 367 struct dc_scl_caps scl_caps; 368 uint8_t num_of_host_routers; 369 uint8_t num_of_dpias_per_host_router; 370 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 371 uint8_t max_odm_combine_factor; 372 }; 373 374 struct dc_bug_wa { 375 bool no_connect_phy_config; 376 bool dedcn20_305_wa; 377 bool skip_clock_update; 378 bool lt_early_cr_pattern; 379 struct { 380 uint8_t uclk : 1; 381 uint8_t fclk : 1; 382 uint8_t dcfclk : 1; 383 uint8_t dcfclk_ds: 1; 384 } clock_update_disable_mask; 385 bool skip_psr_ips_crtc_disable; 386 }; 387 struct dc_dcc_surface_param { 388 struct dc_size surface_size; 389 enum surface_pixel_format format; 390 unsigned int plane0_pitch; 391 struct dc_size plane1_size; 392 unsigned int plane1_pitch; 393 union { 394 enum swizzle_mode_values swizzle_mode; 395 enum swizzle_mode_addr3_values swizzle_mode_addr3; 396 }; 397 enum dc_scan_direction scan; 398 }; 399 400 struct dc_dcc_setting { 401 unsigned int max_compressed_blk_size; 402 unsigned int max_uncompressed_blk_size; 403 bool independent_64b_blks; 404 //These bitfields to be used starting with DCN 3.0 405 struct { 406 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 407 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 408 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 409 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 410 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 411 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 412 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 413 } dcc_controls; 414 }; 415 416 struct dc_surface_dcc_cap { 417 union { 418 struct { 419 struct dc_dcc_setting rgb; 420 } grph; 421 422 struct { 423 struct dc_dcc_setting luma; 424 struct dc_dcc_setting chroma; 425 } video; 426 }; 427 428 bool capable; 429 bool const_color_support; 430 }; 431 432 struct dc_static_screen_params { 433 struct { 434 bool force_trigger; 435 bool cursor_update; 436 bool surface_update; 437 bool overlay_update; 438 } triggers; 439 unsigned int num_frames; 440 }; 441 442 443 /* Surface update type is used by dc_update_surfaces_and_stream 444 * The update type is determined at the very beginning of the function based 445 * on parameters passed in and decides how much programming (or updating) is 446 * going to be done during the call. 447 * 448 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 449 * logical calculations or hardware register programming. This update MUST be 450 * ISR safe on windows. Currently fast update will only be used to flip surface 451 * address. 452 * 453 * UPDATE_TYPE_MED is used for slower updates which require significant hw 454 * re-programming however do not affect bandwidth consumption or clock 455 * requirements. At present, this is the level at which front end updates 456 * that do not require us to run bw_calcs happen. These are in/out transfer func 457 * updates, viewport offset changes, recout size changes and pixel depth changes. 458 * This update can be done at ISR, but we want to minimize how often this happens. 459 * 460 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 461 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 462 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 463 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 464 * a full update. This cannot be done at ISR level and should be a rare event. 465 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 466 * underscan we don't expect to see this call at all. 467 */ 468 469 enum surface_update_type { 470 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 471 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 472 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 473 }; 474 475 enum dc_lock_descriptor { 476 LOCK_DESCRIPTOR_NONE = 0x0, 477 LOCK_DESCRIPTOR_STREAM = 0x1, 478 LOCK_DESCRIPTOR_LINK = 0x2, 479 LOCK_DESCRIPTOR_GLOBAL = 0x4, 480 }; 481 482 struct surface_update_descriptor { 483 enum surface_update_type update_type; 484 enum dc_lock_descriptor lock_descriptor; 485 }; 486 487 /* Forward declaration*/ 488 struct dc; 489 struct dc_plane_state; 490 struct dc_state; 491 492 struct dc_cap_funcs { 493 bool (*get_dcc_compression_cap)(const struct dc *dc, 494 const struct dc_dcc_surface_param *input, 495 struct dc_surface_dcc_cap *output); 496 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 497 }; 498 499 struct link_training_settings; 500 501 union allow_lttpr_non_transparent_mode { 502 struct { 503 bool DP1_4A : 1; 504 bool DP2_0 : 1; 505 } bits; 506 unsigned char raw; 507 }; 508 /* Structure to hold configuration flags set by dm at dc creation. */ 509 struct dc_config { 510 bool gpu_vm_support; 511 bool disable_disp_pll_sharing; 512 bool fbc_support; 513 bool disable_fractional_pwm; 514 bool allow_seamless_boot_optimization; 515 bool seamless_boot_edp_requested; 516 bool edp_not_connected; 517 bool edp_no_power_sequencing; 518 bool force_enum_edp; 519 bool forced_clocks; 520 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 521 bool multi_mon_pp_mclk_switch; 522 bool disable_dmcu; 523 bool enable_4to1MPC; 524 bool enable_windowed_mpo_odm; 525 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 526 uint32_t allow_edp_hotplug_detection; 527 bool skip_riommu_prefetch_wa; 528 bool clamp_min_dcfclk; 529 uint64_t vblank_alignment_dto_params; 530 uint8_t vblank_alignment_max_frame_time_diff; 531 bool is_asymmetric_memory; 532 bool is_single_rank_dimm; 533 bool is_vmin_only_asic; 534 bool use_spl; 535 bool prefer_easf; 536 bool use_pipe_ctx_sync_logic; 537 int smart_mux_version; 538 bool ignore_dpref_ss; 539 bool enable_mipi_converter_optimization; 540 bool use_default_clock_table; 541 bool force_bios_enable_lttpr; 542 uint8_t force_bios_fixed_vs; 543 int sdpif_request_limit_words_per_umc; 544 bool dc_mode_clk_limit_support; 545 bool EnableMinDispClkODM; 546 bool enable_auto_dpm_test_logs; 547 unsigned int disable_ips; 548 unsigned int disable_ips_rcg; 549 unsigned int disable_ips_in_vpb; 550 bool disable_ips_in_dpms_off; 551 bool usb4_bw_alloc_support; 552 bool allow_0_dtb_clk; 553 bool use_assr_psp_message; 554 bool support_edp0_on_dp1; 555 unsigned int enable_fpo_flicker_detection; 556 bool disable_hbr_audio_dp2; 557 bool consolidated_dpia_dp_lt; 558 bool set_pipe_unlock_order; 559 bool enable_dpia_pre_training; 560 bool unify_link_enc_assignment; 561 bool enable_cursor_offload; 562 bool frame_update_cmd_version2; 563 struct spl_sharpness_range dcn_sharpness_range; 564 struct spl_sharpness_range dcn_override_sharpness_range; 565 }; 566 567 enum visual_confirm { 568 VISUAL_CONFIRM_DISABLE = 0, 569 VISUAL_CONFIRM_SURFACE = 1, 570 VISUAL_CONFIRM_HDR = 2, 571 VISUAL_CONFIRM_MPCTREE = 4, 572 VISUAL_CONFIRM_PSR = 5, 573 VISUAL_CONFIRM_SWAPCHAIN = 6, 574 VISUAL_CONFIRM_FAMS = 7, 575 VISUAL_CONFIRM_SWIZZLE = 9, 576 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 577 VISUAL_CONFIRM_REPLAY = 12, 578 VISUAL_CONFIRM_SUBVP = 14, 579 VISUAL_CONFIRM_MCLK_SWITCH = 16, 580 VISUAL_CONFIRM_FAMS2 = 19, 581 VISUAL_CONFIRM_HW_CURSOR = 20, 582 VISUAL_CONFIRM_VABC = 21, 583 VISUAL_CONFIRM_DCC = 22, 584 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 585 }; 586 587 enum dc_psr_power_opts { 588 psr_power_opt_invalid = 0x0, 589 psr_power_opt_smu_opt_static_screen = 0x1, 590 psr_power_opt_z10_static_screen = 0x10, 591 psr_power_opt_ds_disable_allow = 0x100, 592 }; 593 594 enum dml_hostvm_override_opts { 595 DML_HOSTVM_NO_OVERRIDE = 0x0, 596 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 597 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 598 }; 599 600 enum dc_replay_power_opts { 601 replay_power_opt_invalid = 0x0, 602 replay_power_opt_smu_opt_static_screen = 0x1, 603 replay_power_opt_z10_static_screen = 0x10, 604 }; 605 606 enum dcc_option { 607 DCC_ENABLE = 0, 608 DCC_DISABLE = 1, 609 DCC_HALF_REQ_DISALBE = 2, 610 }; 611 612 enum in_game_fams_config { 613 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 614 INGAME_FAMS_DISABLE, // disable in-game fams 615 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 616 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 617 }; 618 619 /** 620 * enum pipe_split_policy - Pipe split strategy supported by DCN 621 * 622 * This enum is used to define the pipe split policy supported by DCN. By 623 * default, DC favors MPC_SPLIT_DYNAMIC. 624 */ 625 enum pipe_split_policy { 626 /** 627 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 628 * pipe in order to bring the best trade-off between performance and 629 * power consumption. This is the recommended option. 630 */ 631 MPC_SPLIT_DYNAMIC = 0, 632 633 /** 634 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 635 * try any sort of split optimization. 636 */ 637 MPC_SPLIT_AVOID = 1, 638 639 /** 640 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 641 * optimize the pipe utilization when using a single display; if the 642 * user connects to a second display, DC will avoid pipe split. 643 */ 644 MPC_SPLIT_AVOID_MULT_DISP = 2, 645 }; 646 647 enum wm_report_mode { 648 WM_REPORT_DEFAULT = 0, 649 WM_REPORT_OVERRIDE = 1, 650 }; 651 enum dtm_pstate{ 652 dtm_level_p0 = 0,/*highest voltage*/ 653 dtm_level_p1, 654 dtm_level_p2, 655 dtm_level_p3, 656 dtm_level_p4,/*when active_display_count = 0*/ 657 }; 658 659 enum dcn_pwr_state { 660 DCN_PWR_STATE_UNKNOWN = -1, 661 DCN_PWR_STATE_MISSION_MODE = 0, 662 DCN_PWR_STATE_LOW_POWER = 3, 663 }; 664 665 enum dcn_zstate_support_state { 666 DCN_ZSTATE_SUPPORT_UNKNOWN, 667 DCN_ZSTATE_SUPPORT_ALLOW, 668 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 669 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 670 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 671 DCN_ZSTATE_SUPPORT_DISALLOW, 672 }; 673 674 /* 675 * struct dc_clocks - DC pipe clocks 676 * 677 * For any clocks that may differ per pipe only the max is stored in this 678 * structure 679 */ 680 struct dc_clocks { 681 int dispclk_khz; 682 int actual_dispclk_khz; 683 int dppclk_khz; 684 int actual_dppclk_khz; 685 int disp_dpp_voltage_level_khz; 686 int dcfclk_khz; 687 int socclk_khz; 688 int dcfclk_deep_sleep_khz; 689 int fclk_khz; 690 int phyclk_khz; 691 int dramclk_khz; 692 bool p_state_change_support; 693 enum dcn_zstate_support_state zstate_support; 694 bool dtbclk_en; 695 int ref_dtbclk_khz; 696 bool fclk_p_state_change_support; 697 enum dcn_pwr_state pwr_state; 698 /* 699 * Elements below are not compared for the purposes of 700 * optimization required 701 */ 702 bool prev_p_state_change_support; 703 bool fclk_prev_p_state_change_support; 704 int num_ways; 705 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 706 707 /* 708 * @fw_based_mclk_switching 709 * 710 * DC has a mechanism that leverage the variable refresh rate to switch 711 * memory clock in cases that we have a large latency to achieve the 712 * memory clock change and a short vblank window. DC has some 713 * requirements to enable this feature, and this field describes if the 714 * system support or not such a feature. 715 */ 716 bool fw_based_mclk_switching; 717 bool fw_based_mclk_switching_shut_down; 718 int prev_num_ways; 719 enum dtm_pstate dtm_level; 720 int max_supported_dppclk_khz; 721 int max_supported_dispclk_khz; 722 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 723 int bw_dispclk_khz; 724 int idle_dramclk_khz; 725 int idle_fclk_khz; 726 int subvp_prefetch_dramclk_khz; 727 int subvp_prefetch_fclk_khz; 728 729 /* Stutter efficiency is technically not clock values 730 * but stored here so the values are part of the update_clocks call similar to num_ways 731 * Efficiencies are stored as percentage (0-100) 732 */ 733 struct { 734 uint8_t base_efficiency; //LP1 735 uint8_t low_power_efficiency; //LP2 736 uint8_t z8_stutter_efficiency; 737 int z8_stutter_period; 738 } stutter_efficiency; 739 }; 740 741 struct dc_bw_validation_profile { 742 bool enable; 743 744 unsigned long long total_ticks; 745 unsigned long long voltage_level_ticks; 746 unsigned long long watermark_ticks; 747 unsigned long long rq_dlg_ticks; 748 749 unsigned long long total_count; 750 unsigned long long skip_fast_count; 751 unsigned long long skip_pass_count; 752 unsigned long long skip_fail_count; 753 }; 754 755 #define BW_VAL_TRACE_SETUP() \ 756 unsigned long long end_tick = 0; \ 757 unsigned long long voltage_level_tick = 0; \ 758 unsigned long long watermark_tick = 0; \ 759 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 760 dm_get_timestamp(dc->ctx) : 0 761 762 #define BW_VAL_TRACE_COUNT() \ 763 if (dc->debug.bw_val_profile.enable) \ 764 dc->debug.bw_val_profile.total_count++ 765 766 #define BW_VAL_TRACE_SKIP(status) \ 767 if (dc->debug.bw_val_profile.enable) { \ 768 if (!voltage_level_tick) \ 769 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 770 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 771 } 772 773 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 774 if (dc->debug.bw_val_profile.enable) \ 775 voltage_level_tick = dm_get_timestamp(dc->ctx) 776 777 #define BW_VAL_TRACE_END_WATERMARKS() \ 778 if (dc->debug.bw_val_profile.enable) \ 779 watermark_tick = dm_get_timestamp(dc->ctx) 780 781 #define BW_VAL_TRACE_FINISH() \ 782 if (dc->debug.bw_val_profile.enable) { \ 783 end_tick = dm_get_timestamp(dc->ctx); \ 784 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 785 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 786 if (watermark_tick) { \ 787 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 788 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 789 } \ 790 } 791 792 union mem_low_power_enable_options { 793 struct { 794 bool vga: 1; 795 bool i2c: 1; 796 bool dmcu: 1; 797 bool dscl: 1; 798 bool cm: 1; 799 bool mpc: 1; 800 bool optc: 1; 801 bool vpg: 1; 802 bool afmt: 1; 803 } bits; 804 uint32_t u32All; 805 }; 806 807 union root_clock_optimization_options { 808 struct { 809 bool dpp: 1; 810 bool dsc: 1; 811 bool hdmistream: 1; 812 bool hdmichar: 1; 813 bool dpstream: 1; 814 bool symclk32_se: 1; 815 bool symclk32_le: 1; 816 bool symclk_fe: 1; 817 bool physymclk: 1; 818 bool dpiasymclk: 1; 819 uint32_t reserved: 22; 820 } bits; 821 uint32_t u32All; 822 }; 823 824 union fine_grain_clock_gating_enable_options { 825 struct { 826 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 827 bool dchub : 1; /* Display controller hub */ 828 bool dchubbub : 1; 829 bool dpp : 1; /* Display pipes and planes */ 830 bool opp : 1; /* Output pixel processing */ 831 bool optc : 1; /* Output pipe timing combiner */ 832 bool dio : 1; /* Display output */ 833 bool dwb : 1; /* Display writeback */ 834 bool mmhubbub : 1; /* Multimedia hub */ 835 bool dmu : 1; /* Display core management unit */ 836 bool az : 1; /* Azalia */ 837 bool dchvm : 1; 838 bool dsc : 1; /* Display stream compression */ 839 840 uint32_t reserved : 19; 841 } bits; 842 uint32_t u32All; 843 }; 844 845 enum pg_hw_pipe_resources { 846 PG_HUBP = 0, 847 PG_DPP, 848 PG_DSC, 849 PG_MPCC, 850 PG_OPP, 851 PG_OPTC, 852 PG_DPSTREAM, 853 PG_HDMISTREAM, 854 PG_PHYSYMCLK, 855 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 856 }; 857 858 enum pg_hw_resources { 859 PG_DCCG = 0, 860 PG_DCIO, 861 PG_DIO, 862 PG_DCHUBBUB, 863 PG_DCHVM, 864 PG_DWB, 865 PG_HPO, 866 PG_DCOH, 867 PG_HW_RESOURCES_NUM_ELEMENT 868 }; 869 870 struct pg_block_update { 871 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 872 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 873 }; 874 875 union dpia_debug_options { 876 struct { 877 uint32_t disable_dpia:1; /* bit 0 */ 878 uint32_t force_non_lttpr:1; /* bit 1 */ 879 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 880 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 881 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 882 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 883 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 884 uint32_t reserved:25; 885 } bits; 886 uint32_t raw; 887 }; 888 889 /* AUX wake work around options 890 * 0: enable/disable work around 891 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 892 * 15-2: reserved 893 * 31-16: timeout in ms 894 */ 895 union aux_wake_wa_options { 896 struct { 897 uint32_t enable_wa : 1; 898 uint32_t use_default_timeout : 1; 899 uint32_t rsvd: 14; 900 uint32_t timeout_ms : 16; 901 } bits; 902 uint32_t raw; 903 }; 904 905 struct dc_debug_data { 906 uint32_t ltFailCount; 907 uint32_t i2cErrorCount; 908 uint32_t auxErrorCount; 909 struct pipe_topology_history topology_history; 910 }; 911 912 struct dc_phy_addr_space_config { 913 struct { 914 uint64_t start_addr; 915 uint64_t end_addr; 916 uint64_t fb_top; 917 uint64_t fb_offset; 918 uint64_t fb_base; 919 uint64_t agp_top; 920 uint64_t agp_bot; 921 uint64_t agp_base; 922 } system_aperture; 923 924 struct { 925 uint64_t page_table_start_addr; 926 uint64_t page_table_end_addr; 927 uint64_t page_table_base_addr; 928 bool base_addr_is_mc_addr; 929 } gart_config; 930 931 bool valid; 932 bool is_hvm_enabled; 933 uint64_t page_table_default_page_addr; 934 }; 935 936 struct dc_virtual_addr_space_config { 937 uint64_t page_table_base_addr; 938 uint64_t page_table_start_addr; 939 uint64_t page_table_end_addr; 940 uint32_t page_table_block_size_in_bytes; 941 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 942 }; 943 944 struct dc_bounding_box_overrides { 945 int sr_exit_time_ns; 946 int sr_enter_plus_exit_time_ns; 947 int sr_exit_z8_time_ns; 948 int sr_enter_plus_exit_z8_time_ns; 949 int urgent_latency_ns; 950 int percent_of_ideal_drambw; 951 int dram_clock_change_latency_ns; 952 int dummy_clock_change_latency_ns; 953 int fclk_clock_change_latency_ns; 954 /* This forces a hard min on the DCFCLK we use 955 * for DML. Unlike the debug option for forcing 956 * DCFCLK, this override affects watermark calculations 957 */ 958 int min_dcfclk_mhz; 959 }; 960 961 struct dc_qos_info { 962 uint32_t actual_peak_bw_in_mbps; 963 uint32_t qos_bandwidth_lb_in_mbps; 964 uint32_t actual_avg_bw_in_mbps; 965 uint32_t calculated_avg_bw_in_mbps; 966 uint32_t actual_max_latency_in_ns; 967 uint32_t actual_min_latency_in_ns; 968 uint32_t qos_max_latency_ub_in_ns; 969 uint32_t actual_avg_latency_in_ns; 970 uint32_t qos_avg_latency_ub_in_ns; 971 uint32_t dcn_bandwidth_ub_in_mbps; 972 }; 973 974 struct dc_state; 975 struct resource_pool; 976 struct dce_hwseq; 977 struct link_service; 978 979 /* 980 * struct dc_debug_options - DC debug struct 981 * 982 * This struct provides a simple mechanism for developers to change some 983 * configurations, enable/disable features, and activate extra debug options. 984 * This can be very handy to narrow down whether some specific feature is 985 * causing an issue or not. 986 */ 987 struct dc_debug_options { 988 bool native422_support; 989 bool disable_dsc; 990 enum visual_confirm visual_confirm; 991 int visual_confirm_rect_height; 992 993 bool sanity_checks; 994 bool max_disp_clk; 995 bool surface_trace; 996 bool clock_trace; 997 bool validation_trace; 998 bool bandwidth_calcs_trace; 999 int max_downscale_src_width; 1000 1001 /* stutter efficiency related */ 1002 bool disable_stutter; 1003 bool use_max_lb; 1004 enum dcc_option disable_dcc; 1005 1006 /* 1007 * @pipe_split_policy: Define which pipe split policy is used by the 1008 * display core. 1009 */ 1010 enum pipe_split_policy pipe_split_policy; 1011 bool force_single_disp_pipe_split; 1012 bool voltage_align_fclk; 1013 bool disable_min_fclk; 1014 1015 bool hdcp_lc_force_fw_enable; 1016 bool hdcp_lc_enable_sw_fallback; 1017 1018 bool disable_dfs_bypass; 1019 bool disable_dpp_power_gate; 1020 bool disable_hubp_power_gate; 1021 bool disable_dsc_power_gate; 1022 bool disable_optc_power_gate; 1023 bool disable_hpo_power_gate; 1024 bool disable_io_clk_power_gate; 1025 bool disable_mem_power_gate; 1026 bool disable_dio_power_gate; 1027 int dsc_min_slice_height_override; 1028 int dsc_bpp_increment_div; 1029 bool disable_pplib_wm_range; 1030 enum wm_report_mode pplib_wm_report_mode; 1031 unsigned int min_disp_clk_khz; 1032 unsigned int min_dpp_clk_khz; 1033 unsigned int min_dram_clk_khz; 1034 int sr_exit_time_dpm0_ns; 1035 int sr_enter_plus_exit_time_dpm0_ns; 1036 int sr_exit_time_ns; 1037 int sr_enter_plus_exit_time_ns; 1038 int sr_exit_z8_time_ns; 1039 int sr_enter_plus_exit_z8_time_ns; 1040 int urgent_latency_ns; 1041 uint32_t underflow_assert_delay_us; 1042 int percent_of_ideal_drambw; 1043 int dram_clock_change_latency_ns; 1044 bool optimized_watermark; 1045 int always_scale; 1046 bool disable_pplib_clock_request; 1047 bool disable_clock_gate; 1048 bool disable_mem_low_power; 1049 bool pstate_enabled; 1050 bool disable_dmcu; 1051 bool force_abm_enable; 1052 bool disable_stereo_support; 1053 bool vsr_support; 1054 bool performance_trace; 1055 bool az_endpoint_mute_only; 1056 bool always_use_regamma; 1057 bool recovery_enabled; 1058 bool avoid_vbios_exec_table; 1059 bool scl_reset_length10; 1060 bool hdmi20_disable; 1061 bool skip_detection_link_training; 1062 uint32_t edid_read_retry_times; 1063 unsigned int force_odm_combine; //bit vector based on otg inst 1064 unsigned int seamless_boot_odm_combine; 1065 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 1066 int minimum_z8_residency_time; 1067 int minimum_z10_residency_time; 1068 bool disable_z9_mpc; 1069 unsigned int force_fclk_khz; 1070 bool enable_tri_buf; 1071 bool ips_disallow_entry; 1072 bool dmub_offload_enabled; 1073 bool dmcub_emulation; 1074 bool disable_idle_power_optimizations; 1075 unsigned int mall_size_override; 1076 unsigned int mall_additional_timer_percent; 1077 bool mall_error_as_fatal; 1078 bool dmub_command_table; /* for testing only */ 1079 struct dc_bw_validation_profile bw_val_profile; 1080 bool disable_fec; 1081 bool disable_48mhz_pwrdwn; 1082 /* This forces a hard min on the DCFCLK requested to SMU/PP 1083 * watermarks are not affected. 1084 */ 1085 unsigned int force_min_dcfclk_mhz; 1086 int dwb_fi_phase; 1087 bool disable_timing_sync; 1088 bool cm_in_bypass; 1089 int force_clock_mode;/*every mode change.*/ 1090 1091 bool disable_dram_clock_change_vactive_support; 1092 bool validate_dml_output; 1093 bool enable_dmcub_surface_flip; 1094 bool usbc_combo_phy_reset_wa; 1095 bool enable_dram_clock_change_one_display_vactive; 1096 /* TODO - remove once tested */ 1097 bool legacy_dp2_lt; 1098 bool set_mst_en_for_sst; 1099 bool disable_uhbr; 1100 bool force_dp2_lt_fallback_method; 1101 bool ignore_cable_id; 1102 union mem_low_power_enable_options enable_mem_low_power; 1103 union root_clock_optimization_options root_clock_optimization; 1104 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1105 bool hpo_optimization; 1106 bool force_vblank_alignment; 1107 1108 /* Enable dmub aux for legacy ddc */ 1109 bool enable_dmub_aux_for_legacy_ddc; 1110 bool disable_fams; 1111 enum in_game_fams_config disable_fams_gaming; 1112 /* FEC/PSR1 sequence enable delay in 100us */ 1113 uint8_t fec_enable_delay_in100us; 1114 bool enable_driver_sequence_debug; 1115 enum det_size crb_alloc_policy; 1116 int crb_alloc_policy_min_disp_count; 1117 bool disable_z10; 1118 bool enable_z9_disable_interface; 1119 bool psr_skip_crtc_disable; 1120 uint32_t ips_skip_crtc_disable_mask; 1121 union dpia_debug_options dpia_debug; 1122 bool disable_fixed_vs_aux_timeout_wa; 1123 uint32_t fixed_vs_aux_delay_config_wa; 1124 bool force_disable_subvp; 1125 bool force_subvp_mclk_switch; 1126 bool allow_sw_cursor_fallback; 1127 unsigned int force_subvp_num_ways; 1128 unsigned int force_mall_ss_num_ways; 1129 bool alloc_extra_way_for_cursor; 1130 uint32_t subvp_extra_lines; 1131 bool disable_force_pstate_allow_on_hw_release; 1132 bool force_usr_allow; 1133 /* uses value at boot and disables switch */ 1134 bool disable_dtb_ref_clk_switch; 1135 bool extended_blank_optimization; 1136 union aux_wake_wa_options aux_wake_wa; 1137 uint32_t mst_start_top_delay; 1138 uint8_t psr_power_use_phy_fsm; 1139 enum dml_hostvm_override_opts dml_hostvm_override; 1140 bool dml_disallow_alternate_prefetch_modes; 1141 bool use_legacy_soc_bb_mechanism; 1142 bool exit_idle_opt_for_cursor_updates; 1143 bool using_dml2; 1144 bool enable_single_display_2to1_odm_policy; 1145 bool enable_double_buffered_dsc_pg_support; 1146 bool enable_dp_dig_pixel_rate_div_policy; 1147 bool using_dml21; 1148 enum lttpr_mode lttpr_mode_override; 1149 unsigned int dsc_delay_factor_wa_x1000; 1150 unsigned int min_prefetch_in_strobe_ns; 1151 bool disable_unbounded_requesting; 1152 bool dig_fifo_off_in_blank; 1153 bool override_dispclk_programming; 1154 bool otg_crc_db; 1155 bool disallow_dispclk_dppclk_ds; 1156 bool disable_fpo_optimizations; 1157 bool support_eDP1_5; 1158 uint32_t fpo_vactive_margin_us; 1159 bool disable_fpo_vactive; 1160 bool disable_boot_optimizations; 1161 bool override_odm_optimization; 1162 bool minimize_dispclk_using_odm; 1163 bool disable_subvp_high_refresh; 1164 bool disable_dp_plus_plus_wa; 1165 uint32_t fpo_vactive_min_active_margin_us; 1166 uint32_t fpo_vactive_max_blank_us; 1167 bool enable_hpo_pg_support; 1168 bool disable_dc_mode_overwrite; 1169 bool replay_skip_crtc_disabled; 1170 bool ignore_pg;/*do nothing, let pmfw control it*/ 1171 bool psp_disabled_wa; 1172 unsigned int ips2_eval_delay_us; 1173 unsigned int ips2_entry_delay_us; 1174 bool optimize_ips_handshake; 1175 bool disable_dmub_reallow_idle; 1176 bool disable_timeout; 1177 bool disable_extblankadj; 1178 bool enable_idle_reg_checks; 1179 unsigned int static_screen_wait_frames; 1180 uint32_t pwm_freq; 1181 bool force_chroma_subsampling_1tap; 1182 unsigned int dcc_meta_propagation_delay_us; 1183 bool disable_422_left_edge_pixel; 1184 bool dml21_force_pstate_method; 1185 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1186 uint32_t dml21_disable_pstate_method_mask; 1187 union fw_assisted_mclk_switch_version fams_version; 1188 union dmub_fams2_global_feature_config fams2_config; 1189 unsigned int force_cositing; 1190 unsigned int disable_spl; 1191 unsigned int force_easf; 1192 unsigned int force_sharpness; 1193 unsigned int force_sharpness_level; 1194 unsigned int force_lls; 1195 bool notify_dpia_hr_bw; 1196 bool enable_ips_visual_confirm; 1197 unsigned int sharpen_policy; 1198 unsigned int scale_to_sharpness_policy; 1199 unsigned int enable_oled_edp_power_up_opt; 1200 bool enable_hblank_borrow; 1201 bool force_subvp_df_throttle; 1202 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1203 bool enable_pg_cntl_debug_logs; 1204 unsigned int auxless_alpm_lfps_setup_ns; 1205 unsigned int auxless_alpm_lfps_period_ns; 1206 unsigned int auxless_alpm_lfps_silence_ns; 1207 unsigned int auxless_alpm_lfps_t1t2_us; 1208 short auxless_alpm_lfps_t1t2_offset_us; 1209 bool disable_stutter_for_wm_program; 1210 bool enable_block_sequence_programming; 1211 uint32_t custom_psp_footer_size; 1212 bool disable_deferred_minimal_transitions; 1213 unsigned int num_fast_flips_to_steady_state_override; 1214 bool enable_dmu_recovery; 1215 unsigned int force_vmin_threshold; 1216 bool enable_otg_frame_sync_pwa; 1217 }; 1218 1219 1220 /* Generic structure that can be used to query properties of DC. More fields 1221 * can be added as required. 1222 */ 1223 struct dc_current_properties { 1224 unsigned int cursor_size_limit; 1225 }; 1226 1227 enum frame_buffer_mode { 1228 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1229 FRAME_BUFFER_MODE_ZFB_ONLY, 1230 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1231 } ; 1232 1233 struct dchub_init_data { 1234 int64_t zfb_phys_addr_base; 1235 int64_t zfb_mc_base_addr; 1236 uint64_t zfb_size_in_byte; 1237 enum frame_buffer_mode fb_mode; 1238 bool dchub_initialzied; 1239 bool dchub_info_valid; 1240 }; 1241 1242 struct dml2_soc_bb; 1243 1244 struct dc_init_data { 1245 struct hw_asic_id asic_id; 1246 void *driver; /* ctx */ 1247 struct cgs_device *cgs_device; 1248 struct dc_bounding_box_overrides bb_overrides; 1249 1250 int num_virtual_links; 1251 /* 1252 * If 'vbios_override' not NULL, it will be called instead 1253 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1254 */ 1255 struct dc_bios *vbios_override; 1256 enum dce_environment dce_environment; 1257 1258 struct dmub_offload_funcs *dmub_if; 1259 struct dc_reg_helper_state *dmub_offload; 1260 1261 struct dc_config flags; 1262 uint64_t log_mask; 1263 1264 struct dpcd_vendor_signature vendor_signature; 1265 bool force_smu_not_present; 1266 /* 1267 * IP offset for run time initializaion of register addresses 1268 * 1269 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1270 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1271 * before them. 1272 */ 1273 uint32_t *dcn_reg_offsets; 1274 uint32_t *nbio_reg_offsets; 1275 uint32_t *clk_reg_offsets; 1276 void *bb_from_dmub; 1277 }; 1278 1279 struct dc_callback_init { 1280 struct cp_psp cp_psp; 1281 }; 1282 1283 struct dc *dc_create(const struct dc_init_data *init_params); 1284 void dc_hardware_init(struct dc *dc); 1285 1286 int dc_get_vmid_use_vector(struct dc *dc); 1287 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1288 /* Returns the number of vmids supported */ 1289 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1290 void dc_init_callbacks(struct dc *dc, 1291 const struct dc_callback_init *init_params); 1292 void dc_deinit_callbacks(struct dc *dc); 1293 void dc_destroy(struct dc **dc); 1294 1295 /* Surface Interfaces */ 1296 1297 enum { 1298 TRANSFER_FUNC_POINTS = 1025 1299 }; 1300 1301 struct dc_hdr_static_metadata { 1302 /* display chromaticities and white point in units of 0.00001 */ 1303 unsigned int chromaticity_green_x; 1304 unsigned int chromaticity_green_y; 1305 unsigned int chromaticity_blue_x; 1306 unsigned int chromaticity_blue_y; 1307 unsigned int chromaticity_red_x; 1308 unsigned int chromaticity_red_y; 1309 unsigned int chromaticity_white_point_x; 1310 unsigned int chromaticity_white_point_y; 1311 1312 uint32_t min_luminance; 1313 uint32_t max_luminance; 1314 uint32_t maximum_content_light_level; 1315 uint32_t maximum_frame_average_light_level; 1316 }; 1317 1318 enum dc_transfer_func_type { 1319 TF_TYPE_PREDEFINED, 1320 TF_TYPE_DISTRIBUTED_POINTS, 1321 TF_TYPE_BYPASS, 1322 TF_TYPE_HWPWL 1323 }; 1324 1325 struct dc_transfer_func_distributed_points { 1326 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1327 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1328 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1329 1330 uint16_t end_exponent; 1331 uint16_t x_point_at_y1_red; 1332 uint16_t x_point_at_y1_green; 1333 uint16_t x_point_at_y1_blue; 1334 }; 1335 1336 enum dc_transfer_func_predefined { 1337 TRANSFER_FUNCTION_SRGB, 1338 TRANSFER_FUNCTION_BT709, 1339 TRANSFER_FUNCTION_PQ, 1340 TRANSFER_FUNCTION_LINEAR, 1341 TRANSFER_FUNCTION_UNITY, 1342 TRANSFER_FUNCTION_HLG, 1343 TRANSFER_FUNCTION_HLG12, 1344 TRANSFER_FUNCTION_GAMMA22, 1345 TRANSFER_FUNCTION_GAMMA24, 1346 TRANSFER_FUNCTION_GAMMA26 1347 }; 1348 1349 1350 struct dc_transfer_func { 1351 struct kref refcount; 1352 enum dc_transfer_func_type type; 1353 enum dc_transfer_func_predefined tf; 1354 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1355 uint32_t sdr_ref_white_level; 1356 union { 1357 struct pwl_params pwl; 1358 struct dc_transfer_func_distributed_points tf_pts; 1359 }; 1360 }; 1361 1362 1363 union dc_3dlut_state { 1364 struct { 1365 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1366 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1367 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1368 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1369 uint32_t mpc_rmu1_mux:4; 1370 uint32_t mpc_rmu2_mux:4; 1371 uint32_t reserved:15; 1372 } bits; 1373 uint32_t raw; 1374 }; 1375 1376 1377 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1378 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1379 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1380 1381 struct lut_rgb { 1382 uint16_t b; 1383 uint16_t g; 1384 uint16_t r; 1385 uint16_t padding; 1386 }; 1387 1388 //this structure maps directly to how the lut will read it from memory 1389 struct lut_mem_mapping { 1390 union { 1391 //NATIVE MODE 1, 2 1392 //RGB layout [b][g][r] //red is 128 byte aligned 1393 //BGR layout [r][g][b] //blue is 128 byte aligned 1394 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1395 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1396 1397 //TRANSFORMED 1398 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1399 }; 1400 uint16_t size; 1401 }; 1402 1403 struct dc_rmcm_3dlut { 1404 bool isInUse; 1405 const struct dc_stream_state *stream; 1406 uint8_t protection_bits; 1407 }; 1408 1409 struct dc_3dlut { 1410 struct kref refcount; 1411 struct tetrahedral_params lut_3d; 1412 struct fixed31_32 hdr_multiplier; 1413 union dc_3dlut_state state; 1414 }; 1415 /* 1416 * This structure is filled in by dc_surface_get_status and contains 1417 * the last requested address and the currently active address so the called 1418 * can determine if there are any outstanding flips 1419 */ 1420 struct dc_plane_status { 1421 struct dc_plane_address requested_address; 1422 struct dc_plane_address current_address; 1423 bool is_flip_pending; 1424 bool is_right_eye; 1425 struct cm_hist cm_hist; 1426 }; 1427 1428 union surface_update_flags { 1429 1430 struct { 1431 uint32_t addr_update:1; 1432 /* Medium updates */ 1433 uint32_t dcc_change:1; 1434 uint32_t color_space_change:1; 1435 uint32_t horizontal_mirror_change:1; 1436 uint32_t per_pixel_alpha_change:1; 1437 uint32_t global_alpha_change:1; 1438 uint32_t hdr_mult:1; 1439 uint32_t rotation_change:1; 1440 uint32_t swizzle_change:1; 1441 uint32_t scaling_change:1; 1442 uint32_t position_change:1; 1443 uint32_t in_transfer_func_change:1; 1444 uint32_t input_csc_change:1; 1445 uint32_t coeff_reduction_change:1; 1446 uint32_t pixel_format_change:1; 1447 uint32_t plane_size_change:1; 1448 uint32_t gamut_remap_change:1; 1449 1450 /* Full updates */ 1451 uint32_t new_plane:1; 1452 uint32_t bpp_change:1; 1453 uint32_t gamma_change:1; 1454 uint32_t bandwidth_change:1; 1455 uint32_t clock_change:1; 1456 uint32_t stereo_format_change:1; 1457 uint32_t lut_3d:1; 1458 uint32_t tmz_changed:1; 1459 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1460 uint32_t full_update:1; 1461 uint32_t sdr_white_level_nits:1; 1462 uint32_t cm_hist_change:1; 1463 } bits; 1464 1465 uint32_t raw; 1466 }; 1467 1468 #define DC_REMOVE_PLANE_POINTERS 1 1469 1470 struct dc_plane_state { 1471 struct dc_plane_address address; 1472 struct dc_plane_flip_time time; 1473 bool triplebuffer_flips; 1474 struct scaling_taps scaling_quality; 1475 struct rect src_rect; 1476 struct rect dst_rect; 1477 struct rect clip_rect; 1478 1479 struct plane_size plane_size; 1480 struct dc_tiling_info tiling_info; 1481 1482 struct dc_plane_dcc_param dcc; 1483 1484 struct dc_gamma gamma_correction; 1485 struct dc_transfer_func in_transfer_func; 1486 struct dc_bias_and_scale bias_and_scale; 1487 struct dc_csc_transform input_csc_color_matrix; 1488 struct fixed31_32 coeff_reduction_factor; 1489 struct fixed31_32 hdr_mult; 1490 struct colorspace_transform gamut_remap_matrix; 1491 1492 // TODO: No longer used, remove 1493 struct dc_hdr_static_metadata hdr_static_ctx; 1494 1495 enum dc_color_space color_space; 1496 1497 struct dc_3dlut lut3d_func; 1498 struct dc_transfer_func in_shaper_func; 1499 struct dc_transfer_func blend_tf; 1500 1501 struct dc_transfer_func *gamcor_tf; 1502 enum surface_pixel_format format; 1503 enum dc_rotation_angle rotation; 1504 enum plane_stereo_format stereo_format; 1505 1506 bool is_tiling_rotated; 1507 bool per_pixel_alpha; 1508 bool pre_multiplied_alpha; 1509 bool global_alpha; 1510 int global_alpha_value; 1511 bool visible; 1512 bool flip_immediate; 1513 bool horizontal_mirror; 1514 int layer_index; 1515 1516 union surface_update_flags update_flags; 1517 bool flip_int_enabled; 1518 bool skip_manual_trigger; 1519 1520 /* private to DC core */ 1521 struct dc_plane_status status; 1522 struct dc_context *ctx; 1523 1524 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1525 bool force_full_update; 1526 1527 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1528 1529 /* private to dc_surface.c */ 1530 enum dc_irq_source irq_source; 1531 struct kref refcount; 1532 struct tg_color visual_confirm_color; 1533 1534 bool is_statically_allocated; 1535 enum chroma_cositing cositing; 1536 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1537 bool mcm_lut1d_enable; 1538 struct dc_cm2_func_luts mcm_luts; 1539 bool lut_bank_a; 1540 enum mpcc_movable_cm_location mcm_location; 1541 struct dc_csc_transform cursor_csc_color_matrix; 1542 bool adaptive_sharpness_en; 1543 int adaptive_sharpness_policy; 1544 int sharpness_level; 1545 enum linear_light_scaling linear_light_scaling; 1546 unsigned int sdr_white_level_nits; 1547 struct cm_hist_control cm_hist_control; 1548 struct spl_sharpness_range sharpness_range; 1549 enum sharpness_range_source sharpness_source; 1550 }; 1551 1552 struct dc_plane_info { 1553 struct plane_size plane_size; 1554 struct dc_tiling_info tiling_info; 1555 struct dc_plane_dcc_param dcc; 1556 enum surface_pixel_format format; 1557 enum dc_rotation_angle rotation; 1558 enum plane_stereo_format stereo_format; 1559 enum dc_color_space color_space; 1560 bool horizontal_mirror; 1561 bool visible; 1562 bool per_pixel_alpha; 1563 bool pre_multiplied_alpha; 1564 bool global_alpha; 1565 int global_alpha_value; 1566 bool input_csc_enabled; 1567 int layer_index; 1568 enum chroma_cositing cositing; 1569 }; 1570 1571 #include "dc_stream.h" 1572 1573 struct dc_scratch_space { 1574 /* used to temporarily backup plane states of a stream during 1575 * dc update. The reason is that plane states are overwritten 1576 * with surface updates in dc update. Once they are overwritten 1577 * current state is no longer valid. We want to temporarily 1578 * store current value in plane states so we can still recover 1579 * a valid current state during dc update. 1580 */ 1581 struct dc_plane_state plane_states[MAX_SURFACES]; 1582 1583 struct dc_stream_state stream_state; 1584 }; 1585 1586 /* 1587 * A link contains one or more sinks and their connected status. 1588 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1589 */ 1590 struct dc_link { 1591 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1592 unsigned int sink_count; 1593 struct dc_sink *local_sink; 1594 unsigned int link_index; 1595 enum dc_connection_type type; 1596 enum signal_type connector_signal; 1597 enum dc_irq_source irq_source_hpd; 1598 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1599 enum dc_irq_source irq_source_read_request;/* Read Request */ 1600 1601 bool is_hpd_filter_disabled; 1602 bool dp_ss_off; 1603 1604 /** 1605 * @link_state_valid: 1606 * 1607 * If there is no link and local sink, this variable should be set to 1608 * false. Otherwise, it should be set to true; usually, the function 1609 * core_link_enable_stream sets this field to true. 1610 */ 1611 bool link_state_valid; 1612 bool aux_access_disabled; 1613 bool sync_lt_in_progress; 1614 bool skip_stream_reenable; 1615 bool is_internal_display; 1616 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1617 bool is_dig_mapping_flexible; 1618 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1619 bool is_hpd_pending; /* Indicates a new received hpd */ 1620 1621 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1622 * for every link training. This is incompatible with DP LL compliance automation, 1623 * which expects the same link settings to be used every retry on a link loss. 1624 * This flag is used to skip the fallback when link loss occurs during automation. 1625 */ 1626 bool skip_fallback_on_link_loss; 1627 1628 bool edp_sink_present; 1629 1630 struct dp_trace dp_trace; 1631 1632 /* caps is the same as reported_link_cap. link_traing use 1633 * reported_link_cap. Will clean up. TODO 1634 */ 1635 struct dc_link_settings reported_link_cap; 1636 struct dc_link_settings verified_link_cap; 1637 struct dc_link_settings cur_link_settings; 1638 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1639 struct dc_link_settings preferred_link_setting; 1640 /* preferred_training_settings are override values that 1641 * come from DM. DM is responsible for the memory 1642 * management of the override pointers. 1643 */ 1644 struct dc_link_training_overrides preferred_training_settings; 1645 struct dp_audio_test_data audio_test_data; 1646 1647 uint8_t ddc_hw_inst; 1648 1649 uint8_t hpd_src; 1650 1651 uint8_t link_enc_hw_inst; 1652 /* DIG link encoder ID. Used as index in link encoder resource pool. 1653 * For links with fixed mapping to DIG, this is not changed after dc_link 1654 * object creation. 1655 */ 1656 enum engine_id eng_id; 1657 enum engine_id dpia_preferred_eng_id; 1658 1659 bool test_pattern_enabled; 1660 /* Pending/Current test pattern are only used to perform and track 1661 * FIXED_VS retimer test pattern/lane adjustment override state. 1662 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1663 * to perform specific lane adjust overrides before setting certain 1664 * PHY test patterns. In cases when lane adjust and set test pattern 1665 * calls are not performed atomically (i.e. performing link training), 1666 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1667 * and current_test_pattern will contain required context for any future 1668 * set pattern/set lane adjust to transition between override state(s). 1669 * */ 1670 enum dp_test_pattern current_test_pattern; 1671 enum dp_test_pattern pending_test_pattern; 1672 1673 union compliance_test_state compliance_test_state; 1674 1675 void *priv; 1676 1677 struct ddc_service *ddc; 1678 1679 enum dp_panel_mode panel_mode; 1680 bool aux_mode; 1681 1682 /* Private to DC core */ 1683 1684 const struct dc *dc; 1685 1686 struct dc_context *ctx; 1687 1688 struct panel_cntl *panel_cntl; 1689 struct link_encoder *link_enc; 1690 struct graphics_object_id link_id; 1691 1692 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1693 struct graphics_object_id ext_enc_id; 1694 1695 /* Endpoint type distinguishes display endpoints which do not have entries 1696 * in the BIOS connector table from those that do. Helps when tracking link 1697 * encoder to display endpoint assignments. 1698 */ 1699 enum display_endpoint_type ep_type; 1700 union ddi_channel_mapping ddi_channel_mapping; 1701 struct connector_device_tag_info device_tag; 1702 struct dpcd_caps dpcd_caps; 1703 uint32_t dongle_max_pix_clk; 1704 unsigned short chip_caps; 1705 unsigned int dpcd_sink_count; 1706 struct hdcp_caps hdcp_caps; 1707 enum edp_revision edp_revision; 1708 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1709 1710 struct psr_settings psr_settings; 1711 struct replay_settings replay_settings; 1712 1713 /* Drive settings read from integrated info table */ 1714 struct dc_lane_settings bios_forced_drive_settings; 1715 1716 /* Vendor specific LTTPR workaround variables */ 1717 uint8_t vendor_specific_lttpr_link_rate_wa; 1718 bool apply_vendor_specific_lttpr_link_rate_wa; 1719 1720 /* MST record stream using this link */ 1721 struct link_flags { 1722 bool dp_keep_receiver_powered; 1723 bool dp_skip_DID2; 1724 bool dp_skip_reset_segment; 1725 bool dp_skip_fs_144hz; 1726 bool dp_mot_reset_segment; 1727 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1728 bool dpia_mst_dsc_always_on; 1729 /* Forced DPIA into TBT3 compatibility mode. */ 1730 bool dpia_forced_tbt3_mode; 1731 bool dongle_mode_timing_override; 1732 bool blank_stream_on_ocs_change; 1733 bool read_dpcd204h_on_irq_hpd; 1734 bool force_dp_ffe_preset; 1735 bool skip_phy_ssc_reduction; 1736 } wa_flags; 1737 union dc_dp_ffe_preset forced_dp_ffe_preset; 1738 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1739 1740 struct dc_link_status link_status; 1741 struct dprx_states dprx_states; 1742 1743 enum dc_link_fec_state fec_state; 1744 bool is_dds; 1745 bool is_display_mux_present; 1746 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1747 1748 struct dc_panel_config panel_config; 1749 enum dc_panel_type panel_type; 1750 struct phy_state phy_state; 1751 uint32_t phy_transition_bitmask; 1752 // BW ALLOCATON USB4 ONLY 1753 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1754 bool skip_implict_edp_power_control; 1755 enum backlight_control_type backlight_control_type; 1756 }; 1757 1758 struct dc { 1759 struct dc_debug_options debug; 1760 struct dc_versions versions; 1761 struct dc_caps caps; 1762 struct dc_check_config check_config; 1763 struct dc_cap_funcs cap_funcs; 1764 struct dc_config config; 1765 struct dc_bounding_box_overrides bb_overrides; 1766 struct dc_bug_wa work_arounds; 1767 struct dc_context *ctx; 1768 struct dc_phy_addr_space_config vm_pa_config; 1769 1770 uint8_t link_count; 1771 struct dc_link *links[MAX_LINKS]; 1772 uint8_t lowest_dpia_link_index; 1773 struct link_service *link_srv; 1774 1775 struct dc_state *current_state; 1776 struct resource_pool *res_pool; 1777 1778 struct clk_mgr *clk_mgr; 1779 1780 /* Display Engine Clock levels */ 1781 struct dm_pp_clock_levels sclk_lvls; 1782 1783 /* Inputs into BW and WM calculations. */ 1784 struct bw_calcs_dceip *bw_dceip; 1785 struct bw_calcs_vbios *bw_vbios; 1786 struct dcn_soc_bounding_box *dcn_soc; 1787 struct dcn_ip_params *dcn_ip; 1788 struct display_mode_lib dml; 1789 1790 /* HW functions */ 1791 struct hw_sequencer_funcs hwss; 1792 struct dce_hwseq *hwseq; 1793 1794 /* Require to optimize clocks and bandwidth for added/removed planes */ 1795 bool optimized_required; 1796 bool idle_optimizations_allowed; 1797 bool enable_c20_dtm_b0; 1798 1799 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1800 1801 /* For eDP to know the switching state of SmartMux */ 1802 bool is_switch_in_progress_orig; 1803 bool is_switch_in_progress_dest; 1804 1805 /* FBC compressor */ 1806 struct compressor *fbc_compressor; 1807 1808 struct dc_debug_data debug_data; 1809 struct dpcd_vendor_signature vendor_signature; 1810 1811 const char *build_id; 1812 struct vm_helper *vm_helper; 1813 1814 uint32_t *dcn_reg_offsets; 1815 uint32_t *nbio_reg_offsets; 1816 uint32_t *clk_reg_offsets; 1817 1818 /* Scratch memory */ 1819 struct { 1820 struct { 1821 /* 1822 * For matching clock_limits table in driver with table 1823 * from PMFW. 1824 */ 1825 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1826 } update_bw_bounding_box; 1827 struct dc_scratch_space current_state; 1828 struct dc_scratch_space new_state; 1829 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1830 struct dc_link temp_link; 1831 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1832 } scratch; 1833 1834 struct dml2_configuration_options dml2_options; 1835 struct dml2_configuration_options dml2_dc_power_options; 1836 enum dc_acpi_cm_power_state power_state; 1837 struct soc_and_ip_translator *soc_and_ip_translator; 1838 }; 1839 1840 struct dc_scaling_info { 1841 struct rect src_rect; 1842 struct rect dst_rect; 1843 struct rect clip_rect; 1844 struct scaling_taps scaling_quality; 1845 }; 1846 1847 struct dc_fast_update { 1848 const struct dc_flip_addrs *flip_addr; 1849 const struct dc_gamma *gamma; 1850 const struct colorspace_transform *gamut_remap_matrix; 1851 const struct dc_csc_transform *input_csc_color_matrix; 1852 const struct fixed31_32 *coeff_reduction_factor; 1853 struct dc_transfer_func *out_transfer_func; 1854 struct dc_csc_transform *output_csc_transform; 1855 const struct dc_csc_transform *cursor_csc_color_matrix; 1856 struct cm_hist_control *cm_hist_control; 1857 }; 1858 1859 struct dc_surface_update { 1860 struct dc_plane_state *surface; 1861 1862 /* isr safe update parameters. null means no updates */ 1863 const struct dc_flip_addrs *flip_addr; 1864 const struct dc_plane_info *plane_info; 1865 const struct dc_scaling_info *scaling_info; 1866 struct fixed31_32 hdr_mult; 1867 /* following updates require alloc/sleep/spin that is not isr safe, 1868 * null means no updates 1869 */ 1870 const struct dc_gamma *gamma; 1871 const struct dc_transfer_func *in_transfer_func; 1872 1873 const struct dc_csc_transform *input_csc_color_matrix; 1874 const struct fixed31_32 *coeff_reduction_factor; 1875 const struct dc_transfer_func *func_shaper; 1876 const struct dc_3dlut *lut3d_func; 1877 const struct dc_transfer_func *blend_tf; 1878 const struct colorspace_transform *gamut_remap_matrix; 1879 /* 1880 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1881 * 1882 * change cm2_params.component_settings: Full update 1883 * change cm2_params.cm2_luts: Fast update 1884 */ 1885 const struct dc_cm2_parameters *cm2_params; 1886 const struct dc_csc_transform *cursor_csc_color_matrix; 1887 unsigned int sdr_white_level_nits; 1888 struct dc_bias_and_scale bias_and_scale; 1889 struct cm_hist_control *cm_hist_control; 1890 }; 1891 1892 struct dc_underflow_debug_data { 1893 struct dcn_hubbub_reg_state *hubbub_reg_state; 1894 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 1895 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 1896 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 1897 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 1898 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 1899 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 1900 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 1901 }; 1902 1903 struct power_features { 1904 bool ips; 1905 bool rcg; 1906 bool replay; 1907 bool dds; 1908 bool sprs; 1909 bool psr; 1910 bool fams; 1911 bool mpo; 1912 bool uclk_p_state; 1913 }; 1914 1915 /* 1916 * Create a new surface with default parameters; 1917 */ 1918 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1919 void dc_gamma_release(struct dc_gamma **dc_gamma); 1920 struct dc_gamma *dc_create_gamma(void); 1921 1922 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1923 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1924 struct dc_transfer_func *dc_create_transfer_func(void); 1925 1926 struct dc_3dlut *dc_create_3dlut_func(void); 1927 void dc_3dlut_func_release(struct dc_3dlut *lut); 1928 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1929 1930 void dc_post_update_surfaces_to_stream( 1931 struct dc *dc); 1932 1933 /** 1934 * struct dc_validation_set - Struct to store surface/stream associations for validation 1935 */ 1936 struct dc_validation_set { 1937 /** 1938 * @stream: Stream state properties 1939 */ 1940 struct dc_stream_state *stream; 1941 1942 /** 1943 * @plane_states: Surface state 1944 */ 1945 struct dc_plane_state *plane_states[MAX_SURFACES]; 1946 1947 /** 1948 * @plane_count: Total of active planes 1949 */ 1950 uint8_t plane_count; 1951 }; 1952 1953 bool dc_validate_boot_timing(const struct dc *dc, 1954 const struct dc_sink *sink, 1955 struct dc_crtc_timing *crtc_timing); 1956 1957 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1958 1959 enum dc_status dc_validate_with_context(struct dc *dc, 1960 const struct dc_validation_set set[], 1961 int set_count, 1962 struct dc_state *context, 1963 enum dc_validate_mode validate_mode); 1964 1965 bool dc_set_generic_gpio_for_stereo(bool enable, 1966 struct gpio_service *gpio_service); 1967 1968 enum dc_status dc_validate_global_state( 1969 struct dc *dc, 1970 struct dc_state *new_ctx, 1971 enum dc_validate_mode validate_mode); 1972 1973 bool dc_acquire_release_mpc_3dlut( 1974 struct dc *dc, bool acquire, 1975 struct dc_stream_state *stream, 1976 struct dc_3dlut **lut, 1977 struct dc_transfer_func **shaper); 1978 1979 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1980 void get_audio_check(struct audio_info *aud_modes, 1981 struct audio_check *aud_chk); 1982 1983 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1984 void populate_fast_updates(struct dc_fast_update *fast_update, 1985 struct dc_surface_update *srf_updates, 1986 int surface_count, 1987 struct dc_stream_update *stream_update); 1988 /* 1989 * Set up streams and links associated to drive sinks 1990 * The streams parameter is an absolute set of all active streams. 1991 * 1992 * After this call: 1993 * Phy, Encoder, Timing Generator are programmed and enabled. 1994 * New streams are enabled with blank stream; no memory read. 1995 */ 1996 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1997 1998 1999 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2000 struct dc_stream_state *stream, 2001 int mpcc_inst); 2002 2003 2004 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2005 2006 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2007 2008 /* The function returns minimum bandwidth required to drive a given timing 2009 * return - minimum required timing bandwidth in kbps. 2010 */ 2011 uint32_t dc_bandwidth_in_kbps_from_timing( 2012 const struct dc_crtc_timing *timing, 2013 const enum dc_link_encoding_format link_encoding); 2014 2015 /* Link Interfaces */ 2016 /* Return an enumerated dc_link. 2017 * dc_link order is constant and determined at 2018 * boot time. They cannot be created or destroyed. 2019 * Use dc_get_caps() to get number of links. 2020 */ 2021 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2022 2023 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2024 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2025 const struct dc_link *link, 2026 unsigned int *inst_out); 2027 2028 /* Return an array of link pointers to edp links. */ 2029 void dc_get_edp_links(const struct dc *dc, 2030 struct dc_link **edp_links, 2031 int *edp_num); 2032 2033 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2034 bool powerOn); 2035 2036 /* The function initiates detection handshake over the given link. It first 2037 * determines if there are display connections over the link. If so it initiates 2038 * detection protocols supported by the connected receiver device. The function 2039 * contains protocol specific handshake sequences which are sometimes mandatory 2040 * to establish a proper connection between TX and RX. So it is always 2041 * recommended to call this function as the first link operation upon HPD event 2042 * or power up event. Upon completion, the function will update link structure 2043 * in place based on latest RX capabilities. The function may also cause dpms 2044 * to be reset to off for all currently enabled streams to the link. It is DM's 2045 * responsibility to serialize detection and DPMS updates. 2046 * 2047 * @reason - Indicate which event triggers this detection. dc may customize 2048 * detection flow depending on the triggering events. 2049 * return false - if detection is not fully completed. This could happen when 2050 * there is an unrecoverable error during detection or detection is partially 2051 * completed (detection has been delegated to dm mst manager ie. 2052 * link->connection_type == dc_connection_mst_branch when returning false). 2053 * return true - detection is completed, link has been fully updated with latest 2054 * detection result. 2055 */ 2056 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2057 2058 struct dc_sink_init_data; 2059 2060 /* When link connection type is dc_connection_mst_branch, remote sink can be 2061 * added to the link. The interface creates a remote sink and associates it with 2062 * current link. The sink will be retained by link until remove remote sink is 2063 * called. 2064 * 2065 * @dc_link - link the remote sink will be added to. 2066 * @edid - byte array of EDID raw data. 2067 * @len - size of the edid in byte 2068 * @init_data - 2069 */ 2070 struct dc_sink *dc_link_add_remote_sink( 2071 struct dc_link *dc_link, 2072 const uint8_t *edid, 2073 int len, 2074 struct dc_sink_init_data *init_data); 2075 2076 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2077 * @link - link the sink should be removed from 2078 * @sink - sink to be removed. 2079 */ 2080 void dc_link_remove_remote_sink( 2081 struct dc_link *link, 2082 struct dc_sink *sink); 2083 2084 /* Enable HPD interrupt handler for a given link */ 2085 void dc_link_enable_hpd(const struct dc_link *link); 2086 2087 /* Disable HPD interrupt handler for a given link */ 2088 void dc_link_disable_hpd(const struct dc_link *link); 2089 2090 /* determine if there is a sink connected to the link 2091 * 2092 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2093 * return - false if an unexpected error occurs, true otherwise. 2094 * 2095 * NOTE: This function doesn't detect downstream sink connections i.e 2096 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2097 * return dc_connection_single if the branch device is connected despite of 2098 * downstream sink's connection status. 2099 */ 2100 bool dc_link_detect_connection_type(struct dc_link *link, 2101 enum dc_connection_type *type); 2102 2103 /* query current hpd pin value 2104 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2105 * 2106 */ 2107 bool dc_link_get_hpd_state(struct dc_link *link); 2108 2109 /* Getter for cached link status from given link */ 2110 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2111 2112 /* enable/disable hardware HPD filter. 2113 * 2114 * @link - The link the HPD pin is associated with. 2115 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2116 * handler once after no HPD change has been detected within dc default HPD 2117 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2118 * pulses within default HPD interval, no HPD event will be received until HPD 2119 * toggles have stopped. Then HPD event will be queued to irq handler once after 2120 * dc default HPD filtering interval since last HPD event. 2121 * 2122 * @enable = false - disable hardware HPD filter. HPD event will be queued 2123 * immediately to irq handler after no HPD change has been detected within 2124 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2125 */ 2126 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2127 2128 /* submit i2c read/write payloads through ddc channel 2129 * @link_index - index to a link with ddc in i2c mode 2130 * @cmd - i2c command structure 2131 * return - true if success, false otherwise. 2132 */ 2133 bool dc_submit_i2c( 2134 struct dc *dc, 2135 uint32_t link_index, 2136 struct i2c_command *cmd); 2137 2138 /* submit i2c read/write payloads through oem channel 2139 * @link_index - index to a link with ddc in i2c mode 2140 * @cmd - i2c command structure 2141 * return - true if success, false otherwise. 2142 */ 2143 bool dc_submit_i2c_oem( 2144 struct dc *dc, 2145 struct i2c_command *cmd); 2146 2147 enum aux_return_code_type; 2148 /* Attempt to transfer the given aux payload. This function does not perform 2149 * retries or handle error states. The reply is returned in the payload->reply 2150 * and the result through operation_result. Returns the number of bytes 2151 * transferred,or -1 on a failure. 2152 */ 2153 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2154 struct aux_payload *payload, 2155 enum aux_return_code_type *operation_result); 2156 2157 struct ddc_service * 2158 dc_get_oem_i2c_device(struct dc *dc); 2159 2160 bool dc_is_oem_i2c_device_present( 2161 struct dc *dc, 2162 size_t slave_address 2163 ); 2164 2165 /* return true if the connected receiver supports the hdcp version */ 2166 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2167 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2168 2169 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2170 * 2171 * TODO - When defer_handling is true the function will have a different purpose. 2172 * It no longer does complete hpd rx irq handling. We should create a separate 2173 * interface specifically for this case. 2174 * 2175 * Return: 2176 * true - Downstream port status changed. DM should call DC to do the 2177 * detection. 2178 * false - no change in Downstream port status. No further action required 2179 * from DM. 2180 */ 2181 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2182 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2183 bool defer_handling, bool *has_left_work); 2184 /* handle DP specs define test automation sequence*/ 2185 void dc_link_dp_handle_automated_test(struct dc_link *link); 2186 2187 /* handle DP Link loss sequence and try to recover RX link loss with best 2188 * effort 2189 */ 2190 void dc_link_dp_handle_link_loss(struct dc_link *link); 2191 2192 /* Determine if hpd rx irq should be handled or ignored 2193 * return true - hpd rx irq should be handled. 2194 * return false - it is safe to ignore hpd rx irq event 2195 */ 2196 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2197 2198 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2199 * @link - link the hpd irq data associated with 2200 * @hpd_irq_dpcd_data - input hpd irq data 2201 * return - true if hpd irq data indicates a link lost 2202 */ 2203 bool dc_link_check_link_loss_status(struct dc_link *link, 2204 union hpd_irq_data *hpd_irq_dpcd_data); 2205 2206 /* Read hpd rx irq data from a given link 2207 * @link - link where the hpd irq data should be read from 2208 * @irq_data - output hpd irq data 2209 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2210 * read has failed. 2211 */ 2212 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2213 struct dc_link *link, 2214 union hpd_irq_data *irq_data); 2215 2216 /* The function clears recorded DP RX states in the link. DM should call this 2217 * function when it is resuming from S3 power state to previously connected links. 2218 * 2219 * TODO - in the future we should consider to expand link resume interface to 2220 * support clearing previous rx states. So we don't have to rely on dm to call 2221 * this interface explicitly. 2222 */ 2223 void dc_link_clear_dprx_states(struct dc_link *link); 2224 2225 /* Destruct the mst topology of the link and reset the allocated payload table 2226 * 2227 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2228 * still wants to reset MST topology on an unplug event */ 2229 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2230 2231 /* The function calculates effective DP link bandwidth when a given link is 2232 * using the given link settings. 2233 * 2234 * return - total effective link bandwidth in kbps. 2235 */ 2236 uint32_t dc_link_bandwidth_kbps( 2237 const struct dc_link *link, 2238 const struct dc_link_settings *link_setting); 2239 2240 struct dp_audio_bandwidth_params { 2241 const struct dc_crtc_timing *crtc_timing; 2242 enum dp_link_encoding link_encoding; 2243 uint32_t channel_count; 2244 uint32_t sample_rate_hz; 2245 }; 2246 2247 /* The function calculates the minimum size of hblank (in bytes) needed to 2248 * support the specified channel count and sample rate combination, given the 2249 * link encoding and timing to be used. This calculation is not supported 2250 * for 8b/10b SST. 2251 * 2252 * return - min hblank size in bytes, 0 if 8b/10b SST. 2253 */ 2254 uint32_t dc_link_required_hblank_size_bytes( 2255 const struct dc_link *link, 2256 struct dp_audio_bandwidth_params *audio_params); 2257 2258 /* The function takes a snapshot of current link resource allocation state 2259 * @dc: pointer to dc of the dm calling this 2260 * @map: a dc link resource snapshot defined internally to dc. 2261 * 2262 * DM needs to capture a snapshot of current link resource allocation mapping 2263 * and store it in its persistent storage. 2264 * 2265 * Some of the link resource is using first come first serve policy. 2266 * The allocation mapping depends on original hotplug order. This information 2267 * is lost after driver is loaded next time. The snapshot is used in order to 2268 * restore link resource to its previous state so user will get consistent 2269 * link capability allocation across reboot. 2270 * 2271 */ 2272 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2273 2274 /* This function restores link resource allocation state from a snapshot 2275 * @dc: pointer to dc of the dm calling this 2276 * @map: a dc link resource snapshot defined internally to dc. 2277 * 2278 * DM needs to call this function after initial link detection on boot and 2279 * before first commit streams to restore link resource allocation state 2280 * from previous boot session. 2281 * 2282 * Some of the link resource is using first come first serve policy. 2283 * The allocation mapping depends on original hotplug order. This information 2284 * is lost after driver is loaded next time. The snapshot is used in order to 2285 * restore link resource to its previous state so user will get consistent 2286 * link capability allocation across reboot. 2287 * 2288 */ 2289 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2290 2291 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2292 * interface i.e stream_update->dsc_config 2293 */ 2294 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2295 2296 /* translate a raw link rate data to bandwidth in kbps */ 2297 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2298 2299 /* determine the optimal bandwidth given link and required bw. 2300 * @link - current detected link 2301 * @req_bw - requested bandwidth in kbps 2302 * @link_settings - returned most optimal link settings that can fit the 2303 * requested bandwidth 2304 * return - false if link can't support requested bandwidth, true if link 2305 * settings is found. 2306 */ 2307 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2308 struct dc_link_settings *link_settings, 2309 uint32_t req_bw); 2310 2311 /* return the max dp link settings can be driven by the link without considering 2312 * connected RX device and its capability 2313 */ 2314 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2315 struct dc_link_settings *max_link_enc_cap); 2316 2317 /* determine when the link is driving MST mode, what DP link channel coding 2318 * format will be used. The decision will remain unchanged until next HPD event. 2319 * 2320 * @link - a link with DP RX connection 2321 * return - if stream is committed to this link with MST signal type, type of 2322 * channel coding format dc will choose. 2323 */ 2324 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2325 const struct dc_link *link); 2326 2327 /* get max dp link settings the link can enable with all things considered. (i.e 2328 * TX/RX/Cable capabilities and dp override policies. 2329 * 2330 * @link - a link with DP RX connection 2331 * return - max dp link settings the link can enable. 2332 * 2333 */ 2334 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2335 2336 /* Get the highest encoding format that the link supports; highest meaning the 2337 * encoding format which supports the maximum bandwidth. 2338 * 2339 * @link - a link with DP RX connection 2340 * return - highest encoding format link supports. 2341 */ 2342 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2343 2344 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2345 * to a link with dp connector signal type. 2346 * @link - a link with dp connector signal type 2347 * return - true if connected, false otherwise 2348 */ 2349 bool dc_link_is_dp_sink_present(struct dc_link *link); 2350 2351 /* Force DP lane settings update to main-link video signal and notify the change 2352 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2353 * tuning purpose. The interface assumes link has already been enabled with DP 2354 * signal. 2355 * 2356 * @lt_settings - a container structure with desired hw_lane_settings 2357 */ 2358 void dc_link_set_drive_settings(struct dc *dc, 2359 struct link_training_settings *lt_settings, 2360 struct dc_link *link); 2361 2362 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2363 * test or debugging purpose. The test pattern will remain until next un-plug. 2364 * 2365 * @link - active link with DP signal output enabled. 2366 * @test_pattern - desired test pattern to output. 2367 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2368 * @test_pattern_color_space - for video test pattern choose a desired color 2369 * space. 2370 * @p_link_settings - For PHY pattern choose a desired link settings 2371 * @p_custom_pattern - some test pattern will require a custom input to 2372 * customize some pattern details. Otherwise keep it to NULL. 2373 * @cust_pattern_size - size of the custom pattern input. 2374 * 2375 */ 2376 bool dc_link_dp_set_test_pattern( 2377 struct dc_link *link, 2378 enum dp_test_pattern test_pattern, 2379 enum dp_test_pattern_color_space test_pattern_color_space, 2380 const struct link_training_settings *p_link_settings, 2381 const unsigned char *p_custom_pattern, 2382 unsigned int cust_pattern_size); 2383 2384 /* Force DP link settings to always use a specific value until reboot to a 2385 * specific link. If link has already been enabled, the interface will also 2386 * switch to desired link settings immediately. This is a debug interface to 2387 * generic dp issue trouble shooting. 2388 */ 2389 void dc_link_set_preferred_link_settings(struct dc *dc, 2390 struct dc_link_settings *link_setting, 2391 struct dc_link *link); 2392 2393 /* Force DP link to customize a specific link training behavior by overriding to 2394 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2395 * display specific link training issues or apply some display specific 2396 * workaround in link training. 2397 * 2398 * @link_settings - if not NULL, force preferred link settings to the link. 2399 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2400 * will apply this particular override in future link training. If NULL is 2401 * passed in, dc resets previous overrides. 2402 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2403 * training settings. 2404 */ 2405 void dc_link_set_preferred_training_settings(struct dc *dc, 2406 struct dc_link_settings *link_setting, 2407 struct dc_link_training_overrides *lt_overrides, 2408 struct dc_link *link, 2409 bool skip_immediate_retrain); 2410 2411 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2412 bool dc_link_is_fec_supported(const struct dc_link *link); 2413 2414 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2415 * link enablement. 2416 * return - true if FEC should be enabled, false otherwise. 2417 */ 2418 bool dc_link_should_enable_fec(const struct dc_link *link); 2419 2420 /* determine lttpr mode the current link should be enabled with a specific link 2421 * settings. 2422 */ 2423 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2424 struct dc_link_settings *link_setting); 2425 2426 /* Force DP RX to update its power state. 2427 * NOTE: this interface doesn't update dp main-link. Calling this function will 2428 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2429 * RX power state back upon finish DM specific execution requiring DP RX in a 2430 * specific power state. 2431 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2432 * state. 2433 */ 2434 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2435 2436 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2437 * current value read from extended receiver cap from 02200h - 0220Fh. 2438 * Some DP RX has problems of providing accurate DP receiver caps from extended 2439 * field, this interface is a workaround to revert link back to use base caps. 2440 */ 2441 void dc_link_overwrite_extended_receiver_cap( 2442 struct dc_link *link); 2443 2444 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2445 bool wait_for_hpd); 2446 2447 /* Set backlight level of an embedded panel (eDP, LVDS). 2448 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2449 * and 16 bit fractional, where 1.0 is max backlight value. 2450 */ 2451 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2452 struct set_backlight_level_params *backlight_level_params); 2453 2454 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2455 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2456 bool isHDR, 2457 uint32_t backlight_millinits, 2458 uint32_t transition_time_in_ms); 2459 2460 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2461 uint32_t *backlight_millinits, 2462 uint32_t *backlight_millinits_peak); 2463 2464 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2465 2466 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2467 2468 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2469 bool wait, bool force_static, const unsigned int *power_opts); 2470 2471 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2472 2473 bool dc_link_setup_psr(struct dc_link *dc_link, 2474 const struct dc_stream_state *stream, struct psr_config *psr_config, 2475 struct psr_context *psr_context); 2476 2477 /* 2478 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2479 * 2480 * @link: pointer to the dc_link struct instance 2481 * @enable: enable(active) or disable(inactive) replay 2482 * @wait: state transition need to wait the active set completed. 2483 * @force_static: force disable(inactive) the replay 2484 * @power_opts: set power optimazation parameters to DMUB. 2485 * 2486 * return: allow Replay active will return true, else will return false. 2487 */ 2488 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2489 bool wait, bool force_static, const unsigned int *power_opts); 2490 2491 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2492 2493 /* 2494 * Enable or disable Panel Replay on the specified link: 2495 * 2496 * @link: pointer to the dc_link struct instance 2497 * @enable: enable or disable Panel Replay 2498 * 2499 * return: true if successful, false otherwise 2500 */ 2501 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2502 2503 /* 2504 * Update Panel Replay state parameters: 2505 * 2506 * @link: pointer to the dc_link struct instance 2507 * @update_state_data: pointer to state update data structure 2508 * 2509 * return: true if successful, false otherwise 2510 */ 2511 bool dc_link_update_pr_state(struct dc_link *link, 2512 struct dmub_cmd_pr_update_state_data *update_state_data); 2513 2514 /* 2515 * Send general command to Panel Replay firmware: 2516 * 2517 * @link: pointer to the dc_link struct instance 2518 * @general_cmd_data: pointer to general command data structure 2519 * 2520 * return: true if successful, false otherwise 2521 */ 2522 bool dc_link_set_pr_general_cmd(struct dc_link *link, 2523 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 2524 2525 /* 2526 * Get Panel Replay state: 2527 * 2528 * @link: pointer to the dc_link struct instance 2529 * @state: pointer to store the Panel Replay state 2530 * 2531 * return: true if successful, false otherwise 2532 */ 2533 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 2534 2535 /* On eDP links this function call will stall until T12 has elapsed. 2536 * If the panel is not in power off state, this function will return 2537 * immediately. 2538 */ 2539 bool dc_link_wait_for_t12(struct dc_link *link); 2540 2541 /* Determine if dp trace has been initialized to reflect upto date result * 2542 * return - true if trace is initialized and has valid data. False dp trace 2543 * doesn't have valid result. 2544 */ 2545 bool dc_dp_trace_is_initialized(struct dc_link *link); 2546 2547 /* Query a dp trace flag to indicate if the current dp trace data has been 2548 * logged before 2549 */ 2550 bool dc_dp_trace_is_logged(struct dc_link *link, 2551 bool in_detection); 2552 2553 /* Set dp trace flag to indicate whether DM has already logged the current dp 2554 * trace data. DM can set is_logged to true upon logging and check 2555 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2556 */ 2557 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2558 bool in_detection, 2559 bool is_logged); 2560 2561 /* Obtain driver time stamp for last dp link training end. The time stamp is 2562 * formatted based on dm_get_timestamp DM function. 2563 * @in_detection - true to get link training end time stamp of last link 2564 * training in detection sequence. false to get link training end time stamp 2565 * of last link training in commit (dpms) sequence 2566 */ 2567 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2568 bool in_detection); 2569 2570 /* Get how many link training attempts dc has done with latest sequence. 2571 * @in_detection - true to get link training count of last link 2572 * training in detection sequence. false to get link training count of last link 2573 * training in commit (dpms) sequence 2574 */ 2575 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2576 bool in_detection); 2577 2578 /* Get how many link loss has happened since last link training attempts */ 2579 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2580 2581 /* 2582 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2583 */ 2584 /* 2585 * Send a request from DP-Tx requesting to allocate BW remotely after 2586 * allocating it locally. This will get processed by CM and a CB function 2587 * will be called. 2588 * 2589 * @link: pointer to the dc_link struct instance 2590 * @req_bw: The requested bw in Kbyte to allocated 2591 * 2592 * return: none 2593 */ 2594 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2595 2596 /* 2597 * Handle the USB4 BW Allocation related functionality here: 2598 * Plug => Try to allocate max bw from timing parameters supported by the sink 2599 * Unplug => de-allocate bw 2600 * 2601 * @link: pointer to the dc_link struct instance 2602 * @peak_bw: Peak bw used by the link/sink 2603 * 2604 */ 2605 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2606 struct dc_link *link, int peak_bw); 2607 2608 /* 2609 * Calculates the DP tunneling bandwidth required for the stream timing 2610 * and aggregates the stream bandwidth for the respective DP tunneling link 2611 * 2612 * return: dc_status 2613 */ 2614 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2615 2616 /* 2617 * Get if ALPM is supported by the link 2618 */ 2619 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 2620 bool *auxwake_support); 2621 2622 /* Sink Interfaces - A sink corresponds to a display output device */ 2623 2624 struct dc_container_id { 2625 // 128bit GUID in binary form 2626 unsigned char guid[16]; 2627 // 8 byte port ID -> ELD.PortID 2628 unsigned int portId[2]; 2629 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2630 unsigned short manufacturerName; 2631 // 2 byte product code -> ELD.ProductCode 2632 unsigned short productCode; 2633 }; 2634 2635 2636 struct dc_sink_dsc_caps { 2637 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2638 // 'false' if they are sink's DSC caps 2639 bool is_virtual_dpcd_dsc; 2640 // 'true' if MST topology supports DSC passthrough for sink 2641 // 'false' if MST topology does not support DSC passthrough 2642 bool is_dsc_passthrough_supported; 2643 struct dsc_dec_dpcd_caps dsc_dec_caps; 2644 }; 2645 2646 struct dc_sink_hblank_expansion_caps { 2647 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2648 // 'false' if they are sink's HBlank expansion caps 2649 bool is_virtual_dpcd_hblank_expansion; 2650 struct hblank_expansion_dpcd_caps dpcd_caps; 2651 }; 2652 2653 struct dc_sink_fec_caps { 2654 bool is_rx_fec_supported; 2655 bool is_topology_fec_supported; 2656 }; 2657 2658 struct scdc_caps { 2659 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2660 union hdmi_scdc_device_id_data device_id; 2661 }; 2662 2663 /* 2664 * The sink structure contains EDID and other display device properties 2665 */ 2666 struct dc_sink { 2667 enum signal_type sink_signal; 2668 struct dc_edid dc_edid; /* raw edid */ 2669 struct dc_edid_caps edid_caps; /* parse display caps */ 2670 struct dc_container_id *dc_container_id; 2671 uint32_t dongle_max_pix_clk; 2672 void *priv; 2673 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2674 bool converter_disable_audio; 2675 2676 struct scdc_caps scdc_caps; 2677 struct dc_sink_dsc_caps dsc_caps; 2678 struct dc_sink_fec_caps fec_caps; 2679 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2680 2681 bool is_vsc_sdp_colorimetry_supported; 2682 2683 /* private to DC core */ 2684 struct dc_link *link; 2685 struct dc_context *ctx; 2686 2687 uint32_t sink_id; 2688 2689 /* private to dc_sink.c */ 2690 // refcount must be the last member in dc_sink, since we want the 2691 // sink structure to be logically cloneable up to (but not including) 2692 // refcount 2693 struct kref refcount; 2694 }; 2695 2696 void dc_sink_retain(struct dc_sink *sink); 2697 void dc_sink_release(struct dc_sink *sink); 2698 2699 struct dc_sink_init_data { 2700 enum signal_type sink_signal; 2701 struct dc_link *link; 2702 uint32_t dongle_max_pix_clk; 2703 bool converter_disable_audio; 2704 }; 2705 2706 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2707 2708 /* Newer interfaces */ 2709 struct dc_cursor { 2710 struct dc_plane_address address; 2711 struct dc_cursor_attributes attributes; 2712 }; 2713 2714 2715 /* Interrupt interfaces */ 2716 enum dc_irq_source dc_interrupt_to_irq_source( 2717 struct dc *dc, 2718 uint32_t src_id, 2719 uint32_t ext_id); 2720 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2721 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2722 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2723 struct dc *dc, uint32_t link_index); 2724 2725 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2726 2727 /* Power Interfaces */ 2728 2729 void dc_set_power_state( 2730 struct dc *dc, 2731 enum dc_acpi_cm_power_state power_state); 2732 void dc_resume(struct dc *dc); 2733 2734 void dc_power_down_on_boot(struct dc *dc); 2735 2736 /* 2737 * HDCP Interfaces 2738 */ 2739 enum hdcp_message_status dc_process_hdcp_msg( 2740 enum signal_type signal, 2741 struct dc_link *link, 2742 struct hdcp_protection_message *message_info); 2743 bool dc_is_dmcu_initialized(struct dc *dc); 2744 2745 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2746 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2747 2748 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2749 unsigned int pitch, 2750 unsigned int height, 2751 enum surface_pixel_format format, 2752 struct dc_cursor_attributes *cursor_attr); 2753 2754 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2755 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2756 2757 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2758 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2759 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2760 2761 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2762 void dc_unlock_memory_clock_frequency(struct dc *dc); 2763 2764 /* set min memory clock to the min required for current mode, max to maxDPM */ 2765 void dc_lock_memory_clock_frequency(struct dc *dc); 2766 2767 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2768 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2769 2770 /* cleanup on driver unload */ 2771 void dc_hardware_release(struct dc *dc); 2772 2773 /* disables fw based mclk switch */ 2774 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2775 2776 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2777 2778 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2779 2780 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2781 2782 void dc_z10_restore(const struct dc *dc); 2783 void dc_z10_save_init(struct dc *dc); 2784 2785 bool dc_is_dmub_outbox_supported(struct dc *dc); 2786 bool dc_enable_dmub_notifications(struct dc *dc); 2787 2788 bool dc_abm_save_restore( 2789 struct dc *dc, 2790 struct dc_stream_state *stream, 2791 struct abm_save_restore *pData); 2792 2793 void dc_enable_dmub_outbox(struct dc *dc); 2794 2795 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2796 uint32_t link_index, 2797 struct aux_payload *payload); 2798 2799 /* 2800 * smart power OLED Interfaces 2801 */ 2802 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 2803 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 2804 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 2805 2806 /* Get dc link index from dpia port index */ 2807 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2808 uint8_t dpia_port_index); 2809 2810 bool dc_process_dmub_set_config_async(struct dc *dc, 2811 uint32_t link_index, 2812 struct set_config_cmd_payload *payload, 2813 struct dmub_notification *notify); 2814 2815 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2816 uint32_t link_index, 2817 uint8_t mst_alloc_slots, 2818 uint8_t *mst_slots_in_use); 2819 2820 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2821 2822 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2823 uint32_t hpd_int_enable); 2824 2825 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2826 2827 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2828 2829 struct dc_power_profile { 2830 int power_level; /* Lower is better */ 2831 }; 2832 2833 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2834 2835 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2836 2837 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2838 2839 void dc_log_preos_dmcub_info(const struct dc *dc); 2840 2841 /* DSC Interfaces */ 2842 #include "dc_dsc.h" 2843 2844 void dc_get_visual_confirm_for_stream( 2845 struct dc *dc, 2846 struct dc_stream_state *stream_state, 2847 struct tg_color *color); 2848 2849 /* Disable acc mode Interfaces */ 2850 void dc_disable_accelerated_mode(struct dc *dc); 2851 2852 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2853 struct dc_stream_state *new_stream); 2854 2855 bool dc_is_cursor_limit_pending(struct dc *dc); 2856 bool dc_can_clear_cursor_limit(const struct dc *dc); 2857 2858 /** 2859 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 2860 * 2861 * @dc: Pointer to the display core context. 2862 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 2863 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 2864 * 2865 * This function collects and logs underflow-related HW states when underflow happens, 2866 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 2867 * The results are stored in the provided out_data structure for further analysis or logging. 2868 */ 2869 void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); 2870 2871 void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); 2872 2873 /* 2874 * Software state variables used to program register fields across the display pipeline 2875 */ 2876 struct dc_register_software_state { 2877 /* HUBP register programming variables for each pipe */ 2878 struct { 2879 bool valid_plane_state; 2880 bool valid_stream; 2881 bool min_dc_gfx_version9; 2882 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 2883 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 2884 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 2885 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 2886 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 2887 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 2888 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 2889 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 2890 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 2891 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 2892 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 2893 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 2894 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 2895 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 2896 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 2897 2898 /* Additional DCC configuration */ 2899 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 2900 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 2901 2902 /* Surface pitch configuration */ 2903 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 2904 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 2905 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 2906 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 2907 2908 /* Surface addresses */ 2909 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 2910 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 2911 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 2912 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 2913 2914 /* TMZ configuration */ 2915 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 2916 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 2917 2918 /* Tiling configuration */ 2919 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 2920 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 2921 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 2922 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 2923 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 2924 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 2925 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 2926 2927 /* DML Request Size Configuration - Luma */ 2928 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 2929 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 2930 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 2931 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 2932 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 2933 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 2934 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 2935 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 2936 2937 /* DML Request Size Configuration - Chroma */ 2938 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 2939 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 2940 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 2941 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 2942 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 2943 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 2944 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 2945 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 2946 2947 /* DML Expansion Modes */ 2948 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 2949 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 2950 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 2951 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 2952 2953 /* DML DLG parameters - nominal */ 2954 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 2955 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 2956 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 2957 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 2958 2959 /* DML prefetch settings */ 2960 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 2961 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 2962 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 2963 2964 /* TTU parameters */ 2965 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 2966 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 2967 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 2968 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 2969 } hubp[MAX_PIPES]; 2970 2971 /* HUBBUB register programming variables */ 2972 struct { 2973 /* Individual DET buffer control per pipe - software state that programs DET registers */ 2974 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 2975 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 2976 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 2977 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 2978 2979 /* Compression buffer control - software state that programs COMPBUF registers */ 2980 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 2981 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 2982 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 2983 } hubbub; 2984 2985 /* DPP register programming variables for each pipe (simplified for available fields) */ 2986 struct { 2987 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 2988 2989 /* Recout (Rectangle of Interest) configuration */ 2990 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 2991 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 2992 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 2993 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 2994 2995 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 2996 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 2997 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 2998 2999 /* DSCL mode configuration */ 3000 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3001 3002 /* Scaler ratios (simplified to integer parts) */ 3003 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3004 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3005 3006 /* Basic scaler taps */ 3007 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3008 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3009 } dpp[MAX_PIPES]; 3010 3011 /* DCCG register programming variables */ 3012 struct { 3013 /* Core Display Clock Control */ 3014 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3015 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3016 3017 /* DPP Clock Control - 4 fields per pipe */ 3018 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3019 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3020 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3021 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3022 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3023 3024 /* DSC Clock Control - 4 fields per DSC resource */ 3025 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3026 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3027 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3028 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3029 3030 /* Pixel Clock Control - per pipe */ 3031 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3032 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3033 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3034 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3035 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3036 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3037 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3038 3039 /* DTBCLK DTO Control - 4 DTOs */ 3040 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3041 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3042 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3043 3044 /* DP Stream Clock Control - 4 pipes */ 3045 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3046 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3047 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3048 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3049 3050 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3051 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3052 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3053 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3054 3055 /* SYMCLK32 SE Control - 4 instances */ 3056 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3057 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3058 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3059 3060 /* SYMCLK32 LE Control - 2 instances */ 3061 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3062 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3063 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3064 3065 /* DPIA Clock Control */ 3066 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3067 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3068 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3069 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3070 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3071 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3072 3073 /* Clock Gating Control */ 3074 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3075 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3076 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3077 3078 /* VSync Control */ 3079 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3080 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3081 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3082 3083 /* Time Base Control */ 3084 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3085 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3086 } dccg; 3087 3088 /* DSC essential configuration for underflow analysis */ 3089 struct { 3090 /* DSC active state - critical for bandwidth analysis */ 3091 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3092 3093 /* DSC configuration affecting bandwidth and timing */ 3094 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3095 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3096 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3097 3098 /* OPP integration - affects pipeline flow */ 3099 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3100 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3101 } dsc[MAX_PIPES]; 3102 3103 /* MPC register programming variables */ 3104 struct { 3105 /* MPCC blending tree and mode control */ 3106 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3107 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3108 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3109 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3110 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3111 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3112 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3113 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3114 3115 /* MPCC blending tree connections */ 3116 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3117 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3118 3119 /* MPCC output gamma control */ 3120 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3121 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3122 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3123 3124 /* MPCC pipe assignment and status */ 3125 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3126 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3127 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3128 3129 /* MPC output processing */ 3130 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3131 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3132 } mpc; 3133 3134 /* OPP register programming variables for each pipe */ 3135 struct { 3136 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3137 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3138 3139 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3140 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3141 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3142 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3143 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3144 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3145 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3146 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3147 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3148 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3149 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3150 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3151 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3152 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3153 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3154 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3155 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3156 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3157 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3158 3159 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3160 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3161 3162 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3163 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3164 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3165 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3166 3167 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3168 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3169 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3170 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3171 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3172 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3173 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3174 3175 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3176 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3177 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3178 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3179 } opp[MAX_PIPES]; 3180 3181 /* OPTC register programming variables for each pipe */ 3182 struct { 3183 uint32_t otg_master_inst; 3184 3185 /* OTG_CONTROL register - 5 fields for OTG control */ 3186 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3187 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3188 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3189 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3190 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3191 3192 /* OTG Horizontal Timing - 7 fields */ 3193 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3194 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3195 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3196 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3197 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3198 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3199 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3200 3201 /* OTG Vertical Timing - 7 fields */ 3202 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3203 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3204 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3205 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3206 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3207 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3208 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3209 3210 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3211 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3212 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3213 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3214 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3215 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3216 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3217 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3218 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3219 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3220 3221 /* OPTC Data Source and ODM - 6 fields */ 3222 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3223 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3224 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3225 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3226 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3227 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3228 3229 /* OPTC Data Format and DSC - 4 fields */ 3230 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3231 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3232 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3233 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3234 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3235 3236 /* OPTC Clock and Underflow Control - 4 fields */ 3237 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3238 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3239 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3240 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3241 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3242 3243 /* OTG Stereo and 3D Control - 6 fields */ 3244 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3245 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3246 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3247 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3248 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3249 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3250 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3251 3252 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3253 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3254 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3255 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3256 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3257 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3258 3259 /* OTG DRR Advanced Control - 4 fields */ 3260 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3261 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3262 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3263 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3264 3265 /* OTG DSC Position Control - 2 fields */ 3266 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3267 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3268 3269 /* OTG Double Buffer Control - 2 fields */ 3270 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3271 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3272 3273 /* OTG Vertical Interrupts - 6 fields */ 3274 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3275 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3276 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3277 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3278 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3279 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3280 3281 /* OTG Global Sync Parameters - 6 fields */ 3282 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3283 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3284 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3285 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3286 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3287 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3288 3289 /* OTG Manual Trigger Control - 11 fields */ 3290 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3291 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3292 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3293 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3294 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3295 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3296 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3297 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3298 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3299 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3300 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3301 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3302 3303 /* OTG Static Screen and Update Control - 6 fields */ 3304 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3305 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3306 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3307 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3308 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3309 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3310 3311 /* VTG Control - 3 fields */ 3312 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3313 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3314 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3315 3316 /* OTG Status (Read-Only) - 12 fields */ 3317 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3318 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3319 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3320 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3321 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3322 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3323 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3324 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3325 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3326 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3327 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3328 } optc[MAX_PIPES]; 3329 3330 /* Metadata */ 3331 uint32_t active_pipe_count; 3332 uint32_t active_stream_count; 3333 bool state_valid; 3334 }; 3335 3336 /** 3337 * dc_capture_register_software_state() - Capture software state for register programming 3338 * @dc: DC context containing current display configuration 3339 * @state: Pointer to dc_register_software_state structure to populate 3340 * 3341 * Extracts all software state variables that are used to program hardware register 3342 * fields across the display driver pipeline. This provides a complete snapshot 3343 * of the software configuration that drives hardware register programming. 3344 * 3345 * The function traverses the DC context and extracts values from: 3346 * - Stream configurations (timing, format, DSC settings) 3347 * - Plane states (surface format, rotation, scaling, cursor) 3348 * - Pipe contexts (resource allocation, blending, viewport) 3349 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3350 * - Resource context (DET buffer allocation, ODM configuration) 3351 * 3352 * This is essential for underflow debugging as it captures the exact software 3353 * state that determines how registers are programmed, allowing analysis of 3354 * whether underflow is caused by incorrect register programming or timing issues. 3355 * 3356 * Return: true if state was successfully captured, false on error 3357 */ 3358 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3359 3360 /** 3361 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3362 * @dc: DC context containing current display configuration 3363 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3364 * 3365 * This function retrieves QoS metrics from the display core that can be used by 3366 * benchmark tools to analyze display system performance. The function may take 3367 * several milliseconds to execute due to hardware measurement requirements. 3368 * 3369 * QoS information includes: 3370 * - Bandwidth bounds (lower limits in Mbps) 3371 * - Latency bounds (upper limits in nanoseconds) 3372 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3373 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3374 * 3375 * The function will populate the provided dc_qos_info structure with current 3376 * QoS measurements. If hardware measurement functions are not available for 3377 * the current DCN version, the function returns false with zero'd info structure. 3378 * 3379 * Return: true if QoS information was successfully retrieved, false if measurement 3380 * functions are unavailable or hardware measurements cannot be performed 3381 */ 3382 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3383 3384 #endif /* DC_INTERFACE_H_ */ 3385