1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 struct abm_save_restore; 48 49 /* forward declaration */ 50 struct aux_payload; 51 struct set_config_cmd_payload; 52 struct dmub_notification; 53 54 #define DC_VER "3.2.268" 55 56 #define MAX_SURFACES 3 57 #define MAX_PLANES 6 58 #define MAX_STREAMS 6 59 #define MIN_VIEWPORT_SIZE 12 60 #define MAX_NUM_EDP 2 61 62 /* Display Core Interfaces */ 63 struct dc_versions { 64 const char *dc_ver; 65 struct dmcu_version dmcu_version; 66 }; 67 68 enum dp_protocol_version { 69 DP_VERSION_1_4 = 0, 70 DP_VERSION_2_1, 71 DP_VERSION_UNKNOWN, 72 }; 73 74 enum dc_plane_type { 75 DC_PLANE_TYPE_INVALID, 76 DC_PLANE_TYPE_DCE_RGB, 77 DC_PLANE_TYPE_DCE_UNDERLAY, 78 DC_PLANE_TYPE_DCN_UNIVERSAL, 79 }; 80 81 // Sizes defined as multiples of 64KB 82 enum det_size { 83 DET_SIZE_DEFAULT = 0, 84 DET_SIZE_192KB = 3, 85 DET_SIZE_256KB = 4, 86 DET_SIZE_320KB = 5, 87 DET_SIZE_384KB = 6 88 }; 89 90 91 struct dc_plane_cap { 92 enum dc_plane_type type; 93 uint32_t per_pixel_alpha : 1; 94 struct { 95 uint32_t argb8888 : 1; 96 uint32_t nv12 : 1; 97 uint32_t fp16 : 1; 98 uint32_t p010 : 1; 99 uint32_t ayuv : 1; 100 } pixel_format_support; 101 // max upscaling factor x1000 102 // upscaling factors are always >= 1 103 // for example, 1080p -> 8K is 4.0, or 4000 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_upscale_factor; 109 // max downscale factor x1000 110 // downscale factors are always <= 1 111 // for example, 8K -> 1080p is 0.25, or 250 raw value 112 struct { 113 uint32_t argb8888; 114 uint32_t nv12; 115 uint32_t fp16; 116 } max_downscale_factor; 117 // minimal width/height 118 uint32_t min_width; 119 uint32_t min_height; 120 }; 121 122 /** 123 * DOC: color-management-caps 124 * 125 * **Color management caps (DPP and MPC)** 126 * 127 * Modules/color calculates various color operations which are translated to 128 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 129 * DCN1, every new generation comes with fairly major differences in color 130 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 131 * decide mapping to HW block based on logical capabilities. 132 */ 133 134 /** 135 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 136 * @srgb: RGB color space transfer func 137 * @bt2020: BT.2020 transfer func 138 * @gamma2_2: standard gamma 139 * @pq: perceptual quantizer transfer function 140 * @hlg: hybrid log–gamma transfer function 141 */ 142 struct rom_curve_caps { 143 uint16_t srgb : 1; 144 uint16_t bt2020 : 1; 145 uint16_t gamma2_2 : 1; 146 uint16_t pq : 1; 147 uint16_t hlg : 1; 148 }; 149 150 /** 151 * struct dpp_color_caps - color pipeline capabilities for display pipe and 152 * plane blocks 153 * 154 * @dcn_arch: all DCE generations treated the same 155 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 156 * just plain 256-entry lookup 157 * @icsc: input color space conversion 158 * @dgam_ram: programmable degamma LUT 159 * @post_csc: post color space conversion, before gamut remap 160 * @gamma_corr: degamma correction 161 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 162 * with MPC by setting mpc:shared_3d_lut flag 163 * @ogam_ram: programmable out/blend gamma LUT 164 * @ocsc: output color space conversion 165 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 166 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 167 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 168 * 169 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 170 */ 171 struct dpp_color_caps { 172 uint16_t dcn_arch : 1; 173 uint16_t input_lut_shared : 1; 174 uint16_t icsc : 1; 175 uint16_t dgam_ram : 1; 176 uint16_t post_csc : 1; 177 uint16_t gamma_corr : 1; 178 uint16_t hw_3d_lut : 1; 179 uint16_t ogam_ram : 1; 180 uint16_t ocsc : 1; 181 uint16_t dgam_rom_for_yuv : 1; 182 struct rom_curve_caps dgam_rom_caps; 183 struct rom_curve_caps ogam_rom_caps; 184 }; 185 186 /** 187 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 188 * plane combined blocks 189 * 190 * @gamut_remap: color transformation matrix 191 * @ogam_ram: programmable out gamma LUT 192 * @ocsc: output color space conversion matrix 193 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 194 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 195 * instance 196 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 197 */ 198 struct mpc_color_caps { 199 uint16_t gamut_remap : 1; 200 uint16_t ogam_ram : 1; 201 uint16_t ocsc : 1; 202 uint16_t num_3dluts : 3; 203 uint16_t shared_3d_lut:1; 204 struct rom_curve_caps ogam_rom_caps; 205 }; 206 207 /** 208 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 209 * @dpp: color pipes caps for DPP 210 * @mpc: color pipes caps for MPC 211 */ 212 struct dc_color_caps { 213 struct dpp_color_caps dpp; 214 struct mpc_color_caps mpc; 215 }; 216 217 struct dc_dmub_caps { 218 bool psr; 219 bool mclk_sw; 220 bool subvp_psr; 221 bool gecc_enable; 222 }; 223 224 struct dc_caps { 225 uint32_t max_streams; 226 uint32_t max_links; 227 uint32_t max_audios; 228 uint32_t max_slave_planes; 229 uint32_t max_slave_yuv_planes; 230 uint32_t max_slave_rgb_planes; 231 uint32_t max_planes; 232 uint32_t max_downscale_ratio; 233 uint32_t i2c_speed_in_khz; 234 uint32_t i2c_speed_in_khz_hdcp; 235 uint32_t dmdata_alloc_size; 236 unsigned int max_cursor_size; 237 unsigned int max_video_width; 238 /* 239 * max video plane width that can be safely assumed to be always 240 * supported by single DPP pipe. 241 */ 242 unsigned int max_optimizable_video_width; 243 unsigned int min_horizontal_blanking_period; 244 int linear_pitch_alignment; 245 bool dcc_const_color; 246 bool dynamic_audio; 247 bool is_apu; 248 bool dual_link_dvi; 249 bool post_blend_color_processing; 250 bool force_dp_tps4_for_cp2520; 251 bool disable_dp_clk_share; 252 bool psp_setup_panel_mode; 253 bool extended_aux_timeout_support; 254 bool dmcub_support; 255 bool zstate_support; 256 bool ips_support; 257 uint32_t num_of_internal_disp; 258 enum dp_protocol_version max_dp_protocol_version; 259 unsigned int mall_size_per_mem_channel; 260 unsigned int mall_size_total; 261 unsigned int cursor_cache_size; 262 struct dc_plane_cap planes[MAX_PLANES]; 263 struct dc_color_caps color; 264 struct dc_dmub_caps dmub_caps; 265 bool dp_hpo; 266 bool dp_hdmi21_pcon_support; 267 bool edp_dsc_support; 268 bool vbios_lttpr_aware; 269 bool vbios_lttpr_enable; 270 uint32_t max_otg_num; 271 uint32_t max_cab_allocation_bytes; 272 uint32_t cache_line_size; 273 uint32_t cache_num_ways; 274 uint16_t subvp_fw_processing_delay_us; 275 uint8_t subvp_drr_max_vblank_margin_us; 276 uint16_t subvp_prefetch_end_to_mall_start_us; 277 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 278 uint16_t subvp_pstate_allow_width_us; 279 uint16_t subvp_vertical_int_margin_us; 280 bool seamless_odm; 281 uint32_t max_v_total; 282 uint32_t max_disp_clock_khz_at_vmin; 283 uint8_t subvp_drr_vblank_start_margin_us; 284 }; 285 286 struct dc_bug_wa { 287 bool no_connect_phy_config; 288 bool dedcn20_305_wa; 289 bool skip_clock_update; 290 bool lt_early_cr_pattern; 291 struct { 292 uint8_t uclk : 1; 293 uint8_t fclk : 1; 294 uint8_t dcfclk : 1; 295 uint8_t dcfclk_ds: 1; 296 } clock_update_disable_mask; 297 }; 298 struct dc_dcc_surface_param { 299 struct dc_size surface_size; 300 enum surface_pixel_format format; 301 enum swizzle_mode_values swizzle_mode; 302 enum dc_scan_direction scan; 303 }; 304 305 struct dc_dcc_setting { 306 unsigned int max_compressed_blk_size; 307 unsigned int max_uncompressed_blk_size; 308 bool independent_64b_blks; 309 //These bitfields to be used starting with DCN 310 struct { 311 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 312 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 313 uint32_t dcc_256_128_128 : 1; //available starting with DCN 314 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 315 } dcc_controls; 316 }; 317 318 struct dc_surface_dcc_cap { 319 union { 320 struct { 321 struct dc_dcc_setting rgb; 322 } grph; 323 324 struct { 325 struct dc_dcc_setting luma; 326 struct dc_dcc_setting chroma; 327 } video; 328 }; 329 330 bool capable; 331 bool const_color_support; 332 }; 333 334 struct dc_static_screen_params { 335 struct { 336 bool force_trigger; 337 bool cursor_update; 338 bool surface_update; 339 bool overlay_update; 340 } triggers; 341 unsigned int num_frames; 342 }; 343 344 345 /* Surface update type is used by dc_update_surfaces_and_stream 346 * The update type is determined at the very beginning of the function based 347 * on parameters passed in and decides how much programming (or updating) is 348 * going to be done during the call. 349 * 350 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 351 * logical calculations or hardware register programming. This update MUST be 352 * ISR safe on windows. Currently fast update will only be used to flip surface 353 * address. 354 * 355 * UPDATE_TYPE_MED is used for slower updates which require significant hw 356 * re-programming however do not affect bandwidth consumption or clock 357 * requirements. At present, this is the level at which front end updates 358 * that do not require us to run bw_calcs happen. These are in/out transfer func 359 * updates, viewport offset changes, recout size changes and pixel depth changes. 360 * This update can be done at ISR, but we want to minimize how often this happens. 361 * 362 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 363 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 364 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 365 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 366 * a full update. This cannot be done at ISR level and should be a rare event. 367 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 368 * underscan we don't expect to see this call at all. 369 */ 370 371 enum surface_update_type { 372 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 373 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 374 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 375 }; 376 377 /* Forward declaration*/ 378 struct dc; 379 struct dc_plane_state; 380 struct dc_state; 381 382 383 struct dc_cap_funcs { 384 bool (*get_dcc_compression_cap)(const struct dc *dc, 385 const struct dc_dcc_surface_param *input, 386 struct dc_surface_dcc_cap *output); 387 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 388 }; 389 390 struct link_training_settings; 391 392 union allow_lttpr_non_transparent_mode { 393 struct { 394 bool DP1_4A : 1; 395 bool DP2_0 : 1; 396 } bits; 397 unsigned char raw; 398 }; 399 400 /* Structure to hold configuration flags set by dm at dc creation. */ 401 struct dc_config { 402 bool gpu_vm_support; 403 bool disable_disp_pll_sharing; 404 bool fbc_support; 405 bool disable_fractional_pwm; 406 bool allow_seamless_boot_optimization; 407 bool seamless_boot_edp_requested; 408 bool edp_not_connected; 409 bool edp_no_power_sequencing; 410 bool force_enum_edp; 411 bool forced_clocks; 412 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 413 bool multi_mon_pp_mclk_switch; 414 bool disable_dmcu; 415 bool enable_4to1MPC; 416 bool enable_windowed_mpo_odm; 417 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 418 uint32_t allow_edp_hotplug_detection; 419 bool clamp_min_dcfclk; 420 uint64_t vblank_alignment_dto_params; 421 uint8_t vblank_alignment_max_frame_time_diff; 422 bool is_asymmetric_memory; 423 bool is_single_rank_dimm; 424 bool is_vmin_only_asic; 425 bool use_pipe_ctx_sync_logic; 426 bool ignore_dpref_ss; 427 bool enable_mipi_converter_optimization; 428 bool use_default_clock_table; 429 bool force_bios_enable_lttpr; 430 uint8_t force_bios_fixed_vs; 431 int sdpif_request_limit_words_per_umc; 432 bool use_old_fixed_vs_sequence; 433 bool dc_mode_clk_limit_support; 434 bool EnableMinDispClkODM; 435 bool enable_auto_dpm_test_logs; 436 unsigned int disable_ips; 437 unsigned int disable_ips_in_vpb; 438 bool usb4_bw_alloc_support; 439 }; 440 441 enum visual_confirm { 442 VISUAL_CONFIRM_DISABLE = 0, 443 VISUAL_CONFIRM_SURFACE = 1, 444 VISUAL_CONFIRM_HDR = 2, 445 VISUAL_CONFIRM_MPCTREE = 4, 446 VISUAL_CONFIRM_PSR = 5, 447 VISUAL_CONFIRM_SWAPCHAIN = 6, 448 VISUAL_CONFIRM_FAMS = 7, 449 VISUAL_CONFIRM_SWIZZLE = 9, 450 VISUAL_CONFIRM_REPLAY = 12, 451 VISUAL_CONFIRM_SUBVP = 14, 452 VISUAL_CONFIRM_MCLK_SWITCH = 16, 453 }; 454 455 enum dc_psr_power_opts { 456 psr_power_opt_invalid = 0x0, 457 psr_power_opt_smu_opt_static_screen = 0x1, 458 psr_power_opt_z10_static_screen = 0x10, 459 psr_power_opt_ds_disable_allow = 0x100, 460 }; 461 462 enum dml_hostvm_override_opts { 463 DML_HOSTVM_NO_OVERRIDE = 0x0, 464 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 465 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 466 }; 467 468 enum dc_replay_power_opts { 469 replay_power_opt_invalid = 0x0, 470 replay_power_opt_smu_opt_static_screen = 0x1, 471 replay_power_opt_z10_static_screen = 0x10, 472 }; 473 474 enum dcc_option { 475 DCC_ENABLE = 0, 476 DCC_DISABLE = 1, 477 DCC_HALF_REQ_DISALBE = 2, 478 }; 479 480 /** 481 * enum pipe_split_policy - Pipe split strategy supported by DCN 482 * 483 * This enum is used to define the pipe split policy supported by DCN. By 484 * default, DC favors MPC_SPLIT_DYNAMIC. 485 */ 486 enum pipe_split_policy { 487 /** 488 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 489 * pipe in order to bring the best trade-off between performance and 490 * power consumption. This is the recommended option. 491 */ 492 MPC_SPLIT_DYNAMIC = 0, 493 494 /** 495 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 496 * try any sort of split optimization. 497 */ 498 MPC_SPLIT_AVOID = 1, 499 500 /** 501 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 502 * optimize the pipe utilization when using a single display; if the 503 * user connects to a second display, DC will avoid pipe split. 504 */ 505 MPC_SPLIT_AVOID_MULT_DISP = 2, 506 }; 507 508 enum wm_report_mode { 509 WM_REPORT_DEFAULT = 0, 510 WM_REPORT_OVERRIDE = 1, 511 }; 512 enum dtm_pstate{ 513 dtm_level_p0 = 0,/*highest voltage*/ 514 dtm_level_p1, 515 dtm_level_p2, 516 dtm_level_p3, 517 dtm_level_p4,/*when active_display_count = 0*/ 518 }; 519 520 enum dcn_pwr_state { 521 DCN_PWR_STATE_UNKNOWN = -1, 522 DCN_PWR_STATE_MISSION_MODE = 0, 523 DCN_PWR_STATE_LOW_POWER = 3, 524 }; 525 526 enum dcn_zstate_support_state { 527 DCN_ZSTATE_SUPPORT_UNKNOWN, 528 DCN_ZSTATE_SUPPORT_ALLOW, 529 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 530 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 531 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 532 DCN_ZSTATE_SUPPORT_DISALLOW, 533 }; 534 535 /* 536 * struct dc_clocks - DC pipe clocks 537 * 538 * For any clocks that may differ per pipe only the max is stored in this 539 * structure 540 */ 541 struct dc_clocks { 542 int dispclk_khz; 543 int actual_dispclk_khz; 544 int dppclk_khz; 545 int actual_dppclk_khz; 546 int disp_dpp_voltage_level_khz; 547 int dcfclk_khz; 548 int socclk_khz; 549 int dcfclk_deep_sleep_khz; 550 int fclk_khz; 551 int phyclk_khz; 552 int dramclk_khz; 553 bool p_state_change_support; 554 enum dcn_zstate_support_state zstate_support; 555 bool dtbclk_en; 556 int ref_dtbclk_khz; 557 bool fclk_p_state_change_support; 558 enum dcn_pwr_state pwr_state; 559 /* 560 * Elements below are not compared for the purposes of 561 * optimization required 562 */ 563 bool prev_p_state_change_support; 564 bool fclk_prev_p_state_change_support; 565 int num_ways; 566 567 /* 568 * @fw_based_mclk_switching 569 * 570 * DC has a mechanism that leverage the variable refresh rate to switch 571 * memory clock in cases that we have a large latency to achieve the 572 * memory clock change and a short vblank window. DC has some 573 * requirements to enable this feature, and this field describes if the 574 * system support or not such a feature. 575 */ 576 bool fw_based_mclk_switching; 577 bool fw_based_mclk_switching_shut_down; 578 int prev_num_ways; 579 enum dtm_pstate dtm_level; 580 int max_supported_dppclk_khz; 581 int max_supported_dispclk_khz; 582 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 583 int bw_dispclk_khz; 584 }; 585 586 struct dc_bw_validation_profile { 587 bool enable; 588 589 unsigned long long total_ticks; 590 unsigned long long voltage_level_ticks; 591 unsigned long long watermark_ticks; 592 unsigned long long rq_dlg_ticks; 593 594 unsigned long long total_count; 595 unsigned long long skip_fast_count; 596 unsigned long long skip_pass_count; 597 unsigned long long skip_fail_count; 598 }; 599 600 #define BW_VAL_TRACE_SETUP() \ 601 unsigned long long end_tick = 0; \ 602 unsigned long long voltage_level_tick = 0; \ 603 unsigned long long watermark_tick = 0; \ 604 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 605 dm_get_timestamp(dc->ctx) : 0 606 607 #define BW_VAL_TRACE_COUNT() \ 608 if (dc->debug.bw_val_profile.enable) \ 609 dc->debug.bw_val_profile.total_count++ 610 611 #define BW_VAL_TRACE_SKIP(status) \ 612 if (dc->debug.bw_val_profile.enable) { \ 613 if (!voltage_level_tick) \ 614 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 615 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 616 } 617 618 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 619 if (dc->debug.bw_val_profile.enable) \ 620 voltage_level_tick = dm_get_timestamp(dc->ctx) 621 622 #define BW_VAL_TRACE_END_WATERMARKS() \ 623 if (dc->debug.bw_val_profile.enable) \ 624 watermark_tick = dm_get_timestamp(dc->ctx) 625 626 #define BW_VAL_TRACE_FINISH() \ 627 if (dc->debug.bw_val_profile.enable) { \ 628 end_tick = dm_get_timestamp(dc->ctx); \ 629 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 630 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 631 if (watermark_tick) { \ 632 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 633 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 634 } \ 635 } 636 637 union mem_low_power_enable_options { 638 struct { 639 bool vga: 1; 640 bool i2c: 1; 641 bool dmcu: 1; 642 bool dscl: 1; 643 bool cm: 1; 644 bool mpc: 1; 645 bool optc: 1; 646 bool vpg: 1; 647 bool afmt: 1; 648 } bits; 649 uint32_t u32All; 650 }; 651 652 union root_clock_optimization_options { 653 struct { 654 bool dpp: 1; 655 bool dsc: 1; 656 bool hdmistream: 1; 657 bool hdmichar: 1; 658 bool dpstream: 1; 659 bool symclk32_se: 1; 660 bool symclk32_le: 1; 661 bool symclk_fe: 1; 662 bool physymclk: 1; 663 bool dpiasymclk: 1; 664 uint32_t reserved: 22; 665 } bits; 666 uint32_t u32All; 667 }; 668 669 union fine_grain_clock_gating_enable_options { 670 struct { 671 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 672 bool dchub : 1; /* Display controller hub */ 673 bool dchubbub : 1; 674 bool dpp : 1; /* Display pipes and planes */ 675 bool opp : 1; /* Output pixel processing */ 676 bool optc : 1; /* Output pipe timing combiner */ 677 bool dio : 1; /* Display output */ 678 bool dwb : 1; /* Display writeback */ 679 bool mmhubbub : 1; /* Multimedia hub */ 680 bool dmu : 1; /* Display core management unit */ 681 bool az : 1; /* Azalia */ 682 bool dchvm : 1; 683 bool dsc : 1; /* Display stream compression */ 684 685 uint32_t reserved : 19; 686 } bits; 687 uint32_t u32All; 688 }; 689 690 enum pg_hw_pipe_resources { 691 PG_HUBP = 0, 692 PG_DPP, 693 PG_DSC, 694 PG_MPCC, 695 PG_OPP, 696 PG_OPTC, 697 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 698 }; 699 700 enum pg_hw_resources { 701 PG_DCCG = 0, 702 PG_DCIO, 703 PG_DIO, 704 PG_DCHUBBUB, 705 PG_DCHVM, 706 PG_DWB, 707 PG_HPO, 708 PG_HW_RESOURCES_NUM_ELEMENT 709 }; 710 711 struct pg_block_update { 712 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 713 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 714 }; 715 716 union dpia_debug_options { 717 struct { 718 uint32_t disable_dpia:1; /* bit 0 */ 719 uint32_t force_non_lttpr:1; /* bit 1 */ 720 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 721 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 722 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 723 uint32_t reserved:27; 724 } bits; 725 uint32_t raw; 726 }; 727 728 /* AUX wake work around options 729 * 0: enable/disable work around 730 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 731 * 15-2: reserved 732 * 31-16: timeout in ms 733 */ 734 union aux_wake_wa_options { 735 struct { 736 uint32_t enable_wa : 1; 737 uint32_t use_default_timeout : 1; 738 uint32_t rsvd: 14; 739 uint32_t timeout_ms : 16; 740 } bits; 741 uint32_t raw; 742 }; 743 744 struct dc_debug_data { 745 uint32_t ltFailCount; 746 uint32_t i2cErrorCount; 747 uint32_t auxErrorCount; 748 }; 749 750 struct dc_phy_addr_space_config { 751 struct { 752 uint64_t start_addr; 753 uint64_t end_addr; 754 uint64_t fb_top; 755 uint64_t fb_offset; 756 uint64_t fb_base; 757 uint64_t agp_top; 758 uint64_t agp_bot; 759 uint64_t agp_base; 760 } system_aperture; 761 762 struct { 763 uint64_t page_table_start_addr; 764 uint64_t page_table_end_addr; 765 uint64_t page_table_base_addr; 766 bool base_addr_is_mc_addr; 767 } gart_config; 768 769 bool valid; 770 bool is_hvm_enabled; 771 uint64_t page_table_default_page_addr; 772 }; 773 774 struct dc_virtual_addr_space_config { 775 uint64_t page_table_base_addr; 776 uint64_t page_table_start_addr; 777 uint64_t page_table_end_addr; 778 uint32_t page_table_block_size_in_bytes; 779 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 780 }; 781 782 struct dc_bounding_box_overrides { 783 int sr_exit_time_ns; 784 int sr_enter_plus_exit_time_ns; 785 int sr_exit_z8_time_ns; 786 int sr_enter_plus_exit_z8_time_ns; 787 int urgent_latency_ns; 788 int percent_of_ideal_drambw; 789 int dram_clock_change_latency_ns; 790 int dummy_clock_change_latency_ns; 791 int fclk_clock_change_latency_ns; 792 /* This forces a hard min on the DCFCLK we use 793 * for DML. Unlike the debug option for forcing 794 * DCFCLK, this override affects watermark calculations 795 */ 796 int min_dcfclk_mhz; 797 }; 798 799 struct dc_state; 800 struct resource_pool; 801 struct dce_hwseq; 802 struct link_service; 803 804 /* 805 * struct dc_debug_options - DC debug struct 806 * 807 * This struct provides a simple mechanism for developers to change some 808 * configurations, enable/disable features, and activate extra debug options. 809 * This can be very handy to narrow down whether some specific feature is 810 * causing an issue or not. 811 */ 812 struct dc_debug_options { 813 bool native422_support; 814 bool disable_dsc; 815 enum visual_confirm visual_confirm; 816 int visual_confirm_rect_height; 817 818 bool sanity_checks; 819 bool max_disp_clk; 820 bool surface_trace; 821 bool timing_trace; 822 bool clock_trace; 823 bool validation_trace; 824 bool bandwidth_calcs_trace; 825 int max_downscale_src_width; 826 827 /* stutter efficiency related */ 828 bool disable_stutter; 829 bool use_max_lb; 830 enum dcc_option disable_dcc; 831 832 /* 833 * @pipe_split_policy: Define which pipe split policy is used by the 834 * display core. 835 */ 836 enum pipe_split_policy pipe_split_policy; 837 bool force_single_disp_pipe_split; 838 bool voltage_align_fclk; 839 bool disable_min_fclk; 840 841 bool disable_dfs_bypass; 842 bool disable_dpp_power_gate; 843 bool disable_hubp_power_gate; 844 bool disable_dsc_power_gate; 845 bool disable_optc_power_gate; 846 bool disable_hpo_power_gate; 847 int dsc_min_slice_height_override; 848 int dsc_bpp_increment_div; 849 bool disable_pplib_wm_range; 850 enum wm_report_mode pplib_wm_report_mode; 851 unsigned int min_disp_clk_khz; 852 unsigned int min_dpp_clk_khz; 853 unsigned int min_dram_clk_khz; 854 int sr_exit_time_dpm0_ns; 855 int sr_enter_plus_exit_time_dpm0_ns; 856 int sr_exit_time_ns; 857 int sr_enter_plus_exit_time_ns; 858 int sr_exit_z8_time_ns; 859 int sr_enter_plus_exit_z8_time_ns; 860 int urgent_latency_ns; 861 uint32_t underflow_assert_delay_us; 862 int percent_of_ideal_drambw; 863 int dram_clock_change_latency_ns; 864 bool optimized_watermark; 865 int always_scale; 866 bool disable_pplib_clock_request; 867 bool disable_clock_gate; 868 bool disable_mem_low_power; 869 bool pstate_enabled; 870 bool disable_dmcu; 871 bool force_abm_enable; 872 bool disable_stereo_support; 873 bool vsr_support; 874 bool performance_trace; 875 bool az_endpoint_mute_only; 876 bool always_use_regamma; 877 bool recovery_enabled; 878 bool avoid_vbios_exec_table; 879 bool scl_reset_length10; 880 bool hdmi20_disable; 881 bool skip_detection_link_training; 882 uint32_t edid_read_retry_times; 883 unsigned int force_odm_combine; //bit vector based on otg inst 884 unsigned int seamless_boot_odm_combine; 885 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 886 int minimum_z8_residency_time; 887 int minimum_z10_residency_time; 888 bool disable_z9_mpc; 889 unsigned int force_fclk_khz; 890 bool enable_tri_buf; 891 bool dmub_offload_enabled; 892 bool dmcub_emulation; 893 bool disable_idle_power_optimizations; 894 unsigned int mall_size_override; 895 unsigned int mall_additional_timer_percent; 896 bool mall_error_as_fatal; 897 bool dmub_command_table; /* for testing only */ 898 struct dc_bw_validation_profile bw_val_profile; 899 bool disable_fec; 900 bool disable_48mhz_pwrdwn; 901 /* This forces a hard min on the DCFCLK requested to SMU/PP 902 * watermarks are not affected. 903 */ 904 unsigned int force_min_dcfclk_mhz; 905 int dwb_fi_phase; 906 bool disable_timing_sync; 907 bool cm_in_bypass; 908 int force_clock_mode;/*every mode change.*/ 909 910 bool disable_dram_clock_change_vactive_support; 911 bool validate_dml_output; 912 bool enable_dmcub_surface_flip; 913 bool usbc_combo_phy_reset_wa; 914 bool enable_dram_clock_change_one_display_vactive; 915 /* TODO - remove once tested */ 916 bool legacy_dp2_lt; 917 bool set_mst_en_for_sst; 918 bool disable_uhbr; 919 bool force_dp2_lt_fallback_method; 920 bool ignore_cable_id; 921 union mem_low_power_enable_options enable_mem_low_power; 922 union root_clock_optimization_options root_clock_optimization; 923 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 924 bool hpo_optimization; 925 bool force_vblank_alignment; 926 927 /* Enable dmub aux for legacy ddc */ 928 bool enable_dmub_aux_for_legacy_ddc; 929 bool disable_fams; 930 bool disable_fams_gaming; 931 /* FEC/PSR1 sequence enable delay in 100us */ 932 uint8_t fec_enable_delay_in100us; 933 bool enable_driver_sequence_debug; 934 enum det_size crb_alloc_policy; 935 int crb_alloc_policy_min_disp_count; 936 bool disable_z10; 937 bool enable_z9_disable_interface; 938 bool psr_skip_crtc_disable; 939 union dpia_debug_options dpia_debug; 940 bool disable_fixed_vs_aux_timeout_wa; 941 uint32_t fixed_vs_aux_delay_config_wa; 942 bool force_disable_subvp; 943 bool force_subvp_mclk_switch; 944 bool allow_sw_cursor_fallback; 945 unsigned int force_subvp_num_ways; 946 unsigned int force_mall_ss_num_ways; 947 bool alloc_extra_way_for_cursor; 948 uint32_t subvp_extra_lines; 949 bool force_usr_allow; 950 /* uses value at boot and disables switch */ 951 bool disable_dtb_ref_clk_switch; 952 bool extended_blank_optimization; 953 union aux_wake_wa_options aux_wake_wa; 954 uint32_t mst_start_top_delay; 955 uint8_t psr_power_use_phy_fsm; 956 enum dml_hostvm_override_opts dml_hostvm_override; 957 bool dml_disallow_alternate_prefetch_modes; 958 bool use_legacy_soc_bb_mechanism; 959 bool exit_idle_opt_for_cursor_updates; 960 bool using_dml2; 961 bool enable_single_display_2to1_odm_policy; 962 bool enable_double_buffered_dsc_pg_support; 963 bool enable_dp_dig_pixel_rate_div_policy; 964 enum lttpr_mode lttpr_mode_override; 965 unsigned int dsc_delay_factor_wa_x1000; 966 unsigned int min_prefetch_in_strobe_ns; 967 bool disable_unbounded_requesting; 968 bool dig_fifo_off_in_blank; 969 bool override_dispclk_programming; 970 bool otg_crc_db; 971 bool disallow_dispclk_dppclk_ds; 972 bool disable_fpo_optimizations; 973 bool support_eDP1_5; 974 uint32_t fpo_vactive_margin_us; 975 bool disable_fpo_vactive; 976 bool disable_boot_optimizations; 977 bool override_odm_optimization; 978 bool minimize_dispclk_using_odm; 979 bool disable_subvp_high_refresh; 980 bool disable_dp_plus_plus_wa; 981 uint32_t fpo_vactive_min_active_margin_us; 982 uint32_t fpo_vactive_max_blank_us; 983 bool enable_hpo_pg_support; 984 bool enable_legacy_fast_update; 985 bool disable_dc_mode_overwrite; 986 bool replay_skip_crtc_disabled; 987 bool ignore_pg;/*do nothing, let pmfw control it*/ 988 bool psp_disabled_wa; 989 unsigned int ips2_eval_delay_us; 990 unsigned int ips2_entry_delay_us; 991 bool disable_timeout; 992 bool disable_extblankadj; 993 unsigned int static_screen_wait_frames; 994 }; 995 996 struct gpu_info_soc_bounding_box_v1_0; 997 998 /* Generic structure that can be used to query properties of DC. More fields 999 * can be added as required. 1000 */ 1001 struct dc_current_properties { 1002 unsigned int cursor_size_limit; 1003 }; 1004 1005 struct dc { 1006 struct dc_debug_options debug; 1007 struct dc_versions versions; 1008 struct dc_caps caps; 1009 struct dc_cap_funcs cap_funcs; 1010 struct dc_config config; 1011 struct dc_bounding_box_overrides bb_overrides; 1012 struct dc_bug_wa work_arounds; 1013 struct dc_context *ctx; 1014 struct dc_phy_addr_space_config vm_pa_config; 1015 1016 uint8_t link_count; 1017 struct dc_link *links[MAX_PIPES * 2]; 1018 struct link_service *link_srv; 1019 1020 struct dc_state *current_state; 1021 struct resource_pool *res_pool; 1022 1023 struct clk_mgr *clk_mgr; 1024 1025 /* Display Engine Clock levels */ 1026 struct dm_pp_clock_levels sclk_lvls; 1027 1028 /* Inputs into BW and WM calculations. */ 1029 struct bw_calcs_dceip *bw_dceip; 1030 struct bw_calcs_vbios *bw_vbios; 1031 struct dcn_soc_bounding_box *dcn_soc; 1032 struct dcn_ip_params *dcn_ip; 1033 struct display_mode_lib dml; 1034 1035 /* HW functions */ 1036 struct hw_sequencer_funcs hwss; 1037 struct dce_hwseq *hwseq; 1038 1039 /* Require to optimize clocks and bandwidth for added/removed planes */ 1040 bool optimized_required; 1041 bool wm_optimized_required; 1042 bool idle_optimizations_allowed; 1043 bool enable_c20_dtm_b0; 1044 1045 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1046 1047 /* FBC compressor */ 1048 struct compressor *fbc_compressor; 1049 1050 struct dc_debug_data debug_data; 1051 struct dpcd_vendor_signature vendor_signature; 1052 1053 const char *build_id; 1054 struct vm_helper *vm_helper; 1055 1056 uint32_t *dcn_reg_offsets; 1057 uint32_t *nbio_reg_offsets; 1058 uint32_t *clk_reg_offsets; 1059 1060 /* Scratch memory */ 1061 struct { 1062 struct { 1063 /* 1064 * For matching clock_limits table in driver with table 1065 * from PMFW. 1066 */ 1067 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1068 } update_bw_bounding_box; 1069 } scratch; 1070 1071 struct dml2_configuration_options dml2_options; 1072 enum dc_acpi_cm_power_state power_state; 1073 }; 1074 1075 enum frame_buffer_mode { 1076 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1077 FRAME_BUFFER_MODE_ZFB_ONLY, 1078 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1079 } ; 1080 1081 struct dchub_init_data { 1082 int64_t zfb_phys_addr_base; 1083 int64_t zfb_mc_base_addr; 1084 uint64_t zfb_size_in_byte; 1085 enum frame_buffer_mode fb_mode; 1086 bool dchub_initialzied; 1087 bool dchub_info_valid; 1088 }; 1089 1090 struct dc_init_data { 1091 struct hw_asic_id asic_id; 1092 void *driver; /* ctx */ 1093 struct cgs_device *cgs_device; 1094 struct dc_bounding_box_overrides bb_overrides; 1095 1096 int num_virtual_links; 1097 /* 1098 * If 'vbios_override' not NULL, it will be called instead 1099 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1100 */ 1101 struct dc_bios *vbios_override; 1102 enum dce_environment dce_environment; 1103 1104 struct dmub_offload_funcs *dmub_if; 1105 struct dc_reg_helper_state *dmub_offload; 1106 1107 struct dc_config flags; 1108 uint64_t log_mask; 1109 1110 struct dpcd_vendor_signature vendor_signature; 1111 bool force_smu_not_present; 1112 /* 1113 * IP offset for run time initializaion of register addresses 1114 * 1115 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1116 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1117 * before them. 1118 */ 1119 uint32_t *dcn_reg_offsets; 1120 uint32_t *nbio_reg_offsets; 1121 uint32_t *clk_reg_offsets; 1122 }; 1123 1124 struct dc_callback_init { 1125 struct cp_psp cp_psp; 1126 }; 1127 1128 struct dc *dc_create(const struct dc_init_data *init_params); 1129 void dc_hardware_init(struct dc *dc); 1130 1131 int dc_get_vmid_use_vector(struct dc *dc); 1132 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1133 /* Returns the number of vmids supported */ 1134 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1135 void dc_init_callbacks(struct dc *dc, 1136 const struct dc_callback_init *init_params); 1137 void dc_deinit_callbacks(struct dc *dc); 1138 void dc_destroy(struct dc **dc); 1139 1140 /* Surface Interfaces */ 1141 1142 enum { 1143 TRANSFER_FUNC_POINTS = 1025 1144 }; 1145 1146 struct dc_hdr_static_metadata { 1147 /* display chromaticities and white point in units of 0.00001 */ 1148 unsigned int chromaticity_green_x; 1149 unsigned int chromaticity_green_y; 1150 unsigned int chromaticity_blue_x; 1151 unsigned int chromaticity_blue_y; 1152 unsigned int chromaticity_red_x; 1153 unsigned int chromaticity_red_y; 1154 unsigned int chromaticity_white_point_x; 1155 unsigned int chromaticity_white_point_y; 1156 1157 uint32_t min_luminance; 1158 uint32_t max_luminance; 1159 uint32_t maximum_content_light_level; 1160 uint32_t maximum_frame_average_light_level; 1161 }; 1162 1163 enum dc_transfer_func_type { 1164 TF_TYPE_PREDEFINED, 1165 TF_TYPE_DISTRIBUTED_POINTS, 1166 TF_TYPE_BYPASS, 1167 TF_TYPE_HWPWL 1168 }; 1169 1170 struct dc_transfer_func_distributed_points { 1171 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1172 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1173 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1174 1175 uint16_t end_exponent; 1176 uint16_t x_point_at_y1_red; 1177 uint16_t x_point_at_y1_green; 1178 uint16_t x_point_at_y1_blue; 1179 }; 1180 1181 enum dc_transfer_func_predefined { 1182 TRANSFER_FUNCTION_SRGB, 1183 TRANSFER_FUNCTION_BT709, 1184 TRANSFER_FUNCTION_PQ, 1185 TRANSFER_FUNCTION_LINEAR, 1186 TRANSFER_FUNCTION_UNITY, 1187 TRANSFER_FUNCTION_HLG, 1188 TRANSFER_FUNCTION_HLG12, 1189 TRANSFER_FUNCTION_GAMMA22, 1190 TRANSFER_FUNCTION_GAMMA24, 1191 TRANSFER_FUNCTION_GAMMA26 1192 }; 1193 1194 1195 struct dc_transfer_func { 1196 struct kref refcount; 1197 enum dc_transfer_func_type type; 1198 enum dc_transfer_func_predefined tf; 1199 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1200 uint32_t sdr_ref_white_level; 1201 union { 1202 struct pwl_params pwl; 1203 struct dc_transfer_func_distributed_points tf_pts; 1204 }; 1205 }; 1206 1207 1208 union dc_3dlut_state { 1209 struct { 1210 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1211 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1212 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1213 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1214 uint32_t mpc_rmu1_mux:4; 1215 uint32_t mpc_rmu2_mux:4; 1216 uint32_t reserved:15; 1217 } bits; 1218 uint32_t raw; 1219 }; 1220 1221 1222 struct dc_3dlut { 1223 struct kref refcount; 1224 struct tetrahedral_params lut_3d; 1225 struct fixed31_32 hdr_multiplier; 1226 union dc_3dlut_state state; 1227 }; 1228 /* 1229 * This structure is filled in by dc_surface_get_status and contains 1230 * the last requested address and the currently active address so the called 1231 * can determine if there are any outstanding flips 1232 */ 1233 struct dc_plane_status { 1234 struct dc_plane_address requested_address; 1235 struct dc_plane_address current_address; 1236 bool is_flip_pending; 1237 bool is_right_eye; 1238 }; 1239 1240 union surface_update_flags { 1241 1242 struct { 1243 uint32_t addr_update:1; 1244 /* Medium updates */ 1245 uint32_t dcc_change:1; 1246 uint32_t color_space_change:1; 1247 uint32_t horizontal_mirror_change:1; 1248 uint32_t per_pixel_alpha_change:1; 1249 uint32_t global_alpha_change:1; 1250 uint32_t hdr_mult:1; 1251 uint32_t rotation_change:1; 1252 uint32_t swizzle_change:1; 1253 uint32_t scaling_change:1; 1254 uint32_t position_change:1; 1255 uint32_t in_transfer_func_change:1; 1256 uint32_t input_csc_change:1; 1257 uint32_t coeff_reduction_change:1; 1258 uint32_t output_tf_change:1; 1259 uint32_t pixel_format_change:1; 1260 uint32_t plane_size_change:1; 1261 uint32_t gamut_remap_change:1; 1262 1263 /* Full updates */ 1264 uint32_t new_plane:1; 1265 uint32_t bpp_change:1; 1266 uint32_t gamma_change:1; 1267 uint32_t bandwidth_change:1; 1268 uint32_t clock_change:1; 1269 uint32_t stereo_format_change:1; 1270 uint32_t lut_3d:1; 1271 uint32_t tmz_changed:1; 1272 uint32_t full_update:1; 1273 } bits; 1274 1275 uint32_t raw; 1276 }; 1277 1278 struct dc_plane_state { 1279 struct dc_plane_address address; 1280 struct dc_plane_flip_time time; 1281 bool triplebuffer_flips; 1282 struct scaling_taps scaling_quality; 1283 struct rect src_rect; 1284 struct rect dst_rect; 1285 struct rect clip_rect; 1286 1287 struct plane_size plane_size; 1288 union dc_tiling_info tiling_info; 1289 1290 struct dc_plane_dcc_param dcc; 1291 1292 struct dc_gamma *gamma_correction; 1293 struct dc_transfer_func *in_transfer_func; 1294 struct dc_bias_and_scale *bias_and_scale; 1295 struct dc_csc_transform input_csc_color_matrix; 1296 struct fixed31_32 coeff_reduction_factor; 1297 struct fixed31_32 hdr_mult; 1298 struct colorspace_transform gamut_remap_matrix; 1299 1300 // TODO: No longer used, remove 1301 struct dc_hdr_static_metadata hdr_static_ctx; 1302 1303 enum dc_color_space color_space; 1304 1305 struct dc_3dlut *lut3d_func; 1306 struct dc_transfer_func *in_shaper_func; 1307 struct dc_transfer_func *blend_tf; 1308 1309 struct dc_transfer_func *gamcor_tf; 1310 enum surface_pixel_format format; 1311 enum dc_rotation_angle rotation; 1312 enum plane_stereo_format stereo_format; 1313 1314 bool is_tiling_rotated; 1315 bool per_pixel_alpha; 1316 bool pre_multiplied_alpha; 1317 bool global_alpha; 1318 int global_alpha_value; 1319 bool visible; 1320 bool flip_immediate; 1321 bool horizontal_mirror; 1322 int layer_index; 1323 1324 union surface_update_flags update_flags; 1325 bool flip_int_enabled; 1326 bool skip_manual_trigger; 1327 1328 /* private to DC core */ 1329 struct dc_plane_status status; 1330 struct dc_context *ctx; 1331 1332 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1333 bool force_full_update; 1334 1335 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1336 1337 /* private to dc_surface.c */ 1338 enum dc_irq_source irq_source; 1339 struct kref refcount; 1340 struct tg_color visual_confirm_color; 1341 1342 bool is_statically_allocated; 1343 }; 1344 1345 struct dc_plane_info { 1346 struct plane_size plane_size; 1347 union dc_tiling_info tiling_info; 1348 struct dc_plane_dcc_param dcc; 1349 enum surface_pixel_format format; 1350 enum dc_rotation_angle rotation; 1351 enum plane_stereo_format stereo_format; 1352 enum dc_color_space color_space; 1353 bool horizontal_mirror; 1354 bool visible; 1355 bool per_pixel_alpha; 1356 bool pre_multiplied_alpha; 1357 bool global_alpha; 1358 int global_alpha_value; 1359 bool input_csc_enabled; 1360 int layer_index; 1361 }; 1362 1363 struct dc_scaling_info { 1364 struct rect src_rect; 1365 struct rect dst_rect; 1366 struct rect clip_rect; 1367 struct scaling_taps scaling_quality; 1368 }; 1369 1370 struct dc_fast_update { 1371 const struct dc_flip_addrs *flip_addr; 1372 const struct dc_gamma *gamma; 1373 const struct colorspace_transform *gamut_remap_matrix; 1374 const struct dc_csc_transform *input_csc_color_matrix; 1375 const struct fixed31_32 *coeff_reduction_factor; 1376 struct dc_transfer_func *out_transfer_func; 1377 struct dc_csc_transform *output_csc_transform; 1378 }; 1379 1380 struct dc_surface_update { 1381 struct dc_plane_state *surface; 1382 1383 /* isr safe update parameters. null means no updates */ 1384 const struct dc_flip_addrs *flip_addr; 1385 const struct dc_plane_info *plane_info; 1386 const struct dc_scaling_info *scaling_info; 1387 struct fixed31_32 hdr_mult; 1388 /* following updates require alloc/sleep/spin that is not isr safe, 1389 * null means no updates 1390 */ 1391 const struct dc_gamma *gamma; 1392 const struct dc_transfer_func *in_transfer_func; 1393 1394 const struct dc_csc_transform *input_csc_color_matrix; 1395 const struct fixed31_32 *coeff_reduction_factor; 1396 const struct dc_transfer_func *func_shaper; 1397 const struct dc_3dlut *lut3d_func; 1398 const struct dc_transfer_func *blend_tf; 1399 const struct colorspace_transform *gamut_remap_matrix; 1400 }; 1401 1402 /* 1403 * Create a new surface with default parameters; 1404 */ 1405 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1406 void dc_gamma_release(struct dc_gamma **dc_gamma); 1407 struct dc_gamma *dc_create_gamma(void); 1408 1409 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1410 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1411 struct dc_transfer_func *dc_create_transfer_func(void); 1412 1413 struct dc_3dlut *dc_create_3dlut_func(void); 1414 void dc_3dlut_func_release(struct dc_3dlut *lut); 1415 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1416 1417 void dc_post_update_surfaces_to_stream( 1418 struct dc *dc); 1419 1420 #include "dc_stream.h" 1421 1422 /** 1423 * struct dc_validation_set - Struct to store surface/stream associations for validation 1424 */ 1425 struct dc_validation_set { 1426 /** 1427 * @stream: Stream state properties 1428 */ 1429 struct dc_stream_state *stream; 1430 1431 /** 1432 * @plane_states: Surface state 1433 */ 1434 struct dc_plane_state *plane_states[MAX_SURFACES]; 1435 1436 /** 1437 * @plane_count: Total of active planes 1438 */ 1439 uint8_t plane_count; 1440 }; 1441 1442 bool dc_validate_boot_timing(const struct dc *dc, 1443 const struct dc_sink *sink, 1444 struct dc_crtc_timing *crtc_timing); 1445 1446 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1447 1448 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1449 1450 enum dc_status dc_validate_with_context(struct dc *dc, 1451 const struct dc_validation_set set[], 1452 int set_count, 1453 struct dc_state *context, 1454 bool fast_validate); 1455 1456 bool dc_set_generic_gpio_for_stereo(bool enable, 1457 struct gpio_service *gpio_service); 1458 1459 /* 1460 * fast_validate: we return after determining if we can support the new state, 1461 * but before we populate the programming info 1462 */ 1463 enum dc_status dc_validate_global_state( 1464 struct dc *dc, 1465 struct dc_state *new_ctx, 1466 bool fast_validate); 1467 1468 bool dc_acquire_release_mpc_3dlut( 1469 struct dc *dc, bool acquire, 1470 struct dc_stream_state *stream, 1471 struct dc_3dlut **lut, 1472 struct dc_transfer_func **shaper); 1473 1474 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1475 void get_audio_check(struct audio_info *aud_modes, 1476 struct audio_check *aud_chk); 1477 1478 enum dc_status dc_commit_streams(struct dc *dc, 1479 struct dc_stream_state *streams[], 1480 uint8_t stream_count); 1481 1482 1483 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1484 struct dc_stream_state *stream, 1485 int mpcc_inst); 1486 1487 1488 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1489 1490 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1491 1492 /* The function returns minimum bandwidth required to drive a given timing 1493 * return - minimum required timing bandwidth in kbps. 1494 */ 1495 uint32_t dc_bandwidth_in_kbps_from_timing( 1496 const struct dc_crtc_timing *timing, 1497 const enum dc_link_encoding_format link_encoding); 1498 1499 /* Link Interfaces */ 1500 /* 1501 * A link contains one or more sinks and their connected status. 1502 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1503 */ 1504 struct dc_link { 1505 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1506 unsigned int sink_count; 1507 struct dc_sink *local_sink; 1508 unsigned int link_index; 1509 enum dc_connection_type type; 1510 enum signal_type connector_signal; 1511 enum dc_irq_source irq_source_hpd; 1512 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1513 1514 bool is_hpd_filter_disabled; 1515 bool dp_ss_off; 1516 1517 /** 1518 * @link_state_valid: 1519 * 1520 * If there is no link and local sink, this variable should be set to 1521 * false. Otherwise, it should be set to true; usually, the function 1522 * core_link_enable_stream sets this field to true. 1523 */ 1524 bool link_state_valid; 1525 bool aux_access_disabled; 1526 bool sync_lt_in_progress; 1527 bool skip_stream_reenable; 1528 bool is_internal_display; 1529 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1530 bool is_dig_mapping_flexible; 1531 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1532 bool is_hpd_pending; /* Indicates a new received hpd */ 1533 1534 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1535 * for every link training. This is incompatible with DP LL compliance automation, 1536 * which expects the same link settings to be used every retry on a link loss. 1537 * This flag is used to skip the fallback when link loss occurs during automation. 1538 */ 1539 bool skip_fallback_on_link_loss; 1540 1541 bool edp_sink_present; 1542 1543 struct dp_trace dp_trace; 1544 1545 /* caps is the same as reported_link_cap. link_traing use 1546 * reported_link_cap. Will clean up. TODO 1547 */ 1548 struct dc_link_settings reported_link_cap; 1549 struct dc_link_settings verified_link_cap; 1550 struct dc_link_settings cur_link_settings; 1551 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1552 struct dc_link_settings preferred_link_setting; 1553 /* preferred_training_settings are override values that 1554 * come from DM. DM is responsible for the memory 1555 * management of the override pointers. 1556 */ 1557 struct dc_link_training_overrides preferred_training_settings; 1558 struct dp_audio_test_data audio_test_data; 1559 1560 uint8_t ddc_hw_inst; 1561 1562 uint8_t hpd_src; 1563 1564 uint8_t link_enc_hw_inst; 1565 /* DIG link encoder ID. Used as index in link encoder resource pool. 1566 * For links with fixed mapping to DIG, this is not changed after dc_link 1567 * object creation. 1568 */ 1569 enum engine_id eng_id; 1570 enum engine_id dpia_preferred_eng_id; 1571 1572 bool test_pattern_enabled; 1573 enum dp_test_pattern current_test_pattern; 1574 union compliance_test_state compliance_test_state; 1575 1576 void *priv; 1577 1578 struct ddc_service *ddc; 1579 1580 enum dp_panel_mode panel_mode; 1581 bool aux_mode; 1582 1583 /* Private to DC core */ 1584 1585 const struct dc *dc; 1586 1587 struct dc_context *ctx; 1588 1589 struct panel_cntl *panel_cntl; 1590 struct link_encoder *link_enc; 1591 struct graphics_object_id link_id; 1592 /* Endpoint type distinguishes display endpoints which do not have entries 1593 * in the BIOS connector table from those that do. Helps when tracking link 1594 * encoder to display endpoint assignments. 1595 */ 1596 enum display_endpoint_type ep_type; 1597 union ddi_channel_mapping ddi_channel_mapping; 1598 struct connector_device_tag_info device_tag; 1599 struct dpcd_caps dpcd_caps; 1600 uint32_t dongle_max_pix_clk; 1601 unsigned short chip_caps; 1602 unsigned int dpcd_sink_count; 1603 struct hdcp_caps hdcp_caps; 1604 enum edp_revision edp_revision; 1605 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1606 1607 struct psr_settings psr_settings; 1608 1609 struct replay_settings replay_settings; 1610 1611 /* Drive settings read from integrated info table */ 1612 struct dc_lane_settings bios_forced_drive_settings; 1613 1614 /* Vendor specific LTTPR workaround variables */ 1615 uint8_t vendor_specific_lttpr_link_rate_wa; 1616 bool apply_vendor_specific_lttpr_link_rate_wa; 1617 1618 /* MST record stream using this link */ 1619 struct link_flags { 1620 bool dp_keep_receiver_powered; 1621 bool dp_skip_DID2; 1622 bool dp_skip_reset_segment; 1623 bool dp_skip_fs_144hz; 1624 bool dp_mot_reset_segment; 1625 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1626 bool dpia_mst_dsc_always_on; 1627 /* Forced DPIA into TBT3 compatibility mode. */ 1628 bool dpia_forced_tbt3_mode; 1629 bool dongle_mode_timing_override; 1630 bool blank_stream_on_ocs_change; 1631 bool read_dpcd204h_on_irq_hpd; 1632 } wa_flags; 1633 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1634 1635 struct dc_link_status link_status; 1636 struct dprx_states dprx_states; 1637 1638 struct gpio *hpd_gpio; 1639 enum dc_link_fec_state fec_state; 1640 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1641 1642 struct dc_panel_config panel_config; 1643 struct phy_state phy_state; 1644 // BW ALLOCATON USB4 ONLY 1645 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1646 bool skip_implict_edp_power_control; 1647 }; 1648 1649 /* Return an enumerated dc_link. 1650 * dc_link order is constant and determined at 1651 * boot time. They cannot be created or destroyed. 1652 * Use dc_get_caps() to get number of links. 1653 */ 1654 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1655 1656 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1657 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1658 const struct dc_link *link, 1659 unsigned int *inst_out); 1660 1661 /* Return an array of link pointers to edp links. */ 1662 void dc_get_edp_links(const struct dc *dc, 1663 struct dc_link **edp_links, 1664 int *edp_num); 1665 1666 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1667 bool powerOn); 1668 1669 /* The function initiates detection handshake over the given link. It first 1670 * determines if there are display connections over the link. If so it initiates 1671 * detection protocols supported by the connected receiver device. The function 1672 * contains protocol specific handshake sequences which are sometimes mandatory 1673 * to establish a proper connection between TX and RX. So it is always 1674 * recommended to call this function as the first link operation upon HPD event 1675 * or power up event. Upon completion, the function will update link structure 1676 * in place based on latest RX capabilities. The function may also cause dpms 1677 * to be reset to off for all currently enabled streams to the link. It is DM's 1678 * responsibility to serialize detection and DPMS updates. 1679 * 1680 * @reason - Indicate which event triggers this detection. dc may customize 1681 * detection flow depending on the triggering events. 1682 * return false - if detection is not fully completed. This could happen when 1683 * there is an unrecoverable error during detection or detection is partially 1684 * completed (detection has been delegated to dm mst manager ie. 1685 * link->connection_type == dc_connection_mst_branch when returning false). 1686 * return true - detection is completed, link has been fully updated with latest 1687 * detection result. 1688 */ 1689 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1690 1691 struct dc_sink_init_data; 1692 1693 /* When link connection type is dc_connection_mst_branch, remote sink can be 1694 * added to the link. The interface creates a remote sink and associates it with 1695 * current link. The sink will be retained by link until remove remote sink is 1696 * called. 1697 * 1698 * @dc_link - link the remote sink will be added to. 1699 * @edid - byte array of EDID raw data. 1700 * @len - size of the edid in byte 1701 * @init_data - 1702 */ 1703 struct dc_sink *dc_link_add_remote_sink( 1704 struct dc_link *dc_link, 1705 const uint8_t *edid, 1706 int len, 1707 struct dc_sink_init_data *init_data); 1708 1709 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1710 * @link - link the sink should be removed from 1711 * @sink - sink to be removed. 1712 */ 1713 void dc_link_remove_remote_sink( 1714 struct dc_link *link, 1715 struct dc_sink *sink); 1716 1717 /* Enable HPD interrupt handler for a given link */ 1718 void dc_link_enable_hpd(const struct dc_link *link); 1719 1720 /* Disable HPD interrupt handler for a given link */ 1721 void dc_link_disable_hpd(const struct dc_link *link); 1722 1723 /* determine if there is a sink connected to the link 1724 * 1725 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1726 * return - false if an unexpected error occurs, true otherwise. 1727 * 1728 * NOTE: This function doesn't detect downstream sink connections i.e 1729 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1730 * return dc_connection_single if the branch device is connected despite of 1731 * downstream sink's connection status. 1732 */ 1733 bool dc_link_detect_connection_type(struct dc_link *link, 1734 enum dc_connection_type *type); 1735 1736 /* query current hpd pin value 1737 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1738 * 1739 */ 1740 bool dc_link_get_hpd_state(struct dc_link *link); 1741 1742 /* Getter for cached link status from given link */ 1743 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1744 1745 /* enable/disable hardware HPD filter. 1746 * 1747 * @link - The link the HPD pin is associated with. 1748 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1749 * handler once after no HPD change has been detected within dc default HPD 1750 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1751 * pulses within default HPD interval, no HPD event will be received until HPD 1752 * toggles have stopped. Then HPD event will be queued to irq handler once after 1753 * dc default HPD filtering interval since last HPD event. 1754 * 1755 * @enable = false - disable hardware HPD filter. HPD event will be queued 1756 * immediately to irq handler after no HPD change has been detected within 1757 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1758 */ 1759 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1760 1761 /* submit i2c read/write payloads through ddc channel 1762 * @link_index - index to a link with ddc in i2c mode 1763 * @cmd - i2c command structure 1764 * return - true if success, false otherwise. 1765 */ 1766 bool dc_submit_i2c( 1767 struct dc *dc, 1768 uint32_t link_index, 1769 struct i2c_command *cmd); 1770 1771 /* submit i2c read/write payloads through oem channel 1772 * @link_index - index to a link with ddc in i2c mode 1773 * @cmd - i2c command structure 1774 * return - true if success, false otherwise. 1775 */ 1776 bool dc_submit_i2c_oem( 1777 struct dc *dc, 1778 struct i2c_command *cmd); 1779 1780 enum aux_return_code_type; 1781 /* Attempt to transfer the given aux payload. This function does not perform 1782 * retries or handle error states. The reply is returned in the payload->reply 1783 * and the result through operation_result. Returns the number of bytes 1784 * transferred,or -1 on a failure. 1785 */ 1786 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1787 struct aux_payload *payload, 1788 enum aux_return_code_type *operation_result); 1789 1790 bool dc_is_oem_i2c_device_present( 1791 struct dc *dc, 1792 size_t slave_address 1793 ); 1794 1795 /* return true if the connected receiver supports the hdcp version */ 1796 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1797 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1798 1799 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1800 * 1801 * TODO - When defer_handling is true the function will have a different purpose. 1802 * It no longer does complete hpd rx irq handling. We should create a separate 1803 * interface specifically for this case. 1804 * 1805 * Return: 1806 * true - Downstream port status changed. DM should call DC to do the 1807 * detection. 1808 * false - no change in Downstream port status. No further action required 1809 * from DM. 1810 */ 1811 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1812 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1813 bool defer_handling, bool *has_left_work); 1814 /* handle DP specs define test automation sequence*/ 1815 void dc_link_dp_handle_automated_test(struct dc_link *link); 1816 1817 /* handle DP Link loss sequence and try to recover RX link loss with best 1818 * effort 1819 */ 1820 void dc_link_dp_handle_link_loss(struct dc_link *link); 1821 1822 /* Determine if hpd rx irq should be handled or ignored 1823 * return true - hpd rx irq should be handled. 1824 * return false - it is safe to ignore hpd rx irq event 1825 */ 1826 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1827 1828 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1829 * @link - link the hpd irq data associated with 1830 * @hpd_irq_dpcd_data - input hpd irq data 1831 * return - true if hpd irq data indicates a link lost 1832 */ 1833 bool dc_link_check_link_loss_status(struct dc_link *link, 1834 union hpd_irq_data *hpd_irq_dpcd_data); 1835 1836 /* Read hpd rx irq data from a given link 1837 * @link - link where the hpd irq data should be read from 1838 * @irq_data - output hpd irq data 1839 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1840 * read has failed. 1841 */ 1842 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1843 struct dc_link *link, 1844 union hpd_irq_data *irq_data); 1845 1846 /* The function clears recorded DP RX states in the link. DM should call this 1847 * function when it is resuming from S3 power state to previously connected links. 1848 * 1849 * TODO - in the future we should consider to expand link resume interface to 1850 * support clearing previous rx states. So we don't have to rely on dm to call 1851 * this interface explicitly. 1852 */ 1853 void dc_link_clear_dprx_states(struct dc_link *link); 1854 1855 /* Destruct the mst topology of the link and reset the allocated payload table 1856 * 1857 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1858 * still wants to reset MST topology on an unplug event */ 1859 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1860 1861 /* The function calculates effective DP link bandwidth when a given link is 1862 * using the given link settings. 1863 * 1864 * return - total effective link bandwidth in kbps. 1865 */ 1866 uint32_t dc_link_bandwidth_kbps( 1867 const struct dc_link *link, 1868 const struct dc_link_settings *link_setting); 1869 1870 /* The function takes a snapshot of current link resource allocation state 1871 * @dc: pointer to dc of the dm calling this 1872 * @map: a dc link resource snapshot defined internally to dc. 1873 * 1874 * DM needs to capture a snapshot of current link resource allocation mapping 1875 * and store it in its persistent storage. 1876 * 1877 * Some of the link resource is using first come first serve policy. 1878 * The allocation mapping depends on original hotplug order. This information 1879 * is lost after driver is loaded next time. The snapshot is used in order to 1880 * restore link resource to its previous state so user will get consistent 1881 * link capability allocation across reboot. 1882 * 1883 */ 1884 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1885 1886 /* This function restores link resource allocation state from a snapshot 1887 * @dc: pointer to dc of the dm calling this 1888 * @map: a dc link resource snapshot defined internally to dc. 1889 * 1890 * DM needs to call this function after initial link detection on boot and 1891 * before first commit streams to restore link resource allocation state 1892 * from previous boot session. 1893 * 1894 * Some of the link resource is using first come first serve policy. 1895 * The allocation mapping depends on original hotplug order. This information 1896 * is lost after driver is loaded next time. The snapshot is used in order to 1897 * restore link resource to its previous state so user will get consistent 1898 * link capability allocation across reboot. 1899 * 1900 */ 1901 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1902 1903 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1904 * interface i.e stream_update->dsc_config 1905 */ 1906 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1907 1908 /* translate a raw link rate data to bandwidth in kbps */ 1909 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1910 1911 /* determine the optimal bandwidth given link and required bw. 1912 * @link - current detected link 1913 * @req_bw - requested bandwidth in kbps 1914 * @link_settings - returned most optimal link settings that can fit the 1915 * requested bandwidth 1916 * return - false if link can't support requested bandwidth, true if link 1917 * settings is found. 1918 */ 1919 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1920 struct dc_link_settings *link_settings, 1921 uint32_t req_bw); 1922 1923 /* return the max dp link settings can be driven by the link without considering 1924 * connected RX device and its capability 1925 */ 1926 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1927 struct dc_link_settings *max_link_enc_cap); 1928 1929 /* determine when the link is driving MST mode, what DP link channel coding 1930 * format will be used. The decision will remain unchanged until next HPD event. 1931 * 1932 * @link - a link with DP RX connection 1933 * return - if stream is committed to this link with MST signal type, type of 1934 * channel coding format dc will choose. 1935 */ 1936 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1937 const struct dc_link *link); 1938 1939 /* get max dp link settings the link can enable with all things considered. (i.e 1940 * TX/RX/Cable capabilities and dp override policies. 1941 * 1942 * @link - a link with DP RX connection 1943 * return - max dp link settings the link can enable. 1944 * 1945 */ 1946 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1947 1948 /* Get the highest encoding format that the link supports; highest meaning the 1949 * encoding format which supports the maximum bandwidth. 1950 * 1951 * @link - a link with DP RX connection 1952 * return - highest encoding format link supports. 1953 */ 1954 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 1955 1956 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1957 * to a link with dp connector signal type. 1958 * @link - a link with dp connector signal type 1959 * return - true if connected, false otherwise 1960 */ 1961 bool dc_link_is_dp_sink_present(struct dc_link *link); 1962 1963 /* Force DP lane settings update to main-link video signal and notify the change 1964 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1965 * tuning purpose. The interface assumes link has already been enabled with DP 1966 * signal. 1967 * 1968 * @lt_settings - a container structure with desired hw_lane_settings 1969 */ 1970 void dc_link_set_drive_settings(struct dc *dc, 1971 struct link_training_settings *lt_settings, 1972 struct dc_link *link); 1973 1974 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1975 * test or debugging purpose. The test pattern will remain until next un-plug. 1976 * 1977 * @link - active link with DP signal output enabled. 1978 * @test_pattern - desired test pattern to output. 1979 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1980 * @test_pattern_color_space - for video test pattern choose a desired color 1981 * space. 1982 * @p_link_settings - For PHY pattern choose a desired link settings 1983 * @p_custom_pattern - some test pattern will require a custom input to 1984 * customize some pattern details. Otherwise keep it to NULL. 1985 * @cust_pattern_size - size of the custom pattern input. 1986 * 1987 */ 1988 bool dc_link_dp_set_test_pattern( 1989 struct dc_link *link, 1990 enum dp_test_pattern test_pattern, 1991 enum dp_test_pattern_color_space test_pattern_color_space, 1992 const struct link_training_settings *p_link_settings, 1993 const unsigned char *p_custom_pattern, 1994 unsigned int cust_pattern_size); 1995 1996 /* Force DP link settings to always use a specific value until reboot to a 1997 * specific link. If link has already been enabled, the interface will also 1998 * switch to desired link settings immediately. This is a debug interface to 1999 * generic dp issue trouble shooting. 2000 */ 2001 void dc_link_set_preferred_link_settings(struct dc *dc, 2002 struct dc_link_settings *link_setting, 2003 struct dc_link *link); 2004 2005 /* Force DP link to customize a specific link training behavior by overriding to 2006 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2007 * display specific link training issues or apply some display specific 2008 * workaround in link training. 2009 * 2010 * @link_settings - if not NULL, force preferred link settings to the link. 2011 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2012 * will apply this particular override in future link training. If NULL is 2013 * passed in, dc resets previous overrides. 2014 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2015 * training settings. 2016 */ 2017 void dc_link_set_preferred_training_settings(struct dc *dc, 2018 struct dc_link_settings *link_setting, 2019 struct dc_link_training_overrides *lt_overrides, 2020 struct dc_link *link, 2021 bool skip_immediate_retrain); 2022 2023 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2024 bool dc_link_is_fec_supported(const struct dc_link *link); 2025 2026 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2027 * link enablement. 2028 * return - true if FEC should be enabled, false otherwise. 2029 */ 2030 bool dc_link_should_enable_fec(const struct dc_link *link); 2031 2032 /* determine lttpr mode the current link should be enabled with a specific link 2033 * settings. 2034 */ 2035 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2036 struct dc_link_settings *link_setting); 2037 2038 /* Force DP RX to update its power state. 2039 * NOTE: this interface doesn't update dp main-link. Calling this function will 2040 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2041 * RX power state back upon finish DM specific execution requiring DP RX in a 2042 * specific power state. 2043 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2044 * state. 2045 */ 2046 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2047 2048 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2049 * current value read from extended receiver cap from 02200h - 0220Fh. 2050 * Some DP RX has problems of providing accurate DP receiver caps from extended 2051 * field, this interface is a workaround to revert link back to use base caps. 2052 */ 2053 void dc_link_overwrite_extended_receiver_cap( 2054 struct dc_link *link); 2055 2056 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2057 bool wait_for_hpd); 2058 2059 /* Set backlight level of an embedded panel (eDP, LVDS). 2060 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2061 * and 16 bit fractional, where 1.0 is max backlight value. 2062 */ 2063 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2064 uint32_t backlight_pwm_u16_16, 2065 uint32_t frame_ramp); 2066 2067 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2068 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2069 bool isHDR, 2070 uint32_t backlight_millinits, 2071 uint32_t transition_time_in_ms); 2072 2073 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2074 uint32_t *backlight_millinits, 2075 uint32_t *backlight_millinits_peak); 2076 2077 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2078 2079 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2080 2081 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2082 bool wait, bool force_static, const unsigned int *power_opts); 2083 2084 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2085 2086 bool dc_link_setup_psr(struct dc_link *dc_link, 2087 const struct dc_stream_state *stream, struct psr_config *psr_config, 2088 struct psr_context *psr_context); 2089 2090 /* 2091 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2092 * 2093 * @link: pointer to the dc_link struct instance 2094 * @enable: enable(active) or disable(inactive) replay 2095 * @wait: state transition need to wait the active set completed. 2096 * @force_static: force disable(inactive) the replay 2097 * @power_opts: set power optimazation parameters to DMUB. 2098 * 2099 * return: allow Replay active will return true, else will return false. 2100 */ 2101 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2102 bool wait, bool force_static, const unsigned int *power_opts); 2103 2104 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2105 2106 /* On eDP links this function call will stall until T12 has elapsed. 2107 * If the panel is not in power off state, this function will return 2108 * immediately. 2109 */ 2110 bool dc_link_wait_for_t12(struct dc_link *link); 2111 2112 /* Determine if dp trace has been initialized to reflect upto date result * 2113 * return - true if trace is initialized and has valid data. False dp trace 2114 * doesn't have valid result. 2115 */ 2116 bool dc_dp_trace_is_initialized(struct dc_link *link); 2117 2118 /* Query a dp trace flag to indicate if the current dp trace data has been 2119 * logged before 2120 */ 2121 bool dc_dp_trace_is_logged(struct dc_link *link, 2122 bool in_detection); 2123 2124 /* Set dp trace flag to indicate whether DM has already logged the current dp 2125 * trace data. DM can set is_logged to true upon logging and check 2126 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2127 */ 2128 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2129 bool in_detection, 2130 bool is_logged); 2131 2132 /* Obtain driver time stamp for last dp link training end. The time stamp is 2133 * formatted based on dm_get_timestamp DM function. 2134 * @in_detection - true to get link training end time stamp of last link 2135 * training in detection sequence. false to get link training end time stamp 2136 * of last link training in commit (dpms) sequence 2137 */ 2138 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2139 bool in_detection); 2140 2141 /* Get how many link training attempts dc has done with latest sequence. 2142 * @in_detection - true to get link training count of last link 2143 * training in detection sequence. false to get link training count of last link 2144 * training in commit (dpms) sequence 2145 */ 2146 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2147 bool in_detection); 2148 2149 /* Get how many link loss has happened since last link training attempts */ 2150 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2151 2152 /* 2153 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2154 */ 2155 /* 2156 * Send a request from DP-Tx requesting to allocate BW remotely after 2157 * allocating it locally. This will get processed by CM and a CB function 2158 * will be called. 2159 * 2160 * @link: pointer to the dc_link struct instance 2161 * @req_bw: The requested bw in Kbyte to allocated 2162 * 2163 * return: none 2164 */ 2165 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2166 2167 /* 2168 * Handle function for when the status of the Request above is complete. 2169 * We will find out the result of allocating on CM and update structs. 2170 * 2171 * @link: pointer to the dc_link struct instance 2172 * @bw: Allocated or Estimated BW depending on the result 2173 * @result: Response type 2174 * 2175 * return: none 2176 */ 2177 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2178 uint8_t bw, uint8_t result); 2179 2180 /* 2181 * Handle the USB4 BW Allocation related functionality here: 2182 * Plug => Try to allocate max bw from timing parameters supported by the sink 2183 * Unplug => de-allocate bw 2184 * 2185 * @link: pointer to the dc_link struct instance 2186 * @peak_bw: Peak bw used by the link/sink 2187 * 2188 * return: allocated bw else return 0 2189 */ 2190 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2191 struct dc_link *link, int peak_bw); 2192 2193 /* 2194 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2195 * available BW for each host router 2196 * 2197 * @dc: pointer to dc struct 2198 * @stream: pointer to all possible streams 2199 * @count: number of valid DPIA streams 2200 * 2201 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2202 */ 2203 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2204 const unsigned int count); 2205 2206 /* Sink Interfaces - A sink corresponds to a display output device */ 2207 2208 struct dc_container_id { 2209 // 128bit GUID in binary form 2210 unsigned char guid[16]; 2211 // 8 byte port ID -> ELD.PortID 2212 unsigned int portId[2]; 2213 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2214 unsigned short manufacturerName; 2215 // 2 byte product code -> ELD.ProductCode 2216 unsigned short productCode; 2217 }; 2218 2219 2220 struct dc_sink_dsc_caps { 2221 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2222 // 'false' if they are sink's DSC caps 2223 bool is_virtual_dpcd_dsc; 2224 #if defined(CONFIG_DRM_AMD_DC_FP) 2225 // 'true' if MST topology supports DSC passthrough for sink 2226 // 'false' if MST topology does not support DSC passthrough 2227 bool is_dsc_passthrough_supported; 2228 #endif 2229 struct dsc_dec_dpcd_caps dsc_dec_caps; 2230 }; 2231 2232 struct dc_sink_fec_caps { 2233 bool is_rx_fec_supported; 2234 bool is_topology_fec_supported; 2235 }; 2236 2237 struct scdc_caps { 2238 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2239 union hdmi_scdc_device_id_data device_id; 2240 }; 2241 2242 /* 2243 * The sink structure contains EDID and other display device properties 2244 */ 2245 struct dc_sink { 2246 enum signal_type sink_signal; 2247 struct dc_edid dc_edid; /* raw edid */ 2248 struct dc_edid_caps edid_caps; /* parse display caps */ 2249 struct dc_container_id *dc_container_id; 2250 uint32_t dongle_max_pix_clk; 2251 void *priv; 2252 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2253 bool converter_disable_audio; 2254 2255 struct scdc_caps scdc_caps; 2256 struct dc_sink_dsc_caps dsc_caps; 2257 struct dc_sink_fec_caps fec_caps; 2258 2259 bool is_vsc_sdp_colorimetry_supported; 2260 2261 /* private to DC core */ 2262 struct dc_link *link; 2263 struct dc_context *ctx; 2264 2265 uint32_t sink_id; 2266 2267 /* private to dc_sink.c */ 2268 // refcount must be the last member in dc_sink, since we want the 2269 // sink structure to be logically cloneable up to (but not including) 2270 // refcount 2271 struct kref refcount; 2272 }; 2273 2274 void dc_sink_retain(struct dc_sink *sink); 2275 void dc_sink_release(struct dc_sink *sink); 2276 2277 struct dc_sink_init_data { 2278 enum signal_type sink_signal; 2279 struct dc_link *link; 2280 uint32_t dongle_max_pix_clk; 2281 bool converter_disable_audio; 2282 }; 2283 2284 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2285 2286 /* Newer interfaces */ 2287 struct dc_cursor { 2288 struct dc_plane_address address; 2289 struct dc_cursor_attributes attributes; 2290 }; 2291 2292 2293 /* Interrupt interfaces */ 2294 enum dc_irq_source dc_interrupt_to_irq_source( 2295 struct dc *dc, 2296 uint32_t src_id, 2297 uint32_t ext_id); 2298 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2299 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2300 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2301 struct dc *dc, uint32_t link_index); 2302 2303 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2304 2305 /* Power Interfaces */ 2306 2307 void dc_set_power_state( 2308 struct dc *dc, 2309 enum dc_acpi_cm_power_state power_state); 2310 void dc_resume(struct dc *dc); 2311 2312 void dc_power_down_on_boot(struct dc *dc); 2313 2314 /* 2315 * HDCP Interfaces 2316 */ 2317 enum hdcp_message_status dc_process_hdcp_msg( 2318 enum signal_type signal, 2319 struct dc_link *link, 2320 struct hdcp_protection_message *message_info); 2321 bool dc_is_dmcu_initialized(struct dc *dc); 2322 2323 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2324 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2325 2326 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2327 struct dc_cursor_attributes *cursor_attr); 2328 2329 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2330 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2331 2332 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2333 void dc_unlock_memory_clock_frequency(struct dc *dc); 2334 2335 /* set min memory clock to the min required for current mode, max to maxDPM */ 2336 void dc_lock_memory_clock_frequency(struct dc *dc); 2337 2338 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2339 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2340 2341 /* cleanup on driver unload */ 2342 void dc_hardware_release(struct dc *dc); 2343 2344 /* disables fw based mclk switch */ 2345 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2346 2347 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2348 2349 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2350 2351 void dc_z10_restore(const struct dc *dc); 2352 void dc_z10_save_init(struct dc *dc); 2353 2354 bool dc_is_dmub_outbox_supported(struct dc *dc); 2355 bool dc_enable_dmub_notifications(struct dc *dc); 2356 2357 bool dc_abm_save_restore( 2358 struct dc *dc, 2359 struct dc_stream_state *stream, 2360 struct abm_save_restore *pData); 2361 2362 void dc_enable_dmub_outbox(struct dc *dc); 2363 2364 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2365 uint32_t link_index, 2366 struct aux_payload *payload); 2367 2368 /* Get dc link index from dpia port index */ 2369 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2370 uint8_t dpia_port_index); 2371 2372 bool dc_process_dmub_set_config_async(struct dc *dc, 2373 uint32_t link_index, 2374 struct set_config_cmd_payload *payload, 2375 struct dmub_notification *notify); 2376 2377 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2378 uint32_t link_index, 2379 uint8_t mst_alloc_slots, 2380 uint8_t *mst_slots_in_use); 2381 2382 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2383 uint32_t hpd_int_enable); 2384 2385 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2386 2387 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2388 2389 struct dc_power_profile { 2390 int power_level; /* Lower is better */ 2391 }; 2392 2393 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2394 2395 /* DSC Interfaces */ 2396 #include "dc_dsc.h" 2397 2398 /* Disable acc mode Interfaces */ 2399 void dc_disable_accelerated_mode(struct dc *dc); 2400 2401 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2402 struct dc_stream_state *new_stream); 2403 2404 #endif /* DC_INTERFACE_H_ */ 2405