1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.163" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 struct dc_plane_cap { 79 enum dc_plane_type type; 80 uint32_t blends_with_above : 1; 81 uint32_t blends_with_below : 1; 82 uint32_t per_pixel_alpha : 1; 83 struct { 84 uint32_t argb8888 : 1; 85 uint32_t nv12 : 1; 86 uint32_t fp16 : 1; 87 uint32_t p010 : 1; 88 uint32_t ayuv : 1; 89 } pixel_format_support; 90 // max upscaling factor x1000 91 // upscaling factors are always >= 1 92 // for example, 1080p -> 8K is 4.0, or 4000 raw value 93 struct { 94 uint32_t argb8888; 95 uint32_t nv12; 96 uint32_t fp16; 97 } max_upscale_factor; 98 // max downscale factor x1000 99 // downscale factors are always <= 1 100 // for example, 8K -> 1080p is 0.25, or 250 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_downscale_factor; 106 // minimal width/height 107 uint32_t min_width; 108 uint32_t min_height; 109 }; 110 111 // Color management caps (DPP and MPC) 112 struct rom_curve_caps { 113 uint16_t srgb : 1; 114 uint16_t bt2020 : 1; 115 uint16_t gamma2_2 : 1; 116 uint16_t pq : 1; 117 uint16_t hlg : 1; 118 }; 119 120 struct dpp_color_caps { 121 uint16_t dcn_arch : 1; // all DCE generations treated the same 122 // input lut is different than most LUTs, just plain 256-entry lookup 123 uint16_t input_lut_shared : 1; // shared with DGAM 124 uint16_t icsc : 1; 125 uint16_t dgam_ram : 1; 126 uint16_t post_csc : 1; // before gamut remap 127 uint16_t gamma_corr : 1; 128 129 // hdr_mult and gamut remap always available in DPP (in that order) 130 // 3d lut implies shaper LUT, 131 // it may be shared with MPC - check MPC:shared_3d_lut flag 132 uint16_t hw_3d_lut : 1; 133 uint16_t ogam_ram : 1; // blnd gam 134 uint16_t ocsc : 1; 135 uint16_t dgam_rom_for_yuv : 1; 136 struct rom_curve_caps dgam_rom_caps; 137 struct rom_curve_caps ogam_rom_caps; 138 }; 139 140 struct mpc_color_caps { 141 uint16_t gamut_remap : 1; 142 uint16_t ogam_ram : 1; 143 uint16_t ocsc : 1; 144 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 145 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 146 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct dc_color_caps { 151 struct dpp_color_caps dpp; 152 struct mpc_color_caps mpc; 153 }; 154 155 struct dc_caps { 156 uint32_t max_streams; 157 uint32_t max_links; 158 uint32_t max_audios; 159 uint32_t max_slave_planes; 160 uint32_t max_slave_yuv_planes; 161 uint32_t max_slave_rgb_planes; 162 uint32_t max_planes; 163 uint32_t max_downscale_ratio; 164 uint32_t i2c_speed_in_khz; 165 uint32_t i2c_speed_in_khz_hdcp; 166 uint32_t dmdata_alloc_size; 167 unsigned int max_cursor_size; 168 unsigned int max_video_width; 169 unsigned int min_horizontal_blanking_period; 170 int linear_pitch_alignment; 171 bool dcc_const_color; 172 bool dynamic_audio; 173 bool is_apu; 174 bool dual_link_dvi; 175 bool post_blend_color_processing; 176 bool force_dp_tps4_for_cp2520; 177 bool disable_dp_clk_share; 178 bool psp_setup_panel_mode; 179 bool extended_aux_timeout_support; 180 bool dmcub_support; 181 uint32_t num_of_internal_disp; 182 enum dp_protocol_version max_dp_protocol_version; 183 unsigned int mall_size_per_mem_channel; 184 unsigned int mall_size_total; 185 unsigned int cursor_cache_size; 186 struct dc_plane_cap planes[MAX_PLANES]; 187 struct dc_color_caps color; 188 #if defined(CONFIG_DRM_AMD_DC_DCN) 189 bool dp_hpo; 190 #endif 191 bool edp_dsc_support; 192 bool vbios_lttpr_aware; 193 bool vbios_lttpr_enable; 194 }; 195 196 struct dc_bug_wa { 197 bool no_connect_phy_config; 198 bool dedcn20_305_wa; 199 bool skip_clock_update; 200 bool lt_early_cr_pattern; 201 }; 202 203 struct dc_dcc_surface_param { 204 struct dc_size surface_size; 205 enum surface_pixel_format format; 206 enum swizzle_mode_values swizzle_mode; 207 enum dc_scan_direction scan; 208 }; 209 210 struct dc_dcc_setting { 211 unsigned int max_compressed_blk_size; 212 unsigned int max_uncompressed_blk_size; 213 bool independent_64b_blks; 214 #if defined(CONFIG_DRM_AMD_DC_DCN) 215 //These bitfields to be used starting with DCN 216 struct { 217 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 218 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 219 uint32_t dcc_256_128_128 : 1; //available starting with DCN 220 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 221 } dcc_controls; 222 #endif 223 }; 224 225 struct dc_surface_dcc_cap { 226 union { 227 struct { 228 struct dc_dcc_setting rgb; 229 } grph; 230 231 struct { 232 struct dc_dcc_setting luma; 233 struct dc_dcc_setting chroma; 234 } video; 235 }; 236 237 bool capable; 238 bool const_color_support; 239 }; 240 241 struct dc_static_screen_params { 242 struct { 243 bool force_trigger; 244 bool cursor_update; 245 bool surface_update; 246 bool overlay_update; 247 } triggers; 248 unsigned int num_frames; 249 }; 250 251 252 /* Surface update type is used by dc_update_surfaces_and_stream 253 * The update type is determined at the very beginning of the function based 254 * on parameters passed in and decides how much programming (or updating) is 255 * going to be done during the call. 256 * 257 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 258 * logical calculations or hardware register programming. This update MUST be 259 * ISR safe on windows. Currently fast update will only be used to flip surface 260 * address. 261 * 262 * UPDATE_TYPE_MED is used for slower updates which require significant hw 263 * re-programming however do not affect bandwidth consumption or clock 264 * requirements. At present, this is the level at which front end updates 265 * that do not require us to run bw_calcs happen. These are in/out transfer func 266 * updates, viewport offset changes, recout size changes and pixel depth changes. 267 * This update can be done at ISR, but we want to minimize how often this happens. 268 * 269 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 270 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 271 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 272 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 273 * a full update. This cannot be done at ISR level and should be a rare event. 274 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 275 * underscan we don't expect to see this call at all. 276 */ 277 278 enum surface_update_type { 279 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 280 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 281 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 282 }; 283 284 /* Forward declaration*/ 285 struct dc; 286 struct dc_plane_state; 287 struct dc_state; 288 289 290 struct dc_cap_funcs { 291 bool (*get_dcc_compression_cap)(const struct dc *dc, 292 const struct dc_dcc_surface_param *input, 293 struct dc_surface_dcc_cap *output); 294 }; 295 296 struct link_training_settings; 297 298 #if defined(CONFIG_DRM_AMD_DC_DCN) 299 union allow_lttpr_non_transparent_mode { 300 struct { 301 bool DP1_4A : 1; 302 bool DP2_0 : 1; 303 } bits; 304 unsigned char raw; 305 }; 306 #endif 307 /* Structure to hold configuration flags set by dm at dc creation. */ 308 struct dc_config { 309 bool gpu_vm_support; 310 bool disable_disp_pll_sharing; 311 bool fbc_support; 312 bool disable_fractional_pwm; 313 bool allow_seamless_boot_optimization; 314 bool power_down_display_on_boot; 315 bool edp_not_connected; 316 bool edp_no_power_sequencing; 317 bool force_enum_edp; 318 bool forced_clocks; 319 #if defined(CONFIG_DRM_AMD_DC_DCN) 320 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 321 #else 322 bool allow_lttpr_non_transparent_mode; 323 #endif 324 bool multi_mon_pp_mclk_switch; 325 bool disable_dmcu; 326 bool enable_4to1MPC; 327 bool enable_windowed_mpo_odm; 328 bool allow_edp_hotplug_detection; 329 #if defined(CONFIG_DRM_AMD_DC_DCN) 330 bool clamp_min_dcfclk; 331 #endif 332 uint64_t vblank_alignment_dto_params; 333 uint8_t vblank_alignment_max_frame_time_diff; 334 bool is_asymmetric_memory; 335 bool is_single_rank_dimm; 336 }; 337 338 enum visual_confirm { 339 VISUAL_CONFIRM_DISABLE = 0, 340 VISUAL_CONFIRM_SURFACE = 1, 341 VISUAL_CONFIRM_HDR = 2, 342 VISUAL_CONFIRM_MPCTREE = 4, 343 VISUAL_CONFIRM_PSR = 5, 344 VISUAL_CONFIRM_SWIZZLE = 9, 345 }; 346 347 enum dc_psr_power_opts { 348 psr_power_opt_invalid = 0x0, 349 psr_power_opt_smu_opt_static_screen = 0x1, 350 psr_power_opt_z10_static_screen = 0x10, 351 }; 352 353 enum dcc_option { 354 DCC_ENABLE = 0, 355 DCC_DISABLE = 1, 356 DCC_HALF_REQ_DISALBE = 2, 357 }; 358 359 enum pipe_split_policy { 360 MPC_SPLIT_DYNAMIC = 0, 361 MPC_SPLIT_AVOID = 1, 362 MPC_SPLIT_AVOID_MULT_DISP = 2, 363 }; 364 365 enum wm_report_mode { 366 WM_REPORT_DEFAULT = 0, 367 WM_REPORT_OVERRIDE = 1, 368 }; 369 enum dtm_pstate{ 370 dtm_level_p0 = 0,/*highest voltage*/ 371 dtm_level_p1, 372 dtm_level_p2, 373 dtm_level_p3, 374 dtm_level_p4,/*when active_display_count = 0*/ 375 }; 376 377 enum dcn_pwr_state { 378 DCN_PWR_STATE_UNKNOWN = -1, 379 DCN_PWR_STATE_MISSION_MODE = 0, 380 DCN_PWR_STATE_LOW_POWER = 3, 381 }; 382 383 #if defined(CONFIG_DRM_AMD_DC_DCN) 384 enum dcn_zstate_support_state { 385 DCN_ZSTATE_SUPPORT_UNKNOWN, 386 DCN_ZSTATE_SUPPORT_ALLOW, 387 DCN_ZSTATE_SUPPORT_DISALLOW, 388 }; 389 #endif 390 /* 391 * For any clocks that may differ per pipe 392 * only the max is stored in this structure 393 */ 394 struct dc_clocks { 395 int dispclk_khz; 396 int actual_dispclk_khz; 397 int dppclk_khz; 398 int actual_dppclk_khz; 399 int disp_dpp_voltage_level_khz; 400 int dcfclk_khz; 401 int socclk_khz; 402 int dcfclk_deep_sleep_khz; 403 int fclk_khz; 404 int phyclk_khz; 405 int dramclk_khz; 406 bool p_state_change_support; 407 #if defined(CONFIG_DRM_AMD_DC_DCN) 408 enum dcn_zstate_support_state zstate_support; 409 bool dtbclk_en; 410 #endif 411 enum dcn_pwr_state pwr_state; 412 /* 413 * Elements below are not compared for the purposes of 414 * optimization required 415 */ 416 bool prev_p_state_change_support; 417 enum dtm_pstate dtm_level; 418 int max_supported_dppclk_khz; 419 int max_supported_dispclk_khz; 420 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 421 int bw_dispclk_khz; 422 }; 423 424 struct dc_bw_validation_profile { 425 bool enable; 426 427 unsigned long long total_ticks; 428 unsigned long long voltage_level_ticks; 429 unsigned long long watermark_ticks; 430 unsigned long long rq_dlg_ticks; 431 432 unsigned long long total_count; 433 unsigned long long skip_fast_count; 434 unsigned long long skip_pass_count; 435 unsigned long long skip_fail_count; 436 }; 437 438 #define BW_VAL_TRACE_SETUP() \ 439 unsigned long long end_tick = 0; \ 440 unsigned long long voltage_level_tick = 0; \ 441 unsigned long long watermark_tick = 0; \ 442 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 443 dm_get_timestamp(dc->ctx) : 0 444 445 #define BW_VAL_TRACE_COUNT() \ 446 if (dc->debug.bw_val_profile.enable) \ 447 dc->debug.bw_val_profile.total_count++ 448 449 #define BW_VAL_TRACE_SKIP(status) \ 450 if (dc->debug.bw_val_profile.enable) { \ 451 if (!voltage_level_tick) \ 452 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 453 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 454 } 455 456 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 457 if (dc->debug.bw_val_profile.enable) \ 458 voltage_level_tick = dm_get_timestamp(dc->ctx) 459 460 #define BW_VAL_TRACE_END_WATERMARKS() \ 461 if (dc->debug.bw_val_profile.enable) \ 462 watermark_tick = dm_get_timestamp(dc->ctx) 463 464 #define BW_VAL_TRACE_FINISH() \ 465 if (dc->debug.bw_val_profile.enable) { \ 466 end_tick = dm_get_timestamp(dc->ctx); \ 467 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 468 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 469 if (watermark_tick) { \ 470 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 471 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 472 } \ 473 } 474 475 union mem_low_power_enable_options { 476 struct { 477 bool vga: 1; 478 bool i2c: 1; 479 bool dmcu: 1; 480 bool dscl: 1; 481 bool cm: 1; 482 bool mpc: 1; 483 bool optc: 1; 484 bool vpg: 1; 485 bool afmt: 1; 486 } bits; 487 uint32_t u32All; 488 }; 489 490 union root_clock_optimization_options { 491 struct { 492 bool dpp: 1; 493 bool dsc: 1; 494 bool hdmistream: 1; 495 bool hdmichar: 1; 496 bool dpstream: 1; 497 bool symclk32_se: 1; 498 bool symclk32_le: 1; 499 bool symclk_fe: 1; 500 bool physymclk: 1; 501 bool dpiasymclk: 1; 502 uint32_t reserved: 22; 503 } bits; 504 uint32_t u32All; 505 }; 506 507 union dpia_debug_options { 508 struct { 509 uint32_t disable_dpia:1; 510 uint32_t force_non_lttpr:1; 511 uint32_t extend_aux_rd_interval:1; 512 uint32_t disable_mst_dsc_work_around:1; 513 uint32_t reserved:28; 514 } bits; 515 uint32_t raw; 516 }; 517 518 struct dc_debug_data { 519 uint32_t ltFailCount; 520 uint32_t i2cErrorCount; 521 uint32_t auxErrorCount; 522 }; 523 524 struct dc_phy_addr_space_config { 525 struct { 526 uint64_t start_addr; 527 uint64_t end_addr; 528 uint64_t fb_top; 529 uint64_t fb_offset; 530 uint64_t fb_base; 531 uint64_t agp_top; 532 uint64_t agp_bot; 533 uint64_t agp_base; 534 } system_aperture; 535 536 struct { 537 uint64_t page_table_start_addr; 538 uint64_t page_table_end_addr; 539 uint64_t page_table_base_addr; 540 bool base_addr_is_mc_addr; 541 } gart_config; 542 543 bool valid; 544 bool is_hvm_enabled; 545 uint64_t page_table_default_page_addr; 546 }; 547 548 struct dc_virtual_addr_space_config { 549 uint64_t page_table_base_addr; 550 uint64_t page_table_start_addr; 551 uint64_t page_table_end_addr; 552 uint32_t page_table_block_size_in_bytes; 553 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 554 }; 555 556 struct dc_bounding_box_overrides { 557 int sr_exit_time_ns; 558 int sr_enter_plus_exit_time_ns; 559 int urgent_latency_ns; 560 int percent_of_ideal_drambw; 561 int dram_clock_change_latency_ns; 562 int dummy_clock_change_latency_ns; 563 /* This forces a hard min on the DCFCLK we use 564 * for DML. Unlike the debug option for forcing 565 * DCFCLK, this override affects watermark calculations 566 */ 567 int min_dcfclk_mhz; 568 }; 569 570 struct dc_state; 571 struct resource_pool; 572 struct dce_hwseq; 573 574 struct dc_debug_options { 575 bool native422_support; 576 bool disable_dsc; 577 enum visual_confirm visual_confirm; 578 int visual_confirm_rect_height; 579 580 bool sanity_checks; 581 bool max_disp_clk; 582 bool surface_trace; 583 bool timing_trace; 584 bool clock_trace; 585 bool validation_trace; 586 bool bandwidth_calcs_trace; 587 int max_downscale_src_width; 588 589 /* stutter efficiency related */ 590 bool disable_stutter; 591 bool use_max_lb; 592 enum dcc_option disable_dcc; 593 enum pipe_split_policy pipe_split_policy; 594 bool force_single_disp_pipe_split; 595 bool voltage_align_fclk; 596 bool disable_min_fclk; 597 598 bool disable_dfs_bypass; 599 bool disable_dpp_power_gate; 600 bool disable_hubp_power_gate; 601 bool disable_dsc_power_gate; 602 int dsc_min_slice_height_override; 603 int dsc_bpp_increment_div; 604 bool disable_pplib_wm_range; 605 enum wm_report_mode pplib_wm_report_mode; 606 unsigned int min_disp_clk_khz; 607 unsigned int min_dpp_clk_khz; 608 unsigned int min_dram_clk_khz; 609 int sr_exit_time_dpm0_ns; 610 int sr_enter_plus_exit_time_dpm0_ns; 611 int sr_exit_time_ns; 612 int sr_enter_plus_exit_time_ns; 613 int urgent_latency_ns; 614 uint32_t underflow_assert_delay_us; 615 int percent_of_ideal_drambw; 616 int dram_clock_change_latency_ns; 617 bool optimized_watermark; 618 int always_scale; 619 bool disable_pplib_clock_request; 620 bool disable_clock_gate; 621 bool disable_mem_low_power; 622 #if defined(CONFIG_DRM_AMD_DC_DCN) 623 bool pstate_enabled; 624 #endif 625 bool disable_dmcu; 626 bool disable_psr; 627 bool force_abm_enable; 628 bool disable_stereo_support; 629 bool vsr_support; 630 bool performance_trace; 631 bool az_endpoint_mute_only; 632 bool always_use_regamma; 633 bool recovery_enabled; 634 bool avoid_vbios_exec_table; 635 bool scl_reset_length10; 636 bool hdmi20_disable; 637 bool skip_detection_link_training; 638 uint32_t edid_read_retry_times; 639 bool remove_disconnect_edp; 640 unsigned int force_odm_combine; //bit vector based on otg inst 641 #if defined(CONFIG_DRM_AMD_DC_DCN) 642 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 643 bool disable_z9_mpc; 644 #endif 645 unsigned int force_fclk_khz; 646 bool enable_tri_buf; 647 bool dmub_offload_enabled; 648 bool dmcub_emulation; 649 #if defined(CONFIG_DRM_AMD_DC_DCN) 650 bool disable_idle_power_optimizations; 651 unsigned int mall_size_override; 652 unsigned int mall_additional_timer_percent; 653 bool mall_error_as_fatal; 654 #endif 655 bool dmub_command_table; /* for testing only */ 656 struct dc_bw_validation_profile bw_val_profile; 657 bool disable_fec; 658 bool disable_48mhz_pwrdwn; 659 /* This forces a hard min on the DCFCLK requested to SMU/PP 660 * watermarks are not affected. 661 */ 662 unsigned int force_min_dcfclk_mhz; 663 #if defined(CONFIG_DRM_AMD_DC_DCN) 664 int dwb_fi_phase; 665 #endif 666 bool disable_timing_sync; 667 bool cm_in_bypass; 668 int force_clock_mode;/*every mode change.*/ 669 670 bool disable_dram_clock_change_vactive_support; 671 bool validate_dml_output; 672 bool enable_dmcub_surface_flip; 673 bool usbc_combo_phy_reset_wa; 674 bool disable_dsc_edp; 675 unsigned int force_dsc_edp_policy; 676 bool enable_dram_clock_change_one_display_vactive; 677 #if defined(CONFIG_DRM_AMD_DC_DCN) 678 /* TODO - remove once tested */ 679 bool legacy_dp2_lt; 680 bool set_mst_en_for_sst; 681 #endif 682 union mem_low_power_enable_options enable_mem_low_power; 683 union root_clock_optimization_options root_clock_optimization; 684 bool hpo_optimization; 685 bool force_vblank_alignment; 686 687 /* Enable dmub aux for legacy ddc */ 688 bool enable_dmub_aux_for_legacy_ddc; 689 bool optimize_edp_link_rate; /* eDP ILR */ 690 /* FEC/PSR1 sequence enable delay in 100us */ 691 uint8_t fec_enable_delay_in100us; 692 bool enable_driver_sequence_debug; 693 #if defined(CONFIG_DRM_AMD_DC_DCN) 694 bool disable_z10; 695 bool enable_sw_cntl_psr; 696 union dpia_debug_options dpia_debug; 697 #endif 698 }; 699 700 struct gpu_info_soc_bounding_box_v1_0; 701 struct dc { 702 struct dc_debug_options debug; 703 struct dc_versions versions; 704 struct dc_caps caps; 705 struct dc_cap_funcs cap_funcs; 706 struct dc_config config; 707 struct dc_bounding_box_overrides bb_overrides; 708 struct dc_bug_wa work_arounds; 709 struct dc_context *ctx; 710 struct dc_phy_addr_space_config vm_pa_config; 711 712 uint8_t link_count; 713 struct dc_link *links[MAX_PIPES * 2]; 714 715 struct dc_state *current_state; 716 struct resource_pool *res_pool; 717 718 struct clk_mgr *clk_mgr; 719 720 /* Display Engine Clock levels */ 721 struct dm_pp_clock_levels sclk_lvls; 722 723 /* Inputs into BW and WM calculations. */ 724 struct bw_calcs_dceip *bw_dceip; 725 struct bw_calcs_vbios *bw_vbios; 726 #ifdef CONFIG_DRM_AMD_DC_DCN 727 struct dcn_soc_bounding_box *dcn_soc; 728 struct dcn_ip_params *dcn_ip; 729 struct display_mode_lib dml; 730 #endif 731 732 /* HW functions */ 733 struct hw_sequencer_funcs hwss; 734 struct dce_hwseq *hwseq; 735 736 /* Require to optimize clocks and bandwidth for added/removed planes */ 737 bool optimized_required; 738 bool wm_optimized_required; 739 #if defined(CONFIG_DRM_AMD_DC_DCN) 740 bool idle_optimizations_allowed; 741 #endif 742 #if defined(CONFIG_DRM_AMD_DC_DCN) 743 bool enable_c20_dtm_b0; 744 #endif 745 746 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 747 748 /* FBC compressor */ 749 struct compressor *fbc_compressor; 750 751 struct dc_debug_data debug_data; 752 struct dpcd_vendor_signature vendor_signature; 753 754 const char *build_id; 755 struct vm_helper *vm_helper; 756 }; 757 758 enum frame_buffer_mode { 759 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 760 FRAME_BUFFER_MODE_ZFB_ONLY, 761 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 762 } ; 763 764 struct dchub_init_data { 765 int64_t zfb_phys_addr_base; 766 int64_t zfb_mc_base_addr; 767 uint64_t zfb_size_in_byte; 768 enum frame_buffer_mode fb_mode; 769 bool dchub_initialzied; 770 bool dchub_info_valid; 771 }; 772 773 struct dc_init_data { 774 struct hw_asic_id asic_id; 775 void *driver; /* ctx */ 776 struct cgs_device *cgs_device; 777 struct dc_bounding_box_overrides bb_overrides; 778 779 int num_virtual_links; 780 /* 781 * If 'vbios_override' not NULL, it will be called instead 782 * of the real VBIOS. Intended use is Diagnostics on FPGA. 783 */ 784 struct dc_bios *vbios_override; 785 enum dce_environment dce_environment; 786 787 struct dmub_offload_funcs *dmub_if; 788 struct dc_reg_helper_state *dmub_offload; 789 790 struct dc_config flags; 791 uint64_t log_mask; 792 793 struct dpcd_vendor_signature vendor_signature; 794 #if defined(CONFIG_DRM_AMD_DC_DCN) 795 bool force_smu_not_present; 796 #endif 797 }; 798 799 struct dc_callback_init { 800 #ifdef CONFIG_DRM_AMD_DC_HDCP 801 struct cp_psp cp_psp; 802 #else 803 uint8_t reserved; 804 #endif 805 }; 806 807 struct dc *dc_create(const struct dc_init_data *init_params); 808 void dc_hardware_init(struct dc *dc); 809 810 int dc_get_vmid_use_vector(struct dc *dc); 811 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 812 /* Returns the number of vmids supported */ 813 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 814 void dc_init_callbacks(struct dc *dc, 815 const struct dc_callback_init *init_params); 816 void dc_deinit_callbacks(struct dc *dc); 817 void dc_destroy(struct dc **dc); 818 819 /******************************************************************************* 820 * Surface Interfaces 821 ******************************************************************************/ 822 823 enum { 824 TRANSFER_FUNC_POINTS = 1025 825 }; 826 827 struct dc_hdr_static_metadata { 828 /* display chromaticities and white point in units of 0.00001 */ 829 unsigned int chromaticity_green_x; 830 unsigned int chromaticity_green_y; 831 unsigned int chromaticity_blue_x; 832 unsigned int chromaticity_blue_y; 833 unsigned int chromaticity_red_x; 834 unsigned int chromaticity_red_y; 835 unsigned int chromaticity_white_point_x; 836 unsigned int chromaticity_white_point_y; 837 838 uint32_t min_luminance; 839 uint32_t max_luminance; 840 uint32_t maximum_content_light_level; 841 uint32_t maximum_frame_average_light_level; 842 }; 843 844 enum dc_transfer_func_type { 845 TF_TYPE_PREDEFINED, 846 TF_TYPE_DISTRIBUTED_POINTS, 847 TF_TYPE_BYPASS, 848 TF_TYPE_HWPWL 849 }; 850 851 struct dc_transfer_func_distributed_points { 852 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 853 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 854 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 855 856 uint16_t end_exponent; 857 uint16_t x_point_at_y1_red; 858 uint16_t x_point_at_y1_green; 859 uint16_t x_point_at_y1_blue; 860 }; 861 862 enum dc_transfer_func_predefined { 863 TRANSFER_FUNCTION_SRGB, 864 TRANSFER_FUNCTION_BT709, 865 TRANSFER_FUNCTION_PQ, 866 TRANSFER_FUNCTION_LINEAR, 867 TRANSFER_FUNCTION_UNITY, 868 TRANSFER_FUNCTION_HLG, 869 TRANSFER_FUNCTION_HLG12, 870 TRANSFER_FUNCTION_GAMMA22, 871 TRANSFER_FUNCTION_GAMMA24, 872 TRANSFER_FUNCTION_GAMMA26 873 }; 874 875 876 struct dc_transfer_func { 877 struct kref refcount; 878 enum dc_transfer_func_type type; 879 enum dc_transfer_func_predefined tf; 880 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 881 uint32_t sdr_ref_white_level; 882 union { 883 struct pwl_params pwl; 884 struct dc_transfer_func_distributed_points tf_pts; 885 }; 886 }; 887 888 889 union dc_3dlut_state { 890 struct { 891 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 892 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 893 uint32_t rmu_mux_num:3; /*index of mux to use*/ 894 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 895 uint32_t mpc_rmu1_mux:4; 896 uint32_t mpc_rmu2_mux:4; 897 uint32_t reserved:15; 898 } bits; 899 uint32_t raw; 900 }; 901 902 903 struct dc_3dlut { 904 struct kref refcount; 905 struct tetrahedral_params lut_3d; 906 struct fixed31_32 hdr_multiplier; 907 union dc_3dlut_state state; 908 }; 909 /* 910 * This structure is filled in by dc_surface_get_status and contains 911 * the last requested address and the currently active address so the called 912 * can determine if there are any outstanding flips 913 */ 914 struct dc_plane_status { 915 struct dc_plane_address requested_address; 916 struct dc_plane_address current_address; 917 bool is_flip_pending; 918 bool is_right_eye; 919 }; 920 921 union surface_update_flags { 922 923 struct { 924 uint32_t addr_update:1; 925 /* Medium updates */ 926 uint32_t dcc_change:1; 927 uint32_t color_space_change:1; 928 uint32_t horizontal_mirror_change:1; 929 uint32_t per_pixel_alpha_change:1; 930 uint32_t global_alpha_change:1; 931 uint32_t hdr_mult:1; 932 uint32_t rotation_change:1; 933 uint32_t swizzle_change:1; 934 uint32_t scaling_change:1; 935 uint32_t position_change:1; 936 uint32_t in_transfer_func_change:1; 937 uint32_t input_csc_change:1; 938 uint32_t coeff_reduction_change:1; 939 uint32_t output_tf_change:1; 940 uint32_t pixel_format_change:1; 941 uint32_t plane_size_change:1; 942 uint32_t gamut_remap_change:1; 943 944 /* Full updates */ 945 uint32_t new_plane:1; 946 uint32_t bpp_change:1; 947 uint32_t gamma_change:1; 948 uint32_t bandwidth_change:1; 949 uint32_t clock_change:1; 950 uint32_t stereo_format_change:1; 951 uint32_t lut_3d:1; 952 uint32_t full_update:1; 953 } bits; 954 955 uint32_t raw; 956 }; 957 958 struct dc_plane_state { 959 struct dc_plane_address address; 960 struct dc_plane_flip_time time; 961 bool triplebuffer_flips; 962 struct scaling_taps scaling_quality; 963 struct rect src_rect; 964 struct rect dst_rect; 965 struct rect clip_rect; 966 967 struct plane_size plane_size; 968 union dc_tiling_info tiling_info; 969 970 struct dc_plane_dcc_param dcc; 971 972 struct dc_gamma *gamma_correction; 973 struct dc_transfer_func *in_transfer_func; 974 struct dc_bias_and_scale *bias_and_scale; 975 struct dc_csc_transform input_csc_color_matrix; 976 struct fixed31_32 coeff_reduction_factor; 977 struct fixed31_32 hdr_mult; 978 struct colorspace_transform gamut_remap_matrix; 979 980 // TODO: No longer used, remove 981 struct dc_hdr_static_metadata hdr_static_ctx; 982 983 enum dc_color_space color_space; 984 985 struct dc_3dlut *lut3d_func; 986 struct dc_transfer_func *in_shaper_func; 987 struct dc_transfer_func *blend_tf; 988 989 #if defined(CONFIG_DRM_AMD_DC_DCN) 990 struct dc_transfer_func *gamcor_tf; 991 #endif 992 enum surface_pixel_format format; 993 enum dc_rotation_angle rotation; 994 enum plane_stereo_format stereo_format; 995 996 bool is_tiling_rotated; 997 bool per_pixel_alpha; 998 bool global_alpha; 999 int global_alpha_value; 1000 bool visible; 1001 bool flip_immediate; 1002 bool horizontal_mirror; 1003 int layer_index; 1004 1005 union surface_update_flags update_flags; 1006 bool flip_int_enabled; 1007 bool skip_manual_trigger; 1008 1009 /* private to DC core */ 1010 struct dc_plane_status status; 1011 struct dc_context *ctx; 1012 1013 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1014 bool force_full_update; 1015 1016 /* private to dc_surface.c */ 1017 enum dc_irq_source irq_source; 1018 struct kref refcount; 1019 }; 1020 1021 struct dc_plane_info { 1022 struct plane_size plane_size; 1023 union dc_tiling_info tiling_info; 1024 struct dc_plane_dcc_param dcc; 1025 enum surface_pixel_format format; 1026 enum dc_rotation_angle rotation; 1027 enum plane_stereo_format stereo_format; 1028 enum dc_color_space color_space; 1029 bool horizontal_mirror; 1030 bool visible; 1031 bool per_pixel_alpha; 1032 bool global_alpha; 1033 int global_alpha_value; 1034 bool input_csc_enabled; 1035 int layer_index; 1036 }; 1037 1038 struct dc_scaling_info { 1039 struct rect src_rect; 1040 struct rect dst_rect; 1041 struct rect clip_rect; 1042 struct scaling_taps scaling_quality; 1043 }; 1044 1045 struct dc_surface_update { 1046 struct dc_plane_state *surface; 1047 1048 /* isr safe update parameters. null means no updates */ 1049 const struct dc_flip_addrs *flip_addr; 1050 const struct dc_plane_info *plane_info; 1051 const struct dc_scaling_info *scaling_info; 1052 struct fixed31_32 hdr_mult; 1053 /* following updates require alloc/sleep/spin that is not isr safe, 1054 * null means no updates 1055 */ 1056 const struct dc_gamma *gamma; 1057 const struct dc_transfer_func *in_transfer_func; 1058 1059 const struct dc_csc_transform *input_csc_color_matrix; 1060 const struct fixed31_32 *coeff_reduction_factor; 1061 const struct dc_transfer_func *func_shaper; 1062 const struct dc_3dlut *lut3d_func; 1063 const struct dc_transfer_func *blend_tf; 1064 const struct colorspace_transform *gamut_remap_matrix; 1065 }; 1066 1067 /* 1068 * Create a new surface with default parameters; 1069 */ 1070 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1071 const struct dc_plane_status *dc_plane_get_status( 1072 const struct dc_plane_state *plane_state); 1073 1074 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1075 void dc_plane_state_release(struct dc_plane_state *plane_state); 1076 1077 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1078 void dc_gamma_release(struct dc_gamma **dc_gamma); 1079 struct dc_gamma *dc_create_gamma(void); 1080 1081 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1082 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1083 struct dc_transfer_func *dc_create_transfer_func(void); 1084 1085 struct dc_3dlut *dc_create_3dlut_func(void); 1086 void dc_3dlut_func_release(struct dc_3dlut *lut); 1087 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1088 /* 1089 * This structure holds a surface address. There could be multiple addresses 1090 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1091 * as frame durations and DCC format can also be set. 1092 */ 1093 struct dc_flip_addrs { 1094 struct dc_plane_address address; 1095 unsigned int flip_timestamp_in_us; 1096 bool flip_immediate; 1097 /* TODO: add flip duration for FreeSync */ 1098 bool triplebuffer_flips; 1099 }; 1100 1101 void dc_post_update_surfaces_to_stream( 1102 struct dc *dc); 1103 1104 #include "dc_stream.h" 1105 1106 /* 1107 * Structure to store surface/stream associations for validation 1108 */ 1109 struct dc_validation_set { 1110 struct dc_stream_state *stream; 1111 struct dc_plane_state *plane_states[MAX_SURFACES]; 1112 uint8_t plane_count; 1113 }; 1114 1115 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1116 const struct dc_sink *sink, 1117 struct dc_crtc_timing *crtc_timing); 1118 1119 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1120 1121 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1122 1123 bool dc_set_generic_gpio_for_stereo(bool enable, 1124 struct gpio_service *gpio_service); 1125 1126 /* 1127 * fast_validate: we return after determining if we can support the new state, 1128 * but before we populate the programming info 1129 */ 1130 enum dc_status dc_validate_global_state( 1131 struct dc *dc, 1132 struct dc_state *new_ctx, 1133 bool fast_validate); 1134 1135 1136 void dc_resource_state_construct( 1137 const struct dc *dc, 1138 struct dc_state *dst_ctx); 1139 1140 #if defined(CONFIG_DRM_AMD_DC_DCN) 1141 bool dc_acquire_release_mpc_3dlut( 1142 struct dc *dc, bool acquire, 1143 struct dc_stream_state *stream, 1144 struct dc_3dlut **lut, 1145 struct dc_transfer_func **shaper); 1146 #endif 1147 1148 void dc_resource_state_copy_construct( 1149 const struct dc_state *src_ctx, 1150 struct dc_state *dst_ctx); 1151 1152 void dc_resource_state_copy_construct_current( 1153 const struct dc *dc, 1154 struct dc_state *dst_ctx); 1155 1156 void dc_resource_state_destruct(struct dc_state *context); 1157 1158 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1159 1160 /* 1161 * TODO update to make it about validation sets 1162 * Set up streams and links associated to drive sinks 1163 * The streams parameter is an absolute set of all active streams. 1164 * 1165 * After this call: 1166 * Phy, Encoder, Timing Generator are programmed and enabled. 1167 * New streams are enabled with blank stream; no memory read. 1168 */ 1169 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1170 1171 struct dc_state *dc_create_state(struct dc *dc); 1172 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1173 void dc_retain_state(struct dc_state *context); 1174 void dc_release_state(struct dc_state *context); 1175 1176 /******************************************************************************* 1177 * Link Interfaces 1178 ******************************************************************************/ 1179 1180 struct dpcd_caps { 1181 union dpcd_rev dpcd_rev; 1182 union max_lane_count max_ln_count; 1183 union max_down_spread max_down_spread; 1184 union dprx_feature dprx_feature; 1185 1186 /* valid only for eDP v1.4 or higher*/ 1187 uint8_t edp_supported_link_rates_count; 1188 enum dc_link_rate edp_supported_link_rates[8]; 1189 1190 /* dongle type (DP converter, CV smart dongle) */ 1191 enum display_dongle_type dongle_type; 1192 /* branch device or sink device */ 1193 bool is_branch_dev; 1194 /* Dongle's downstream count. */ 1195 union sink_count sink_count; 1196 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1197 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1198 struct dc_dongle_caps dongle_caps; 1199 1200 uint32_t sink_dev_id; 1201 int8_t sink_dev_id_str[6]; 1202 int8_t sink_hw_revision; 1203 int8_t sink_fw_revision[2]; 1204 1205 uint32_t branch_dev_id; 1206 int8_t branch_dev_name[6]; 1207 int8_t branch_hw_revision; 1208 int8_t branch_fw_revision[2]; 1209 1210 bool allow_invalid_MSA_timing_param; 1211 bool panel_mode_edp; 1212 bool dpcd_display_control_capable; 1213 bool ext_receiver_cap_field_present; 1214 bool dynamic_backlight_capable_edp; 1215 union dpcd_fec_capability fec_cap; 1216 struct dpcd_dsc_capabilities dsc_caps; 1217 struct dc_lttpr_caps lttpr_caps; 1218 struct psr_caps psr_caps; 1219 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1220 1221 #if defined(CONFIG_DRM_AMD_DC_DCN) 1222 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1223 union dp_main_line_channel_coding_cap channel_coding_cap; 1224 union dp_sink_video_fallback_formats fallback_formats; 1225 union dp_fec_capability1 fec_cap1; 1226 #endif 1227 }; 1228 1229 union dpcd_sink_ext_caps { 1230 struct { 1231 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1232 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1233 */ 1234 uint8_t sdr_aux_backlight_control : 1; 1235 uint8_t hdr_aux_backlight_control : 1; 1236 uint8_t reserved_1 : 2; 1237 uint8_t oled : 1; 1238 uint8_t reserved : 3; 1239 } bits; 1240 uint8_t raw; 1241 }; 1242 1243 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1244 union hdcp_rx_caps { 1245 struct { 1246 uint8_t version; 1247 uint8_t reserved; 1248 struct { 1249 uint8_t repeater : 1; 1250 uint8_t hdcp_capable : 1; 1251 uint8_t reserved : 6; 1252 } byte0; 1253 } fields; 1254 uint8_t raw[3]; 1255 }; 1256 1257 union hdcp_bcaps { 1258 struct { 1259 uint8_t HDCP_CAPABLE:1; 1260 uint8_t REPEATER:1; 1261 uint8_t RESERVED:6; 1262 } bits; 1263 uint8_t raw; 1264 }; 1265 1266 struct hdcp_caps { 1267 union hdcp_rx_caps rx_caps; 1268 union hdcp_bcaps bcaps; 1269 }; 1270 #endif 1271 1272 #include "dc_link.h" 1273 1274 #if defined(CONFIG_DRM_AMD_DC_DCN) 1275 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1276 1277 #endif 1278 /******************************************************************************* 1279 * Sink Interfaces - A sink corresponds to a display output device 1280 ******************************************************************************/ 1281 1282 struct dc_container_id { 1283 // 128bit GUID in binary form 1284 unsigned char guid[16]; 1285 // 8 byte port ID -> ELD.PortID 1286 unsigned int portId[2]; 1287 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1288 unsigned short manufacturerName; 1289 // 2 byte product code -> ELD.ProductCode 1290 unsigned short productCode; 1291 }; 1292 1293 1294 struct dc_sink_dsc_caps { 1295 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1296 // 'false' if they are sink's DSC caps 1297 bool is_virtual_dpcd_dsc; 1298 struct dsc_dec_dpcd_caps dsc_dec_caps; 1299 }; 1300 1301 struct dc_sink_fec_caps { 1302 bool is_rx_fec_supported; 1303 bool is_topology_fec_supported; 1304 }; 1305 1306 /* 1307 * The sink structure contains EDID and other display device properties 1308 */ 1309 struct dc_sink { 1310 enum signal_type sink_signal; 1311 struct dc_edid dc_edid; /* raw edid */ 1312 struct dc_edid_caps edid_caps; /* parse display caps */ 1313 struct dc_container_id *dc_container_id; 1314 uint32_t dongle_max_pix_clk; 1315 void *priv; 1316 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1317 bool converter_disable_audio; 1318 1319 struct dc_sink_dsc_caps dsc_caps; 1320 struct dc_sink_fec_caps fec_caps; 1321 1322 bool is_vsc_sdp_colorimetry_supported; 1323 1324 /* private to DC core */ 1325 struct dc_link *link; 1326 struct dc_context *ctx; 1327 1328 uint32_t sink_id; 1329 1330 /* private to dc_sink.c */ 1331 // refcount must be the last member in dc_sink, since we want the 1332 // sink structure to be logically cloneable up to (but not including) 1333 // refcount 1334 struct kref refcount; 1335 }; 1336 1337 void dc_sink_retain(struct dc_sink *sink); 1338 void dc_sink_release(struct dc_sink *sink); 1339 1340 struct dc_sink_init_data { 1341 enum signal_type sink_signal; 1342 struct dc_link *link; 1343 uint32_t dongle_max_pix_clk; 1344 bool converter_disable_audio; 1345 }; 1346 1347 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1348 1349 /* Newer interfaces */ 1350 struct dc_cursor { 1351 struct dc_plane_address address; 1352 struct dc_cursor_attributes attributes; 1353 }; 1354 1355 1356 /******************************************************************************* 1357 * Interrupt interfaces 1358 ******************************************************************************/ 1359 enum dc_irq_source dc_interrupt_to_irq_source( 1360 struct dc *dc, 1361 uint32_t src_id, 1362 uint32_t ext_id); 1363 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1364 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1365 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1366 struct dc *dc, uint32_t link_index); 1367 1368 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1369 1370 /******************************************************************************* 1371 * Power Interfaces 1372 ******************************************************************************/ 1373 1374 void dc_set_power_state( 1375 struct dc *dc, 1376 enum dc_acpi_cm_power_state power_state); 1377 void dc_resume(struct dc *dc); 1378 1379 void dc_power_down_on_boot(struct dc *dc); 1380 1381 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1382 /* 1383 * HDCP Interfaces 1384 */ 1385 enum hdcp_message_status dc_process_hdcp_msg( 1386 enum signal_type signal, 1387 struct dc_link *link, 1388 struct hdcp_protection_message *message_info); 1389 #endif 1390 bool dc_is_dmcu_initialized(struct dc *dc); 1391 1392 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1393 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1394 #if defined(CONFIG_DRM_AMD_DC_DCN) 1395 1396 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1397 struct dc_cursor_attributes *cursor_attr); 1398 1399 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1400 1401 /* 1402 * blank all streams, and set min and max memory clock to 1403 * lowest and highest DPM level, respectively 1404 */ 1405 void dc_unlock_memory_clock_frequency(struct dc *dc); 1406 1407 /* 1408 * set min memory clock to the min required for current mode, 1409 * max to maxDPM, and unblank streams 1410 */ 1411 void dc_lock_memory_clock_frequency(struct dc *dc); 1412 1413 /* cleanup on driver unload */ 1414 void dc_hardware_release(struct dc *dc); 1415 1416 #endif 1417 1418 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1419 #if defined(CONFIG_DRM_AMD_DC_DCN) 1420 void dc_z10_restore(const struct dc *dc); 1421 void dc_z10_save_init(struct dc *dc); 1422 #endif 1423 1424 bool dc_enable_dmub_notifications(struct dc *dc); 1425 1426 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1427 uint32_t link_index, 1428 struct aux_payload *payload); 1429 1430 /* Get dc link index from dpia port index */ 1431 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1432 uint8_t dpia_port_index); 1433 1434 bool dc_process_dmub_set_config_async(struct dc *dc, 1435 uint32_t link_index, 1436 struct set_config_cmd_payload *payload, 1437 struct dmub_notification *notify); 1438 1439 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1440 uint32_t link_index, 1441 uint8_t mst_alloc_slots, 1442 uint8_t *mst_slots_in_use); 1443 1444 /******************************************************************************* 1445 * DSC Interfaces 1446 ******************************************************************************/ 1447 #include "dc_dsc.h" 1448 1449 /******************************************************************************* 1450 * Disable acc mode Interfaces 1451 ******************************************************************************/ 1452 void dc_disable_accelerated_mode(struct dc *dc); 1453 1454 #endif /* DC_INTERFACE_H_ */ 1455