1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.124" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 56 /******************************************************************************* 57 * Display Core Interfaces 58 ******************************************************************************/ 59 struct dc_versions { 60 const char *dc_ver; 61 struct dmcu_version dmcu_version; 62 }; 63 64 enum dp_protocol_version { 65 DP_VERSION_1_4, 66 }; 67 68 enum dc_plane_type { 69 DC_PLANE_TYPE_INVALID, 70 DC_PLANE_TYPE_DCE_RGB, 71 DC_PLANE_TYPE_DCE_UNDERLAY, 72 DC_PLANE_TYPE_DCN_UNIVERSAL, 73 }; 74 75 struct dc_plane_cap { 76 enum dc_plane_type type; 77 uint32_t blends_with_above : 1; 78 uint32_t blends_with_below : 1; 79 uint32_t per_pixel_alpha : 1; 80 struct { 81 uint32_t argb8888 : 1; 82 uint32_t nv12 : 1; 83 uint32_t fp16 : 1; 84 uint32_t p010 : 1; 85 uint32_t ayuv : 1; 86 } pixel_format_support; 87 // max upscaling factor x1000 88 // upscaling factors are always >= 1 89 // for example, 1080p -> 8K is 4.0, or 4000 raw value 90 struct { 91 uint32_t argb8888; 92 uint32_t nv12; 93 uint32_t fp16; 94 } max_upscale_factor; 95 // max downscale factor x1000 96 // downscale factors are always <= 1 97 // for example, 8K -> 1080p is 0.25, or 250 raw value 98 struct { 99 uint32_t argb8888; 100 uint32_t nv12; 101 uint32_t fp16; 102 } max_downscale_factor; 103 // minimal width/height 104 uint32_t min_width; 105 uint32_t min_height; 106 }; 107 108 // Color management caps (DPP and MPC) 109 struct rom_curve_caps { 110 uint16_t srgb : 1; 111 uint16_t bt2020 : 1; 112 uint16_t gamma2_2 : 1; 113 uint16_t pq : 1; 114 uint16_t hlg : 1; 115 }; 116 117 struct dpp_color_caps { 118 uint16_t dcn_arch : 1; // all DCE generations treated the same 119 // input lut is different than most LUTs, just plain 256-entry lookup 120 uint16_t input_lut_shared : 1; // shared with DGAM 121 uint16_t icsc : 1; 122 uint16_t dgam_ram : 1; 123 uint16_t post_csc : 1; // before gamut remap 124 uint16_t gamma_corr : 1; 125 126 // hdr_mult and gamut remap always available in DPP (in that order) 127 // 3d lut implies shaper LUT, 128 // it may be shared with MPC - check MPC:shared_3d_lut flag 129 uint16_t hw_3d_lut : 1; 130 uint16_t ogam_ram : 1; // blnd gam 131 uint16_t ocsc : 1; 132 uint16_t dgam_rom_for_yuv : 1; 133 struct rom_curve_caps dgam_rom_caps; 134 struct rom_curve_caps ogam_rom_caps; 135 }; 136 137 struct mpc_color_caps { 138 uint16_t gamut_remap : 1; 139 uint16_t ogam_ram : 1; 140 uint16_t ocsc : 1; 141 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 142 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 143 144 struct rom_curve_caps ogam_rom_caps; 145 }; 146 147 struct dc_color_caps { 148 struct dpp_color_caps dpp; 149 struct mpc_color_caps mpc; 150 }; 151 152 struct dc_caps { 153 uint32_t max_streams; 154 uint32_t max_links; 155 uint32_t max_audios; 156 uint32_t max_slave_planes; 157 uint32_t max_planes; 158 uint32_t max_downscale_ratio; 159 uint32_t i2c_speed_in_khz; 160 uint32_t i2c_speed_in_khz_hdcp; 161 uint32_t dmdata_alloc_size; 162 unsigned int max_cursor_size; 163 unsigned int max_video_width; 164 unsigned int min_horizontal_blanking_period; 165 int linear_pitch_alignment; 166 bool dcc_const_color; 167 bool dynamic_audio; 168 bool is_apu; 169 bool dual_link_dvi; 170 bool post_blend_color_processing; 171 bool force_dp_tps4_for_cp2520; 172 bool disable_dp_clk_share; 173 bool psp_setup_panel_mode; 174 bool extended_aux_timeout_support; 175 bool dmcub_support; 176 uint32_t num_of_internal_disp; 177 enum dp_protocol_version max_dp_protocol_version; 178 unsigned int mall_size_per_mem_channel; 179 unsigned int mall_size_total; 180 unsigned int cursor_cache_size; 181 struct dc_plane_cap planes[MAX_PLANES]; 182 struct dc_color_caps color; 183 }; 184 185 struct dc_bug_wa { 186 bool no_connect_phy_config; 187 bool dedcn20_305_wa; 188 bool skip_clock_update; 189 bool lt_early_cr_pattern; 190 }; 191 192 struct dc_dcc_surface_param { 193 struct dc_size surface_size; 194 enum surface_pixel_format format; 195 enum swizzle_mode_values swizzle_mode; 196 enum dc_scan_direction scan; 197 }; 198 199 struct dc_dcc_setting { 200 unsigned int max_compressed_blk_size; 201 unsigned int max_uncompressed_blk_size; 202 bool independent_64b_blks; 203 #if defined(CONFIG_DRM_AMD_DC_DCN) 204 //These bitfields to be used starting with DCN 3.0 205 struct { 206 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 207 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 208 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 209 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 210 } dcc_controls; 211 #endif 212 }; 213 214 struct dc_surface_dcc_cap { 215 union { 216 struct { 217 struct dc_dcc_setting rgb; 218 } grph; 219 220 struct { 221 struct dc_dcc_setting luma; 222 struct dc_dcc_setting chroma; 223 } video; 224 }; 225 226 bool capable; 227 bool const_color_support; 228 }; 229 230 struct dc_static_screen_params { 231 struct { 232 bool force_trigger; 233 bool cursor_update; 234 bool surface_update; 235 bool overlay_update; 236 } triggers; 237 unsigned int num_frames; 238 }; 239 240 241 /* Surface update type is used by dc_update_surfaces_and_stream 242 * The update type is determined at the very beginning of the function based 243 * on parameters passed in and decides how much programming (or updating) is 244 * going to be done during the call. 245 * 246 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 247 * logical calculations or hardware register programming. This update MUST be 248 * ISR safe on windows. Currently fast update will only be used to flip surface 249 * address. 250 * 251 * UPDATE_TYPE_MED is used for slower updates which require significant hw 252 * re-programming however do not affect bandwidth consumption or clock 253 * requirements. At present, this is the level at which front end updates 254 * that do not require us to run bw_calcs happen. These are in/out transfer func 255 * updates, viewport offset changes, recout size changes and pixel depth changes. 256 * This update can be done at ISR, but we want to minimize how often this happens. 257 * 258 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 259 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 260 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 261 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 262 * a full update. This cannot be done at ISR level and should be a rare event. 263 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 264 * underscan we don't expect to see this call at all. 265 */ 266 267 enum surface_update_type { 268 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 269 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 270 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 271 }; 272 273 /* Forward declaration*/ 274 struct dc; 275 struct dc_plane_state; 276 struct dc_state; 277 278 279 struct dc_cap_funcs { 280 bool (*get_dcc_compression_cap)(const struct dc *dc, 281 const struct dc_dcc_surface_param *input, 282 struct dc_surface_dcc_cap *output); 283 }; 284 285 struct link_training_settings; 286 287 288 /* Structure to hold configuration flags set by dm at dc creation. */ 289 struct dc_config { 290 bool gpu_vm_support; 291 bool disable_disp_pll_sharing; 292 bool fbc_support; 293 bool optimize_edp_link_rate; 294 bool disable_fractional_pwm; 295 bool allow_seamless_boot_optimization; 296 bool power_down_display_on_boot; 297 bool edp_not_connected; 298 bool force_enum_edp; 299 bool forced_clocks; 300 bool allow_lttpr_non_transparent_mode; 301 bool multi_mon_pp_mclk_switch; 302 bool disable_dmcu; 303 bool enable_4to1MPC; 304 #if defined(CONFIG_DRM_AMD_DC_DCN) 305 bool clamp_min_dcfclk; 306 #endif 307 uint64_t vblank_alignment_dto_params; 308 uint8_t vblank_alignment_max_frame_time_diff; 309 }; 310 311 enum visual_confirm { 312 VISUAL_CONFIRM_DISABLE = 0, 313 VISUAL_CONFIRM_SURFACE = 1, 314 VISUAL_CONFIRM_HDR = 2, 315 VISUAL_CONFIRM_MPCTREE = 4, 316 VISUAL_CONFIRM_PSR = 5, 317 }; 318 319 enum dcc_option { 320 DCC_ENABLE = 0, 321 DCC_DISABLE = 1, 322 DCC_HALF_REQ_DISALBE = 2, 323 }; 324 325 enum pipe_split_policy { 326 MPC_SPLIT_DYNAMIC = 0, 327 MPC_SPLIT_AVOID = 1, 328 MPC_SPLIT_AVOID_MULT_DISP = 2, 329 }; 330 331 enum wm_report_mode { 332 WM_REPORT_DEFAULT = 0, 333 WM_REPORT_OVERRIDE = 1, 334 }; 335 enum dtm_pstate{ 336 dtm_level_p0 = 0,/*highest voltage*/ 337 dtm_level_p1, 338 dtm_level_p2, 339 dtm_level_p3, 340 dtm_level_p4,/*when active_display_count = 0*/ 341 }; 342 343 enum dcn_pwr_state { 344 DCN_PWR_STATE_UNKNOWN = -1, 345 DCN_PWR_STATE_MISSION_MODE = 0, 346 DCN_PWR_STATE_LOW_POWER = 3, 347 }; 348 349 /* 350 * For any clocks that may differ per pipe 351 * only the max is stored in this structure 352 */ 353 struct dc_clocks { 354 int dispclk_khz; 355 int actual_dispclk_khz; 356 int dppclk_khz; 357 int actual_dppclk_khz; 358 int disp_dpp_voltage_level_khz; 359 int dcfclk_khz; 360 int socclk_khz; 361 int dcfclk_deep_sleep_khz; 362 int fclk_khz; 363 int phyclk_khz; 364 int dramclk_khz; 365 bool p_state_change_support; 366 enum dcn_pwr_state pwr_state; 367 /* 368 * Elements below are not compared for the purposes of 369 * optimization required 370 */ 371 bool prev_p_state_change_support; 372 enum dtm_pstate dtm_level; 373 int max_supported_dppclk_khz; 374 int max_supported_dispclk_khz; 375 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 376 int bw_dispclk_khz; 377 }; 378 379 struct dc_bw_validation_profile { 380 bool enable; 381 382 unsigned long long total_ticks; 383 unsigned long long voltage_level_ticks; 384 unsigned long long watermark_ticks; 385 unsigned long long rq_dlg_ticks; 386 387 unsigned long long total_count; 388 unsigned long long skip_fast_count; 389 unsigned long long skip_pass_count; 390 unsigned long long skip_fail_count; 391 }; 392 393 #define BW_VAL_TRACE_SETUP() \ 394 unsigned long long end_tick = 0; \ 395 unsigned long long voltage_level_tick = 0; \ 396 unsigned long long watermark_tick = 0; \ 397 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 398 dm_get_timestamp(dc->ctx) : 0 399 400 #define BW_VAL_TRACE_COUNT() \ 401 if (dc->debug.bw_val_profile.enable) \ 402 dc->debug.bw_val_profile.total_count++ 403 404 #define BW_VAL_TRACE_SKIP(status) \ 405 if (dc->debug.bw_val_profile.enable) { \ 406 if (!voltage_level_tick) \ 407 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 408 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 409 } 410 411 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 412 if (dc->debug.bw_val_profile.enable) \ 413 voltage_level_tick = dm_get_timestamp(dc->ctx) 414 415 #define BW_VAL_TRACE_END_WATERMARKS() \ 416 if (dc->debug.bw_val_profile.enable) \ 417 watermark_tick = dm_get_timestamp(dc->ctx) 418 419 #define BW_VAL_TRACE_FINISH() \ 420 if (dc->debug.bw_val_profile.enable) { \ 421 end_tick = dm_get_timestamp(dc->ctx); \ 422 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 423 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 424 if (watermark_tick) { \ 425 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 426 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 427 } \ 428 } 429 430 union mem_low_power_enable_options { 431 struct { 432 bool i2c: 1; 433 bool dmcu: 1; 434 bool dscl: 1; 435 bool cm: 1; 436 bool mpc: 1; 437 bool optc: 1; 438 } bits; 439 uint32_t u32All; 440 }; 441 442 struct dc_debug_options { 443 enum visual_confirm visual_confirm; 444 bool sanity_checks; 445 bool max_disp_clk; 446 bool surface_trace; 447 bool timing_trace; 448 bool clock_trace; 449 bool validation_trace; 450 bool bandwidth_calcs_trace; 451 int max_downscale_src_width; 452 453 /* stutter efficiency related */ 454 bool disable_stutter; 455 bool use_max_lb; 456 enum dcc_option disable_dcc; 457 enum pipe_split_policy pipe_split_policy; 458 bool force_single_disp_pipe_split; 459 bool voltage_align_fclk; 460 461 bool disable_dfs_bypass; 462 bool disable_dpp_power_gate; 463 bool disable_hubp_power_gate; 464 bool disable_dsc_power_gate; 465 int dsc_min_slice_height_override; 466 int dsc_bpp_increment_div; 467 bool native422_support; 468 bool disable_pplib_wm_range; 469 enum wm_report_mode pplib_wm_report_mode; 470 unsigned int min_disp_clk_khz; 471 unsigned int min_dpp_clk_khz; 472 int sr_exit_time_dpm0_ns; 473 int sr_enter_plus_exit_time_dpm0_ns; 474 int sr_exit_time_ns; 475 int sr_enter_plus_exit_time_ns; 476 int urgent_latency_ns; 477 uint32_t underflow_assert_delay_us; 478 int percent_of_ideal_drambw; 479 int dram_clock_change_latency_ns; 480 bool optimized_watermark; 481 int always_scale; 482 bool disable_pplib_clock_request; 483 bool disable_clock_gate; 484 bool disable_mem_low_power; 485 bool disable_dmcu; 486 bool disable_psr; 487 bool force_abm_enable; 488 bool disable_stereo_support; 489 bool vsr_support; 490 bool performance_trace; 491 bool az_endpoint_mute_only; 492 bool always_use_regamma; 493 bool recovery_enabled; 494 bool avoid_vbios_exec_table; 495 bool scl_reset_length10; 496 bool hdmi20_disable; 497 bool skip_detection_link_training; 498 uint32_t edid_read_retry_times; 499 bool remove_disconnect_edp; 500 unsigned int force_odm_combine; //bit vector based on otg inst 501 #if defined(CONFIG_DRM_AMD_DC_DCN) 502 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 503 #endif 504 unsigned int force_fclk_khz; 505 bool enable_tri_buf; 506 bool dmub_offload_enabled; 507 bool dmcub_emulation; 508 #if defined(CONFIG_DRM_AMD_DC_DCN) 509 bool disable_idle_power_optimizations; 510 unsigned int mall_size_override; 511 unsigned int mall_additional_timer_percent; 512 bool mall_error_as_fatal; 513 #endif 514 bool dmub_command_table; /* for testing only */ 515 struct dc_bw_validation_profile bw_val_profile; 516 bool disable_fec; 517 bool disable_48mhz_pwrdwn; 518 /* This forces a hard min on the DCFCLK requested to SMU/PP 519 * watermarks are not affected. 520 */ 521 unsigned int force_min_dcfclk_mhz; 522 #if defined(CONFIG_DRM_AMD_DC_DCN) 523 int dwb_fi_phase; 524 #endif 525 bool disable_timing_sync; 526 bool cm_in_bypass; 527 int force_clock_mode;/*every mode change.*/ 528 529 bool disable_dram_clock_change_vactive_support; 530 bool validate_dml_output; 531 bool enable_dmcub_surface_flip; 532 bool usbc_combo_phy_reset_wa; 533 bool disable_dsc; 534 bool enable_dram_clock_change_one_display_vactive; 535 union mem_low_power_enable_options enable_mem_low_power; 536 bool force_vblank_alignment; 537 538 /* Enable dmub aux for legacy ddc */ 539 bool enable_dmub_aux_for_legacy_ddc; 540 }; 541 542 struct dc_debug_data { 543 uint32_t ltFailCount; 544 uint32_t i2cErrorCount; 545 uint32_t auxErrorCount; 546 }; 547 548 struct dc_phy_addr_space_config { 549 struct { 550 uint64_t start_addr; 551 uint64_t end_addr; 552 uint64_t fb_top; 553 uint64_t fb_offset; 554 uint64_t fb_base; 555 uint64_t agp_top; 556 uint64_t agp_bot; 557 uint64_t agp_base; 558 } system_aperture; 559 560 struct { 561 uint64_t page_table_start_addr; 562 uint64_t page_table_end_addr; 563 uint64_t page_table_base_addr; 564 } gart_config; 565 566 bool valid; 567 bool is_hvm_enabled; 568 uint64_t page_table_default_page_addr; 569 }; 570 571 struct dc_virtual_addr_space_config { 572 uint64_t page_table_base_addr; 573 uint64_t page_table_start_addr; 574 uint64_t page_table_end_addr; 575 uint32_t page_table_block_size_in_bytes; 576 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 577 }; 578 579 struct dc_bounding_box_overrides { 580 int sr_exit_time_ns; 581 int sr_enter_plus_exit_time_ns; 582 int urgent_latency_ns; 583 int percent_of_ideal_drambw; 584 int dram_clock_change_latency_ns; 585 int dummy_clock_change_latency_ns; 586 /* This forces a hard min on the DCFCLK we use 587 * for DML. Unlike the debug option for forcing 588 * DCFCLK, this override affects watermark calculations 589 */ 590 int min_dcfclk_mhz; 591 }; 592 593 struct dc_state; 594 struct resource_pool; 595 struct dce_hwseq; 596 struct gpu_info_soc_bounding_box_v1_0; 597 struct dc { 598 struct dc_versions versions; 599 struct dc_caps caps; 600 struct dc_cap_funcs cap_funcs; 601 struct dc_config config; 602 struct dc_debug_options debug; 603 struct dc_bounding_box_overrides bb_overrides; 604 struct dc_bug_wa work_arounds; 605 struct dc_context *ctx; 606 struct dc_phy_addr_space_config vm_pa_config; 607 608 uint8_t link_count; 609 struct dc_link *links[MAX_PIPES * 2]; 610 611 struct dc_state *current_state; 612 struct resource_pool *res_pool; 613 614 struct clk_mgr *clk_mgr; 615 616 /* Display Engine Clock levels */ 617 struct dm_pp_clock_levels sclk_lvls; 618 619 /* Inputs into BW and WM calculations. */ 620 struct bw_calcs_dceip *bw_dceip; 621 struct bw_calcs_vbios *bw_vbios; 622 #ifdef CONFIG_DRM_AMD_DC_DCN 623 struct dcn_soc_bounding_box *dcn_soc; 624 struct dcn_ip_params *dcn_ip; 625 struct display_mode_lib dml; 626 #endif 627 628 /* HW functions */ 629 struct hw_sequencer_funcs hwss; 630 struct dce_hwseq *hwseq; 631 632 /* Require to optimize clocks and bandwidth for added/removed planes */ 633 bool optimized_required; 634 bool wm_optimized_required; 635 #if defined(CONFIG_DRM_AMD_DC_DCN) 636 bool idle_optimizations_allowed; 637 #endif 638 639 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 640 641 /* FBC compressor */ 642 struct compressor *fbc_compressor; 643 644 struct dc_debug_data debug_data; 645 struct dpcd_vendor_signature vendor_signature; 646 647 const char *build_id; 648 struct vm_helper *vm_helper; 649 }; 650 651 enum frame_buffer_mode { 652 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 653 FRAME_BUFFER_MODE_ZFB_ONLY, 654 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 655 } ; 656 657 struct dchub_init_data { 658 int64_t zfb_phys_addr_base; 659 int64_t zfb_mc_base_addr; 660 uint64_t zfb_size_in_byte; 661 enum frame_buffer_mode fb_mode; 662 bool dchub_initialzied; 663 bool dchub_info_valid; 664 }; 665 666 struct dc_init_data { 667 struct hw_asic_id asic_id; 668 void *driver; /* ctx */ 669 struct cgs_device *cgs_device; 670 struct dc_bounding_box_overrides bb_overrides; 671 672 int num_virtual_links; 673 /* 674 * If 'vbios_override' not NULL, it will be called instead 675 * of the real VBIOS. Intended use is Diagnostics on FPGA. 676 */ 677 struct dc_bios *vbios_override; 678 enum dce_environment dce_environment; 679 680 struct dmub_offload_funcs *dmub_if; 681 struct dc_reg_helper_state *dmub_offload; 682 683 struct dc_config flags; 684 uint64_t log_mask; 685 686 struct dpcd_vendor_signature vendor_signature; 687 #if defined(CONFIG_DRM_AMD_DC_DCN) 688 bool force_smu_not_present; 689 #endif 690 }; 691 692 struct dc_callback_init { 693 #ifdef CONFIG_DRM_AMD_DC_HDCP 694 struct cp_psp cp_psp; 695 #else 696 uint8_t reserved; 697 #endif 698 }; 699 700 struct dc *dc_create(const struct dc_init_data *init_params); 701 void dc_hardware_init(struct dc *dc); 702 703 int dc_get_vmid_use_vector(struct dc *dc); 704 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 705 /* Returns the number of vmids supported */ 706 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 707 void dc_init_callbacks(struct dc *dc, 708 const struct dc_callback_init *init_params); 709 void dc_deinit_callbacks(struct dc *dc); 710 void dc_destroy(struct dc **dc); 711 712 /******************************************************************************* 713 * Surface Interfaces 714 ******************************************************************************/ 715 716 enum { 717 TRANSFER_FUNC_POINTS = 1025 718 }; 719 720 struct dc_hdr_static_metadata { 721 /* display chromaticities and white point in units of 0.00001 */ 722 unsigned int chromaticity_green_x; 723 unsigned int chromaticity_green_y; 724 unsigned int chromaticity_blue_x; 725 unsigned int chromaticity_blue_y; 726 unsigned int chromaticity_red_x; 727 unsigned int chromaticity_red_y; 728 unsigned int chromaticity_white_point_x; 729 unsigned int chromaticity_white_point_y; 730 731 uint32_t min_luminance; 732 uint32_t max_luminance; 733 uint32_t maximum_content_light_level; 734 uint32_t maximum_frame_average_light_level; 735 }; 736 737 enum dc_transfer_func_type { 738 TF_TYPE_PREDEFINED, 739 TF_TYPE_DISTRIBUTED_POINTS, 740 TF_TYPE_BYPASS, 741 TF_TYPE_HWPWL 742 }; 743 744 struct dc_transfer_func_distributed_points { 745 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 746 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 747 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 748 749 uint16_t end_exponent; 750 uint16_t x_point_at_y1_red; 751 uint16_t x_point_at_y1_green; 752 uint16_t x_point_at_y1_blue; 753 }; 754 755 enum dc_transfer_func_predefined { 756 TRANSFER_FUNCTION_SRGB, 757 TRANSFER_FUNCTION_BT709, 758 TRANSFER_FUNCTION_PQ, 759 TRANSFER_FUNCTION_LINEAR, 760 TRANSFER_FUNCTION_UNITY, 761 TRANSFER_FUNCTION_HLG, 762 TRANSFER_FUNCTION_HLG12, 763 TRANSFER_FUNCTION_GAMMA22, 764 TRANSFER_FUNCTION_GAMMA24, 765 TRANSFER_FUNCTION_GAMMA26 766 }; 767 768 769 struct dc_transfer_func { 770 struct kref refcount; 771 enum dc_transfer_func_type type; 772 enum dc_transfer_func_predefined tf; 773 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 774 uint32_t sdr_ref_white_level; 775 union { 776 struct pwl_params pwl; 777 struct dc_transfer_func_distributed_points tf_pts; 778 }; 779 }; 780 781 782 union dc_3dlut_state { 783 struct { 784 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 785 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 786 uint32_t rmu_mux_num:3; /*index of mux to use*/ 787 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 788 uint32_t mpc_rmu1_mux:4; 789 uint32_t mpc_rmu2_mux:4; 790 uint32_t reserved:15; 791 } bits; 792 uint32_t raw; 793 }; 794 795 796 struct dc_3dlut { 797 struct kref refcount; 798 struct tetrahedral_params lut_3d; 799 struct fixed31_32 hdr_multiplier; 800 union dc_3dlut_state state; 801 }; 802 /* 803 * This structure is filled in by dc_surface_get_status and contains 804 * the last requested address and the currently active address so the called 805 * can determine if there are any outstanding flips 806 */ 807 struct dc_plane_status { 808 struct dc_plane_address requested_address; 809 struct dc_plane_address current_address; 810 bool is_flip_pending; 811 bool is_right_eye; 812 }; 813 814 union surface_update_flags { 815 816 struct { 817 uint32_t addr_update:1; 818 /* Medium updates */ 819 uint32_t dcc_change:1; 820 uint32_t color_space_change:1; 821 uint32_t horizontal_mirror_change:1; 822 uint32_t per_pixel_alpha_change:1; 823 uint32_t global_alpha_change:1; 824 uint32_t hdr_mult:1; 825 uint32_t rotation_change:1; 826 uint32_t swizzle_change:1; 827 uint32_t scaling_change:1; 828 uint32_t position_change:1; 829 uint32_t in_transfer_func_change:1; 830 uint32_t input_csc_change:1; 831 uint32_t coeff_reduction_change:1; 832 uint32_t output_tf_change:1; 833 uint32_t pixel_format_change:1; 834 uint32_t plane_size_change:1; 835 uint32_t gamut_remap_change:1; 836 837 /* Full updates */ 838 uint32_t new_plane:1; 839 uint32_t bpp_change:1; 840 uint32_t gamma_change:1; 841 uint32_t bandwidth_change:1; 842 uint32_t clock_change:1; 843 uint32_t stereo_format_change:1; 844 uint32_t full_update:1; 845 } bits; 846 847 uint32_t raw; 848 }; 849 850 struct dc_plane_state { 851 struct dc_plane_address address; 852 struct dc_plane_flip_time time; 853 bool triplebuffer_flips; 854 struct scaling_taps scaling_quality; 855 struct rect src_rect; 856 struct rect dst_rect; 857 struct rect clip_rect; 858 859 struct plane_size plane_size; 860 union dc_tiling_info tiling_info; 861 862 struct dc_plane_dcc_param dcc; 863 864 struct dc_gamma *gamma_correction; 865 struct dc_transfer_func *in_transfer_func; 866 struct dc_bias_and_scale *bias_and_scale; 867 struct dc_csc_transform input_csc_color_matrix; 868 struct fixed31_32 coeff_reduction_factor; 869 struct fixed31_32 hdr_mult; 870 struct colorspace_transform gamut_remap_matrix; 871 872 // TODO: No longer used, remove 873 struct dc_hdr_static_metadata hdr_static_ctx; 874 875 enum dc_color_space color_space; 876 877 struct dc_3dlut *lut3d_func; 878 struct dc_transfer_func *in_shaper_func; 879 struct dc_transfer_func *blend_tf; 880 881 #if defined(CONFIG_DRM_AMD_DC_DCN) 882 struct dc_transfer_func *gamcor_tf; 883 #endif 884 enum surface_pixel_format format; 885 enum dc_rotation_angle rotation; 886 enum plane_stereo_format stereo_format; 887 888 bool is_tiling_rotated; 889 bool per_pixel_alpha; 890 bool global_alpha; 891 int global_alpha_value; 892 bool visible; 893 bool flip_immediate; 894 bool horizontal_mirror; 895 int layer_index; 896 897 union surface_update_flags update_flags; 898 /* private to DC core */ 899 struct dc_plane_status status; 900 struct dc_context *ctx; 901 902 /* HACK: Workaround for forcing full reprogramming under some conditions */ 903 bool force_full_update; 904 905 /* private to dc_surface.c */ 906 enum dc_irq_source irq_source; 907 struct kref refcount; 908 }; 909 910 struct dc_plane_info { 911 struct plane_size plane_size; 912 union dc_tiling_info tiling_info; 913 struct dc_plane_dcc_param dcc; 914 enum surface_pixel_format format; 915 enum dc_rotation_angle rotation; 916 enum plane_stereo_format stereo_format; 917 enum dc_color_space color_space; 918 bool horizontal_mirror; 919 bool visible; 920 bool per_pixel_alpha; 921 bool global_alpha; 922 int global_alpha_value; 923 bool input_csc_enabled; 924 int layer_index; 925 }; 926 927 struct dc_scaling_info { 928 struct rect src_rect; 929 struct rect dst_rect; 930 struct rect clip_rect; 931 struct scaling_taps scaling_quality; 932 }; 933 934 struct dc_surface_update { 935 struct dc_plane_state *surface; 936 937 /* isr safe update parameters. null means no updates */ 938 const struct dc_flip_addrs *flip_addr; 939 const struct dc_plane_info *plane_info; 940 const struct dc_scaling_info *scaling_info; 941 struct fixed31_32 hdr_mult; 942 /* following updates require alloc/sleep/spin that is not isr safe, 943 * null means no updates 944 */ 945 const struct dc_gamma *gamma; 946 const struct dc_transfer_func *in_transfer_func; 947 948 const struct dc_csc_transform *input_csc_color_matrix; 949 const struct fixed31_32 *coeff_reduction_factor; 950 const struct dc_transfer_func *func_shaper; 951 const struct dc_3dlut *lut3d_func; 952 const struct dc_transfer_func *blend_tf; 953 const struct colorspace_transform *gamut_remap_matrix; 954 }; 955 956 /* 957 * Create a new surface with default parameters; 958 */ 959 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 960 const struct dc_plane_status *dc_plane_get_status( 961 const struct dc_plane_state *plane_state); 962 963 void dc_plane_state_retain(struct dc_plane_state *plane_state); 964 void dc_plane_state_release(struct dc_plane_state *plane_state); 965 966 void dc_gamma_retain(struct dc_gamma *dc_gamma); 967 void dc_gamma_release(struct dc_gamma **dc_gamma); 968 struct dc_gamma *dc_create_gamma(void); 969 970 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 971 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 972 struct dc_transfer_func *dc_create_transfer_func(void); 973 974 struct dc_3dlut *dc_create_3dlut_func(void); 975 void dc_3dlut_func_release(struct dc_3dlut *lut); 976 void dc_3dlut_func_retain(struct dc_3dlut *lut); 977 /* 978 * This structure holds a surface address. There could be multiple addresses 979 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 980 * as frame durations and DCC format can also be set. 981 */ 982 struct dc_flip_addrs { 983 struct dc_plane_address address; 984 unsigned int flip_timestamp_in_us; 985 bool flip_immediate; 986 /* TODO: add flip duration for FreeSync */ 987 bool triplebuffer_flips; 988 }; 989 990 void dc_post_update_surfaces_to_stream( 991 struct dc *dc); 992 993 #include "dc_stream.h" 994 995 /* 996 * Structure to store surface/stream associations for validation 997 */ 998 struct dc_validation_set { 999 struct dc_stream_state *stream; 1000 struct dc_plane_state *plane_states[MAX_SURFACES]; 1001 uint8_t plane_count; 1002 }; 1003 1004 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1005 const struct dc_sink *sink, 1006 struct dc_crtc_timing *crtc_timing); 1007 1008 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1009 1010 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1011 1012 bool dc_set_generic_gpio_for_stereo(bool enable, 1013 struct gpio_service *gpio_service); 1014 1015 /* 1016 * fast_validate: we return after determining if we can support the new state, 1017 * but before we populate the programming info 1018 */ 1019 enum dc_status dc_validate_global_state( 1020 struct dc *dc, 1021 struct dc_state *new_ctx, 1022 bool fast_validate); 1023 1024 1025 void dc_resource_state_construct( 1026 const struct dc *dc, 1027 struct dc_state *dst_ctx); 1028 1029 #if defined(CONFIG_DRM_AMD_DC_DCN) 1030 bool dc_acquire_release_mpc_3dlut( 1031 struct dc *dc, bool acquire, 1032 struct dc_stream_state *stream, 1033 struct dc_3dlut **lut, 1034 struct dc_transfer_func **shaper); 1035 #endif 1036 1037 void dc_resource_state_copy_construct( 1038 const struct dc_state *src_ctx, 1039 struct dc_state *dst_ctx); 1040 1041 void dc_resource_state_copy_construct_current( 1042 const struct dc *dc, 1043 struct dc_state *dst_ctx); 1044 1045 void dc_resource_state_destruct(struct dc_state *context); 1046 1047 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1048 1049 /* 1050 * TODO update to make it about validation sets 1051 * Set up streams and links associated to drive sinks 1052 * The streams parameter is an absolute set of all active streams. 1053 * 1054 * After this call: 1055 * Phy, Encoder, Timing Generator are programmed and enabled. 1056 * New streams are enabled with blank stream; no memory read. 1057 */ 1058 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1059 1060 void dc_power_down_on_boot(struct dc *dc); 1061 1062 struct dc_state *dc_create_state(struct dc *dc); 1063 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1064 void dc_retain_state(struct dc_state *context); 1065 void dc_release_state(struct dc_state *context); 1066 1067 /******************************************************************************* 1068 * Link Interfaces 1069 ******************************************************************************/ 1070 1071 struct dpcd_caps { 1072 union dpcd_rev dpcd_rev; 1073 union max_lane_count max_ln_count; 1074 union max_down_spread max_down_spread; 1075 union dprx_feature dprx_feature; 1076 1077 /* valid only for eDP v1.4 or higher*/ 1078 uint8_t edp_supported_link_rates_count; 1079 enum dc_link_rate edp_supported_link_rates[8]; 1080 1081 /* dongle type (DP converter, CV smart dongle) */ 1082 enum display_dongle_type dongle_type; 1083 /* branch device or sink device */ 1084 bool is_branch_dev; 1085 /* Dongle's downstream count. */ 1086 union sink_count sink_count; 1087 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1088 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1089 struct dc_dongle_caps dongle_caps; 1090 1091 uint32_t sink_dev_id; 1092 int8_t sink_dev_id_str[6]; 1093 int8_t sink_hw_revision; 1094 int8_t sink_fw_revision[2]; 1095 1096 uint32_t branch_dev_id; 1097 int8_t branch_dev_name[6]; 1098 int8_t branch_hw_revision; 1099 int8_t branch_fw_revision[2]; 1100 1101 bool allow_invalid_MSA_timing_param; 1102 bool panel_mode_edp; 1103 bool dpcd_display_control_capable; 1104 bool ext_receiver_cap_field_present; 1105 bool dynamic_backlight_capable_edp; 1106 union dpcd_fec_capability fec_cap; 1107 struct dpcd_dsc_capabilities dsc_caps; 1108 struct dc_lttpr_caps lttpr_caps; 1109 struct psr_caps psr_caps; 1110 1111 }; 1112 1113 union dpcd_sink_ext_caps { 1114 struct { 1115 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1116 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1117 */ 1118 uint8_t sdr_aux_backlight_control : 1; 1119 uint8_t hdr_aux_backlight_control : 1; 1120 uint8_t reserved_1 : 2; 1121 uint8_t oled : 1; 1122 uint8_t reserved : 3; 1123 } bits; 1124 uint8_t raw; 1125 }; 1126 1127 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1128 union hdcp_rx_caps { 1129 struct { 1130 uint8_t version; 1131 uint8_t reserved; 1132 struct { 1133 uint8_t repeater : 1; 1134 uint8_t hdcp_capable : 1; 1135 uint8_t reserved : 6; 1136 } byte0; 1137 } fields; 1138 uint8_t raw[3]; 1139 }; 1140 1141 union hdcp_bcaps { 1142 struct { 1143 uint8_t HDCP_CAPABLE:1; 1144 uint8_t REPEATER:1; 1145 uint8_t RESERVED:6; 1146 } bits; 1147 uint8_t raw; 1148 }; 1149 1150 struct hdcp_caps { 1151 union hdcp_rx_caps rx_caps; 1152 union hdcp_bcaps bcaps; 1153 }; 1154 #endif 1155 1156 #include "dc_link.h" 1157 1158 #if defined(CONFIG_DRM_AMD_DC_DCN) 1159 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1160 1161 #endif 1162 /******************************************************************************* 1163 * Sink Interfaces - A sink corresponds to a display output device 1164 ******************************************************************************/ 1165 1166 struct dc_container_id { 1167 // 128bit GUID in binary form 1168 unsigned char guid[16]; 1169 // 8 byte port ID -> ELD.PortID 1170 unsigned int portId[2]; 1171 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1172 unsigned short manufacturerName; 1173 // 2 byte product code -> ELD.ProductCode 1174 unsigned short productCode; 1175 }; 1176 1177 1178 struct dc_sink_dsc_caps { 1179 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1180 // 'false' if they are sink's DSC caps 1181 bool is_virtual_dpcd_dsc; 1182 struct dsc_dec_dpcd_caps dsc_dec_caps; 1183 }; 1184 1185 struct dc_sink_fec_caps { 1186 bool is_rx_fec_supported; 1187 bool is_topology_fec_supported; 1188 }; 1189 1190 /* 1191 * The sink structure contains EDID and other display device properties 1192 */ 1193 struct dc_sink { 1194 enum signal_type sink_signal; 1195 struct dc_edid dc_edid; /* raw edid */ 1196 struct dc_edid_caps edid_caps; /* parse display caps */ 1197 struct dc_container_id *dc_container_id; 1198 uint32_t dongle_max_pix_clk; 1199 void *priv; 1200 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1201 bool converter_disable_audio; 1202 1203 struct dc_sink_dsc_caps dsc_caps; 1204 struct dc_sink_fec_caps fec_caps; 1205 1206 bool is_vsc_sdp_colorimetry_supported; 1207 1208 /* private to DC core */ 1209 struct dc_link *link; 1210 struct dc_context *ctx; 1211 1212 uint32_t sink_id; 1213 1214 /* private to dc_sink.c */ 1215 // refcount must be the last member in dc_sink, since we want the 1216 // sink structure to be logically cloneable up to (but not including) 1217 // refcount 1218 struct kref refcount; 1219 }; 1220 1221 void dc_sink_retain(struct dc_sink *sink); 1222 void dc_sink_release(struct dc_sink *sink); 1223 1224 struct dc_sink_init_data { 1225 enum signal_type sink_signal; 1226 struct dc_link *link; 1227 uint32_t dongle_max_pix_clk; 1228 bool converter_disable_audio; 1229 }; 1230 1231 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1232 1233 /* Newer interfaces */ 1234 struct dc_cursor { 1235 struct dc_plane_address address; 1236 struct dc_cursor_attributes attributes; 1237 }; 1238 1239 1240 /******************************************************************************* 1241 * Interrupt interfaces 1242 ******************************************************************************/ 1243 enum dc_irq_source dc_interrupt_to_irq_source( 1244 struct dc *dc, 1245 uint32_t src_id, 1246 uint32_t ext_id); 1247 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1248 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1249 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1250 struct dc *dc, uint32_t link_index); 1251 1252 /******************************************************************************* 1253 * Power Interfaces 1254 ******************************************************************************/ 1255 1256 void dc_set_power_state( 1257 struct dc *dc, 1258 enum dc_acpi_cm_power_state power_state); 1259 void dc_resume(struct dc *dc); 1260 1261 void dc_power_down_on_boot(struct dc *dc); 1262 1263 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1264 /* 1265 * HDCP Interfaces 1266 */ 1267 enum hdcp_message_status dc_process_hdcp_msg( 1268 enum signal_type signal, 1269 struct dc_link *link, 1270 struct hdcp_protection_message *message_info); 1271 #endif 1272 bool dc_is_dmcu_initialized(struct dc *dc); 1273 1274 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1275 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1276 #if defined(CONFIG_DRM_AMD_DC_DCN) 1277 1278 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1279 struct dc_cursor_attributes *cursor_attr); 1280 1281 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1282 1283 /* 1284 * blank all streams, and set min and max memory clock to 1285 * lowest and highest DPM level, respectively 1286 */ 1287 void dc_unlock_memory_clock_frequency(struct dc *dc); 1288 1289 /* 1290 * set min memory clock to the min required for current mode, 1291 * max to maxDPM, and unblank streams 1292 */ 1293 void dc_lock_memory_clock_frequency(struct dc *dc); 1294 1295 /* cleanup on driver unload */ 1296 void dc_hardware_release(struct dc *dc); 1297 1298 #endif 1299 1300 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1301 1302 bool dc_enable_dmub_notifications(struct dc *dc); 1303 1304 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1305 uint32_t link_index, 1306 struct aux_payload *payload); 1307 1308 /******************************************************************************* 1309 * DSC Interfaces 1310 ******************************************************************************/ 1311 #include "dc_dsc.h" 1312 #endif /* DC_INTERFACE_H_ */ 1313