1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.177" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_caps { 166 uint32_t max_streams; 167 uint32_t max_links; 168 uint32_t max_audios; 169 uint32_t max_slave_planes; 170 uint32_t max_slave_yuv_planes; 171 uint32_t max_slave_rgb_planes; 172 uint32_t max_planes; 173 uint32_t max_downscale_ratio; 174 uint32_t i2c_speed_in_khz; 175 uint32_t i2c_speed_in_khz_hdcp; 176 uint32_t dmdata_alloc_size; 177 unsigned int max_cursor_size; 178 unsigned int max_video_width; 179 unsigned int min_horizontal_blanking_period; 180 int linear_pitch_alignment; 181 bool dcc_const_color; 182 bool dynamic_audio; 183 bool is_apu; 184 bool dual_link_dvi; 185 bool post_blend_color_processing; 186 bool force_dp_tps4_for_cp2520; 187 bool disable_dp_clk_share; 188 bool psp_setup_panel_mode; 189 bool extended_aux_timeout_support; 190 bool dmcub_support; 191 uint32_t num_of_internal_disp; 192 enum dp_protocol_version max_dp_protocol_version; 193 unsigned int mall_size_per_mem_channel; 194 unsigned int mall_size_total; 195 unsigned int cursor_cache_size; 196 struct dc_plane_cap planes[MAX_PLANES]; 197 struct dc_color_caps color; 198 bool dp_hpo; 199 bool hdmi_frl_pcon_support; 200 bool edp_dsc_support; 201 bool vbios_lttpr_aware; 202 bool vbios_lttpr_enable; 203 uint32_t max_otg_num; 204 }; 205 206 struct dc_bug_wa { 207 bool no_connect_phy_config; 208 bool dedcn20_305_wa; 209 bool skip_clock_update; 210 bool lt_early_cr_pattern; 211 }; 212 213 struct dc_dcc_surface_param { 214 struct dc_size surface_size; 215 enum surface_pixel_format format; 216 enum swizzle_mode_values swizzle_mode; 217 enum dc_scan_direction scan; 218 }; 219 220 struct dc_dcc_setting { 221 unsigned int max_compressed_blk_size; 222 unsigned int max_uncompressed_blk_size; 223 bool independent_64b_blks; 224 #if defined(CONFIG_DRM_AMD_DC_DCN) 225 //These bitfields to be used starting with DCN 226 struct { 227 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 228 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 229 uint32_t dcc_256_128_128 : 1; //available starting with DCN 230 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 231 } dcc_controls; 232 #endif 233 }; 234 235 struct dc_surface_dcc_cap { 236 union { 237 struct { 238 struct dc_dcc_setting rgb; 239 } grph; 240 241 struct { 242 struct dc_dcc_setting luma; 243 struct dc_dcc_setting chroma; 244 } video; 245 }; 246 247 bool capable; 248 bool const_color_support; 249 }; 250 251 struct dc_static_screen_params { 252 struct { 253 bool force_trigger; 254 bool cursor_update; 255 bool surface_update; 256 bool overlay_update; 257 } triggers; 258 unsigned int num_frames; 259 }; 260 261 262 /* Surface update type is used by dc_update_surfaces_and_stream 263 * The update type is determined at the very beginning of the function based 264 * on parameters passed in and decides how much programming (or updating) is 265 * going to be done during the call. 266 * 267 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 268 * logical calculations or hardware register programming. This update MUST be 269 * ISR safe on windows. Currently fast update will only be used to flip surface 270 * address. 271 * 272 * UPDATE_TYPE_MED is used for slower updates which require significant hw 273 * re-programming however do not affect bandwidth consumption or clock 274 * requirements. At present, this is the level at which front end updates 275 * that do not require us to run bw_calcs happen. These are in/out transfer func 276 * updates, viewport offset changes, recout size changes and pixel depth changes. 277 * This update can be done at ISR, but we want to minimize how often this happens. 278 * 279 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 280 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 281 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 282 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 283 * a full update. This cannot be done at ISR level and should be a rare event. 284 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 285 * underscan we don't expect to see this call at all. 286 */ 287 288 enum surface_update_type { 289 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 290 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 291 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 292 }; 293 294 /* Forward declaration*/ 295 struct dc; 296 struct dc_plane_state; 297 struct dc_state; 298 299 300 struct dc_cap_funcs { 301 bool (*get_dcc_compression_cap)(const struct dc *dc, 302 const struct dc_dcc_surface_param *input, 303 struct dc_surface_dcc_cap *output); 304 }; 305 306 struct link_training_settings; 307 308 union allow_lttpr_non_transparent_mode { 309 struct { 310 bool DP1_4A : 1; 311 bool DP2_0 : 1; 312 } bits; 313 unsigned char raw; 314 }; 315 316 /* Structure to hold configuration flags set by dm at dc creation. */ 317 struct dc_config { 318 bool gpu_vm_support; 319 bool disable_disp_pll_sharing; 320 bool fbc_support; 321 bool disable_fractional_pwm; 322 bool allow_seamless_boot_optimization; 323 bool seamless_boot_edp_requested; 324 bool edp_not_connected; 325 bool edp_no_power_sequencing; 326 bool force_enum_edp; 327 bool forced_clocks; 328 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 329 bool multi_mon_pp_mclk_switch; 330 bool disable_dmcu; 331 bool enable_4to1MPC; 332 bool enable_windowed_mpo_odm; 333 bool allow_edp_hotplug_detection; 334 #if defined(CONFIG_DRM_AMD_DC_DCN) 335 bool clamp_min_dcfclk; 336 #endif 337 uint64_t vblank_alignment_dto_params; 338 uint8_t vblank_alignment_max_frame_time_diff; 339 bool is_asymmetric_memory; 340 bool is_single_rank_dimm; 341 bool use_pipe_ctx_sync_logic; 342 }; 343 344 enum visual_confirm { 345 VISUAL_CONFIRM_DISABLE = 0, 346 VISUAL_CONFIRM_SURFACE = 1, 347 VISUAL_CONFIRM_HDR = 2, 348 VISUAL_CONFIRM_MPCTREE = 4, 349 VISUAL_CONFIRM_PSR = 5, 350 VISUAL_CONFIRM_SWIZZLE = 9, 351 }; 352 353 enum dc_psr_power_opts { 354 psr_power_opt_invalid = 0x0, 355 psr_power_opt_smu_opt_static_screen = 0x1, 356 psr_power_opt_z10_static_screen = 0x10, 357 psr_power_opt_ds_disable_allow = 0x100, 358 }; 359 360 enum dcc_option { 361 DCC_ENABLE = 0, 362 DCC_DISABLE = 1, 363 DCC_HALF_REQ_DISALBE = 2, 364 }; 365 366 enum pipe_split_policy { 367 MPC_SPLIT_DYNAMIC = 0, 368 MPC_SPLIT_AVOID = 1, 369 MPC_SPLIT_AVOID_MULT_DISP = 2, 370 }; 371 372 enum wm_report_mode { 373 WM_REPORT_DEFAULT = 0, 374 WM_REPORT_OVERRIDE = 1, 375 }; 376 enum dtm_pstate{ 377 dtm_level_p0 = 0,/*highest voltage*/ 378 dtm_level_p1, 379 dtm_level_p2, 380 dtm_level_p3, 381 dtm_level_p4,/*when active_display_count = 0*/ 382 }; 383 384 enum dcn_pwr_state { 385 DCN_PWR_STATE_UNKNOWN = -1, 386 DCN_PWR_STATE_MISSION_MODE = 0, 387 DCN_PWR_STATE_LOW_POWER = 3, 388 }; 389 390 #if defined(CONFIG_DRM_AMD_DC_DCN) 391 enum dcn_zstate_support_state { 392 DCN_ZSTATE_SUPPORT_UNKNOWN, 393 DCN_ZSTATE_SUPPORT_ALLOW, 394 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 395 DCN_ZSTATE_SUPPORT_DISALLOW, 396 }; 397 #endif 398 /* 399 * For any clocks that may differ per pipe 400 * only the max is stored in this structure 401 */ 402 struct dc_clocks { 403 int dispclk_khz; 404 int actual_dispclk_khz; 405 int dppclk_khz; 406 int actual_dppclk_khz; 407 int disp_dpp_voltage_level_khz; 408 int dcfclk_khz; 409 int socclk_khz; 410 int dcfclk_deep_sleep_khz; 411 int fclk_khz; 412 int phyclk_khz; 413 int dramclk_khz; 414 bool p_state_change_support; 415 #if defined(CONFIG_DRM_AMD_DC_DCN) 416 enum dcn_zstate_support_state zstate_support; 417 bool dtbclk_en; 418 #endif 419 enum dcn_pwr_state pwr_state; 420 /* 421 * Elements below are not compared for the purposes of 422 * optimization required 423 */ 424 bool prev_p_state_change_support; 425 enum dtm_pstate dtm_level; 426 int max_supported_dppclk_khz; 427 int max_supported_dispclk_khz; 428 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 429 int bw_dispclk_khz; 430 }; 431 432 struct dc_bw_validation_profile { 433 bool enable; 434 435 unsigned long long total_ticks; 436 unsigned long long voltage_level_ticks; 437 unsigned long long watermark_ticks; 438 unsigned long long rq_dlg_ticks; 439 440 unsigned long long total_count; 441 unsigned long long skip_fast_count; 442 unsigned long long skip_pass_count; 443 unsigned long long skip_fail_count; 444 }; 445 446 #define BW_VAL_TRACE_SETUP() \ 447 unsigned long long end_tick = 0; \ 448 unsigned long long voltage_level_tick = 0; \ 449 unsigned long long watermark_tick = 0; \ 450 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 451 dm_get_timestamp(dc->ctx) : 0 452 453 #define BW_VAL_TRACE_COUNT() \ 454 if (dc->debug.bw_val_profile.enable) \ 455 dc->debug.bw_val_profile.total_count++ 456 457 #define BW_VAL_TRACE_SKIP(status) \ 458 if (dc->debug.bw_val_profile.enable) { \ 459 if (!voltage_level_tick) \ 460 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 461 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 462 } 463 464 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 465 if (dc->debug.bw_val_profile.enable) \ 466 voltage_level_tick = dm_get_timestamp(dc->ctx) 467 468 #define BW_VAL_TRACE_END_WATERMARKS() \ 469 if (dc->debug.bw_val_profile.enable) \ 470 watermark_tick = dm_get_timestamp(dc->ctx) 471 472 #define BW_VAL_TRACE_FINISH() \ 473 if (dc->debug.bw_val_profile.enable) { \ 474 end_tick = dm_get_timestamp(dc->ctx); \ 475 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 476 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 477 if (watermark_tick) { \ 478 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 479 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 480 } \ 481 } 482 483 union mem_low_power_enable_options { 484 struct { 485 bool vga: 1; 486 bool i2c: 1; 487 bool dmcu: 1; 488 bool dscl: 1; 489 bool cm: 1; 490 bool mpc: 1; 491 bool optc: 1; 492 bool vpg: 1; 493 bool afmt: 1; 494 } bits; 495 uint32_t u32All; 496 }; 497 498 union root_clock_optimization_options { 499 struct { 500 bool dpp: 1; 501 bool dsc: 1; 502 bool hdmistream: 1; 503 bool hdmichar: 1; 504 bool dpstream: 1; 505 bool symclk32_se: 1; 506 bool symclk32_le: 1; 507 bool symclk_fe: 1; 508 bool physymclk: 1; 509 bool dpiasymclk: 1; 510 uint32_t reserved: 22; 511 } bits; 512 uint32_t u32All; 513 }; 514 515 union dpia_debug_options { 516 struct { 517 uint32_t disable_dpia:1; /* bit 0 */ 518 uint32_t force_non_lttpr:1; /* bit 1 */ 519 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 520 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 521 uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ 522 uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ 523 uint32_t reserved:15; 524 } bits; 525 uint32_t raw; 526 }; 527 528 struct dc_debug_data { 529 uint32_t ltFailCount; 530 uint32_t i2cErrorCount; 531 uint32_t auxErrorCount; 532 }; 533 534 struct dc_phy_addr_space_config { 535 struct { 536 uint64_t start_addr; 537 uint64_t end_addr; 538 uint64_t fb_top; 539 uint64_t fb_offset; 540 uint64_t fb_base; 541 uint64_t agp_top; 542 uint64_t agp_bot; 543 uint64_t agp_base; 544 } system_aperture; 545 546 struct { 547 uint64_t page_table_start_addr; 548 uint64_t page_table_end_addr; 549 uint64_t page_table_base_addr; 550 bool base_addr_is_mc_addr; 551 } gart_config; 552 553 bool valid; 554 bool is_hvm_enabled; 555 uint64_t page_table_default_page_addr; 556 }; 557 558 struct dc_virtual_addr_space_config { 559 uint64_t page_table_base_addr; 560 uint64_t page_table_start_addr; 561 uint64_t page_table_end_addr; 562 uint32_t page_table_block_size_in_bytes; 563 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 564 }; 565 566 struct dc_bounding_box_overrides { 567 int sr_exit_time_ns; 568 int sr_enter_plus_exit_time_ns; 569 int urgent_latency_ns; 570 int percent_of_ideal_drambw; 571 int dram_clock_change_latency_ns; 572 int dummy_clock_change_latency_ns; 573 /* This forces a hard min on the DCFCLK we use 574 * for DML. Unlike the debug option for forcing 575 * DCFCLK, this override affects watermark calculations 576 */ 577 int min_dcfclk_mhz; 578 }; 579 580 struct dc_state; 581 struct resource_pool; 582 struct dce_hwseq; 583 584 struct dc_debug_options { 585 bool native422_support; 586 bool disable_dsc; 587 enum visual_confirm visual_confirm; 588 int visual_confirm_rect_height; 589 590 bool sanity_checks; 591 bool max_disp_clk; 592 bool surface_trace; 593 bool timing_trace; 594 bool clock_trace; 595 bool validation_trace; 596 bool bandwidth_calcs_trace; 597 int max_downscale_src_width; 598 599 /* stutter efficiency related */ 600 bool disable_stutter; 601 bool use_max_lb; 602 enum dcc_option disable_dcc; 603 enum pipe_split_policy pipe_split_policy; 604 bool force_single_disp_pipe_split; 605 bool voltage_align_fclk; 606 bool disable_min_fclk; 607 608 bool disable_dfs_bypass; 609 bool disable_dpp_power_gate; 610 bool disable_hubp_power_gate; 611 bool disable_dsc_power_gate; 612 int dsc_min_slice_height_override; 613 int dsc_bpp_increment_div; 614 bool disable_pplib_wm_range; 615 enum wm_report_mode pplib_wm_report_mode; 616 unsigned int min_disp_clk_khz; 617 unsigned int min_dpp_clk_khz; 618 unsigned int min_dram_clk_khz; 619 int sr_exit_time_dpm0_ns; 620 int sr_enter_plus_exit_time_dpm0_ns; 621 int sr_exit_time_ns; 622 int sr_enter_plus_exit_time_ns; 623 int urgent_latency_ns; 624 uint32_t underflow_assert_delay_us; 625 int percent_of_ideal_drambw; 626 int dram_clock_change_latency_ns; 627 bool optimized_watermark; 628 int always_scale; 629 bool disable_pplib_clock_request; 630 bool disable_clock_gate; 631 bool disable_mem_low_power; 632 #if defined(CONFIG_DRM_AMD_DC_DCN) 633 bool pstate_enabled; 634 #endif 635 bool disable_dmcu; 636 bool disable_psr; 637 bool force_abm_enable; 638 bool disable_stereo_support; 639 bool vsr_support; 640 bool performance_trace; 641 bool az_endpoint_mute_only; 642 bool always_use_regamma; 643 bool recovery_enabled; 644 bool avoid_vbios_exec_table; 645 bool scl_reset_length10; 646 bool hdmi20_disable; 647 bool skip_detection_link_training; 648 uint32_t edid_read_retry_times; 649 bool remove_disconnect_edp; 650 unsigned int force_odm_combine; //bit vector based on otg inst 651 #if defined(CONFIG_DRM_AMD_DC_DCN) 652 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 653 bool disable_z9_mpc; 654 #endif 655 unsigned int force_fclk_khz; 656 bool enable_tri_buf; 657 bool dmub_offload_enabled; 658 bool dmcub_emulation; 659 #if defined(CONFIG_DRM_AMD_DC_DCN) 660 bool disable_idle_power_optimizations; 661 unsigned int mall_size_override; 662 unsigned int mall_additional_timer_percent; 663 bool mall_error_as_fatal; 664 #endif 665 bool dmub_command_table; /* for testing only */ 666 struct dc_bw_validation_profile bw_val_profile; 667 bool disable_fec; 668 bool disable_48mhz_pwrdwn; 669 /* This forces a hard min on the DCFCLK requested to SMU/PP 670 * watermarks are not affected. 671 */ 672 unsigned int force_min_dcfclk_mhz; 673 #if defined(CONFIG_DRM_AMD_DC_DCN) 674 int dwb_fi_phase; 675 #endif 676 bool disable_timing_sync; 677 bool cm_in_bypass; 678 int force_clock_mode;/*every mode change.*/ 679 680 bool disable_dram_clock_change_vactive_support; 681 bool validate_dml_output; 682 bool enable_dmcub_surface_flip; 683 bool usbc_combo_phy_reset_wa; 684 bool disable_dsc_edp; 685 unsigned int force_dsc_edp_policy; 686 bool enable_dram_clock_change_one_display_vactive; 687 /* TODO - remove once tested */ 688 bool legacy_dp2_lt; 689 bool set_mst_en_for_sst; 690 bool disable_uhbr; 691 bool force_dp2_lt_fallback_method; 692 bool ignore_cable_id; 693 union mem_low_power_enable_options enable_mem_low_power; 694 union root_clock_optimization_options root_clock_optimization; 695 bool hpo_optimization; 696 bool force_vblank_alignment; 697 698 /* Enable dmub aux for legacy ddc */ 699 bool enable_dmub_aux_for_legacy_ddc; 700 bool optimize_edp_link_rate; /* eDP ILR */ 701 /* FEC/PSR1 sequence enable delay in 100us */ 702 uint8_t fec_enable_delay_in100us; 703 bool enable_driver_sequence_debug; 704 enum det_size crb_alloc_policy; 705 int crb_alloc_policy_min_disp_count; 706 #if defined(CONFIG_DRM_AMD_DC_DCN) 707 bool disable_z10; 708 bool enable_z9_disable_interface; 709 bool enable_sw_cntl_psr; 710 union dpia_debug_options dpia_debug; 711 #endif 712 bool apply_vendor_specific_lttpr_wa; 713 bool ignore_dpref_ss; 714 uint8_t psr_power_use_phy_fsm; 715 }; 716 717 struct gpu_info_soc_bounding_box_v1_0; 718 struct dc { 719 struct dc_debug_options debug; 720 struct dc_versions versions; 721 struct dc_caps caps; 722 struct dc_cap_funcs cap_funcs; 723 struct dc_config config; 724 struct dc_bounding_box_overrides bb_overrides; 725 struct dc_bug_wa work_arounds; 726 struct dc_context *ctx; 727 struct dc_phy_addr_space_config vm_pa_config; 728 729 uint8_t link_count; 730 struct dc_link *links[MAX_PIPES * 2]; 731 732 struct dc_state *current_state; 733 struct resource_pool *res_pool; 734 735 struct clk_mgr *clk_mgr; 736 737 /* Display Engine Clock levels */ 738 struct dm_pp_clock_levels sclk_lvls; 739 740 /* Inputs into BW and WM calculations. */ 741 struct bw_calcs_dceip *bw_dceip; 742 struct bw_calcs_vbios *bw_vbios; 743 #ifdef CONFIG_DRM_AMD_DC_DCN 744 struct dcn_soc_bounding_box *dcn_soc; 745 struct dcn_ip_params *dcn_ip; 746 struct display_mode_lib dml; 747 #endif 748 749 /* HW functions */ 750 struct hw_sequencer_funcs hwss; 751 struct dce_hwseq *hwseq; 752 753 /* Require to optimize clocks and bandwidth for added/removed planes */ 754 bool optimized_required; 755 bool wm_optimized_required; 756 #if defined(CONFIG_DRM_AMD_DC_DCN) 757 bool idle_optimizations_allowed; 758 #endif 759 #if defined(CONFIG_DRM_AMD_DC_DCN) 760 bool enable_c20_dtm_b0; 761 #endif 762 763 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 764 765 /* FBC compressor */ 766 struct compressor *fbc_compressor; 767 768 struct dc_debug_data debug_data; 769 struct dpcd_vendor_signature vendor_signature; 770 771 const char *build_id; 772 struct vm_helper *vm_helper; 773 }; 774 775 enum frame_buffer_mode { 776 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 777 FRAME_BUFFER_MODE_ZFB_ONLY, 778 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 779 } ; 780 781 struct dchub_init_data { 782 int64_t zfb_phys_addr_base; 783 int64_t zfb_mc_base_addr; 784 uint64_t zfb_size_in_byte; 785 enum frame_buffer_mode fb_mode; 786 bool dchub_initialzied; 787 bool dchub_info_valid; 788 }; 789 790 struct dc_init_data { 791 struct hw_asic_id asic_id; 792 void *driver; /* ctx */ 793 struct cgs_device *cgs_device; 794 struct dc_bounding_box_overrides bb_overrides; 795 796 int num_virtual_links; 797 /* 798 * If 'vbios_override' not NULL, it will be called instead 799 * of the real VBIOS. Intended use is Diagnostics on FPGA. 800 */ 801 struct dc_bios *vbios_override; 802 enum dce_environment dce_environment; 803 804 struct dmub_offload_funcs *dmub_if; 805 struct dc_reg_helper_state *dmub_offload; 806 807 struct dc_config flags; 808 uint64_t log_mask; 809 810 struct dpcd_vendor_signature vendor_signature; 811 #if defined(CONFIG_DRM_AMD_DC_DCN) 812 bool force_smu_not_present; 813 #endif 814 }; 815 816 struct dc_callback_init { 817 #ifdef CONFIG_DRM_AMD_DC_HDCP 818 struct cp_psp cp_psp; 819 #else 820 uint8_t reserved; 821 #endif 822 }; 823 824 struct dc *dc_create(const struct dc_init_data *init_params); 825 void dc_hardware_init(struct dc *dc); 826 827 int dc_get_vmid_use_vector(struct dc *dc); 828 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 829 /* Returns the number of vmids supported */ 830 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 831 void dc_init_callbacks(struct dc *dc, 832 const struct dc_callback_init *init_params); 833 void dc_deinit_callbacks(struct dc *dc); 834 void dc_destroy(struct dc **dc); 835 836 /******************************************************************************* 837 * Surface Interfaces 838 ******************************************************************************/ 839 840 enum { 841 TRANSFER_FUNC_POINTS = 1025 842 }; 843 844 struct dc_hdr_static_metadata { 845 /* display chromaticities and white point in units of 0.00001 */ 846 unsigned int chromaticity_green_x; 847 unsigned int chromaticity_green_y; 848 unsigned int chromaticity_blue_x; 849 unsigned int chromaticity_blue_y; 850 unsigned int chromaticity_red_x; 851 unsigned int chromaticity_red_y; 852 unsigned int chromaticity_white_point_x; 853 unsigned int chromaticity_white_point_y; 854 855 uint32_t min_luminance; 856 uint32_t max_luminance; 857 uint32_t maximum_content_light_level; 858 uint32_t maximum_frame_average_light_level; 859 }; 860 861 enum dc_transfer_func_type { 862 TF_TYPE_PREDEFINED, 863 TF_TYPE_DISTRIBUTED_POINTS, 864 TF_TYPE_BYPASS, 865 TF_TYPE_HWPWL 866 }; 867 868 struct dc_transfer_func_distributed_points { 869 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 870 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 871 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 872 873 uint16_t end_exponent; 874 uint16_t x_point_at_y1_red; 875 uint16_t x_point_at_y1_green; 876 uint16_t x_point_at_y1_blue; 877 }; 878 879 enum dc_transfer_func_predefined { 880 TRANSFER_FUNCTION_SRGB, 881 TRANSFER_FUNCTION_BT709, 882 TRANSFER_FUNCTION_PQ, 883 TRANSFER_FUNCTION_LINEAR, 884 TRANSFER_FUNCTION_UNITY, 885 TRANSFER_FUNCTION_HLG, 886 TRANSFER_FUNCTION_HLG12, 887 TRANSFER_FUNCTION_GAMMA22, 888 TRANSFER_FUNCTION_GAMMA24, 889 TRANSFER_FUNCTION_GAMMA26 890 }; 891 892 893 struct dc_transfer_func { 894 struct kref refcount; 895 enum dc_transfer_func_type type; 896 enum dc_transfer_func_predefined tf; 897 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 898 uint32_t sdr_ref_white_level; 899 union { 900 struct pwl_params pwl; 901 struct dc_transfer_func_distributed_points tf_pts; 902 }; 903 }; 904 905 906 union dc_3dlut_state { 907 struct { 908 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 909 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 910 uint32_t rmu_mux_num:3; /*index of mux to use*/ 911 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 912 uint32_t mpc_rmu1_mux:4; 913 uint32_t mpc_rmu2_mux:4; 914 uint32_t reserved:15; 915 } bits; 916 uint32_t raw; 917 }; 918 919 920 struct dc_3dlut { 921 struct kref refcount; 922 struct tetrahedral_params lut_3d; 923 struct fixed31_32 hdr_multiplier; 924 union dc_3dlut_state state; 925 }; 926 /* 927 * This structure is filled in by dc_surface_get_status and contains 928 * the last requested address and the currently active address so the called 929 * can determine if there are any outstanding flips 930 */ 931 struct dc_plane_status { 932 struct dc_plane_address requested_address; 933 struct dc_plane_address current_address; 934 bool is_flip_pending; 935 bool is_right_eye; 936 }; 937 938 union surface_update_flags { 939 940 struct { 941 uint32_t addr_update:1; 942 /* Medium updates */ 943 uint32_t dcc_change:1; 944 uint32_t color_space_change:1; 945 uint32_t horizontal_mirror_change:1; 946 uint32_t per_pixel_alpha_change:1; 947 uint32_t global_alpha_change:1; 948 uint32_t hdr_mult:1; 949 uint32_t rotation_change:1; 950 uint32_t swizzle_change:1; 951 uint32_t scaling_change:1; 952 uint32_t position_change:1; 953 uint32_t in_transfer_func_change:1; 954 uint32_t input_csc_change:1; 955 uint32_t coeff_reduction_change:1; 956 uint32_t output_tf_change:1; 957 uint32_t pixel_format_change:1; 958 uint32_t plane_size_change:1; 959 uint32_t gamut_remap_change:1; 960 961 /* Full updates */ 962 uint32_t new_plane:1; 963 uint32_t bpp_change:1; 964 uint32_t gamma_change:1; 965 uint32_t bandwidth_change:1; 966 uint32_t clock_change:1; 967 uint32_t stereo_format_change:1; 968 uint32_t lut_3d:1; 969 uint32_t full_update:1; 970 } bits; 971 972 uint32_t raw; 973 }; 974 975 struct dc_plane_state { 976 struct dc_plane_address address; 977 struct dc_plane_flip_time time; 978 bool triplebuffer_flips; 979 struct scaling_taps scaling_quality; 980 struct rect src_rect; 981 struct rect dst_rect; 982 struct rect clip_rect; 983 984 struct plane_size plane_size; 985 union dc_tiling_info tiling_info; 986 987 struct dc_plane_dcc_param dcc; 988 989 struct dc_gamma *gamma_correction; 990 struct dc_transfer_func *in_transfer_func; 991 struct dc_bias_and_scale *bias_and_scale; 992 struct dc_csc_transform input_csc_color_matrix; 993 struct fixed31_32 coeff_reduction_factor; 994 struct fixed31_32 hdr_mult; 995 struct colorspace_transform gamut_remap_matrix; 996 997 // TODO: No longer used, remove 998 struct dc_hdr_static_metadata hdr_static_ctx; 999 1000 enum dc_color_space color_space; 1001 1002 struct dc_3dlut *lut3d_func; 1003 struct dc_transfer_func *in_shaper_func; 1004 struct dc_transfer_func *blend_tf; 1005 1006 #if defined(CONFIG_DRM_AMD_DC_DCN) 1007 struct dc_transfer_func *gamcor_tf; 1008 #endif 1009 enum surface_pixel_format format; 1010 enum dc_rotation_angle rotation; 1011 enum plane_stereo_format stereo_format; 1012 1013 bool is_tiling_rotated; 1014 bool per_pixel_alpha; 1015 bool global_alpha; 1016 int global_alpha_value; 1017 bool visible; 1018 bool flip_immediate; 1019 bool horizontal_mirror; 1020 int layer_index; 1021 1022 union surface_update_flags update_flags; 1023 bool flip_int_enabled; 1024 bool skip_manual_trigger; 1025 1026 /* private to DC core */ 1027 struct dc_plane_status status; 1028 struct dc_context *ctx; 1029 1030 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1031 bool force_full_update; 1032 1033 /* private to dc_surface.c */ 1034 enum dc_irq_source irq_source; 1035 struct kref refcount; 1036 }; 1037 1038 struct dc_plane_info { 1039 struct plane_size plane_size; 1040 union dc_tiling_info tiling_info; 1041 struct dc_plane_dcc_param dcc; 1042 enum surface_pixel_format format; 1043 enum dc_rotation_angle rotation; 1044 enum plane_stereo_format stereo_format; 1045 enum dc_color_space color_space; 1046 bool horizontal_mirror; 1047 bool visible; 1048 bool per_pixel_alpha; 1049 bool global_alpha; 1050 int global_alpha_value; 1051 bool input_csc_enabled; 1052 int layer_index; 1053 }; 1054 1055 struct dc_scaling_info { 1056 struct rect src_rect; 1057 struct rect dst_rect; 1058 struct rect clip_rect; 1059 struct scaling_taps scaling_quality; 1060 }; 1061 1062 struct dc_surface_update { 1063 struct dc_plane_state *surface; 1064 1065 /* isr safe update parameters. null means no updates */ 1066 const struct dc_flip_addrs *flip_addr; 1067 const struct dc_plane_info *plane_info; 1068 const struct dc_scaling_info *scaling_info; 1069 struct fixed31_32 hdr_mult; 1070 /* following updates require alloc/sleep/spin that is not isr safe, 1071 * null means no updates 1072 */ 1073 const struct dc_gamma *gamma; 1074 const struct dc_transfer_func *in_transfer_func; 1075 1076 const struct dc_csc_transform *input_csc_color_matrix; 1077 const struct fixed31_32 *coeff_reduction_factor; 1078 const struct dc_transfer_func *func_shaper; 1079 const struct dc_3dlut *lut3d_func; 1080 const struct dc_transfer_func *blend_tf; 1081 const struct colorspace_transform *gamut_remap_matrix; 1082 }; 1083 1084 /* 1085 * Create a new surface with default parameters; 1086 */ 1087 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1088 const struct dc_plane_status *dc_plane_get_status( 1089 const struct dc_plane_state *plane_state); 1090 1091 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1092 void dc_plane_state_release(struct dc_plane_state *plane_state); 1093 1094 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1095 void dc_gamma_release(struct dc_gamma **dc_gamma); 1096 struct dc_gamma *dc_create_gamma(void); 1097 1098 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1099 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1100 struct dc_transfer_func *dc_create_transfer_func(void); 1101 1102 struct dc_3dlut *dc_create_3dlut_func(void); 1103 void dc_3dlut_func_release(struct dc_3dlut *lut); 1104 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1105 /* 1106 * This structure holds a surface address. There could be multiple addresses 1107 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1108 * as frame durations and DCC format can also be set. 1109 */ 1110 struct dc_flip_addrs { 1111 struct dc_plane_address address; 1112 unsigned int flip_timestamp_in_us; 1113 bool flip_immediate; 1114 /* TODO: add flip duration for FreeSync */ 1115 bool triplebuffer_flips; 1116 }; 1117 1118 void dc_post_update_surfaces_to_stream( 1119 struct dc *dc); 1120 1121 #include "dc_stream.h" 1122 1123 /* 1124 * Structure to store surface/stream associations for validation 1125 */ 1126 struct dc_validation_set { 1127 struct dc_stream_state *stream; 1128 struct dc_plane_state *plane_states[MAX_SURFACES]; 1129 uint8_t plane_count; 1130 }; 1131 1132 bool dc_validate_boot_timing(const struct dc *dc, 1133 const struct dc_sink *sink, 1134 struct dc_crtc_timing *crtc_timing); 1135 1136 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1137 1138 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1139 1140 bool dc_set_generic_gpio_for_stereo(bool enable, 1141 struct gpio_service *gpio_service); 1142 1143 /* 1144 * fast_validate: we return after determining if we can support the new state, 1145 * but before we populate the programming info 1146 */ 1147 enum dc_status dc_validate_global_state( 1148 struct dc *dc, 1149 struct dc_state *new_ctx, 1150 bool fast_validate); 1151 1152 1153 void dc_resource_state_construct( 1154 const struct dc *dc, 1155 struct dc_state *dst_ctx); 1156 1157 #if defined(CONFIG_DRM_AMD_DC_DCN) 1158 bool dc_acquire_release_mpc_3dlut( 1159 struct dc *dc, bool acquire, 1160 struct dc_stream_state *stream, 1161 struct dc_3dlut **lut, 1162 struct dc_transfer_func **shaper); 1163 #endif 1164 1165 void dc_resource_state_copy_construct( 1166 const struct dc_state *src_ctx, 1167 struct dc_state *dst_ctx); 1168 1169 void dc_resource_state_copy_construct_current( 1170 const struct dc *dc, 1171 struct dc_state *dst_ctx); 1172 1173 void dc_resource_state_destruct(struct dc_state *context); 1174 1175 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1176 1177 /* 1178 * TODO update to make it about validation sets 1179 * Set up streams and links associated to drive sinks 1180 * The streams parameter is an absolute set of all active streams. 1181 * 1182 * After this call: 1183 * Phy, Encoder, Timing Generator are programmed and enabled. 1184 * New streams are enabled with blank stream; no memory read. 1185 */ 1186 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1187 1188 struct dc_state *dc_create_state(struct dc *dc); 1189 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1190 void dc_retain_state(struct dc_state *context); 1191 void dc_release_state(struct dc_state *context); 1192 1193 /******************************************************************************* 1194 * Link Interfaces 1195 ******************************************************************************/ 1196 1197 struct dpcd_caps { 1198 union dpcd_rev dpcd_rev; 1199 union max_lane_count max_ln_count; 1200 union max_down_spread max_down_spread; 1201 union dprx_feature dprx_feature; 1202 1203 /* valid only for eDP v1.4 or higher*/ 1204 uint8_t edp_supported_link_rates_count; 1205 enum dc_link_rate edp_supported_link_rates[8]; 1206 1207 /* dongle type (DP converter, CV smart dongle) */ 1208 enum display_dongle_type dongle_type; 1209 bool is_dongle_type_one; 1210 /* branch device or sink device */ 1211 bool is_branch_dev; 1212 /* Dongle's downstream count. */ 1213 union sink_count sink_count; 1214 bool is_mst_capable; 1215 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1216 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1217 struct dc_dongle_caps dongle_caps; 1218 1219 uint32_t sink_dev_id; 1220 int8_t sink_dev_id_str[6]; 1221 int8_t sink_hw_revision; 1222 int8_t sink_fw_revision[2]; 1223 1224 uint32_t branch_dev_id; 1225 int8_t branch_dev_name[6]; 1226 int8_t branch_hw_revision; 1227 int8_t branch_fw_revision[2]; 1228 1229 bool allow_invalid_MSA_timing_param; 1230 bool panel_mode_edp; 1231 bool dpcd_display_control_capable; 1232 bool ext_receiver_cap_field_present; 1233 bool dynamic_backlight_capable_edp; 1234 union dpcd_fec_capability fec_cap; 1235 struct dpcd_dsc_capabilities dsc_caps; 1236 struct dc_lttpr_caps lttpr_caps; 1237 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1238 1239 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1240 union dp_main_line_channel_coding_cap channel_coding_cap; 1241 union dp_sink_video_fallback_formats fallback_formats; 1242 union dp_fec_capability1 fec_cap1; 1243 union dp_cable_id cable_id; 1244 uint8_t edp_rev; 1245 union edp_alpm_caps alpm_caps; 1246 struct edp_psr_info psr_info; 1247 }; 1248 1249 union dpcd_sink_ext_caps { 1250 struct { 1251 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1252 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1253 */ 1254 uint8_t sdr_aux_backlight_control : 1; 1255 uint8_t hdr_aux_backlight_control : 1; 1256 uint8_t reserved_1 : 2; 1257 uint8_t oled : 1; 1258 uint8_t reserved : 3; 1259 } bits; 1260 uint8_t raw; 1261 }; 1262 1263 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1264 union hdcp_rx_caps { 1265 struct { 1266 uint8_t version; 1267 uint8_t reserved; 1268 struct { 1269 uint8_t repeater : 1; 1270 uint8_t hdcp_capable : 1; 1271 uint8_t reserved : 6; 1272 } byte0; 1273 } fields; 1274 uint8_t raw[3]; 1275 }; 1276 1277 union hdcp_bcaps { 1278 struct { 1279 uint8_t HDCP_CAPABLE:1; 1280 uint8_t REPEATER:1; 1281 uint8_t RESERVED:6; 1282 } bits; 1283 uint8_t raw; 1284 }; 1285 1286 struct hdcp_caps { 1287 union hdcp_rx_caps rx_caps; 1288 union hdcp_bcaps bcaps; 1289 }; 1290 #endif 1291 1292 #include "dc_link.h" 1293 1294 #if defined(CONFIG_DRM_AMD_DC_DCN) 1295 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1296 1297 #endif 1298 /******************************************************************************* 1299 * Sink Interfaces - A sink corresponds to a display output device 1300 ******************************************************************************/ 1301 1302 struct dc_container_id { 1303 // 128bit GUID in binary form 1304 unsigned char guid[16]; 1305 // 8 byte port ID -> ELD.PortID 1306 unsigned int portId[2]; 1307 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1308 unsigned short manufacturerName; 1309 // 2 byte product code -> ELD.ProductCode 1310 unsigned short productCode; 1311 }; 1312 1313 1314 struct dc_sink_dsc_caps { 1315 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1316 // 'false' if they are sink's DSC caps 1317 bool is_virtual_dpcd_dsc; 1318 #if defined(CONFIG_DRM_AMD_DC_DCN) 1319 // 'true' if MST topology supports DSC passthrough for sink 1320 // 'false' if MST topology does not support DSC passthrough 1321 bool is_dsc_passthrough_supported; 1322 #endif 1323 struct dsc_dec_dpcd_caps dsc_dec_caps; 1324 }; 1325 1326 struct dc_sink_fec_caps { 1327 bool is_rx_fec_supported; 1328 bool is_topology_fec_supported; 1329 }; 1330 1331 /* 1332 * The sink structure contains EDID and other display device properties 1333 */ 1334 struct dc_sink { 1335 enum signal_type sink_signal; 1336 struct dc_edid dc_edid; /* raw edid */ 1337 struct dc_edid_caps edid_caps; /* parse display caps */ 1338 struct dc_container_id *dc_container_id; 1339 uint32_t dongle_max_pix_clk; 1340 void *priv; 1341 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1342 bool converter_disable_audio; 1343 1344 struct dc_sink_dsc_caps dsc_caps; 1345 struct dc_sink_fec_caps fec_caps; 1346 1347 bool is_vsc_sdp_colorimetry_supported; 1348 1349 /* private to DC core */ 1350 struct dc_link *link; 1351 struct dc_context *ctx; 1352 1353 uint32_t sink_id; 1354 1355 /* private to dc_sink.c */ 1356 // refcount must be the last member in dc_sink, since we want the 1357 // sink structure to be logically cloneable up to (but not including) 1358 // refcount 1359 struct kref refcount; 1360 }; 1361 1362 void dc_sink_retain(struct dc_sink *sink); 1363 void dc_sink_release(struct dc_sink *sink); 1364 1365 struct dc_sink_init_data { 1366 enum signal_type sink_signal; 1367 struct dc_link *link; 1368 uint32_t dongle_max_pix_clk; 1369 bool converter_disable_audio; 1370 }; 1371 1372 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1373 1374 /* Newer interfaces */ 1375 struct dc_cursor { 1376 struct dc_plane_address address; 1377 struct dc_cursor_attributes attributes; 1378 }; 1379 1380 1381 /******************************************************************************* 1382 * Interrupt interfaces 1383 ******************************************************************************/ 1384 enum dc_irq_source dc_interrupt_to_irq_source( 1385 struct dc *dc, 1386 uint32_t src_id, 1387 uint32_t ext_id); 1388 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1389 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1390 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1391 struct dc *dc, uint32_t link_index); 1392 1393 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1394 1395 /******************************************************************************* 1396 * Power Interfaces 1397 ******************************************************************************/ 1398 1399 void dc_set_power_state( 1400 struct dc *dc, 1401 enum dc_acpi_cm_power_state power_state); 1402 void dc_resume(struct dc *dc); 1403 1404 void dc_power_down_on_boot(struct dc *dc); 1405 1406 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1407 /* 1408 * HDCP Interfaces 1409 */ 1410 enum hdcp_message_status dc_process_hdcp_msg( 1411 enum signal_type signal, 1412 struct dc_link *link, 1413 struct hdcp_protection_message *message_info); 1414 #endif 1415 bool dc_is_dmcu_initialized(struct dc *dc); 1416 1417 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1418 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1419 #if defined(CONFIG_DRM_AMD_DC_DCN) 1420 1421 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1422 struct dc_cursor_attributes *cursor_attr); 1423 1424 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1425 1426 /* 1427 * blank all streams, and set min and max memory clock to 1428 * lowest and highest DPM level, respectively 1429 */ 1430 void dc_unlock_memory_clock_frequency(struct dc *dc); 1431 1432 /* 1433 * set min memory clock to the min required for current mode, 1434 * max to maxDPM, and unblank streams 1435 */ 1436 void dc_lock_memory_clock_frequency(struct dc *dc); 1437 1438 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1439 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1440 1441 /* cleanup on driver unload */ 1442 void dc_hardware_release(struct dc *dc); 1443 1444 #endif 1445 1446 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1447 #if defined(CONFIG_DRM_AMD_DC_DCN) 1448 void dc_z10_restore(const struct dc *dc); 1449 void dc_z10_save_init(struct dc *dc); 1450 #endif 1451 1452 bool dc_is_dmub_outbox_supported(struct dc *dc); 1453 bool dc_enable_dmub_notifications(struct dc *dc); 1454 1455 void dc_enable_dmub_outbox(struct dc *dc); 1456 1457 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1458 uint32_t link_index, 1459 struct aux_payload *payload); 1460 1461 /* Get dc link index from dpia port index */ 1462 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1463 uint8_t dpia_port_index); 1464 1465 bool dc_process_dmub_set_config_async(struct dc *dc, 1466 uint32_t link_index, 1467 struct set_config_cmd_payload *payload, 1468 struct dmub_notification *notify); 1469 1470 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1471 uint32_t link_index, 1472 uint8_t mst_alloc_slots, 1473 uint8_t *mst_slots_in_use); 1474 1475 /******************************************************************************* 1476 * DSC Interfaces 1477 ******************************************************************************/ 1478 #include "dc_dsc.h" 1479 1480 /******************************************************************************* 1481 * Disable acc mode Interfaces 1482 ******************************************************************************/ 1483 void dc_disable_accelerated_mode(struct dc *dc); 1484 1485 #endif /* DC_INTERFACE_H_ */ 1486