xref: /linux/drivers/gpu/drm/amd/display/dc/dc.h (revision 170aafe35cb98e0f3fbacb446ea86389fbce22ea)
1 /*
2  * Copyright 2012-2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
28 
29 #include "dc_types.h"
30 #include "dc_state.h"
31 #include "dc_plane.h"
32 #include "grph_object_defs.h"
33 #include "logger_types.h"
34 #include "hdcp_msg_types.h"
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
39 
40 #include "hwss/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
44 
45 #include "dml2/dml2_wrapper.h"
46 
47 #include "dmub/inc/dmub_cmd.h"
48 
49 #include "spl/dc_spl_types.h"
50 
51 struct abm_save_restore;
52 
53 /* forward declaration */
54 struct aux_payload;
55 struct set_config_cmd_payload;
56 struct dmub_notification;
57 
58 #define DC_VER "3.2.291"
59 
60 #define MAX_SURFACES 3
61 #define MAX_PLANES 6
62 #define MAX_STREAMS 6
63 #define MIN_VIEWPORT_SIZE 12
64 #define MAX_NUM_EDP 2
65 #define MAX_HOST_ROUTERS_NUM 2
66 
67 /* Display Core Interfaces */
68 struct dc_versions {
69 	const char *dc_ver;
70 	struct dmcu_version dmcu_version;
71 };
72 
73 enum dp_protocol_version {
74 	DP_VERSION_1_4 = 0,
75 	DP_VERSION_2_1,
76 	DP_VERSION_UNKNOWN,
77 };
78 
79 enum dc_plane_type {
80 	DC_PLANE_TYPE_INVALID,
81 	DC_PLANE_TYPE_DCE_RGB,
82 	DC_PLANE_TYPE_DCE_UNDERLAY,
83 	DC_PLANE_TYPE_DCN_UNIVERSAL,
84 };
85 
86 // Sizes defined as multiples of 64KB
87 enum det_size {
88 	DET_SIZE_DEFAULT = 0,
89 	DET_SIZE_192KB = 3,
90 	DET_SIZE_256KB = 4,
91 	DET_SIZE_320KB = 5,
92 	DET_SIZE_384KB = 6
93 };
94 
95 
96 struct dc_plane_cap {
97 	enum dc_plane_type type;
98 	uint32_t per_pixel_alpha : 1;
99 	struct {
100 		uint32_t argb8888 : 1;
101 		uint32_t nv12 : 1;
102 		uint32_t fp16 : 1;
103 		uint32_t p010 : 1;
104 		uint32_t ayuv : 1;
105 	} pixel_format_support;
106 	// max upscaling factor x1000
107 	// upscaling factors are always >= 1
108 	// for example, 1080p -> 8K is 4.0, or 4000 raw value
109 	struct {
110 		uint32_t argb8888;
111 		uint32_t nv12;
112 		uint32_t fp16;
113 	} max_upscale_factor;
114 	// max downscale factor x1000
115 	// downscale factors are always <= 1
116 	// for example, 8K -> 1080p is 0.25, or 250 raw value
117 	struct {
118 		uint32_t argb8888;
119 		uint32_t nv12;
120 		uint32_t fp16;
121 	} max_downscale_factor;
122 	// minimal width/height
123 	uint32_t min_width;
124 	uint32_t min_height;
125 };
126 
127 /**
128  * DOC: color-management-caps
129  *
130  * **Color management caps (DPP and MPC)**
131  *
132  * Modules/color calculates various color operations which are translated to
133  * abstracted HW. DCE 5-12 had almost no important changes, but starting with
134  * DCN1, every new generation comes with fairly major differences in color
135  * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
136  * decide mapping to HW block based on logical capabilities.
137  */
138 
139 /**
140  * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
141  * @srgb: RGB color space transfer func
142  * @bt2020: BT.2020 transfer func
143  * @gamma2_2: standard gamma
144  * @pq: perceptual quantizer transfer function
145  * @hlg: hybrid log–gamma transfer function
146  */
147 struct rom_curve_caps {
148 	uint16_t srgb : 1;
149 	uint16_t bt2020 : 1;
150 	uint16_t gamma2_2 : 1;
151 	uint16_t pq : 1;
152 	uint16_t hlg : 1;
153 };
154 
155 /**
156  * struct dpp_color_caps - color pipeline capabilities for display pipe and
157  * plane blocks
158  *
159  * @dcn_arch: all DCE generations treated the same
160  * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
161  * just plain 256-entry lookup
162  * @icsc: input color space conversion
163  * @dgam_ram: programmable degamma LUT
164  * @post_csc: post color space conversion, before gamut remap
165  * @gamma_corr: degamma correction
166  * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
167  * with MPC by setting mpc:shared_3d_lut flag
168  * @ogam_ram: programmable out/blend gamma LUT
169  * @ocsc: output color space conversion
170  * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171  * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
172  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
173  *
174  * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
175  */
176 struct dpp_color_caps {
177 	uint16_t dcn_arch : 1;
178 	uint16_t input_lut_shared : 1;
179 	uint16_t icsc : 1;
180 	uint16_t dgam_ram : 1;
181 	uint16_t post_csc : 1;
182 	uint16_t gamma_corr : 1;
183 	uint16_t hw_3d_lut : 1;
184 	uint16_t ogam_ram : 1;
185 	uint16_t ocsc : 1;
186 	uint16_t dgam_rom_for_yuv : 1;
187 	struct rom_curve_caps dgam_rom_caps;
188 	struct rom_curve_caps ogam_rom_caps;
189 };
190 
191 /**
192  * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
193  * plane combined blocks
194  *
195  * @gamut_remap: color transformation matrix
196  * @ogam_ram: programmable out gamma LUT
197  * @ocsc: output color space conversion matrix
198  * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
199  * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
200  * instance
201  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
202  */
203 struct mpc_color_caps {
204 	uint16_t gamut_remap : 1;
205 	uint16_t ogam_ram : 1;
206 	uint16_t ocsc : 1;
207 	uint16_t num_3dluts : 3;
208 	uint16_t shared_3d_lut:1;
209 	struct rom_curve_caps ogam_rom_caps;
210 };
211 
212 /**
213  * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
214  * @dpp: color pipes caps for DPP
215  * @mpc: color pipes caps for MPC
216  */
217 struct dc_color_caps {
218 	struct dpp_color_caps dpp;
219 	struct mpc_color_caps mpc;
220 };
221 
222 struct dc_dmub_caps {
223 	bool psr;
224 	bool mclk_sw;
225 	bool subvp_psr;
226 	bool gecc_enable;
227 	uint8_t fams_ver;
228 };
229 
230 struct dc_caps {
231 	uint32_t max_streams;
232 	uint32_t max_links;
233 	uint32_t max_audios;
234 	uint32_t max_slave_planes;
235 	uint32_t max_slave_yuv_planes;
236 	uint32_t max_slave_rgb_planes;
237 	uint32_t max_planes;
238 	uint32_t max_downscale_ratio;
239 	uint32_t i2c_speed_in_khz;
240 	uint32_t i2c_speed_in_khz_hdcp;
241 	uint32_t dmdata_alloc_size;
242 	unsigned int max_cursor_size;
243 	unsigned int max_video_width;
244 	/*
245 	 * max video plane width that can be safely assumed to be always
246 	 * supported by single DPP pipe.
247 	 */
248 	unsigned int max_optimizable_video_width;
249 	unsigned int min_horizontal_blanking_period;
250 	int linear_pitch_alignment;
251 	bool dcc_const_color;
252 	bool dynamic_audio;
253 	bool is_apu;
254 	bool dual_link_dvi;
255 	bool post_blend_color_processing;
256 	bool force_dp_tps4_for_cp2520;
257 	bool disable_dp_clk_share;
258 	bool psp_setup_panel_mode;
259 	bool extended_aux_timeout_support;
260 	bool dmcub_support;
261 	bool zstate_support;
262 	bool ips_support;
263 	uint32_t num_of_internal_disp;
264 	uint32_t max_dwb_htap;
265 	uint32_t max_dwb_vtap;
266 	enum dp_protocol_version max_dp_protocol_version;
267 	bool spdif_aud;
268 	unsigned int mall_size_per_mem_channel;
269 	unsigned int mall_size_total;
270 	unsigned int cursor_cache_size;
271 	struct dc_plane_cap planes[MAX_PLANES];
272 	struct dc_color_caps color;
273 	struct dc_dmub_caps dmub_caps;
274 	bool dp_hpo;
275 	bool dp_hdmi21_pcon_support;
276 	bool edp_dsc_support;
277 	bool vbios_lttpr_aware;
278 	bool vbios_lttpr_enable;
279 	uint32_t max_otg_num;
280 	uint32_t max_cab_allocation_bytes;
281 	uint32_t cache_line_size;
282 	uint32_t cache_num_ways;
283 	uint16_t subvp_fw_processing_delay_us;
284 	uint8_t subvp_drr_max_vblank_margin_us;
285 	uint16_t subvp_prefetch_end_to_mall_start_us;
286 	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
287 	uint16_t subvp_pstate_allow_width_us;
288 	uint16_t subvp_vertical_int_margin_us;
289 	bool seamless_odm;
290 	uint32_t max_v_total;
291 	uint32_t max_disp_clock_khz_at_vmin;
292 	uint8_t subvp_drr_vblank_start_margin_us;
293 	bool cursor_not_scaled;
294 	bool dcmode_power_limits_present;
295 	bool sequential_ono;
296 	/* Conservative limit for DCC cases which require ODM4:1 to support*/
297 	uint32_t dcc_plane_width_limit;
298 };
299 
300 struct dc_bug_wa {
301 	bool no_connect_phy_config;
302 	bool dedcn20_305_wa;
303 	bool skip_clock_update;
304 	bool lt_early_cr_pattern;
305 	struct {
306 		uint8_t uclk : 1;
307 		uint8_t fclk : 1;
308 		uint8_t dcfclk : 1;
309 		uint8_t dcfclk_ds: 1;
310 	} clock_update_disable_mask;
311 	bool skip_psr_ips_crtc_disable;
312 	//Customer Specific WAs
313 	uint32_t force_backlight_start_level;
314 };
315 struct dc_dcc_surface_param {
316 	struct dc_size surface_size;
317 	enum surface_pixel_format format;
318 	unsigned int plane0_pitch;
319 	struct dc_size plane1_size;
320 	unsigned int plane1_pitch;
321 	union {
322 		enum swizzle_mode_values swizzle_mode;
323 		enum swizzle_mode_addr3_values swizzle_mode_addr3;
324 	};
325 	enum dc_scan_direction scan;
326 };
327 
328 struct dc_dcc_setting {
329 	unsigned int max_compressed_blk_size;
330 	unsigned int max_uncompressed_blk_size;
331 	bool independent_64b_blks;
332 	//These bitfields to be used starting with DCN 3.0
333 	struct {
334 		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
335 		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN 3.0
336 		uint32_t dcc_256_128_128 : 1;		//available starting with DCN 3.0
337 		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN 3.0 (the best compression case)
338 		uint32_t dcc_256_256 : 1;  //available in ASICs starting with DCN 4.0x (the best compression case)
339 		uint32_t dcc_256_128 : 1;  //available in ASICs starting with DCN 4.0x
340 		uint32_t dcc_256_64 : 1;   //available in ASICs starting with DCN 4.0x (the worst compression case)
341 	} dcc_controls;
342 };
343 
344 struct dc_surface_dcc_cap {
345 	union {
346 		struct {
347 			struct dc_dcc_setting rgb;
348 		} grph;
349 
350 		struct {
351 			struct dc_dcc_setting luma;
352 			struct dc_dcc_setting chroma;
353 		} video;
354 	};
355 
356 	bool capable;
357 	bool const_color_support;
358 };
359 
360 struct dc_static_screen_params {
361 	struct {
362 		bool force_trigger;
363 		bool cursor_update;
364 		bool surface_update;
365 		bool overlay_update;
366 	} triggers;
367 	unsigned int num_frames;
368 };
369 
370 
371 /* Surface update type is used by dc_update_surfaces_and_stream
372  * The update type is determined at the very beginning of the function based
373  * on parameters passed in and decides how much programming (or updating) is
374  * going to be done during the call.
375  *
376  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
377  * logical calculations or hardware register programming. This update MUST be
378  * ISR safe on windows. Currently fast update will only be used to flip surface
379  * address.
380  *
381  * UPDATE_TYPE_MED is used for slower updates which require significant hw
382  * re-programming however do not affect bandwidth consumption or clock
383  * requirements. At present, this is the level at which front end updates
384  * that do not require us to run bw_calcs happen. These are in/out transfer func
385  * updates, viewport offset changes, recout size changes and pixel depth changes.
386  * This update can be done at ISR, but we want to minimize how often this happens.
387  *
388  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
389  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
390  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
391  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
392  * a full update. This cannot be done at ISR level and should be a rare event.
393  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
394  * underscan we don't expect to see this call at all.
395  */
396 
397 enum surface_update_type {
398 	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
399 	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
400 	UPDATE_TYPE_FULL, /* may need to shuffle resources */
401 };
402 
403 /* Forward declaration*/
404 struct dc;
405 struct dc_plane_state;
406 struct dc_state;
407 
408 struct dc_cap_funcs {
409 	bool (*get_dcc_compression_cap)(const struct dc *dc,
410 			const struct dc_dcc_surface_param *input,
411 			struct dc_surface_dcc_cap *output);
412 	bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
413 };
414 
415 struct link_training_settings;
416 
417 union allow_lttpr_non_transparent_mode {
418 	struct {
419 		bool DP1_4A : 1;
420 		bool DP2_0 : 1;
421 	} bits;
422 	unsigned char raw;
423 };
424 
425 /* Structure to hold configuration flags set by dm at dc creation. */
426 struct dc_config {
427 	bool gpu_vm_support;
428 	bool disable_disp_pll_sharing;
429 	bool fbc_support;
430 	bool disable_fractional_pwm;
431 	bool allow_seamless_boot_optimization;
432 	bool seamless_boot_edp_requested;
433 	bool edp_not_connected;
434 	bool edp_no_power_sequencing;
435 	bool force_enum_edp;
436 	bool forced_clocks;
437 	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
438 	bool multi_mon_pp_mclk_switch;
439 	bool disable_dmcu;
440 	bool enable_4to1MPC;
441 	bool enable_windowed_mpo_odm;
442 	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
443 	uint32_t allow_edp_hotplug_detection;
444 	bool clamp_min_dcfclk;
445 	uint64_t vblank_alignment_dto_params;
446 	uint8_t  vblank_alignment_max_frame_time_diff;
447 	bool is_asymmetric_memory;
448 	bool is_single_rank_dimm;
449 	bool is_vmin_only_asic;
450 	bool use_spl;
451 	bool prefer_easf;
452 	bool use_pipe_ctx_sync_logic;
453 	bool ignore_dpref_ss;
454 	bool enable_mipi_converter_optimization;
455 	bool use_default_clock_table;
456 	bool force_bios_enable_lttpr;
457 	uint8_t force_bios_fixed_vs;
458 	int sdpif_request_limit_words_per_umc;
459 	bool dc_mode_clk_limit_support;
460 	bool EnableMinDispClkODM;
461 	bool enable_auto_dpm_test_logs;
462 	unsigned int disable_ips;
463 	unsigned int disable_ips_in_vpb;
464 	bool usb4_bw_alloc_support;
465 	bool allow_0_dtb_clk;
466 	bool use_assr_psp_message;
467 	bool support_edp0_on_dp1;
468 	unsigned int enable_fpo_flicker_detection;
469 };
470 
471 enum visual_confirm {
472 	VISUAL_CONFIRM_DISABLE = 0,
473 	VISUAL_CONFIRM_SURFACE = 1,
474 	VISUAL_CONFIRM_HDR = 2,
475 	VISUAL_CONFIRM_MPCTREE = 4,
476 	VISUAL_CONFIRM_PSR = 5,
477 	VISUAL_CONFIRM_SWAPCHAIN = 6,
478 	VISUAL_CONFIRM_FAMS = 7,
479 	VISUAL_CONFIRM_SWIZZLE = 9,
480 	VISUAL_CONFIRM_REPLAY = 12,
481 	VISUAL_CONFIRM_SUBVP = 14,
482 	VISUAL_CONFIRM_MCLK_SWITCH = 16,
483 	VISUAL_CONFIRM_FAMS2 = 19,
484 	VISUAL_CONFIRM_HW_CURSOR = 20,
485 };
486 
487 enum dc_psr_power_opts {
488 	psr_power_opt_invalid = 0x0,
489 	psr_power_opt_smu_opt_static_screen = 0x1,
490 	psr_power_opt_z10_static_screen = 0x10,
491 	psr_power_opt_ds_disable_allow = 0x100,
492 };
493 
494 enum dml_hostvm_override_opts {
495 	DML_HOSTVM_NO_OVERRIDE = 0x0,
496 	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
497 	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
498 };
499 
500 enum dc_replay_power_opts {
501 	replay_power_opt_invalid		= 0x0,
502 	replay_power_opt_smu_opt_static_screen	= 0x1,
503 	replay_power_opt_z10_static_screen	= 0x10,
504 };
505 
506 enum dcc_option {
507 	DCC_ENABLE = 0,
508 	DCC_DISABLE = 1,
509 	DCC_HALF_REQ_DISALBE = 2,
510 };
511 
512 enum in_game_fams_config {
513 	INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
514 	INGAME_FAMS_DISABLE, // disable in-game fams
515 	INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
516 };
517 
518 /**
519  * enum pipe_split_policy - Pipe split strategy supported by DCN
520  *
521  * This enum is used to define the pipe split policy supported by DCN. By
522  * default, DC favors MPC_SPLIT_DYNAMIC.
523  */
524 enum pipe_split_policy {
525 	/**
526 	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
527 	 * pipe in order to bring the best trade-off between performance and
528 	 * power consumption. This is the recommended option.
529 	 */
530 	MPC_SPLIT_DYNAMIC = 0,
531 
532 	/**
533 	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
534 	 * try any sort of split optimization.
535 	 */
536 	MPC_SPLIT_AVOID = 1,
537 
538 	/**
539 	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
540 	 * optimize the pipe utilization when using a single display; if the
541 	 * user connects to a second display, DC will avoid pipe split.
542 	 */
543 	MPC_SPLIT_AVOID_MULT_DISP = 2,
544 };
545 
546 enum wm_report_mode {
547 	WM_REPORT_DEFAULT = 0,
548 	WM_REPORT_OVERRIDE = 1,
549 };
550 enum dtm_pstate{
551 	dtm_level_p0 = 0,/*highest voltage*/
552 	dtm_level_p1,
553 	dtm_level_p2,
554 	dtm_level_p3,
555 	dtm_level_p4,/*when active_display_count = 0*/
556 };
557 
558 enum dcn_pwr_state {
559 	DCN_PWR_STATE_UNKNOWN = -1,
560 	DCN_PWR_STATE_MISSION_MODE = 0,
561 	DCN_PWR_STATE_LOW_POWER = 3,
562 };
563 
564 enum dcn_zstate_support_state {
565 	DCN_ZSTATE_SUPPORT_UNKNOWN,
566 	DCN_ZSTATE_SUPPORT_ALLOW,
567 	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
568 	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
569 	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
570 	DCN_ZSTATE_SUPPORT_DISALLOW,
571 };
572 
573 /*
574  * struct dc_clocks - DC pipe clocks
575  *
576  * For any clocks that may differ per pipe only the max is stored in this
577  * structure
578  */
579 struct dc_clocks {
580 	int dispclk_khz;
581 	int actual_dispclk_khz;
582 	int dppclk_khz;
583 	int actual_dppclk_khz;
584 	int disp_dpp_voltage_level_khz;
585 	int dcfclk_khz;
586 	int socclk_khz;
587 	int dcfclk_deep_sleep_khz;
588 	int fclk_khz;
589 	int phyclk_khz;
590 	int dramclk_khz;
591 	bool p_state_change_support;
592 	enum dcn_zstate_support_state zstate_support;
593 	bool dtbclk_en;
594 	int ref_dtbclk_khz;
595 	bool fclk_p_state_change_support;
596 	enum dcn_pwr_state pwr_state;
597 	/*
598 	 * Elements below are not compared for the purposes of
599 	 * optimization required
600 	 */
601 	bool prev_p_state_change_support;
602 	bool fclk_prev_p_state_change_support;
603 	int num_ways;
604 	int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];
605 
606 	/*
607 	 * @fw_based_mclk_switching
608 	 *
609 	 * DC has a mechanism that leverage the variable refresh rate to switch
610 	 * memory clock in cases that we have a large latency to achieve the
611 	 * memory clock change and a short vblank window. DC has some
612 	 * requirements to enable this feature, and this field describes if the
613 	 * system support or not such a feature.
614 	 */
615 	bool fw_based_mclk_switching;
616 	bool fw_based_mclk_switching_shut_down;
617 	int prev_num_ways;
618 	enum dtm_pstate dtm_level;
619 	int max_supported_dppclk_khz;
620 	int max_supported_dispclk_khz;
621 	int bw_dppclk_khz; /*a copy of dppclk_khz*/
622 	int bw_dispclk_khz;
623 	int idle_dramclk_khz;
624 	int idle_fclk_khz;
625 };
626 
627 struct dc_bw_validation_profile {
628 	bool enable;
629 
630 	unsigned long long total_ticks;
631 	unsigned long long voltage_level_ticks;
632 	unsigned long long watermark_ticks;
633 	unsigned long long rq_dlg_ticks;
634 
635 	unsigned long long total_count;
636 	unsigned long long skip_fast_count;
637 	unsigned long long skip_pass_count;
638 	unsigned long long skip_fail_count;
639 };
640 
641 #define BW_VAL_TRACE_SETUP() \
642 		unsigned long long end_tick = 0; \
643 		unsigned long long voltage_level_tick = 0; \
644 		unsigned long long watermark_tick = 0; \
645 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
646 				dm_get_timestamp(dc->ctx) : 0
647 
648 #define BW_VAL_TRACE_COUNT() \
649 		if (dc->debug.bw_val_profile.enable) \
650 			dc->debug.bw_val_profile.total_count++
651 
652 #define BW_VAL_TRACE_SKIP(status) \
653 		if (dc->debug.bw_val_profile.enable) { \
654 			if (!voltage_level_tick) \
655 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
656 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
657 		}
658 
659 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
660 		if (dc->debug.bw_val_profile.enable) \
661 			voltage_level_tick = dm_get_timestamp(dc->ctx)
662 
663 #define BW_VAL_TRACE_END_WATERMARKS() \
664 		if (dc->debug.bw_val_profile.enable) \
665 			watermark_tick = dm_get_timestamp(dc->ctx)
666 
667 #define BW_VAL_TRACE_FINISH() \
668 		if (dc->debug.bw_val_profile.enable) { \
669 			end_tick = dm_get_timestamp(dc->ctx); \
670 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
671 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
672 			if (watermark_tick) { \
673 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
674 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
675 			} \
676 		}
677 
678 union mem_low_power_enable_options {
679 	struct {
680 		bool vga: 1;
681 		bool i2c: 1;
682 		bool dmcu: 1;
683 		bool dscl: 1;
684 		bool cm: 1;
685 		bool mpc: 1;
686 		bool optc: 1;
687 		bool vpg: 1;
688 		bool afmt: 1;
689 	} bits;
690 	uint32_t u32All;
691 };
692 
693 union root_clock_optimization_options {
694 	struct {
695 		bool dpp: 1;
696 		bool dsc: 1;
697 		bool hdmistream: 1;
698 		bool hdmichar: 1;
699 		bool dpstream: 1;
700 		bool symclk32_se: 1;
701 		bool symclk32_le: 1;
702 		bool symclk_fe: 1;
703 		bool physymclk: 1;
704 		bool dpiasymclk: 1;
705 		uint32_t reserved: 22;
706 	} bits;
707 	uint32_t u32All;
708 };
709 
710 union fine_grain_clock_gating_enable_options {
711 	struct {
712 		bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
713 		bool dchub : 1;	   /* Display controller hub */
714 		bool dchubbub : 1;
715 		bool dpp : 1;	   /* Display pipes and planes */
716 		bool opp : 1;	   /* Output pixel processing */
717 		bool optc : 1;	   /* Output pipe timing combiner */
718 		bool dio : 1;	   /* Display output */
719 		bool dwb : 1;	   /* Display writeback */
720 		bool mmhubbub : 1; /* Multimedia hub */
721 		bool dmu : 1;	   /* Display core management unit */
722 		bool az : 1;	   /* Azalia */
723 		bool dchvm : 1;
724 		bool dsc : 1;	   /* Display stream compression */
725 
726 		uint32_t reserved : 19;
727 	} bits;
728 	uint32_t u32All;
729 };
730 
731 enum pg_hw_pipe_resources {
732 	PG_HUBP = 0,
733 	PG_DPP,
734 	PG_DSC,
735 	PG_MPCC,
736 	PG_OPP,
737 	PG_OPTC,
738 	PG_DPSTREAM,
739 	PG_HDMISTREAM,
740 	PG_PHYSYMCLK,
741 	PG_HW_PIPE_RESOURCES_NUM_ELEMENT
742 };
743 
744 enum pg_hw_resources {
745 	PG_DCCG = 0,
746 	PG_DCIO,
747 	PG_DIO,
748 	PG_DCHUBBUB,
749 	PG_DCHVM,
750 	PG_DWB,
751 	PG_HPO,
752 	PG_HW_RESOURCES_NUM_ELEMENT
753 };
754 
755 struct pg_block_update {
756 	bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
757 	bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
758 };
759 
760 union dpia_debug_options {
761 	struct {
762 		uint32_t disable_dpia:1; /* bit 0 */
763 		uint32_t force_non_lttpr:1; /* bit 1 */
764 		uint32_t extend_aux_rd_interval:1; /* bit 2 */
765 		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
766 		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
767 		uint32_t reserved:27;
768 	} bits;
769 	uint32_t raw;
770 };
771 
772 /* AUX wake work around options
773  * 0: enable/disable work around
774  * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
775  * 15-2: reserved
776  * 31-16: timeout in ms
777  */
778 union aux_wake_wa_options {
779 	struct {
780 		uint32_t enable_wa : 1;
781 		uint32_t use_default_timeout : 1;
782 		uint32_t rsvd: 14;
783 		uint32_t timeout_ms : 16;
784 	} bits;
785 	uint32_t raw;
786 };
787 
788 struct dc_debug_data {
789 	uint32_t ltFailCount;
790 	uint32_t i2cErrorCount;
791 	uint32_t auxErrorCount;
792 };
793 
794 struct dc_phy_addr_space_config {
795 	struct {
796 		uint64_t start_addr;
797 		uint64_t end_addr;
798 		uint64_t fb_top;
799 		uint64_t fb_offset;
800 		uint64_t fb_base;
801 		uint64_t agp_top;
802 		uint64_t agp_bot;
803 		uint64_t agp_base;
804 	} system_aperture;
805 
806 	struct {
807 		uint64_t page_table_start_addr;
808 		uint64_t page_table_end_addr;
809 		uint64_t page_table_base_addr;
810 		bool base_addr_is_mc_addr;
811 	} gart_config;
812 
813 	bool valid;
814 	bool is_hvm_enabled;
815 	uint64_t page_table_default_page_addr;
816 };
817 
818 struct dc_virtual_addr_space_config {
819 	uint64_t	page_table_base_addr;
820 	uint64_t	page_table_start_addr;
821 	uint64_t	page_table_end_addr;
822 	uint32_t	page_table_block_size_in_bytes;
823 	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
824 };
825 
826 struct dc_bounding_box_overrides {
827 	int sr_exit_time_ns;
828 	int sr_enter_plus_exit_time_ns;
829 	int sr_exit_z8_time_ns;
830 	int sr_enter_plus_exit_z8_time_ns;
831 	int urgent_latency_ns;
832 	int percent_of_ideal_drambw;
833 	int dram_clock_change_latency_ns;
834 	int dummy_clock_change_latency_ns;
835 	int fclk_clock_change_latency_ns;
836 	/* This forces a hard min on the DCFCLK we use
837 	 * for DML.  Unlike the debug option for forcing
838 	 * DCFCLK, this override affects watermark calculations
839 	 */
840 	int min_dcfclk_mhz;
841 };
842 
843 struct dc_state;
844 struct resource_pool;
845 struct dce_hwseq;
846 struct link_service;
847 
848 /*
849  * struct dc_debug_options - DC debug struct
850  *
851  * This struct provides a simple mechanism for developers to change some
852  * configurations, enable/disable features, and activate extra debug options.
853  * This can be very handy to narrow down whether some specific feature is
854  * causing an issue or not.
855  */
856 struct dc_debug_options {
857 	bool native422_support;
858 	bool disable_dsc;
859 	enum visual_confirm visual_confirm;
860 	int visual_confirm_rect_height;
861 
862 	bool sanity_checks;
863 	bool max_disp_clk;
864 	bool surface_trace;
865 	bool timing_trace;
866 	bool clock_trace;
867 	bool validation_trace;
868 	bool bandwidth_calcs_trace;
869 	int max_downscale_src_width;
870 
871 	/* stutter efficiency related */
872 	bool disable_stutter;
873 	bool use_max_lb;
874 	enum dcc_option disable_dcc;
875 
876 	/*
877 	 * @pipe_split_policy: Define which pipe split policy is used by the
878 	 * display core.
879 	 */
880 	enum pipe_split_policy pipe_split_policy;
881 	bool force_single_disp_pipe_split;
882 	bool voltage_align_fclk;
883 	bool disable_min_fclk;
884 
885 	bool disable_dfs_bypass;
886 	bool disable_dpp_power_gate;
887 	bool disable_hubp_power_gate;
888 	bool disable_dsc_power_gate;
889 	bool disable_optc_power_gate;
890 	bool disable_hpo_power_gate;
891 	int dsc_min_slice_height_override;
892 	int dsc_bpp_increment_div;
893 	bool disable_pplib_wm_range;
894 	enum wm_report_mode pplib_wm_report_mode;
895 	unsigned int min_disp_clk_khz;
896 	unsigned int min_dpp_clk_khz;
897 	unsigned int min_dram_clk_khz;
898 	int sr_exit_time_dpm0_ns;
899 	int sr_enter_plus_exit_time_dpm0_ns;
900 	int sr_exit_time_ns;
901 	int sr_enter_plus_exit_time_ns;
902 	int sr_exit_z8_time_ns;
903 	int sr_enter_plus_exit_z8_time_ns;
904 	int urgent_latency_ns;
905 	uint32_t underflow_assert_delay_us;
906 	int percent_of_ideal_drambw;
907 	int dram_clock_change_latency_ns;
908 	bool optimized_watermark;
909 	int always_scale;
910 	bool disable_pplib_clock_request;
911 	bool disable_clock_gate;
912 	bool disable_mem_low_power;
913 	bool pstate_enabled;
914 	bool disable_dmcu;
915 	bool force_abm_enable;
916 	bool disable_stereo_support;
917 	bool vsr_support;
918 	bool performance_trace;
919 	bool az_endpoint_mute_only;
920 	bool always_use_regamma;
921 	bool recovery_enabled;
922 	bool avoid_vbios_exec_table;
923 	bool scl_reset_length10;
924 	bool hdmi20_disable;
925 	bool skip_detection_link_training;
926 	uint32_t edid_read_retry_times;
927 	unsigned int force_odm_combine; //bit vector based on otg inst
928 	unsigned int seamless_boot_odm_combine;
929 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
930 	int minimum_z8_residency_time;
931 	int minimum_z10_residency_time;
932 	bool disable_z9_mpc;
933 	unsigned int force_fclk_khz;
934 	bool enable_tri_buf;
935 	bool ips_disallow_entry;
936 	bool dmub_offload_enabled;
937 	bool dmcub_emulation;
938 	bool disable_idle_power_optimizations;
939 	unsigned int mall_size_override;
940 	unsigned int mall_additional_timer_percent;
941 	bool mall_error_as_fatal;
942 	bool dmub_command_table; /* for testing only */
943 	struct dc_bw_validation_profile bw_val_profile;
944 	bool disable_fec;
945 	bool disable_48mhz_pwrdwn;
946 	/* This forces a hard min on the DCFCLK requested to SMU/PP
947 	 * watermarks are not affected.
948 	 */
949 	unsigned int force_min_dcfclk_mhz;
950 	int dwb_fi_phase;
951 	bool disable_timing_sync;
952 	bool cm_in_bypass;
953 	int force_clock_mode;/*every mode change.*/
954 
955 	bool disable_dram_clock_change_vactive_support;
956 	bool validate_dml_output;
957 	bool enable_dmcub_surface_flip;
958 	bool usbc_combo_phy_reset_wa;
959 	bool enable_dram_clock_change_one_display_vactive;
960 	/* TODO - remove once tested */
961 	bool legacy_dp2_lt;
962 	bool set_mst_en_for_sst;
963 	bool disable_uhbr;
964 	bool force_dp2_lt_fallback_method;
965 	bool ignore_cable_id;
966 	union mem_low_power_enable_options enable_mem_low_power;
967 	union root_clock_optimization_options root_clock_optimization;
968 	union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
969 	bool hpo_optimization;
970 	bool force_vblank_alignment;
971 
972 	/* Enable dmub aux for legacy ddc */
973 	bool enable_dmub_aux_for_legacy_ddc;
974 	bool disable_fams;
975 	enum in_game_fams_config disable_fams_gaming;
976 	/* FEC/PSR1 sequence enable delay in 100us */
977 	uint8_t fec_enable_delay_in100us;
978 	bool enable_driver_sequence_debug;
979 	enum det_size crb_alloc_policy;
980 	int crb_alloc_policy_min_disp_count;
981 	bool disable_z10;
982 	bool enable_z9_disable_interface;
983 	bool psr_skip_crtc_disable;
984 	union dpia_debug_options dpia_debug;
985 	bool disable_fixed_vs_aux_timeout_wa;
986 	uint32_t fixed_vs_aux_delay_config_wa;
987 	bool force_disable_subvp;
988 	bool force_subvp_mclk_switch;
989 	bool allow_sw_cursor_fallback;
990 	unsigned int force_subvp_num_ways;
991 	unsigned int force_mall_ss_num_ways;
992 	bool alloc_extra_way_for_cursor;
993 	uint32_t subvp_extra_lines;
994 	bool force_usr_allow;
995 	/* uses value at boot and disables switch */
996 	bool disable_dtb_ref_clk_switch;
997 	bool extended_blank_optimization;
998 	union aux_wake_wa_options aux_wake_wa;
999 	uint32_t mst_start_top_delay;
1000 	uint8_t psr_power_use_phy_fsm;
1001 	enum dml_hostvm_override_opts dml_hostvm_override;
1002 	bool dml_disallow_alternate_prefetch_modes;
1003 	bool use_legacy_soc_bb_mechanism;
1004 	bool exit_idle_opt_for_cursor_updates;
1005 	bool using_dml2;
1006 	bool enable_single_display_2to1_odm_policy;
1007 	bool enable_double_buffered_dsc_pg_support;
1008 	bool enable_dp_dig_pixel_rate_div_policy;
1009 	bool using_dml21;
1010 	enum lttpr_mode lttpr_mode_override;
1011 	unsigned int dsc_delay_factor_wa_x1000;
1012 	unsigned int min_prefetch_in_strobe_ns;
1013 	bool disable_unbounded_requesting;
1014 	bool dig_fifo_off_in_blank;
1015 	bool override_dispclk_programming;
1016 	bool otg_crc_db;
1017 	bool disallow_dispclk_dppclk_ds;
1018 	bool disable_fpo_optimizations;
1019 	bool support_eDP1_5;
1020 	uint32_t fpo_vactive_margin_us;
1021 	bool disable_fpo_vactive;
1022 	bool disable_boot_optimizations;
1023 	bool override_odm_optimization;
1024 	bool minimize_dispclk_using_odm;
1025 	bool disable_subvp_high_refresh;
1026 	bool disable_dp_plus_plus_wa;
1027 	uint32_t fpo_vactive_min_active_margin_us;
1028 	uint32_t fpo_vactive_max_blank_us;
1029 	bool enable_hpo_pg_support;
1030 	bool enable_legacy_fast_update;
1031 	bool disable_dc_mode_overwrite;
1032 	bool replay_skip_crtc_disabled;
1033 	bool ignore_pg;/*do nothing, let pmfw control it*/
1034 	bool psp_disabled_wa;
1035 	unsigned int ips2_eval_delay_us;
1036 	unsigned int ips2_entry_delay_us;
1037 	bool optimize_ips_handshake;
1038 	bool disable_dmub_reallow_idle;
1039 	bool disable_timeout;
1040 	bool disable_extblankadj;
1041 	bool enable_idle_reg_checks;
1042 	unsigned int static_screen_wait_frames;
1043 	uint32_t pwm_freq;
1044 	bool force_chroma_subsampling_1tap;
1045 	unsigned int dcc_meta_propagation_delay_us;
1046 	bool disable_422_left_edge_pixel;
1047 	bool dml21_force_pstate_method;
1048 	uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1049 	uint32_t dml21_disable_pstate_method_mask;
1050 	union dmub_fams2_global_feature_config fams2_config;
1051 	bool enable_legacy_clock_update;
1052 	unsigned int force_cositing;
1053 	unsigned int disable_spl;
1054 	unsigned int force_easf;
1055 	unsigned int force_sharpness;
1056 	unsigned int force_lls;
1057 	bool notify_dpia_hr_bw;
1058 };
1059 
1060 
1061 /* Generic structure that can be used to query properties of DC. More fields
1062  * can be added as required.
1063  */
1064 struct dc_current_properties {
1065 	unsigned int cursor_size_limit;
1066 };
1067 
1068 enum frame_buffer_mode {
1069 	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1070 	FRAME_BUFFER_MODE_ZFB_ONLY,
1071 	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1072 } ;
1073 
1074 struct dchub_init_data {
1075 	int64_t zfb_phys_addr_base;
1076 	int64_t zfb_mc_base_addr;
1077 	uint64_t zfb_size_in_byte;
1078 	enum frame_buffer_mode fb_mode;
1079 	bool dchub_initialzied;
1080 	bool dchub_info_valid;
1081 };
1082 
1083 struct dml2_soc_bb;
1084 
1085 struct dc_init_data {
1086 	struct hw_asic_id asic_id;
1087 	void *driver; /* ctx */
1088 	struct cgs_device *cgs_device;
1089 	struct dc_bounding_box_overrides bb_overrides;
1090 
1091 	int num_virtual_links;
1092 	/*
1093 	 * If 'vbios_override' not NULL, it will be called instead
1094 	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1095 	 */
1096 	struct dc_bios *vbios_override;
1097 	enum dce_environment dce_environment;
1098 
1099 	struct dmub_offload_funcs *dmub_if;
1100 	struct dc_reg_helper_state *dmub_offload;
1101 
1102 	struct dc_config flags;
1103 	uint64_t log_mask;
1104 
1105 	struct dpcd_vendor_signature vendor_signature;
1106 	bool force_smu_not_present;
1107 	/*
1108 	 * IP offset for run time initializaion of register addresses
1109 	 *
1110 	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1111 	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1112 	 * before them.
1113 	 */
1114 	uint32_t *dcn_reg_offsets;
1115 	uint32_t *nbio_reg_offsets;
1116 	uint32_t *clk_reg_offsets;
1117 	struct dml2_soc_bb *bb_from_dmub;
1118 };
1119 
1120 struct dc_callback_init {
1121 	struct cp_psp cp_psp;
1122 };
1123 
1124 struct dc *dc_create(const struct dc_init_data *init_params);
1125 void dc_hardware_init(struct dc *dc);
1126 
1127 int dc_get_vmid_use_vector(struct dc *dc);
1128 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1129 /* Returns the number of vmids supported */
1130 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1131 void dc_init_callbacks(struct dc *dc,
1132 		const struct dc_callback_init *init_params);
1133 void dc_deinit_callbacks(struct dc *dc);
1134 void dc_destroy(struct dc **dc);
1135 
1136 /* Surface Interfaces */
1137 
1138 enum {
1139 	TRANSFER_FUNC_POINTS = 1025
1140 };
1141 
1142 struct dc_hdr_static_metadata {
1143 	/* display chromaticities and white point in units of 0.00001 */
1144 	unsigned int chromaticity_green_x;
1145 	unsigned int chromaticity_green_y;
1146 	unsigned int chromaticity_blue_x;
1147 	unsigned int chromaticity_blue_y;
1148 	unsigned int chromaticity_red_x;
1149 	unsigned int chromaticity_red_y;
1150 	unsigned int chromaticity_white_point_x;
1151 	unsigned int chromaticity_white_point_y;
1152 
1153 	uint32_t min_luminance;
1154 	uint32_t max_luminance;
1155 	uint32_t maximum_content_light_level;
1156 	uint32_t maximum_frame_average_light_level;
1157 };
1158 
1159 enum dc_transfer_func_type {
1160 	TF_TYPE_PREDEFINED,
1161 	TF_TYPE_DISTRIBUTED_POINTS,
1162 	TF_TYPE_BYPASS,
1163 	TF_TYPE_HWPWL
1164 };
1165 
1166 struct dc_transfer_func_distributed_points {
1167 	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1168 	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1169 	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1170 
1171 	uint16_t end_exponent;
1172 	uint16_t x_point_at_y1_red;
1173 	uint16_t x_point_at_y1_green;
1174 	uint16_t x_point_at_y1_blue;
1175 };
1176 
1177 enum dc_transfer_func_predefined {
1178 	TRANSFER_FUNCTION_SRGB,
1179 	TRANSFER_FUNCTION_BT709,
1180 	TRANSFER_FUNCTION_PQ,
1181 	TRANSFER_FUNCTION_LINEAR,
1182 	TRANSFER_FUNCTION_UNITY,
1183 	TRANSFER_FUNCTION_HLG,
1184 	TRANSFER_FUNCTION_HLG12,
1185 	TRANSFER_FUNCTION_GAMMA22,
1186 	TRANSFER_FUNCTION_GAMMA24,
1187 	TRANSFER_FUNCTION_GAMMA26
1188 };
1189 
1190 
1191 struct dc_transfer_func {
1192 	struct kref refcount;
1193 	enum dc_transfer_func_type type;
1194 	enum dc_transfer_func_predefined tf;
1195 	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1196 	uint32_t sdr_ref_white_level;
1197 	union {
1198 		struct pwl_params pwl;
1199 		struct dc_transfer_func_distributed_points tf_pts;
1200 	};
1201 };
1202 
1203 
1204 union dc_3dlut_state {
1205 	struct {
1206 		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
1207 		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
1208 		uint32_t rmu_mux_num:3;		/*index of mux to use*/
1209 		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1210 		uint32_t mpc_rmu1_mux:4;
1211 		uint32_t mpc_rmu2_mux:4;
1212 		uint32_t reserved:15;
1213 	} bits;
1214 	uint32_t raw;
1215 };
1216 
1217 
1218 struct dc_3dlut {
1219 	struct kref refcount;
1220 	struct tetrahedral_params lut_3d;
1221 	struct fixed31_32 hdr_multiplier;
1222 	union dc_3dlut_state state;
1223 };
1224 /*
1225  * This structure is filled in by dc_surface_get_status and contains
1226  * the last requested address and the currently active address so the called
1227  * can determine if there are any outstanding flips
1228  */
1229 struct dc_plane_status {
1230 	struct dc_plane_address requested_address;
1231 	struct dc_plane_address current_address;
1232 	bool is_flip_pending;
1233 	bool is_right_eye;
1234 };
1235 
1236 union surface_update_flags {
1237 
1238 	struct {
1239 		uint32_t addr_update:1;
1240 		/* Medium updates */
1241 		uint32_t dcc_change:1;
1242 		uint32_t color_space_change:1;
1243 		uint32_t horizontal_mirror_change:1;
1244 		uint32_t per_pixel_alpha_change:1;
1245 		uint32_t global_alpha_change:1;
1246 		uint32_t hdr_mult:1;
1247 		uint32_t rotation_change:1;
1248 		uint32_t swizzle_change:1;
1249 		uint32_t scaling_change:1;
1250 		uint32_t clip_size_change: 1;
1251 		uint32_t position_change:1;
1252 		uint32_t in_transfer_func_change:1;
1253 		uint32_t input_csc_change:1;
1254 		uint32_t coeff_reduction_change:1;
1255 		uint32_t output_tf_change:1;
1256 		uint32_t pixel_format_change:1;
1257 		uint32_t plane_size_change:1;
1258 		uint32_t gamut_remap_change:1;
1259 
1260 		/* Full updates */
1261 		uint32_t new_plane:1;
1262 		uint32_t bpp_change:1;
1263 		uint32_t gamma_change:1;
1264 		uint32_t bandwidth_change:1;
1265 		uint32_t clock_change:1;
1266 		uint32_t stereo_format_change:1;
1267 		uint32_t lut_3d:1;
1268 		uint32_t tmz_changed:1;
1269 		uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
1270 		uint32_t full_update:1;
1271 	} bits;
1272 
1273 	uint32_t raw;
1274 };
1275 
1276 #define DC_REMOVE_PLANE_POINTERS 1
1277 
1278 struct dc_plane_state {
1279 	struct dc_plane_address address;
1280 	struct dc_plane_flip_time time;
1281 	bool triplebuffer_flips;
1282 	struct scaling_taps scaling_quality;
1283 	struct rect src_rect;
1284 	struct rect dst_rect;
1285 	struct rect clip_rect;
1286 
1287 	struct plane_size plane_size;
1288 	union dc_tiling_info tiling_info;
1289 
1290 	struct dc_plane_dcc_param dcc;
1291 
1292 	struct dc_gamma gamma_correction;
1293 	struct dc_transfer_func in_transfer_func;
1294 	struct dc_bias_and_scale *bias_and_scale;
1295 	struct dc_csc_transform input_csc_color_matrix;
1296 	struct fixed31_32 coeff_reduction_factor;
1297 	struct fixed31_32 hdr_mult;
1298 	struct colorspace_transform gamut_remap_matrix;
1299 
1300 	// TODO: No longer used, remove
1301 	struct dc_hdr_static_metadata hdr_static_ctx;
1302 
1303 	enum dc_color_space color_space;
1304 
1305 	struct dc_3dlut lut3d_func;
1306 	struct dc_transfer_func in_shaper_func;
1307 	struct dc_transfer_func blend_tf;
1308 
1309 	struct dc_transfer_func *gamcor_tf;
1310 	enum surface_pixel_format format;
1311 	enum dc_rotation_angle rotation;
1312 	enum plane_stereo_format stereo_format;
1313 
1314 	bool is_tiling_rotated;
1315 	bool per_pixel_alpha;
1316 	bool pre_multiplied_alpha;
1317 	bool global_alpha;
1318 	int  global_alpha_value;
1319 	bool visible;
1320 	bool flip_immediate;
1321 	bool horizontal_mirror;
1322 	int layer_index;
1323 
1324 	union surface_update_flags update_flags;
1325 	bool flip_int_enabled;
1326 	bool skip_manual_trigger;
1327 
1328 	/* private to DC core */
1329 	struct dc_plane_status status;
1330 	struct dc_context *ctx;
1331 
1332 	/* HACK: Workaround for forcing full reprogramming under some conditions */
1333 	bool force_full_update;
1334 
1335 	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1336 
1337 	/* private to dc_surface.c */
1338 	enum dc_irq_source irq_source;
1339 	struct kref refcount;
1340 	struct tg_color visual_confirm_color;
1341 
1342 	bool is_statically_allocated;
1343 	enum chroma_cositing cositing;
1344 	enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;
1345 	bool mcm_lut1d_enable;
1346 	struct dc_cm2_func_luts mcm_luts;
1347 	bool lut_bank_a;
1348 	enum mpcc_movable_cm_location mcm_location;
1349 	struct dc_csc_transform cursor_csc_color_matrix;
1350 	bool adaptive_sharpness_en;
1351 	unsigned int sharpnessX1000;
1352 	enum linear_light_scaling linear_light_scaling;
1353 };
1354 
1355 struct dc_plane_info {
1356 	struct plane_size plane_size;
1357 	union dc_tiling_info tiling_info;
1358 	struct dc_plane_dcc_param dcc;
1359 	enum surface_pixel_format format;
1360 	enum dc_rotation_angle rotation;
1361 	enum plane_stereo_format stereo_format;
1362 	enum dc_color_space color_space;
1363 	bool horizontal_mirror;
1364 	bool visible;
1365 	bool per_pixel_alpha;
1366 	bool pre_multiplied_alpha;
1367 	bool global_alpha;
1368 	int  global_alpha_value;
1369 	bool input_csc_enabled;
1370 	int layer_index;
1371 	bool front_buffer_rendering_active;
1372 	enum chroma_cositing cositing;
1373 };
1374 
1375 #include "dc_stream.h"
1376 
1377 struct dc_scratch_space {
1378 	/* used to temporarily backup plane states of a stream during
1379 	 * dc update. The reason is that plane states are overwritten
1380 	 * with surface updates in dc update. Once they are overwritten
1381 	 * current state is no longer valid. We want to temporarily
1382 	 * store current value in plane states so we can still recover
1383 	 * a valid current state during dc update.
1384 	 */
1385 	struct dc_plane_state plane_states[MAX_SURFACE_NUM];
1386 
1387 	struct dc_stream_state stream_state;
1388 };
1389 
1390 struct dc {
1391 	struct dc_debug_options debug;
1392 	struct dc_versions versions;
1393 	struct dc_caps caps;
1394 	struct dc_cap_funcs cap_funcs;
1395 	struct dc_config config;
1396 	struct dc_bounding_box_overrides bb_overrides;
1397 	struct dc_bug_wa work_arounds;
1398 	struct dc_context *ctx;
1399 	struct dc_phy_addr_space_config vm_pa_config;
1400 
1401 	uint8_t link_count;
1402 	struct dc_link *links[MAX_LINKS];
1403 	struct link_service *link_srv;
1404 
1405 	struct dc_state *current_state;
1406 	struct resource_pool *res_pool;
1407 
1408 	struct clk_mgr *clk_mgr;
1409 
1410 	/* Display Engine Clock levels */
1411 	struct dm_pp_clock_levels sclk_lvls;
1412 
1413 	/* Inputs into BW and WM calculations. */
1414 	struct bw_calcs_dceip *bw_dceip;
1415 	struct bw_calcs_vbios *bw_vbios;
1416 	struct dcn_soc_bounding_box *dcn_soc;
1417 	struct dcn_ip_params *dcn_ip;
1418 	struct display_mode_lib dml;
1419 
1420 	/* HW functions */
1421 	struct hw_sequencer_funcs hwss;
1422 	struct dce_hwseq *hwseq;
1423 
1424 	/* Require to optimize clocks and bandwidth for added/removed planes */
1425 	bool optimized_required;
1426 	bool wm_optimized_required;
1427 	bool idle_optimizations_allowed;
1428 	bool enable_c20_dtm_b0;
1429 
1430 	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
1431 
1432 	/* FBC compressor */
1433 	struct compressor *fbc_compressor;
1434 
1435 	struct dc_debug_data debug_data;
1436 	struct dpcd_vendor_signature vendor_signature;
1437 
1438 	const char *build_id;
1439 	struct vm_helper *vm_helper;
1440 
1441 	uint32_t *dcn_reg_offsets;
1442 	uint32_t *nbio_reg_offsets;
1443 	uint32_t *clk_reg_offsets;
1444 
1445 	/* Scratch memory */
1446 	struct {
1447 		struct {
1448 			/*
1449 			 * For matching clock_limits table in driver with table
1450 			 * from PMFW.
1451 			 */
1452 			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1453 		} update_bw_bounding_box;
1454 		struct dc_scratch_space current_state;
1455 		struct dc_scratch_space new_state;
1456 		struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
1457 	} scratch;
1458 
1459 	struct dml2_configuration_options dml2_options;
1460 	struct dml2_configuration_options dml2_tmp;
1461 	enum dc_acpi_cm_power_state power_state;
1462 
1463 };
1464 
1465 struct dc_scaling_info {
1466 	struct rect src_rect;
1467 	struct rect dst_rect;
1468 	struct rect clip_rect;
1469 	struct scaling_taps scaling_quality;
1470 };
1471 
1472 struct dc_fast_update {
1473 	const struct dc_flip_addrs *flip_addr;
1474 	const struct dc_gamma *gamma;
1475 	const struct colorspace_transform *gamut_remap_matrix;
1476 	const struct dc_csc_transform *input_csc_color_matrix;
1477 	const struct fixed31_32 *coeff_reduction_factor;
1478 	struct dc_transfer_func *out_transfer_func;
1479 	struct dc_csc_transform *output_csc_transform;
1480 	const struct dc_csc_transform *cursor_csc_color_matrix;
1481 };
1482 
1483 struct dc_surface_update {
1484 	struct dc_plane_state *surface;
1485 
1486 	/* isr safe update parameters.  null means no updates */
1487 	const struct dc_flip_addrs *flip_addr;
1488 	const struct dc_plane_info *plane_info;
1489 	const struct dc_scaling_info *scaling_info;
1490 	struct fixed31_32 hdr_mult;
1491 	/* following updates require alloc/sleep/spin that is not isr safe,
1492 	 * null means no updates
1493 	 */
1494 	const struct dc_gamma *gamma;
1495 	const struct dc_transfer_func *in_transfer_func;
1496 
1497 	const struct dc_csc_transform *input_csc_color_matrix;
1498 	const struct fixed31_32 *coeff_reduction_factor;
1499 	const struct dc_transfer_func *func_shaper;
1500 	const struct dc_3dlut *lut3d_func;
1501 	const struct dc_transfer_func *blend_tf;
1502 	const struct colorspace_transform *gamut_remap_matrix;
1503 	/*
1504 	 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1505 	 *
1506 	 * change cm2_params.component_settings: Full update
1507 	 * change cm2_params.cm2_luts: Fast update
1508 	 */
1509 	struct dc_cm2_parameters *cm2_params;
1510 	const struct dc_csc_transform *cursor_csc_color_matrix;
1511 };
1512 
1513 /*
1514  * Create a new surface with default parameters;
1515  */
1516 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1517 void dc_gamma_release(struct dc_gamma **dc_gamma);
1518 struct dc_gamma *dc_create_gamma(void);
1519 
1520 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1521 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1522 struct dc_transfer_func *dc_create_transfer_func(void);
1523 
1524 struct dc_3dlut *dc_create_3dlut_func(void);
1525 void dc_3dlut_func_release(struct dc_3dlut *lut);
1526 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1527 
1528 void dc_post_update_surfaces_to_stream(
1529 		struct dc *dc);
1530 
1531 #include "dc_stream.h"
1532 
1533 /**
1534  * struct dc_validation_set - Struct to store surface/stream associations for validation
1535  */
1536 struct dc_validation_set {
1537 	/**
1538 	 * @stream: Stream state properties
1539 	 */
1540 	struct dc_stream_state *stream;
1541 
1542 	/**
1543 	 * @plane_states: Surface state
1544 	 */
1545 	struct dc_plane_state *plane_states[MAX_SURFACES];
1546 
1547 	/**
1548 	 * @plane_count: Total of active planes
1549 	 */
1550 	uint8_t plane_count;
1551 };
1552 
1553 bool dc_validate_boot_timing(const struct dc *dc,
1554 				const struct dc_sink *sink,
1555 				struct dc_crtc_timing *crtc_timing);
1556 
1557 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1558 
1559 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1560 
1561 enum dc_status dc_validate_with_context(struct dc *dc,
1562 					const struct dc_validation_set set[],
1563 					int set_count,
1564 					struct dc_state *context,
1565 					bool fast_validate);
1566 
1567 bool dc_set_generic_gpio_for_stereo(bool enable,
1568 		struct gpio_service *gpio_service);
1569 
1570 /*
1571  * fast_validate: we return after determining if we can support the new state,
1572  * but before we populate the programming info
1573  */
1574 enum dc_status dc_validate_global_state(
1575 		struct dc *dc,
1576 		struct dc_state *new_ctx,
1577 		bool fast_validate);
1578 
1579 bool dc_acquire_release_mpc_3dlut(
1580 		struct dc *dc, bool acquire,
1581 		struct dc_stream_state *stream,
1582 		struct dc_3dlut **lut,
1583 		struct dc_transfer_func **shaper);
1584 
1585 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1586 void get_audio_check(struct audio_info *aud_modes,
1587 	struct audio_check *aud_chk);
1588 /*
1589  * Set up streams and links associated to drive sinks
1590  * The streams parameter is an absolute set of all active streams.
1591  *
1592  * After this call:
1593  *   Phy, Encoder, Timing Generator are programmed and enabled.
1594  *   New streams are enabled with blank stream; no memory read.
1595  */
1596 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1597 
1598 
1599 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1600 		struct dc_stream_state *stream,
1601 		int mpcc_inst);
1602 
1603 
1604 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1605 
1606 void dc_set_disable_128b_132b_stream_overhead(bool disable);
1607 
1608 /* The function returns minimum bandwidth required to drive a given timing
1609  * return - minimum required timing bandwidth in kbps.
1610  */
1611 uint32_t dc_bandwidth_in_kbps_from_timing(
1612 		const struct dc_crtc_timing *timing,
1613 		const enum dc_link_encoding_format link_encoding);
1614 
1615 /* Link Interfaces */
1616 /*
1617  * A link contains one or more sinks and their connected status.
1618  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1619  */
1620 struct dc_link {
1621 	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1622 	unsigned int sink_count;
1623 	struct dc_sink *local_sink;
1624 	unsigned int link_index;
1625 	enum dc_connection_type type;
1626 	enum signal_type connector_signal;
1627 	enum dc_irq_source irq_source_hpd;
1628 	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
1629 
1630 	bool is_hpd_filter_disabled;
1631 	bool dp_ss_off;
1632 
1633 	/**
1634 	 * @link_state_valid:
1635 	 *
1636 	 * If there is no link and local sink, this variable should be set to
1637 	 * false. Otherwise, it should be set to true; usually, the function
1638 	 * core_link_enable_stream sets this field to true.
1639 	 */
1640 	bool link_state_valid;
1641 	bool aux_access_disabled;
1642 	bool sync_lt_in_progress;
1643 	bool skip_stream_reenable;
1644 	bool is_internal_display;
1645 	/** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1646 	bool is_dig_mapping_flexible;
1647 	bool hpd_status; /* HPD status of link without physical HPD pin. */
1648 	bool is_hpd_pending; /* Indicates a new received hpd */
1649 
1650 	/* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1651 	 * for every link training. This is incompatible with DP LL compliance automation,
1652 	 * which expects the same link settings to be used every retry on a link loss.
1653 	 * This flag is used to skip the fallback when link loss occurs during automation.
1654 	 */
1655 	bool skip_fallback_on_link_loss;
1656 
1657 	bool edp_sink_present;
1658 
1659 	struct dp_trace dp_trace;
1660 
1661 	/* caps is the same as reported_link_cap. link_traing use
1662 	 * reported_link_cap. Will clean up.  TODO
1663 	 */
1664 	struct dc_link_settings reported_link_cap;
1665 	struct dc_link_settings verified_link_cap;
1666 	struct dc_link_settings cur_link_settings;
1667 	struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1668 	struct dc_link_settings preferred_link_setting;
1669 	/* preferred_training_settings are override values that
1670 	 * come from DM. DM is responsible for the memory
1671 	 * management of the override pointers.
1672 	 */
1673 	struct dc_link_training_overrides preferred_training_settings;
1674 	struct dp_audio_test_data audio_test_data;
1675 
1676 	uint8_t ddc_hw_inst;
1677 
1678 	uint8_t hpd_src;
1679 
1680 	uint8_t link_enc_hw_inst;
1681 	/* DIG link encoder ID. Used as index in link encoder resource pool.
1682 	 * For links with fixed mapping to DIG, this is not changed after dc_link
1683 	 * object creation.
1684 	 */
1685 	enum engine_id eng_id;
1686 	enum engine_id dpia_preferred_eng_id;
1687 
1688 	bool test_pattern_enabled;
1689 	/* Pending/Current test pattern are only used to perform and track
1690 	 * FIXED_VS retimer test pattern/lane adjustment override state.
1691 	 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1692 	 * to perform specific lane adjust overrides before setting certain
1693 	 * PHY test patterns. In cases when lane adjust and set test pattern
1694 	 * calls are not performed atomically (i.e. performing link training),
1695 	 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1696 	 * and current_test_pattern will contain required context for any future
1697 	 * set pattern/set lane adjust to transition between override state(s).
1698 	 * */
1699 	enum dp_test_pattern current_test_pattern;
1700 	enum dp_test_pattern pending_test_pattern;
1701 
1702 	union compliance_test_state compliance_test_state;
1703 
1704 	void *priv;
1705 
1706 	struct ddc_service *ddc;
1707 
1708 	enum dp_panel_mode panel_mode;
1709 	bool aux_mode;
1710 
1711 	/* Private to DC core */
1712 
1713 	const struct dc *dc;
1714 
1715 	struct dc_context *ctx;
1716 
1717 	struct panel_cntl *panel_cntl;
1718 	struct link_encoder *link_enc;
1719 	struct graphics_object_id link_id;
1720 	/* Endpoint type distinguishes display endpoints which do not have entries
1721 	 * in the BIOS connector table from those that do. Helps when tracking link
1722 	 * encoder to display endpoint assignments.
1723 	 */
1724 	enum display_endpoint_type ep_type;
1725 	union ddi_channel_mapping ddi_channel_mapping;
1726 	struct connector_device_tag_info device_tag;
1727 	struct dpcd_caps dpcd_caps;
1728 	uint32_t dongle_max_pix_clk;
1729 	unsigned short chip_caps;
1730 	unsigned int dpcd_sink_count;
1731 	struct hdcp_caps hdcp_caps;
1732 	enum edp_revision edp_revision;
1733 	union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1734 
1735 	struct psr_settings psr_settings;
1736 	struct replay_settings replay_settings;
1737 
1738 	/* Drive settings read from integrated info table */
1739 	struct dc_lane_settings bios_forced_drive_settings;
1740 
1741 	/* Vendor specific LTTPR workaround variables */
1742 	uint8_t vendor_specific_lttpr_link_rate_wa;
1743 	bool apply_vendor_specific_lttpr_link_rate_wa;
1744 
1745 	/* MST record stream using this link */
1746 	struct link_flags {
1747 		bool dp_keep_receiver_powered;
1748 		bool dp_skip_DID2;
1749 		bool dp_skip_reset_segment;
1750 		bool dp_skip_fs_144hz;
1751 		bool dp_mot_reset_segment;
1752 		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1753 		bool dpia_mst_dsc_always_on;
1754 		/* Forced DPIA into TBT3 compatibility mode. */
1755 		bool dpia_forced_tbt3_mode;
1756 		bool dongle_mode_timing_override;
1757 		bool blank_stream_on_ocs_change;
1758 		bool read_dpcd204h_on_irq_hpd;
1759 	} wa_flags;
1760 	struct link_mst_stream_allocation_table mst_stream_alloc_table;
1761 
1762 	struct dc_link_status link_status;
1763 	struct dprx_states dprx_states;
1764 
1765 	struct gpio *hpd_gpio;
1766 	enum dc_link_fec_state fec_state;
1767 	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly
1768 
1769 	struct dc_panel_config panel_config;
1770 	struct phy_state phy_state;
1771 	// BW ALLOCATON USB4 ONLY
1772 	struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1773 	bool skip_implict_edp_power_control;
1774 };
1775 
1776 /* Return an enumerated dc_link.
1777  * dc_link order is constant and determined at
1778  * boot time.  They cannot be created or destroyed.
1779  * Use dc_get_caps() to get number of links.
1780  */
1781 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1782 
1783 /* Return instance id of the edp link. Inst 0 is primary edp link. */
1784 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1785 		const struct dc_link *link,
1786 		unsigned int *inst_out);
1787 
1788 /* Return an array of link pointers to edp links. */
1789 void dc_get_edp_links(const struct dc *dc,
1790 		struct dc_link **edp_links,
1791 		int *edp_num);
1792 
1793 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1794 				 bool powerOn);
1795 
1796 /* The function initiates detection handshake over the given link. It first
1797  * determines if there are display connections over the link. If so it initiates
1798  * detection protocols supported by the connected receiver device. The function
1799  * contains protocol specific handshake sequences which are sometimes mandatory
1800  * to establish a proper connection between TX and RX. So it is always
1801  * recommended to call this function as the first link operation upon HPD event
1802  * or power up event. Upon completion, the function will update link structure
1803  * in place based on latest RX capabilities. The function may also cause dpms
1804  * to be reset to off for all currently enabled streams to the link. It is DM's
1805  * responsibility to serialize detection and DPMS updates.
1806  *
1807  * @reason - Indicate which event triggers this detection. dc may customize
1808  * detection flow depending on the triggering events.
1809  * return false - if detection is not fully completed. This could happen when
1810  * there is an unrecoverable error during detection or detection is partially
1811  * completed (detection has been delegated to dm mst manager ie.
1812  * link->connection_type == dc_connection_mst_branch when returning false).
1813  * return true - detection is completed, link has been fully updated with latest
1814  * detection result.
1815  */
1816 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1817 
1818 struct dc_sink_init_data;
1819 
1820 /* When link connection type is dc_connection_mst_branch, remote sink can be
1821  * added to the link. The interface creates a remote sink and associates it with
1822  * current link. The sink will be retained by link until remove remote sink is
1823  * called.
1824  *
1825  * @dc_link - link the remote sink will be added to.
1826  * @edid - byte array of EDID raw data.
1827  * @len - size of the edid in byte
1828  * @init_data -
1829  */
1830 struct dc_sink *dc_link_add_remote_sink(
1831 		struct dc_link *dc_link,
1832 		const uint8_t *edid,
1833 		int len,
1834 		struct dc_sink_init_data *init_data);
1835 
1836 /* Remove remote sink from a link with dc_connection_mst_branch connection type.
1837  * @link - link the sink should be removed from
1838  * @sink - sink to be removed.
1839  */
1840 void dc_link_remove_remote_sink(
1841 	struct dc_link *link,
1842 	struct dc_sink *sink);
1843 
1844 /* Enable HPD interrupt handler for a given link */
1845 void dc_link_enable_hpd(const struct dc_link *link);
1846 
1847 /* Disable HPD interrupt handler for a given link */
1848 void dc_link_disable_hpd(const struct dc_link *link);
1849 
1850 /* determine if there is a sink connected to the link
1851  *
1852  * @type - dc_connection_single if connected, dc_connection_none otherwise.
1853  * return - false if an unexpected error occurs, true otherwise.
1854  *
1855  * NOTE: This function doesn't detect downstream sink connections i.e
1856  * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1857  * return dc_connection_single if the branch device is connected despite of
1858  * downstream sink's connection status.
1859  */
1860 bool dc_link_detect_connection_type(struct dc_link *link,
1861 		enum dc_connection_type *type);
1862 
1863 /* query current hpd pin value
1864  * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1865  *
1866  */
1867 bool dc_link_get_hpd_state(struct dc_link *link);
1868 
1869 /* Getter for cached link status from given link */
1870 const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1871 
1872 /* enable/disable hardware HPD filter.
1873  *
1874  * @link - The link the HPD pin is associated with.
1875  * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1876  * handler once after no HPD change has been detected within dc default HPD
1877  * filtering interval since last HPD event. i.e if display keeps toggling hpd
1878  * pulses within default HPD interval, no HPD event will be received until HPD
1879  * toggles have stopped. Then HPD event will be queued to irq handler once after
1880  * dc default HPD filtering interval since last HPD event.
1881  *
1882  * @enable = false - disable hardware HPD filter. HPD event will be queued
1883  * immediately to irq handler after no HPD change has been detected within
1884  * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1885  */
1886 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1887 
1888 /* submit i2c read/write payloads through ddc channel
1889  * @link_index - index to a link with ddc in i2c mode
1890  * @cmd - i2c command structure
1891  * return - true if success, false otherwise.
1892  */
1893 bool dc_submit_i2c(
1894 		struct dc *dc,
1895 		uint32_t link_index,
1896 		struct i2c_command *cmd);
1897 
1898 /* submit i2c read/write payloads through oem channel
1899  * @link_index - index to a link with ddc in i2c mode
1900  * @cmd - i2c command structure
1901  * return - true if success, false otherwise.
1902  */
1903 bool dc_submit_i2c_oem(
1904 		struct dc *dc,
1905 		struct i2c_command *cmd);
1906 
1907 enum aux_return_code_type;
1908 /* Attempt to transfer the given aux payload. This function does not perform
1909  * retries or handle error states. The reply is returned in the payload->reply
1910  * and the result through operation_result. Returns the number of bytes
1911  * transferred,or -1 on a failure.
1912  */
1913 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1914 		struct aux_payload *payload,
1915 		enum aux_return_code_type *operation_result);
1916 
1917 bool dc_is_oem_i2c_device_present(
1918 	struct dc *dc,
1919 	size_t slave_address
1920 );
1921 
1922 /* return true if the connected receiver supports the hdcp version */
1923 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1924 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1925 
1926 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1927  *
1928  * TODO - When defer_handling is true the function will have a different purpose.
1929  * It no longer does complete hpd rx irq handling. We should create a separate
1930  * interface specifically for this case.
1931  *
1932  * Return:
1933  * true - Downstream port status changed. DM should call DC to do the
1934  * detection.
1935  * false - no change in Downstream port status. No further action required
1936  * from DM.
1937  */
1938 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1939 		union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1940 		bool defer_handling, bool *has_left_work);
1941 /* handle DP specs define test automation sequence*/
1942 void dc_link_dp_handle_automated_test(struct dc_link *link);
1943 
1944 /* handle DP Link loss sequence and try to recover RX link loss with best
1945  * effort
1946  */
1947 void dc_link_dp_handle_link_loss(struct dc_link *link);
1948 
1949 /* Determine if hpd rx irq should be handled or ignored
1950  * return true - hpd rx irq should be handled.
1951  * return false - it is safe to ignore hpd rx irq event
1952  */
1953 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1954 
1955 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1956  * @link - link the hpd irq data associated with
1957  * @hpd_irq_dpcd_data - input hpd irq data
1958  * return - true if hpd irq data indicates a link lost
1959  */
1960 bool dc_link_check_link_loss_status(struct dc_link *link,
1961 		union hpd_irq_data *hpd_irq_dpcd_data);
1962 
1963 /* Read hpd rx irq data from a given link
1964  * @link - link where the hpd irq data should be read from
1965  * @irq_data - output hpd irq data
1966  * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1967  * read has failed.
1968  */
1969 enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1970 	struct dc_link *link,
1971 	union hpd_irq_data *irq_data);
1972 
1973 /* The function clears recorded DP RX states in the link. DM should call this
1974  * function when it is resuming from S3 power state to previously connected links.
1975  *
1976  * TODO - in the future we should consider to expand link resume interface to
1977  * support clearing previous rx states. So we don't have to rely on dm to call
1978  * this interface explicitly.
1979  */
1980 void dc_link_clear_dprx_states(struct dc_link *link);
1981 
1982 /* Destruct the mst topology of the link and reset the allocated payload table
1983  *
1984  * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1985  * still wants to reset MST topology on an unplug event */
1986 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1987 
1988 /* The function calculates effective DP link bandwidth when a given link is
1989  * using the given link settings.
1990  *
1991  * return - total effective link bandwidth in kbps.
1992  */
1993 uint32_t dc_link_bandwidth_kbps(
1994 	const struct dc_link *link,
1995 	const struct dc_link_settings *link_setting);
1996 
1997 /* The function takes a snapshot of current link resource allocation state
1998  * @dc: pointer to dc of the dm calling this
1999  * @map: a dc link resource snapshot defined internally to dc.
2000  *
2001  * DM needs to capture a snapshot of current link resource allocation mapping
2002  * and store it in its persistent storage.
2003  *
2004  * Some of the link resource is using first come first serve policy.
2005  * The allocation mapping depends on original hotplug order. This information
2006  * is lost after driver is loaded next time. The snapshot is used in order to
2007  * restore link resource to its previous state so user will get consistent
2008  * link capability allocation across reboot.
2009  *
2010  */
2011 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2012 
2013 /* This function restores link resource allocation state from a snapshot
2014  * @dc: pointer to dc of the dm calling this
2015  * @map: a dc link resource snapshot defined internally to dc.
2016  *
2017  * DM needs to call this function after initial link detection on boot and
2018  * before first commit streams to restore link resource allocation state
2019  * from previous boot session.
2020  *
2021  * Some of the link resource is using first come first serve policy.
2022  * The allocation mapping depends on original hotplug order. This information
2023  * is lost after driver is loaded next time. The snapshot is used in order to
2024  * restore link resource to its previous state so user will get consistent
2025  * link capability allocation across reboot.
2026  *
2027  */
2028 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2029 
2030 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
2031  * interface i.e stream_update->dsc_config
2032  */
2033 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
2034 
2035 /* translate a raw link rate data to bandwidth in kbps */
2036 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2037 
2038 /* determine the optimal bandwidth given link and required bw.
2039  * @link - current detected link
2040  * @req_bw - requested bandwidth in kbps
2041  * @link_settings - returned most optimal link settings that can fit the
2042  * requested bandwidth
2043  * return - false if link can't support requested bandwidth, true if link
2044  * settings is found.
2045  */
2046 bool dc_link_decide_edp_link_settings(struct dc_link *link,
2047 		struct dc_link_settings *link_settings,
2048 		uint32_t req_bw);
2049 
2050 /* return the max dp link settings can be driven by the link without considering
2051  * connected RX device and its capability
2052  */
2053 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
2054 		struct dc_link_settings *max_link_enc_cap);
2055 
2056 /* determine when the link is driving MST mode, what DP link channel coding
2057  * format will be used. The decision will remain unchanged until next HPD event.
2058  *
2059  * @link -  a link with DP RX connection
2060  * return - if stream is committed to this link with MST signal type, type of
2061  * channel coding format dc will choose.
2062  */
2063 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
2064 		const struct dc_link *link);
2065 
2066 /* get max dp link settings the link can enable with all things considered. (i.e
2067  * TX/RX/Cable capabilities and dp override policies.
2068  *
2069  * @link - a link with DP RX connection
2070  * return - max dp link settings the link can enable.
2071  *
2072  */
2073 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
2074 
2075 /* Get the highest encoding format that the link supports; highest meaning the
2076  * encoding format which supports the maximum bandwidth.
2077  *
2078  * @link - a link with DP RX connection
2079  * return - highest encoding format link supports.
2080  */
2081 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
2082 
2083 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
2084  * to a link with dp connector signal type.
2085  * @link - a link with dp connector signal type
2086  * return - true if connected, false otherwise
2087  */
2088 bool dc_link_is_dp_sink_present(struct dc_link *link);
2089 
2090 /* Force DP lane settings update to main-link video signal and notify the change
2091  * to DP RX via DPCD. This is a debug interface used for video signal integrity
2092  * tuning purpose. The interface assumes link has already been enabled with DP
2093  * signal.
2094  *
2095  * @lt_settings - a container structure with desired hw_lane_settings
2096  */
2097 void dc_link_set_drive_settings(struct dc *dc,
2098 				struct link_training_settings *lt_settings,
2099 				struct dc_link *link);
2100 
2101 /* Enable a test pattern in Link or PHY layer in an active link for compliance
2102  * test or debugging purpose. The test pattern will remain until next un-plug.
2103  *
2104  * @link - active link with DP signal output enabled.
2105  * @test_pattern - desired test pattern to output.
2106  * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
2107  * @test_pattern_color_space - for video test pattern choose a desired color
2108  * space.
2109  * @p_link_settings - For PHY pattern choose a desired link settings
2110  * @p_custom_pattern - some test pattern will require a custom input to
2111  * customize some pattern details. Otherwise keep it to NULL.
2112  * @cust_pattern_size - size of the custom pattern input.
2113  *
2114  */
2115 bool dc_link_dp_set_test_pattern(
2116 	struct dc_link *link,
2117 	enum dp_test_pattern test_pattern,
2118 	enum dp_test_pattern_color_space test_pattern_color_space,
2119 	const struct link_training_settings *p_link_settings,
2120 	const unsigned char *p_custom_pattern,
2121 	unsigned int cust_pattern_size);
2122 
2123 /* Force DP link settings to always use a specific value until reboot to a
2124  * specific link. If link has already been enabled, the interface will also
2125  * switch to desired link settings immediately. This is a debug interface to
2126  * generic dp issue trouble shooting.
2127  */
2128 void dc_link_set_preferred_link_settings(struct dc *dc,
2129 		struct dc_link_settings *link_setting,
2130 		struct dc_link *link);
2131 
2132 /* Force DP link to customize a specific link training behavior by overriding to
2133  * standard DP specs defined protocol. This is a debug interface to trouble shoot
2134  * display specific link training issues or apply some display specific
2135  * workaround in link training.
2136  *
2137  * @link_settings - if not NULL, force preferred link settings to the link.
2138  * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2139  * will apply this particular override in future link training. If NULL is
2140  * passed in, dc resets previous overrides.
2141  * NOTE: DM must keep the memory from override pointers until DM resets preferred
2142  * training settings.
2143  */
2144 void dc_link_set_preferred_training_settings(struct dc *dc,
2145 		struct dc_link_settings *link_setting,
2146 		struct dc_link_training_overrides *lt_overrides,
2147 		struct dc_link *link,
2148 		bool skip_immediate_retrain);
2149 
2150 /* return - true if FEC is supported with connected DP RX, false otherwise */
2151 bool dc_link_is_fec_supported(const struct dc_link *link);
2152 
2153 /* query FEC enablement policy to determine if FEC will be enabled by dc during
2154  * link enablement.
2155  * return - true if FEC should be enabled, false otherwise.
2156  */
2157 bool dc_link_should_enable_fec(const struct dc_link *link);
2158 
2159 /* determine lttpr mode the current link should be enabled with a specific link
2160  * settings.
2161  */
2162 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2163 		struct dc_link_settings *link_setting);
2164 
2165 /* Force DP RX to update its power state.
2166  * NOTE: this interface doesn't update dp main-link. Calling this function will
2167  * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2168  * RX power state back upon finish DM specific execution requiring DP RX in a
2169  * specific power state.
2170  * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2171  * state.
2172  */
2173 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2174 
2175 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2176  * current value read from extended receiver cap from 02200h - 0220Fh.
2177  * Some DP RX has problems of providing accurate DP receiver caps from extended
2178  * field, this interface is a workaround to revert link back to use base caps.
2179  */
2180 void dc_link_overwrite_extended_receiver_cap(
2181 		struct dc_link *link);
2182 
2183 void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2184 		bool wait_for_hpd);
2185 
2186 /* Set backlight level of an embedded panel (eDP, LVDS).
2187  * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2188  * and 16 bit fractional, where 1.0 is max backlight value.
2189  */
2190 bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2191 		uint32_t backlight_pwm_u16_16,
2192 		uint32_t frame_ramp);
2193 
2194 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2195 bool dc_link_set_backlight_level_nits(struct dc_link *link,
2196 		bool isHDR,
2197 		uint32_t backlight_millinits,
2198 		uint32_t transition_time_in_ms);
2199 
2200 bool dc_link_get_backlight_level_nits(struct dc_link *link,
2201 		uint32_t *backlight_millinits,
2202 		uint32_t *backlight_millinits_peak);
2203 
2204 int dc_link_get_backlight_level(const struct dc_link *dc_link);
2205 
2206 int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2207 
2208 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2209 		bool wait, bool force_static, const unsigned int *power_opts);
2210 
2211 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2212 
2213 bool dc_link_setup_psr(struct dc_link *dc_link,
2214 		const struct dc_stream_state *stream, struct psr_config *psr_config,
2215 		struct psr_context *psr_context);
2216 
2217 /*
2218  * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2219  *
2220  * @link: pointer to the dc_link struct instance
2221  * @enable: enable(active) or disable(inactive) replay
2222  * @wait: state transition need to wait the active set completed.
2223  * @force_static: force disable(inactive) the replay
2224  * @power_opts: set power optimazation parameters to DMUB.
2225  *
2226  * return: allow Replay active will return true, else will return false.
2227  */
2228 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2229 		bool wait, bool force_static, const unsigned int *power_opts);
2230 
2231 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2232 
2233 /* On eDP links this function call will stall until T12 has elapsed.
2234  * If the panel is not in power off state, this function will return
2235  * immediately.
2236  */
2237 bool dc_link_wait_for_t12(struct dc_link *link);
2238 
2239 /* Determine if dp trace has been initialized to reflect upto date result *
2240  * return - true if trace is initialized and has valid data. False dp trace
2241  * doesn't have valid result.
2242  */
2243 bool dc_dp_trace_is_initialized(struct dc_link *link);
2244 
2245 /* Query a dp trace flag to indicate if the current dp trace data has been
2246  * logged before
2247  */
2248 bool dc_dp_trace_is_logged(struct dc_link *link,
2249 		bool in_detection);
2250 
2251 /* Set dp trace flag to indicate whether DM has already logged the current dp
2252  * trace data. DM can set is_logged to true upon logging and check
2253  * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2254  */
2255 void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2256 		bool in_detection,
2257 		bool is_logged);
2258 
2259 /* Obtain driver time stamp for last dp link training end. The time stamp is
2260  * formatted based on dm_get_timestamp DM function.
2261  * @in_detection - true to get link training end time stamp of last link
2262  * training in detection sequence. false to get link training end time stamp
2263  * of last link training in commit (dpms) sequence
2264  */
2265 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2266 		bool in_detection);
2267 
2268 /* Get how many link training attempts dc has done with latest sequence.
2269  * @in_detection - true to get link training count of last link
2270  * training in detection sequence. false to get link training count of last link
2271  * training in commit (dpms) sequence
2272  */
2273 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2274 		bool in_detection);
2275 
2276 /* Get how many link loss has happened since last link training attempts */
2277 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2278 
2279 /*
2280  *  USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2281  */
2282 /*
2283  * Send a request from DP-Tx requesting to allocate BW remotely after
2284  * allocating it locally. This will get processed by CM and a CB function
2285  * will be called.
2286  *
2287  * @link: pointer to the dc_link struct instance
2288  * @req_bw: The requested bw in Kbyte to allocated
2289  *
2290  * return: none
2291  */
2292 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2293 
2294 /*
2295  * Handle function for when the status of the Request above is complete.
2296  * We will find out the result of allocating on CM and update structs.
2297  *
2298  * @link: pointer to the dc_link struct instance
2299  * @bw: Allocated or Estimated BW depending on the result
2300  * @result: Response type
2301  *
2302  * return: none
2303  */
2304 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2305 		uint8_t bw, uint8_t result);
2306 
2307 /*
2308  * Handle the USB4 BW Allocation related functionality here:
2309  * Plug => Try to allocate max bw from timing parameters supported by the sink
2310  * Unplug => de-allocate bw
2311  *
2312  * @link: pointer to the dc_link struct instance
2313  * @peak_bw: Peak bw used by the link/sink
2314  *
2315  * return: allocated bw else return 0
2316  */
2317 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2318 		struct dc_link *link, int peak_bw);
2319 
2320 /*
2321  * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2322  * available BW for each host router
2323  *
2324  * @dc: pointer to dc struct
2325  * @stream: pointer to all possible streams
2326  * @count: number of valid DPIA streams
2327  *
2328  * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2329  */
2330 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2331 		const unsigned int count);
2332 
2333 /* Sink Interfaces - A sink corresponds to a display output device */
2334 
2335 struct dc_container_id {
2336 	// 128bit GUID in binary form
2337 	unsigned char  guid[16];
2338 	// 8 byte port ID -> ELD.PortID
2339 	unsigned int   portId[2];
2340 	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2341 	unsigned short manufacturerName;
2342 	// 2 byte product code -> ELD.ProductCode
2343 	unsigned short productCode;
2344 };
2345 
2346 
2347 struct dc_sink_dsc_caps {
2348 	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2349 	// 'false' if they are sink's DSC caps
2350 	bool is_virtual_dpcd_dsc;
2351 	// 'true' if MST topology supports DSC passthrough for sink
2352 	// 'false' if MST topology does not support DSC passthrough
2353 	bool is_dsc_passthrough_supported;
2354 	struct dsc_dec_dpcd_caps dsc_dec_caps;
2355 };
2356 
2357 struct dc_sink_fec_caps {
2358 	bool is_rx_fec_supported;
2359 	bool is_topology_fec_supported;
2360 };
2361 
2362 struct scdc_caps {
2363 	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2364 	union hdmi_scdc_device_id_data device_id;
2365 };
2366 
2367 /*
2368  * The sink structure contains EDID and other display device properties
2369  */
2370 struct dc_sink {
2371 	enum signal_type sink_signal;
2372 	struct dc_edid dc_edid; /* raw edid */
2373 	struct dc_edid_caps edid_caps; /* parse display caps */
2374 	struct dc_container_id *dc_container_id;
2375 	uint32_t dongle_max_pix_clk;
2376 	void *priv;
2377 	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2378 	bool converter_disable_audio;
2379 
2380 	struct scdc_caps scdc_caps;
2381 	struct dc_sink_dsc_caps dsc_caps;
2382 	struct dc_sink_fec_caps fec_caps;
2383 
2384 	bool is_vsc_sdp_colorimetry_supported;
2385 
2386 	/* private to DC core */
2387 	struct dc_link *link;
2388 	struct dc_context *ctx;
2389 
2390 	uint32_t sink_id;
2391 
2392 	/* private to dc_sink.c */
2393 	// refcount must be the last member in dc_sink, since we want the
2394 	// sink structure to be logically cloneable up to (but not including)
2395 	// refcount
2396 	struct kref refcount;
2397 };
2398 
2399 void dc_sink_retain(struct dc_sink *sink);
2400 void dc_sink_release(struct dc_sink *sink);
2401 
2402 struct dc_sink_init_data {
2403 	enum signal_type sink_signal;
2404 	struct dc_link *link;
2405 	uint32_t dongle_max_pix_clk;
2406 	bool converter_disable_audio;
2407 };
2408 
2409 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2410 
2411 /* Newer interfaces  */
2412 struct dc_cursor {
2413 	struct dc_plane_address address;
2414 	struct dc_cursor_attributes attributes;
2415 };
2416 
2417 
2418 /* Interrupt interfaces */
2419 enum dc_irq_source dc_interrupt_to_irq_source(
2420 		struct dc *dc,
2421 		uint32_t src_id,
2422 		uint32_t ext_id);
2423 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2424 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2425 enum dc_irq_source dc_get_hpd_irq_source_at_index(
2426 		struct dc *dc, uint32_t link_index);
2427 
2428 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2429 
2430 /* Power Interfaces */
2431 
2432 void dc_set_power_state(
2433 		struct dc *dc,
2434 		enum dc_acpi_cm_power_state power_state);
2435 void dc_resume(struct dc *dc);
2436 
2437 void dc_power_down_on_boot(struct dc *dc);
2438 
2439 /*
2440  * HDCP Interfaces
2441  */
2442 enum hdcp_message_status dc_process_hdcp_msg(
2443 		enum signal_type signal,
2444 		struct dc_link *link,
2445 		struct hdcp_protection_message *message_info);
2446 bool dc_is_dmcu_initialized(struct dc *dc);
2447 
2448 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2449 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2450 
2451 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2452 		unsigned int pitch,
2453 		unsigned int height,
2454 		enum surface_pixel_format format,
2455 		struct dc_cursor_attributes *cursor_attr);
2456 
2457 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)
2458 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)
2459 
2460 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2461 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2462 bool dc_dmub_is_ips_idle_state(struct dc *dc);
2463 
2464 /* set min and max memory clock to lowest and highest DPM level, respectively */
2465 void dc_unlock_memory_clock_frequency(struct dc *dc);
2466 
2467 /* set min memory clock to the min required for current mode, max to maxDPM */
2468 void dc_lock_memory_clock_frequency(struct dc *dc);
2469 
2470 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2471 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2472 
2473 /* cleanup on driver unload */
2474 void dc_hardware_release(struct dc *dc);
2475 
2476 /* disables fw based mclk switch */
2477 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2478 
2479 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2480 
2481 bool dc_set_replay_allow_active(struct dc *dc, bool active);
2482 
2483 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2484 
2485 void dc_z10_restore(const struct dc *dc);
2486 void dc_z10_save_init(struct dc *dc);
2487 
2488 bool dc_is_dmub_outbox_supported(struct dc *dc);
2489 bool dc_enable_dmub_notifications(struct dc *dc);
2490 
2491 bool dc_abm_save_restore(
2492 		struct dc *dc,
2493 		struct dc_stream_state *stream,
2494 		struct abm_save_restore *pData);
2495 
2496 void dc_enable_dmub_outbox(struct dc *dc);
2497 
2498 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2499 				uint32_t link_index,
2500 				struct aux_payload *payload);
2501 
2502 /* Get dc link index from dpia port index */
2503 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2504 				uint8_t dpia_port_index);
2505 
2506 bool dc_process_dmub_set_config_async(struct dc *dc,
2507 				uint32_t link_index,
2508 				struct set_config_cmd_payload *payload,
2509 				struct dmub_notification *notify);
2510 
2511 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2512 				uint32_t link_index,
2513 				uint8_t mst_alloc_slots,
2514 				uint8_t *mst_slots_in_use);
2515 
2516 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2517 				uint32_t hpd_int_enable);
2518 
2519 void dc_print_dmub_diagnostic_data(const struct dc *dc);
2520 
2521 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2522 
2523 struct dc_power_profile {
2524 	int power_level; /* Lower is better */
2525 };
2526 
2527 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2528 
2529 /* DSC Interfaces */
2530 #include "dc_dsc.h"
2531 
2532 /* Disable acc mode Interfaces */
2533 void dc_disable_accelerated_mode(struct dc *dc);
2534 
2535 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2536 		       struct dc_stream_state *new_stream);
2537 
2538 #endif /* DC_INTERFACE_H_ */
2539