1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.75" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dp_protocol_version { 58 DP_VERSION_1_4, 59 }; 60 61 enum dc_plane_type { 62 DC_PLANE_TYPE_INVALID, 63 DC_PLANE_TYPE_DCE_RGB, 64 DC_PLANE_TYPE_DCE_UNDERLAY, 65 DC_PLANE_TYPE_DCN_UNIVERSAL, 66 }; 67 68 struct dc_plane_cap { 69 enum dc_plane_type type; 70 uint32_t blends_with_above : 1; 71 uint32_t blends_with_below : 1; 72 uint32_t per_pixel_alpha : 1; 73 struct { 74 uint32_t argb8888 : 1; 75 uint32_t nv12 : 1; 76 uint32_t fp16 : 1; 77 uint32_t p010 : 1; 78 uint32_t ayuv : 1; 79 } pixel_format_support; 80 // max upscaling factor x1000 81 // upscaling factors are always >= 1 82 // for example, 1080p -> 8K is 4.0, or 4000 raw value 83 struct { 84 uint32_t argb8888; 85 uint32_t nv12; 86 uint32_t fp16; 87 } max_upscale_factor; 88 // max downscale factor x1000 89 // downscale factors are always <= 1 90 // for example, 8K -> 1080p is 0.25, or 250 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_downscale_factor; 96 }; 97 98 struct dc_caps { 99 uint32_t max_streams; 100 uint32_t max_links; 101 uint32_t max_audios; 102 uint32_t max_slave_planes; 103 uint32_t max_planes; 104 uint32_t max_downscale_ratio; 105 uint32_t i2c_speed_in_khz; 106 uint32_t dmdata_alloc_size; 107 unsigned int max_cursor_size; 108 unsigned int max_video_width; 109 int linear_pitch_alignment; 110 bool dcc_const_color; 111 bool dynamic_audio; 112 bool is_apu; 113 bool dual_link_dvi; 114 bool post_blend_color_processing; 115 bool force_dp_tps4_for_cp2520; 116 bool disable_dp_clk_share; 117 bool psp_setup_panel_mode; 118 bool extended_aux_timeout_support; 119 bool dmcub_support; 120 bool hw_3d_lut; 121 enum dp_protocol_version max_dp_protocol_version; 122 struct dc_plane_cap planes[MAX_PLANES]; 123 }; 124 125 struct dc_bug_wa { 126 bool no_connect_phy_config; 127 bool dedcn20_305_wa; 128 bool skip_clock_update; 129 bool lt_early_cr_pattern; 130 }; 131 132 struct dc_dcc_surface_param { 133 struct dc_size surface_size; 134 enum surface_pixel_format format; 135 enum swizzle_mode_values swizzle_mode; 136 enum dc_scan_direction scan; 137 }; 138 139 struct dc_dcc_setting { 140 unsigned int max_compressed_blk_size; 141 unsigned int max_uncompressed_blk_size; 142 bool independent_64b_blks; 143 }; 144 145 struct dc_surface_dcc_cap { 146 union { 147 struct { 148 struct dc_dcc_setting rgb; 149 } grph; 150 151 struct { 152 struct dc_dcc_setting luma; 153 struct dc_dcc_setting chroma; 154 } video; 155 }; 156 157 bool capable; 158 bool const_color_support; 159 }; 160 161 struct dc_static_screen_params { 162 struct { 163 bool force_trigger; 164 bool cursor_update; 165 bool surface_update; 166 bool overlay_update; 167 } triggers; 168 unsigned int num_frames; 169 }; 170 171 172 /* Surface update type is used by dc_update_surfaces_and_stream 173 * The update type is determined at the very beginning of the function based 174 * on parameters passed in and decides how much programming (or updating) is 175 * going to be done during the call. 176 * 177 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 178 * logical calculations or hardware register programming. This update MUST be 179 * ISR safe on windows. Currently fast update will only be used to flip surface 180 * address. 181 * 182 * UPDATE_TYPE_MED is used for slower updates which require significant hw 183 * re-programming however do not affect bandwidth consumption or clock 184 * requirements. At present, this is the level at which front end updates 185 * that do not require us to run bw_calcs happen. These are in/out transfer func 186 * updates, viewport offset changes, recout size changes and pixel depth changes. 187 * This update can be done at ISR, but we want to minimize how often this happens. 188 * 189 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 190 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 191 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 192 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 193 * a full update. This cannot be done at ISR level and should be a rare event. 194 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 195 * underscan we don't expect to see this call at all. 196 */ 197 198 enum surface_update_type { 199 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 200 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 201 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 202 }; 203 204 /* Forward declaration*/ 205 struct dc; 206 struct dc_plane_state; 207 struct dc_state; 208 209 210 struct dc_cap_funcs { 211 bool (*get_dcc_compression_cap)(const struct dc *dc, 212 const struct dc_dcc_surface_param *input, 213 struct dc_surface_dcc_cap *output); 214 }; 215 216 struct link_training_settings; 217 218 219 /* Structure to hold configuration flags set by dm at dc creation. */ 220 struct dc_config { 221 bool gpu_vm_support; 222 bool disable_disp_pll_sharing; 223 bool fbc_support; 224 bool optimize_edp_link_rate; 225 bool disable_fractional_pwm; 226 bool allow_seamless_boot_optimization; 227 bool power_down_display_on_boot; 228 bool edp_not_connected; 229 bool force_enum_edp; 230 bool forced_clocks; 231 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 232 bool multi_mon_pp_mclk_switch; 233 bool psr_on_dmub; 234 }; 235 236 enum visual_confirm { 237 VISUAL_CONFIRM_DISABLE = 0, 238 VISUAL_CONFIRM_SURFACE = 1, 239 VISUAL_CONFIRM_HDR = 2, 240 VISUAL_CONFIRM_MPCTREE = 4, 241 }; 242 243 enum dcc_option { 244 DCC_ENABLE = 0, 245 DCC_DISABLE = 1, 246 DCC_HALF_REQ_DISALBE = 2, 247 }; 248 249 enum pipe_split_policy { 250 MPC_SPLIT_DYNAMIC = 0, 251 MPC_SPLIT_AVOID = 1, 252 MPC_SPLIT_AVOID_MULT_DISP = 2, 253 }; 254 255 enum wm_report_mode { 256 WM_REPORT_DEFAULT = 0, 257 WM_REPORT_OVERRIDE = 1, 258 }; 259 enum dtm_pstate{ 260 dtm_level_p0 = 0,/*highest voltage*/ 261 dtm_level_p1, 262 dtm_level_p2, 263 dtm_level_p3, 264 dtm_level_p4,/*when active_display_count = 0*/ 265 }; 266 267 enum dcn_pwr_state { 268 DCN_PWR_STATE_UNKNOWN = -1, 269 DCN_PWR_STATE_MISSION_MODE = 0, 270 DCN_PWR_STATE_LOW_POWER = 3, 271 }; 272 273 /* 274 * For any clocks that may differ per pipe 275 * only the max is stored in this structure 276 */ 277 struct dc_clocks { 278 int dispclk_khz; 279 int dppclk_khz; 280 int dcfclk_khz; 281 int socclk_khz; 282 int dcfclk_deep_sleep_khz; 283 int fclk_khz; 284 int phyclk_khz; 285 int dramclk_khz; 286 bool p_state_change_support; 287 enum dcn_pwr_state pwr_state; 288 /* 289 * Elements below are not compared for the purposes of 290 * optimization required 291 */ 292 bool prev_p_state_change_support; 293 enum dtm_pstate dtm_level; 294 int max_supported_dppclk_khz; 295 int max_supported_dispclk_khz; 296 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 297 int bw_dispclk_khz; 298 }; 299 300 struct dc_bw_validation_profile { 301 bool enable; 302 303 unsigned long long total_ticks; 304 unsigned long long voltage_level_ticks; 305 unsigned long long watermark_ticks; 306 unsigned long long rq_dlg_ticks; 307 308 unsigned long long total_count; 309 unsigned long long skip_fast_count; 310 unsigned long long skip_pass_count; 311 unsigned long long skip_fail_count; 312 }; 313 314 #define BW_VAL_TRACE_SETUP() \ 315 unsigned long long end_tick = 0; \ 316 unsigned long long voltage_level_tick = 0; \ 317 unsigned long long watermark_tick = 0; \ 318 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 319 dm_get_timestamp(dc->ctx) : 0 320 321 #define BW_VAL_TRACE_COUNT() \ 322 if (dc->debug.bw_val_profile.enable) \ 323 dc->debug.bw_val_profile.total_count++ 324 325 #define BW_VAL_TRACE_SKIP(status) \ 326 if (dc->debug.bw_val_profile.enable) { \ 327 if (!voltage_level_tick) \ 328 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 329 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 330 } 331 332 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 333 if (dc->debug.bw_val_profile.enable) \ 334 voltage_level_tick = dm_get_timestamp(dc->ctx) 335 336 #define BW_VAL_TRACE_END_WATERMARKS() \ 337 if (dc->debug.bw_val_profile.enable) \ 338 watermark_tick = dm_get_timestamp(dc->ctx) 339 340 #define BW_VAL_TRACE_FINISH() \ 341 if (dc->debug.bw_val_profile.enable) { \ 342 end_tick = dm_get_timestamp(dc->ctx); \ 343 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 344 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 345 if (watermark_tick) { \ 346 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 347 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 348 } \ 349 } 350 351 struct dc_debug_options { 352 enum visual_confirm visual_confirm; 353 bool sanity_checks; 354 bool max_disp_clk; 355 bool surface_trace; 356 bool timing_trace; 357 bool clock_trace; 358 bool validation_trace; 359 bool bandwidth_calcs_trace; 360 int max_downscale_src_width; 361 362 /* stutter efficiency related */ 363 bool disable_stutter; 364 bool use_max_lb; 365 enum dcc_option disable_dcc; 366 enum pipe_split_policy pipe_split_policy; 367 bool force_single_disp_pipe_split; 368 bool voltage_align_fclk; 369 370 bool disable_dfs_bypass; 371 bool disable_dpp_power_gate; 372 bool disable_hubp_power_gate; 373 bool disable_dsc_power_gate; 374 int dsc_min_slice_height_override; 375 int dsc_bpp_increment_div; 376 bool native422_support; 377 bool disable_pplib_wm_range; 378 enum wm_report_mode pplib_wm_report_mode; 379 unsigned int min_disp_clk_khz; 380 unsigned int min_dpp_clk_khz; 381 int sr_exit_time_dpm0_ns; 382 int sr_enter_plus_exit_time_dpm0_ns; 383 int sr_exit_time_ns; 384 int sr_enter_plus_exit_time_ns; 385 int urgent_latency_ns; 386 uint32_t underflow_assert_delay_us; 387 int percent_of_ideal_drambw; 388 int dram_clock_change_latency_ns; 389 bool optimized_watermark; 390 int always_scale; 391 bool disable_pplib_clock_request; 392 bool disable_clock_gate; 393 bool disable_dmcu; 394 bool disable_psr; 395 bool force_abm_enable; 396 bool disable_stereo_support; 397 bool vsr_support; 398 bool performance_trace; 399 bool az_endpoint_mute_only; 400 bool always_use_regamma; 401 bool p010_mpo_support; 402 bool recovery_enabled; 403 bool avoid_vbios_exec_table; 404 bool scl_reset_length10; 405 bool hdmi20_disable; 406 bool skip_detection_link_training; 407 bool remove_disconnect_edp; 408 unsigned int force_odm_combine; //bit vector based on otg inst 409 unsigned int force_fclk_khz; 410 bool disable_tri_buf; 411 bool dmub_offload_enabled; 412 bool dmcub_emulation; 413 bool dmub_command_table; /* for testing only */ 414 struct dc_bw_validation_profile bw_val_profile; 415 bool disable_fec; 416 bool disable_48mhz_pwrdwn; 417 /* This forces a hard min on the DCFCLK requested to SMU/PP 418 * watermarks are not affected. 419 */ 420 unsigned int force_min_dcfclk_mhz; 421 bool disable_timing_sync; 422 bool cm_in_bypass; 423 int force_clock_mode;/*every mode change.*/ 424 425 bool nv12_iflip_vm_wa; 426 bool disable_dram_clock_change_vactive_support; 427 bool validate_dml_output; 428 bool enable_dmcub_surface_flip; 429 bool usbc_combo_phy_reset_wa; 430 bool disable_dsc; 431 }; 432 433 struct dc_debug_data { 434 uint32_t ltFailCount; 435 uint32_t i2cErrorCount; 436 uint32_t auxErrorCount; 437 }; 438 439 struct dc_phy_addr_space_config { 440 struct { 441 uint64_t start_addr; 442 uint64_t end_addr; 443 uint64_t fb_top; 444 uint64_t fb_offset; 445 uint64_t fb_base; 446 uint64_t agp_top; 447 uint64_t agp_bot; 448 uint64_t agp_base; 449 } system_aperture; 450 451 struct { 452 uint64_t page_table_start_addr; 453 uint64_t page_table_end_addr; 454 uint64_t page_table_base_addr; 455 } gart_config; 456 457 bool valid; 458 bool is_hvm_enabled; 459 uint64_t page_table_default_page_addr; 460 }; 461 462 struct dc_virtual_addr_space_config { 463 uint64_t page_table_base_addr; 464 uint64_t page_table_start_addr; 465 uint64_t page_table_end_addr; 466 uint32_t page_table_block_size_in_bytes; 467 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 468 }; 469 470 struct dc_bounding_box_overrides { 471 int sr_exit_time_ns; 472 int sr_enter_plus_exit_time_ns; 473 int urgent_latency_ns; 474 int percent_of_ideal_drambw; 475 int dram_clock_change_latency_ns; 476 /* This forces a hard min on the DCFCLK we use 477 * for DML. Unlike the debug option for forcing 478 * DCFCLK, this override affects watermark calculations 479 */ 480 int min_dcfclk_mhz; 481 }; 482 483 struct dc_state; 484 struct resource_pool; 485 struct dce_hwseq; 486 struct gpu_info_soc_bounding_box_v1_0; 487 struct dc { 488 struct dc_versions versions; 489 struct dc_caps caps; 490 struct dc_cap_funcs cap_funcs; 491 struct dc_config config; 492 struct dc_debug_options debug; 493 struct dc_bounding_box_overrides bb_overrides; 494 struct dc_bug_wa work_arounds; 495 struct dc_context *ctx; 496 struct dc_phy_addr_space_config vm_pa_config; 497 498 uint8_t link_count; 499 struct dc_link *links[MAX_PIPES * 2]; 500 501 struct dc_state *current_state; 502 struct resource_pool *res_pool; 503 504 struct clk_mgr *clk_mgr; 505 506 /* Display Engine Clock levels */ 507 struct dm_pp_clock_levels sclk_lvls; 508 509 /* Inputs into BW and WM calculations. */ 510 struct bw_calcs_dceip *bw_dceip; 511 struct bw_calcs_vbios *bw_vbios; 512 #ifdef CONFIG_DRM_AMD_DC_DCN 513 struct dcn_soc_bounding_box *dcn_soc; 514 struct dcn_ip_params *dcn_ip; 515 struct display_mode_lib dml; 516 #endif 517 518 /* HW functions */ 519 struct hw_sequencer_funcs hwss; 520 struct dce_hwseq *hwseq; 521 522 /* Require to optimize clocks and bandwidth for added/removed planes */ 523 bool clk_optimized_required; 524 bool wm_optimized_required; 525 526 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 527 int optimize_seamless_boot_streams; 528 529 /* FBC compressor */ 530 struct compressor *fbc_compressor; 531 532 struct dc_debug_data debug_data; 533 struct dpcd_vendor_signature vendor_signature; 534 535 const char *build_id; 536 struct vm_helper *vm_helper; 537 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 538 }; 539 540 enum frame_buffer_mode { 541 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 542 FRAME_BUFFER_MODE_ZFB_ONLY, 543 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 544 } ; 545 546 struct dchub_init_data { 547 int64_t zfb_phys_addr_base; 548 int64_t zfb_mc_base_addr; 549 uint64_t zfb_size_in_byte; 550 enum frame_buffer_mode fb_mode; 551 bool dchub_initialzied; 552 bool dchub_info_valid; 553 }; 554 555 struct dc_init_data { 556 struct hw_asic_id asic_id; 557 void *driver; /* ctx */ 558 struct cgs_device *cgs_device; 559 struct dc_bounding_box_overrides bb_overrides; 560 561 int num_virtual_links; 562 /* 563 * If 'vbios_override' not NULL, it will be called instead 564 * of the real VBIOS. Intended use is Diagnostics on FPGA. 565 */ 566 struct dc_bios *vbios_override; 567 enum dce_environment dce_environment; 568 569 struct dmub_offload_funcs *dmub_if; 570 struct dc_reg_helper_state *dmub_offload; 571 572 struct dc_config flags; 573 uint64_t log_mask; 574 575 /** 576 * gpu_info FW provided soc bounding box struct or 0 if not 577 * available in FW 578 */ 579 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 580 struct dpcd_vendor_signature vendor_signature; 581 }; 582 583 struct dc_callback_init { 584 #ifdef CONFIG_DRM_AMD_DC_HDCP 585 struct cp_psp cp_psp; 586 #else 587 uint8_t reserved; 588 #endif 589 }; 590 591 struct dc *dc_create(const struct dc_init_data *init_params); 592 void dc_hardware_init(struct dc *dc); 593 594 int dc_get_vmid_use_vector(struct dc *dc); 595 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 596 /* Returns the number of vmids supported */ 597 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 598 void dc_init_callbacks(struct dc *dc, 599 const struct dc_callback_init *init_params); 600 void dc_deinit_callbacks(struct dc *dc); 601 void dc_destroy(struct dc **dc); 602 603 /******************************************************************************* 604 * Surface Interfaces 605 ******************************************************************************/ 606 607 enum { 608 TRANSFER_FUNC_POINTS = 1025 609 }; 610 611 struct dc_hdr_static_metadata { 612 /* display chromaticities and white point in units of 0.00001 */ 613 unsigned int chromaticity_green_x; 614 unsigned int chromaticity_green_y; 615 unsigned int chromaticity_blue_x; 616 unsigned int chromaticity_blue_y; 617 unsigned int chromaticity_red_x; 618 unsigned int chromaticity_red_y; 619 unsigned int chromaticity_white_point_x; 620 unsigned int chromaticity_white_point_y; 621 622 uint32_t min_luminance; 623 uint32_t max_luminance; 624 uint32_t maximum_content_light_level; 625 uint32_t maximum_frame_average_light_level; 626 }; 627 628 enum dc_transfer_func_type { 629 TF_TYPE_PREDEFINED, 630 TF_TYPE_DISTRIBUTED_POINTS, 631 TF_TYPE_BYPASS, 632 TF_TYPE_HWPWL 633 }; 634 635 struct dc_transfer_func_distributed_points { 636 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 637 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 638 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 639 640 uint16_t end_exponent; 641 uint16_t x_point_at_y1_red; 642 uint16_t x_point_at_y1_green; 643 uint16_t x_point_at_y1_blue; 644 }; 645 646 enum dc_transfer_func_predefined { 647 TRANSFER_FUNCTION_SRGB, 648 TRANSFER_FUNCTION_BT709, 649 TRANSFER_FUNCTION_PQ, 650 TRANSFER_FUNCTION_LINEAR, 651 TRANSFER_FUNCTION_UNITY, 652 TRANSFER_FUNCTION_HLG, 653 TRANSFER_FUNCTION_HLG12, 654 TRANSFER_FUNCTION_GAMMA22, 655 TRANSFER_FUNCTION_GAMMA24, 656 TRANSFER_FUNCTION_GAMMA26 657 }; 658 659 660 struct dc_transfer_func { 661 struct kref refcount; 662 enum dc_transfer_func_type type; 663 enum dc_transfer_func_predefined tf; 664 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 665 uint32_t sdr_ref_white_level; 666 struct dc_context *ctx; 667 union { 668 struct pwl_params pwl; 669 struct dc_transfer_func_distributed_points tf_pts; 670 }; 671 }; 672 673 674 union dc_3dlut_state { 675 struct { 676 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 677 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 678 uint32_t rmu_mux_num:3; /*index of mux to use*/ 679 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 680 uint32_t mpc_rmu1_mux:4; 681 uint32_t mpc_rmu2_mux:4; 682 uint32_t reserved:15; 683 } bits; 684 uint32_t raw; 685 }; 686 687 688 struct dc_3dlut { 689 struct kref refcount; 690 struct tetrahedral_params lut_3d; 691 struct fixed31_32 hdr_multiplier; 692 union dc_3dlut_state state; 693 struct dc_context *ctx; 694 }; 695 /* 696 * This structure is filled in by dc_surface_get_status and contains 697 * the last requested address and the currently active address so the called 698 * can determine if there are any outstanding flips 699 */ 700 struct dc_plane_status { 701 struct dc_plane_address requested_address; 702 struct dc_plane_address current_address; 703 bool is_flip_pending; 704 bool is_right_eye; 705 }; 706 707 union surface_update_flags { 708 709 struct { 710 uint32_t addr_update:1; 711 /* Medium updates */ 712 uint32_t dcc_change:1; 713 uint32_t color_space_change:1; 714 uint32_t horizontal_mirror_change:1; 715 uint32_t per_pixel_alpha_change:1; 716 uint32_t global_alpha_change:1; 717 uint32_t hdr_mult:1; 718 uint32_t rotation_change:1; 719 uint32_t swizzle_change:1; 720 uint32_t scaling_change:1; 721 uint32_t position_change:1; 722 uint32_t in_transfer_func_change:1; 723 uint32_t input_csc_change:1; 724 uint32_t coeff_reduction_change:1; 725 uint32_t output_tf_change:1; 726 uint32_t pixel_format_change:1; 727 uint32_t plane_size_change:1; 728 729 /* Full updates */ 730 uint32_t new_plane:1; 731 uint32_t bpp_change:1; 732 uint32_t gamma_change:1; 733 uint32_t bandwidth_change:1; 734 uint32_t clock_change:1; 735 uint32_t stereo_format_change:1; 736 uint32_t full_update:1; 737 } bits; 738 739 uint32_t raw; 740 }; 741 742 struct dc_plane_state { 743 struct dc_plane_address address; 744 struct dc_plane_flip_time time; 745 bool triplebuffer_flips; 746 struct scaling_taps scaling_quality; 747 struct rect src_rect; 748 struct rect dst_rect; 749 struct rect clip_rect; 750 751 struct plane_size plane_size; 752 union dc_tiling_info tiling_info; 753 754 struct dc_plane_dcc_param dcc; 755 756 struct dc_gamma *gamma_correction; 757 struct dc_transfer_func *in_transfer_func; 758 struct dc_bias_and_scale *bias_and_scale; 759 struct dc_csc_transform input_csc_color_matrix; 760 struct fixed31_32 coeff_reduction_factor; 761 struct fixed31_32 hdr_mult; 762 763 // TODO: No longer used, remove 764 struct dc_hdr_static_metadata hdr_static_ctx; 765 766 enum dc_color_space color_space; 767 768 struct dc_3dlut *lut3d_func; 769 struct dc_transfer_func *in_shaper_func; 770 struct dc_transfer_func *blend_tf; 771 772 enum surface_pixel_format format; 773 enum dc_rotation_angle rotation; 774 enum plane_stereo_format stereo_format; 775 776 bool is_tiling_rotated; 777 bool per_pixel_alpha; 778 bool global_alpha; 779 int global_alpha_value; 780 bool visible; 781 bool flip_immediate; 782 bool horizontal_mirror; 783 int layer_index; 784 785 union surface_update_flags update_flags; 786 /* private to DC core */ 787 struct dc_plane_status status; 788 struct dc_context *ctx; 789 790 /* HACK: Workaround for forcing full reprogramming under some conditions */ 791 bool force_full_update; 792 793 /* private to dc_surface.c */ 794 enum dc_irq_source irq_source; 795 struct kref refcount; 796 }; 797 798 struct dc_plane_info { 799 struct plane_size plane_size; 800 union dc_tiling_info tiling_info; 801 struct dc_plane_dcc_param dcc; 802 enum surface_pixel_format format; 803 enum dc_rotation_angle rotation; 804 enum plane_stereo_format stereo_format; 805 enum dc_color_space color_space; 806 bool horizontal_mirror; 807 bool visible; 808 bool per_pixel_alpha; 809 bool global_alpha; 810 int global_alpha_value; 811 bool input_csc_enabled; 812 int layer_index; 813 }; 814 815 struct dc_scaling_info { 816 struct rect src_rect; 817 struct rect dst_rect; 818 struct rect clip_rect; 819 struct scaling_taps scaling_quality; 820 }; 821 822 struct dc_surface_update { 823 struct dc_plane_state *surface; 824 825 /* isr safe update parameters. null means no updates */ 826 const struct dc_flip_addrs *flip_addr; 827 const struct dc_plane_info *plane_info; 828 const struct dc_scaling_info *scaling_info; 829 struct fixed31_32 hdr_mult; 830 /* following updates require alloc/sleep/spin that is not isr safe, 831 * null means no updates 832 */ 833 const struct dc_gamma *gamma; 834 const struct dc_transfer_func *in_transfer_func; 835 836 const struct dc_csc_transform *input_csc_color_matrix; 837 const struct fixed31_32 *coeff_reduction_factor; 838 const struct dc_transfer_func *func_shaper; 839 const struct dc_3dlut *lut3d_func; 840 const struct dc_transfer_func *blend_tf; 841 }; 842 843 /* 844 * Create a new surface with default parameters; 845 */ 846 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 847 const struct dc_plane_status *dc_plane_get_status( 848 const struct dc_plane_state *plane_state); 849 850 void dc_plane_state_retain(struct dc_plane_state *plane_state); 851 void dc_plane_state_release(struct dc_plane_state *plane_state); 852 853 void dc_gamma_retain(struct dc_gamma *dc_gamma); 854 void dc_gamma_release(struct dc_gamma **dc_gamma); 855 struct dc_gamma *dc_create_gamma(void); 856 857 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 858 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 859 struct dc_transfer_func *dc_create_transfer_func(void); 860 861 struct dc_3dlut *dc_create_3dlut_func(void); 862 void dc_3dlut_func_release(struct dc_3dlut *lut); 863 void dc_3dlut_func_retain(struct dc_3dlut *lut); 864 /* 865 * This structure holds a surface address. There could be multiple addresses 866 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 867 * as frame durations and DCC format can also be set. 868 */ 869 struct dc_flip_addrs { 870 struct dc_plane_address address; 871 unsigned int flip_timestamp_in_us; 872 bool flip_immediate; 873 /* TODO: add flip duration for FreeSync */ 874 }; 875 876 bool dc_post_update_surfaces_to_stream( 877 struct dc *dc); 878 879 #include "dc_stream.h" 880 881 /* 882 * Structure to store surface/stream associations for validation 883 */ 884 struct dc_validation_set { 885 struct dc_stream_state *stream; 886 struct dc_plane_state *plane_states[MAX_SURFACES]; 887 uint8_t plane_count; 888 }; 889 890 bool dc_validate_seamless_boot_timing(const struct dc *dc, 891 const struct dc_sink *sink, 892 struct dc_crtc_timing *crtc_timing); 893 894 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 895 896 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 897 898 bool dc_set_generic_gpio_for_stereo(bool enable, 899 struct gpio_service *gpio_service); 900 901 /* 902 * fast_validate: we return after determining if we can support the new state, 903 * but before we populate the programming info 904 */ 905 enum dc_status dc_validate_global_state( 906 struct dc *dc, 907 struct dc_state *new_ctx, 908 bool fast_validate); 909 910 911 void dc_resource_state_construct( 912 const struct dc *dc, 913 struct dc_state *dst_ctx); 914 915 void dc_resource_state_copy_construct( 916 const struct dc_state *src_ctx, 917 struct dc_state *dst_ctx); 918 919 void dc_resource_state_copy_construct_current( 920 const struct dc *dc, 921 struct dc_state *dst_ctx); 922 923 void dc_resource_state_destruct(struct dc_state *context); 924 925 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 926 927 /* 928 * TODO update to make it about validation sets 929 * Set up streams and links associated to drive sinks 930 * The streams parameter is an absolute set of all active streams. 931 * 932 * After this call: 933 * Phy, Encoder, Timing Generator are programmed and enabled. 934 * New streams are enabled with blank stream; no memory read. 935 */ 936 bool dc_commit_state(struct dc *dc, struct dc_state *context); 937 938 939 struct dc_state *dc_create_state(struct dc *dc); 940 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 941 void dc_retain_state(struct dc_state *context); 942 void dc_release_state(struct dc_state *context); 943 944 /******************************************************************************* 945 * Link Interfaces 946 ******************************************************************************/ 947 948 struct dpcd_caps { 949 union dpcd_rev dpcd_rev; 950 union max_lane_count max_ln_count; 951 union max_down_spread max_down_spread; 952 union dprx_feature dprx_feature; 953 954 /* valid only for eDP v1.4 or higher*/ 955 uint8_t edp_supported_link_rates_count; 956 enum dc_link_rate edp_supported_link_rates[8]; 957 958 /* dongle type (DP converter, CV smart dongle) */ 959 enum display_dongle_type dongle_type; 960 /* branch device or sink device */ 961 bool is_branch_dev; 962 /* Dongle's downstream count. */ 963 union sink_count sink_count; 964 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 965 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 966 struct dc_dongle_caps dongle_caps; 967 968 uint32_t sink_dev_id; 969 int8_t sink_dev_id_str[6]; 970 int8_t sink_hw_revision; 971 int8_t sink_fw_revision[2]; 972 973 uint32_t branch_dev_id; 974 int8_t branch_dev_name[6]; 975 int8_t branch_hw_revision; 976 int8_t branch_fw_revision[2]; 977 978 bool allow_invalid_MSA_timing_param; 979 bool panel_mode_edp; 980 bool dpcd_display_control_capable; 981 bool ext_receiver_cap_field_present; 982 union dpcd_fec_capability fec_cap; 983 struct dpcd_dsc_capabilities dsc_caps; 984 struct dc_lttpr_caps lttpr_caps; 985 986 }; 987 988 union dpcd_sink_ext_caps { 989 struct { 990 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 991 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 992 */ 993 uint8_t sdr_aux_backlight_control : 1; 994 uint8_t hdr_aux_backlight_control : 1; 995 uint8_t reserved_1 : 2; 996 uint8_t oled : 1; 997 uint8_t reserved : 3; 998 } bits; 999 uint8_t raw; 1000 }; 1001 1002 #include "dc_link.h" 1003 1004 /******************************************************************************* 1005 * Sink Interfaces - A sink corresponds to a display output device 1006 ******************************************************************************/ 1007 1008 struct dc_container_id { 1009 // 128bit GUID in binary form 1010 unsigned char guid[16]; 1011 // 8 byte port ID -> ELD.PortID 1012 unsigned int portId[2]; 1013 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1014 unsigned short manufacturerName; 1015 // 2 byte product code -> ELD.ProductCode 1016 unsigned short productCode; 1017 }; 1018 1019 1020 struct dc_sink_dsc_caps { 1021 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1022 // 'false' if they are sink's DSC caps 1023 bool is_virtual_dpcd_dsc; 1024 struct dsc_dec_dpcd_caps dsc_dec_caps; 1025 }; 1026 1027 /* 1028 * The sink structure contains EDID and other display device properties 1029 */ 1030 struct dc_sink { 1031 enum signal_type sink_signal; 1032 struct dc_edid dc_edid; /* raw edid */ 1033 struct dc_edid_caps edid_caps; /* parse display caps */ 1034 struct dc_container_id *dc_container_id; 1035 uint32_t dongle_max_pix_clk; 1036 void *priv; 1037 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1038 bool converter_disable_audio; 1039 1040 struct dc_sink_dsc_caps sink_dsc_caps; 1041 1042 /* private to DC core */ 1043 struct dc_link *link; 1044 struct dc_context *ctx; 1045 1046 uint32_t sink_id; 1047 1048 /* private to dc_sink.c */ 1049 // refcount must be the last member in dc_sink, since we want the 1050 // sink structure to be logically cloneable up to (but not including) 1051 // refcount 1052 struct kref refcount; 1053 }; 1054 1055 void dc_sink_retain(struct dc_sink *sink); 1056 void dc_sink_release(struct dc_sink *sink); 1057 1058 struct dc_sink_init_data { 1059 enum signal_type sink_signal; 1060 struct dc_link *link; 1061 uint32_t dongle_max_pix_clk; 1062 bool converter_disable_audio; 1063 }; 1064 1065 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1066 1067 /* Newer interfaces */ 1068 struct dc_cursor { 1069 struct dc_plane_address address; 1070 struct dc_cursor_attributes attributes; 1071 }; 1072 1073 1074 /******************************************************************************* 1075 * Interrupt interfaces 1076 ******************************************************************************/ 1077 enum dc_irq_source dc_interrupt_to_irq_source( 1078 struct dc *dc, 1079 uint32_t src_id, 1080 uint32_t ext_id); 1081 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1082 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1083 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1084 struct dc *dc, uint32_t link_index); 1085 1086 /******************************************************************************* 1087 * Power Interfaces 1088 ******************************************************************************/ 1089 1090 void dc_set_power_state( 1091 struct dc *dc, 1092 enum dc_acpi_cm_power_state power_state); 1093 void dc_resume(struct dc *dc); 1094 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1095 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1096 1097 bool dc_is_dmcu_initialized(struct dc *dc); 1098 1099 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1100 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1101 /******************************************************************************* 1102 * DSC Interfaces 1103 ******************************************************************************/ 1104 #include "dc_dsc.h" 1105 #endif /* DC_INTERFACE_H_ */ 1106