1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 29 #include "ObjectID.h" 30 #include "atomfirmware.h" 31 32 #include "dc_bios_types.h" 33 #include "include/grph_object_ctrl_defs.h" 34 #include "include/bios_parser_interface.h" 35 #include "include/i2caux_interface.h" 36 #include "include/logger_interface.h" 37 38 #include "command_table2.h" 39 40 #include "bios_parser_helper.h" 41 #include "command_table_helper2.h" 42 #include "bios_parser2.h" 43 #include "bios_parser_types_internal2.h" 44 #include "bios_parser_interface.h" 45 46 #include "bios_parser_common.h" 47 48 #define DC_LOGGER \ 49 bp->base.ctx->logger 50 51 #define LAST_RECORD_TYPE 0xff 52 #define SMU9_SYSPLL0_ID 0 53 54 struct i2c_id_config_access { 55 uint8_t bfI2C_LineMux:4; 56 uint8_t bfHW_EngineID:3; 57 uint8_t bfHW_Capable:1; 58 uint8_t ucAccess; 59 }; 60 61 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 62 struct atom_i2c_record *record, 63 struct graphics_object_i2c_info *info); 64 65 static enum bp_result bios_parser_get_firmware_info( 66 struct dc_bios *dcb, 67 struct dc_firmware_info *info); 68 69 static enum bp_result bios_parser_get_encoder_cap_info( 70 struct dc_bios *dcb, 71 struct graphics_object_id object_id, 72 struct bp_encoder_cap_info *info); 73 74 static enum bp_result get_firmware_info_v3_1( 75 struct bios_parser *bp, 76 struct dc_firmware_info *info); 77 78 static enum bp_result get_firmware_info_v3_2( 79 struct bios_parser *bp, 80 struct dc_firmware_info *info); 81 82 static enum bp_result get_firmware_info_v3_4( 83 struct bios_parser *bp, 84 struct dc_firmware_info *info); 85 86 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 87 struct atom_display_object_path_v2 *object); 88 89 static struct atom_encoder_caps_record *get_encoder_cap_record( 90 struct bios_parser *bp, 91 struct atom_display_object_path_v2 *object); 92 93 #define BIOS_IMAGE_SIZE_OFFSET 2 94 #define BIOS_IMAGE_SIZE_UNIT 512 95 96 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 97 98 static void bios_parser2_destruct(struct bios_parser *bp) 99 { 100 kfree(bp->base.bios_local_image); 101 kfree(bp->base.integrated_info); 102 } 103 104 static void firmware_parser_destroy(struct dc_bios **dcb) 105 { 106 struct bios_parser *bp = BP_FROM_DCB(*dcb); 107 108 if (!bp) { 109 BREAK_TO_DEBUGGER(); 110 return; 111 } 112 113 bios_parser2_destruct(bp); 114 115 kfree(bp); 116 *dcb = NULL; 117 } 118 119 static void get_atom_data_table_revision( 120 struct atom_common_table_header *atom_data_tbl, 121 struct atom_data_revision *tbl_revision) 122 { 123 if (!tbl_revision) 124 return; 125 126 /* initialize the revision to 0 which is invalid revision */ 127 tbl_revision->major = 0; 128 tbl_revision->minor = 0; 129 130 if (!atom_data_tbl) 131 return; 132 133 tbl_revision->major = 134 (uint32_t) atom_data_tbl->format_revision & 0x3f; 135 tbl_revision->minor = 136 (uint32_t) atom_data_tbl->content_revision & 0x3f; 137 } 138 139 /* BIOS oject table displaypath is per connector. 140 * There is extra path not for connector. BIOS fill its encoderid as 0 141 */ 142 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 143 { 144 struct bios_parser *bp = BP_FROM_DCB(dcb); 145 unsigned int count = 0; 146 unsigned int i; 147 148 switch (bp->object_info_tbl.revision.minor) { 149 default: 150 case 4: 151 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 152 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 153 count++; 154 155 break; 156 157 case 5: 158 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 159 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 160 count++; 161 162 break; 163 } 164 return count; 165 } 166 167 static struct graphics_object_id bios_parser_get_connector_id( 168 struct dc_bios *dcb, 169 uint8_t i) 170 { 171 struct bios_parser *bp = BP_FROM_DCB(dcb); 172 struct graphics_object_id object_id = dal_graphics_object_id_init( 173 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 174 struct object_info_table *tbl = &bp->object_info_tbl; 175 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 176 177 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 178 179 switch (bp->object_info_tbl.revision.minor) { 180 default: 181 case 4: 182 if (v1_4->number_of_path > i) { 183 /* If display_objid is generic object id, the encoderObj 184 * /extencoderobjId should be 0 185 */ 186 if (v1_4->display_path[i].encoderobjid != 0 && 187 v1_4->display_path[i].display_objid != 0) 188 object_id = object_id_from_bios_object_id( 189 v1_4->display_path[i].display_objid); 190 } 191 break; 192 193 case 5: 194 if (v1_5->number_of_path > i) { 195 /* If display_objid is generic object id, the encoderObjId 196 * should be 0 197 */ 198 if (v1_5->display_path[i].encoderobjid != 0 && 199 v1_5->display_path[i].display_objid != 0) 200 object_id = object_id_from_bios_object_id( 201 v1_5->display_path[i].display_objid); 202 } 203 break; 204 } 205 return object_id; 206 } 207 208 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 209 struct graphics_object_id object_id, uint32_t index, 210 struct graphics_object_id *src_object_id) 211 { 212 struct bios_parser *bp = BP_FROM_DCB(dcb); 213 unsigned int i; 214 enum bp_result bp_result = BP_RESULT_BADINPUT; 215 struct graphics_object_id obj_id = { 0 }; 216 struct object_info_table *tbl = &bp->object_info_tbl; 217 218 if (!src_object_id) 219 return bp_result; 220 221 switch (object_id.type) { 222 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 223 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 224 */ 225 case OBJECT_TYPE_ENCODER: 226 /* TODO: since num of src must be less than 2. 227 * If found in for loop, should break. 228 * DAL2 implementation may be changed too 229 */ 230 switch (bp->object_info_tbl.revision.minor) { 231 default: 232 case 4: 233 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 234 obj_id = object_id_from_bios_object_id( 235 tbl->v1_4->display_path[i].encoderobjid); 236 if (object_id.type == obj_id.type && 237 object_id.id == obj_id.id && 238 object_id.enum_id == obj_id.enum_id) { 239 *src_object_id = 240 object_id_from_bios_object_id( 241 0x1100); 242 /* break; */ 243 } 244 } 245 bp_result = BP_RESULT_OK; 246 break; 247 248 case 5: 249 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 250 obj_id = object_id_from_bios_object_id( 251 tbl->v1_5->display_path[i].encoderobjid); 252 if (object_id.type == obj_id.type && 253 object_id.id == obj_id.id && 254 object_id.enum_id == obj_id.enum_id) { 255 *src_object_id = 256 object_id_from_bios_object_id( 257 0x1100); 258 /* break; */ 259 } 260 } 261 bp_result = BP_RESULT_OK; 262 break; 263 } 264 break; 265 case OBJECT_TYPE_CONNECTOR: 266 switch (bp->object_info_tbl.revision.minor) { 267 default: 268 case 4: 269 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 270 obj_id = object_id_from_bios_object_id( 271 tbl->v1_4->display_path[i] 272 .display_objid); 273 274 if (object_id.type == obj_id.type && 275 object_id.id == obj_id.id && 276 object_id.enum_id == obj_id.enum_id) { 277 *src_object_id = 278 object_id_from_bios_object_id( 279 tbl->v1_4 280 ->display_path[i] 281 .encoderobjid); 282 /* break; */ 283 } 284 } 285 bp_result = BP_RESULT_OK; 286 break; 287 } 288 bp_result = BP_RESULT_OK; 289 break; 290 case 5: 291 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 292 obj_id = object_id_from_bios_object_id( 293 tbl->v1_5->display_path[i].display_objid); 294 295 if (object_id.type == obj_id.type && 296 object_id.id == obj_id.id && 297 object_id.enum_id == obj_id.enum_id) { 298 *src_object_id = object_id_from_bios_object_id( 299 tbl->v1_5->display_path[i].encoderobjid); 300 /* break; */ 301 } 302 } 303 bp_result = BP_RESULT_OK; 304 break; 305 306 default: 307 bp_result = BP_RESULT_OK; 308 break; 309 } 310 311 return bp_result; 312 } 313 314 /* from graphics_object_id, find display path which includes the object_id */ 315 static struct atom_display_object_path_v2 *get_bios_object( 316 struct bios_parser *bp, 317 struct graphics_object_id id) 318 { 319 unsigned int i; 320 struct graphics_object_id obj_id = {0}; 321 322 switch (id.type) { 323 case OBJECT_TYPE_ENCODER: 324 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 325 obj_id = object_id_from_bios_object_id( 326 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 327 if (id.type == obj_id.type && id.id == obj_id.id 328 && id.enum_id == obj_id.enum_id) 329 return &bp->object_info_tbl.v1_4->display_path[i]; 330 } 331 fallthrough; 332 case OBJECT_TYPE_CONNECTOR: 333 case OBJECT_TYPE_GENERIC: 334 /* Both Generic and Connector Object ID 335 * will be stored on display_objid 336 */ 337 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 338 obj_id = object_id_from_bios_object_id( 339 bp->object_info_tbl.v1_4->display_path[i].display_objid); 340 if (id.type == obj_id.type && id.id == obj_id.id 341 && id.enum_id == obj_id.enum_id) 342 return &bp->object_info_tbl.v1_4->display_path[i]; 343 } 344 fallthrough; 345 default: 346 return NULL; 347 } 348 } 349 350 /* from graphics_object_id, find display path which includes the object_id */ 351 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( 352 struct bios_parser *bp, 353 struct graphics_object_id id) 354 { 355 unsigned int i; 356 struct graphics_object_id obj_id = {0}; 357 358 switch (id.type) { 359 case OBJECT_TYPE_ENCODER: 360 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 361 obj_id = object_id_from_bios_object_id( 362 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 363 if (id.type == obj_id.type && id.id == obj_id.id 364 && id.enum_id == obj_id.enum_id) 365 return &bp->object_info_tbl.v1_5->display_path[i]; 366 } 367 break; 368 369 case OBJECT_TYPE_CONNECTOR: 370 case OBJECT_TYPE_GENERIC: 371 /* Both Generic and Connector Object ID 372 * will be stored on display_objid 373 */ 374 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 375 obj_id = object_id_from_bios_object_id( 376 bp->object_info_tbl.v1_5->display_path[i].display_objid); 377 if (id.type == obj_id.type && id.id == obj_id.id 378 && id.enum_id == obj_id.enum_id) 379 return &bp->object_info_tbl.v1_5->display_path[i]; 380 } 381 break; 382 383 default: 384 return NULL; 385 } 386 387 return NULL; 388 } 389 390 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 391 struct graphics_object_id id, 392 struct graphics_object_i2c_info *info) 393 { 394 uint32_t offset; 395 struct atom_display_object_path_v2 *object; 396 397 struct atom_display_object_path_v3 *object_path_v3; 398 399 struct atom_common_record_header *header; 400 struct atom_i2c_record *record; 401 struct atom_i2c_record dummy_record = {0}; 402 struct bios_parser *bp = BP_FROM_DCB(dcb); 403 404 if (!info) 405 return BP_RESULT_BADINPUT; 406 407 if (id.type == OBJECT_TYPE_GENERIC) { 408 dummy_record.i2c_id = id.id; 409 410 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 411 return BP_RESULT_OK; 412 else 413 return BP_RESULT_NORECORD; 414 } 415 416 switch (bp->object_info_tbl.revision.minor) { 417 case 4: 418 default: 419 object = get_bios_object(bp, id); 420 421 if (!object) 422 return BP_RESULT_BADINPUT; 423 424 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 425 break; 426 case 5: 427 object_path_v3 = get_bios_object_from_path_v3(bp, id); 428 429 if (!object_path_v3) 430 return BP_RESULT_BADINPUT; 431 432 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 433 break; 434 } 435 436 for (;;) { 437 header = GET_IMAGE(struct atom_common_record_header, offset); 438 439 if (!header) 440 return BP_RESULT_BADBIOSTABLE; 441 442 if (header->record_type == LAST_RECORD_TYPE || 443 !header->record_size) 444 break; 445 446 if (header->record_type == ATOM_I2C_RECORD_TYPE 447 && sizeof(struct atom_i2c_record) <= 448 header->record_size) { 449 /* get the I2C info */ 450 record = (struct atom_i2c_record *) header; 451 452 if (get_gpio_i2c_info(bp, record, info) == 453 BP_RESULT_OK) 454 return BP_RESULT_OK; 455 } 456 457 offset += header->record_size; 458 } 459 460 return BP_RESULT_NORECORD; 461 } 462 463 static enum bp_result get_gpio_i2c_info( 464 struct bios_parser *bp, 465 struct atom_i2c_record *record, 466 struct graphics_object_i2c_info *info) 467 { 468 struct atom_gpio_pin_lut_v2_1 *header; 469 uint32_t count = 0; 470 unsigned int table_index = 0; 471 bool find_valid = false; 472 473 if (!info) 474 return BP_RESULT_BADINPUT; 475 476 /* get the GPIO_I2C info */ 477 if (!DATA_TABLES(gpio_pin_lut)) 478 return BP_RESULT_BADBIOSTABLE; 479 480 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 481 DATA_TABLES(gpio_pin_lut)); 482 if (!header) 483 return BP_RESULT_BADBIOSTABLE; 484 485 if (sizeof(struct atom_common_table_header) + 486 sizeof(struct atom_gpio_pin_assignment) > 487 le16_to_cpu(header->table_header.structuresize)) 488 return BP_RESULT_BADBIOSTABLE; 489 490 /* TODO: is version change? */ 491 if (header->table_header.content_revision != 1) 492 return BP_RESULT_UNSUPPORTED; 493 494 /* get data count */ 495 count = (le16_to_cpu(header->table_header.structuresize) 496 - sizeof(struct atom_common_table_header)) 497 / sizeof(struct atom_gpio_pin_assignment); 498 499 for (table_index = 0; table_index < count; table_index++) { 500 if (((record->i2c_id & I2C_HW_CAP) == ( 501 header->gpio_pin[table_index].gpio_id & 502 I2C_HW_CAP)) && 503 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 504 (header->gpio_pin[table_index].gpio_id & 505 I2C_HW_ENGINE_ID_MASK)) && 506 ((record->i2c_id & I2C_HW_LANE_MUX) == 507 (header->gpio_pin[table_index].gpio_id & 508 I2C_HW_LANE_MUX))) { 509 /* still valid */ 510 find_valid = true; 511 break; 512 } 513 } 514 515 /* If we don't find the entry that we are looking for then 516 * we will return BP_Result_BadBiosTable. 517 */ 518 if (find_valid == false) 519 return BP_RESULT_BADBIOSTABLE; 520 521 /* get the GPIO_I2C_INFO */ 522 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 523 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 524 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 525 info->i2c_slave_address = record->i2c_slave_addr; 526 527 /* TODO: check how to get register offset for en, Y, etc. */ 528 info->gpio_info.clk_a_register_index = 529 le16_to_cpu( 530 header->gpio_pin[table_index].data_a_reg_index); 531 info->gpio_info.clk_a_shift = 532 header->gpio_pin[table_index].gpio_bitshift; 533 534 return BP_RESULT_OK; 535 } 536 537 static struct atom_hpd_int_record *get_hpd_record_for_path_v3( 538 struct bios_parser *bp, 539 struct atom_display_object_path_v3 *object) 540 { 541 struct atom_common_record_header *header; 542 uint32_t offset; 543 544 if (!object) { 545 BREAK_TO_DEBUGGER(); /* Invalid object */ 546 return NULL; 547 } 548 549 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 550 551 for (;;) { 552 header = GET_IMAGE(struct atom_common_record_header, offset); 553 554 if (!header) 555 return NULL; 556 557 if (header->record_type == ATOM_RECORD_END_TYPE || 558 !header->record_size) 559 break; 560 561 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 562 && sizeof(struct atom_hpd_int_record) <= 563 header->record_size) 564 return (struct atom_hpd_int_record *) header; 565 566 offset += header->record_size; 567 } 568 569 return NULL; 570 } 571 572 static enum bp_result bios_parser_get_hpd_info( 573 struct dc_bios *dcb, 574 struct graphics_object_id id, 575 struct graphics_object_hpd_info *info) 576 { 577 struct bios_parser *bp = BP_FROM_DCB(dcb); 578 struct atom_display_object_path_v2 *object; 579 struct atom_display_object_path_v3 *object_path_v3; 580 struct atom_hpd_int_record *record = NULL; 581 582 if (!info) 583 return BP_RESULT_BADINPUT; 584 585 switch (bp->object_info_tbl.revision.minor) { 586 case 4: 587 default: 588 object = get_bios_object(bp, id); 589 590 if (!object) 591 return BP_RESULT_BADINPUT; 592 593 record = get_hpd_record(bp, object); 594 595 break; 596 case 5: 597 object_path_v3 = get_bios_object_from_path_v3(bp, id); 598 599 if (!object_path_v3) 600 return BP_RESULT_BADINPUT; 601 602 record = get_hpd_record_for_path_v3(bp, object_path_v3); 603 break; 604 } 605 606 if (record != NULL) { 607 info->hpd_int_gpio_uid = record->pin_id; 608 info->hpd_active = record->plugin_pin_state; 609 return BP_RESULT_OK; 610 } 611 612 return BP_RESULT_NORECORD; 613 } 614 615 static struct atom_hpd_int_record *get_hpd_record( 616 struct bios_parser *bp, 617 struct atom_display_object_path_v2 *object) 618 { 619 struct atom_common_record_header *header; 620 uint32_t offset; 621 622 if (!object) { 623 BREAK_TO_DEBUGGER(); /* Invalid object */ 624 return NULL; 625 } 626 627 offset = le16_to_cpu(object->disp_recordoffset) 628 + bp->object_info_tbl_offset; 629 630 for (;;) { 631 header = GET_IMAGE(struct atom_common_record_header, offset); 632 633 if (!header) 634 return NULL; 635 636 if (header->record_type == LAST_RECORD_TYPE || 637 !header->record_size) 638 break; 639 640 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 641 && sizeof(struct atom_hpd_int_record) <= 642 header->record_size) 643 return (struct atom_hpd_int_record *) header; 644 645 offset += header->record_size; 646 } 647 648 return NULL; 649 } 650 651 /** 652 * bios_parser_get_gpio_pin_info 653 * Get GpioPin information of input gpio id 654 * 655 * @dcb: pointer to the DC BIOS 656 * @gpio_id: GPIO ID 657 * @info: GpioPin information structure 658 * return: Bios parser result code 659 * note: 660 * to get the GPIO PIN INFO, we need: 661 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 662 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 663 * to get the registerA offset/mask 664 */ 665 static enum bp_result bios_parser_get_gpio_pin_info( 666 struct dc_bios *dcb, 667 uint32_t gpio_id, 668 struct gpio_pin_info *info) 669 { 670 struct bios_parser *bp = BP_FROM_DCB(dcb); 671 struct atom_gpio_pin_lut_v2_1 *header; 672 uint32_t count = 0; 673 uint32_t i = 0; 674 675 if (!DATA_TABLES(gpio_pin_lut)) 676 return BP_RESULT_BADBIOSTABLE; 677 678 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 679 DATA_TABLES(gpio_pin_lut)); 680 if (!header) 681 return BP_RESULT_BADBIOSTABLE; 682 683 if (sizeof(struct atom_common_table_header) + 684 sizeof(struct atom_gpio_pin_assignment) 685 > le16_to_cpu(header->table_header.structuresize)) 686 return BP_RESULT_BADBIOSTABLE; 687 688 if (header->table_header.content_revision != 1) 689 return BP_RESULT_UNSUPPORTED; 690 691 /* Temporary hard code gpio pin info */ 692 count = (le16_to_cpu(header->table_header.structuresize) 693 - sizeof(struct atom_common_table_header)) 694 / sizeof(struct atom_gpio_pin_assignment); 695 for (i = 0; i < count; ++i) { 696 if (header->gpio_pin[i].gpio_id != gpio_id) 697 continue; 698 699 info->offset = 700 (uint32_t) le16_to_cpu( 701 header->gpio_pin[i].data_a_reg_index); 702 info->offset_y = info->offset + 2; 703 info->offset_en = info->offset + 1; 704 info->offset_mask = info->offset - 1; 705 706 info->mask = (uint32_t) (1 << 707 header->gpio_pin[i].gpio_bitshift); 708 info->mask_y = info->mask + 2; 709 info->mask_en = info->mask + 1; 710 info->mask_mask = info->mask - 1; 711 712 return BP_RESULT_OK; 713 } 714 715 return BP_RESULT_NORECORD; 716 } 717 718 static struct device_id device_type_from_device_id(uint16_t device_id) 719 { 720 721 struct device_id result_device_id; 722 723 result_device_id.raw_device_tag = device_id; 724 725 switch (device_id) { 726 case ATOM_DISPLAY_LCD1_SUPPORT: 727 result_device_id.device_type = DEVICE_TYPE_LCD; 728 result_device_id.enum_id = 1; 729 break; 730 731 case ATOM_DISPLAY_LCD2_SUPPORT: 732 result_device_id.device_type = DEVICE_TYPE_LCD; 733 result_device_id.enum_id = 2; 734 break; 735 736 case ATOM_DISPLAY_DFP1_SUPPORT: 737 result_device_id.device_type = DEVICE_TYPE_DFP; 738 result_device_id.enum_id = 1; 739 break; 740 741 case ATOM_DISPLAY_DFP2_SUPPORT: 742 result_device_id.device_type = DEVICE_TYPE_DFP; 743 result_device_id.enum_id = 2; 744 break; 745 746 case ATOM_DISPLAY_DFP3_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_DFP; 748 result_device_id.enum_id = 3; 749 break; 750 751 case ATOM_DISPLAY_DFP4_SUPPORT: 752 result_device_id.device_type = DEVICE_TYPE_DFP; 753 result_device_id.enum_id = 4; 754 break; 755 756 case ATOM_DISPLAY_DFP5_SUPPORT: 757 result_device_id.device_type = DEVICE_TYPE_DFP; 758 result_device_id.enum_id = 5; 759 break; 760 761 case ATOM_DISPLAY_DFP6_SUPPORT: 762 result_device_id.device_type = DEVICE_TYPE_DFP; 763 result_device_id.enum_id = 6; 764 break; 765 766 default: 767 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 768 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 769 result_device_id.enum_id = 0; 770 } 771 return result_device_id; 772 } 773 774 static enum bp_result bios_parser_get_device_tag( 775 struct dc_bios *dcb, 776 struct graphics_object_id connector_object_id, 777 uint32_t device_tag_index, 778 struct connector_device_tag_info *info) 779 { 780 struct bios_parser *bp = BP_FROM_DCB(dcb); 781 struct atom_display_object_path_v2 *object; 782 783 struct atom_display_object_path_v3 *object_path_v3; 784 785 786 if (!info) 787 return BP_RESULT_BADINPUT; 788 789 switch (bp->object_info_tbl.revision.minor) { 790 case 4: 791 default: 792 /* getBiosObject will return MXM object */ 793 object = get_bios_object(bp, connector_object_id); 794 795 if (!object) { 796 BREAK_TO_DEBUGGER(); /* Invalid object id */ 797 return BP_RESULT_BADINPUT; 798 } 799 800 info->acpi_device = 0; /* BIOS no longer provides this */ 801 info->dev_id = device_type_from_device_id(object->device_tag); 802 break; 803 case 5: 804 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 805 806 if (!object_path_v3) { 807 BREAK_TO_DEBUGGER(); /* Invalid object id */ 808 return BP_RESULT_BADINPUT; 809 } 810 info->acpi_device = 0; /* BIOS no longer provides this */ 811 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 812 break; 813 } 814 815 return BP_RESULT_OK; 816 } 817 818 static enum bp_result get_ss_info_v4_1( 819 struct bios_parser *bp, 820 uint32_t id, 821 uint32_t index, 822 struct spread_spectrum_info *ss_info) 823 { 824 enum bp_result result = BP_RESULT_OK; 825 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 826 struct atom_smu_info_v3_3 *smu_info = NULL; 827 828 if (!ss_info) 829 return BP_RESULT_BADINPUT; 830 831 if (!DATA_TABLES(dce_info)) 832 return BP_RESULT_BADBIOSTABLE; 833 834 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 835 DATA_TABLES(dce_info)); 836 if (!disp_cntl_tbl) 837 return BP_RESULT_BADBIOSTABLE; 838 839 840 ss_info->type.STEP_AND_DELAY_INFO = false; 841 ss_info->spread_percentage_divider = 1000; 842 /* BIOS no longer uses target clock. Always enable for now */ 843 ss_info->target_clock_range = 0xffffffff; 844 845 switch (id) { 846 case AS_SIGNAL_TYPE_DVI: 847 ss_info->spread_spectrum_percentage = 848 disp_cntl_tbl->dvi_ss_percentage; 849 ss_info->spread_spectrum_range = 850 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 851 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 852 ss_info->type.CENTER_MODE = true; 853 854 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 855 break; 856 case AS_SIGNAL_TYPE_HDMI: 857 ss_info->spread_spectrum_percentage = 858 disp_cntl_tbl->hdmi_ss_percentage; 859 ss_info->spread_spectrum_range = 860 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 861 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 862 ss_info->type.CENTER_MODE = true; 863 864 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 865 break; 866 /* TODO LVDS not support anymore? */ 867 case AS_SIGNAL_TYPE_DISPLAY_PORT: 868 ss_info->spread_spectrum_percentage = 869 disp_cntl_tbl->dp_ss_percentage; 870 ss_info->spread_spectrum_range = 871 disp_cntl_tbl->dp_ss_rate_10hz * 10; 872 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 873 ss_info->type.CENTER_MODE = true; 874 875 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 876 break; 877 case AS_SIGNAL_TYPE_GPU_PLL: 878 /* atom_firmware: DAL only get data from dce_info table. 879 * if data within smu_info is needed for DAL, VBIOS should 880 * copy it into dce_info 881 */ 882 result = BP_RESULT_UNSUPPORTED; 883 break; 884 case AS_SIGNAL_TYPE_XGMI: 885 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 886 DATA_TABLES(smu_info)); 887 if (!smu_info) 888 return BP_RESULT_BADBIOSTABLE; 889 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 890 ss_info->spread_spectrum_percentage = 891 smu_info->waflclk_ss_percentage; 892 ss_info->spread_spectrum_range = 893 smu_info->gpuclk_ss_rate_10hz * 10; 894 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 895 ss_info->type.CENTER_MODE = true; 896 897 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 898 break; 899 default: 900 result = BP_RESULT_UNSUPPORTED; 901 } 902 903 return result; 904 } 905 906 static enum bp_result get_ss_info_v4_2( 907 struct bios_parser *bp, 908 uint32_t id, 909 uint32_t index, 910 struct spread_spectrum_info *ss_info) 911 { 912 enum bp_result result = BP_RESULT_OK; 913 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 914 struct atom_smu_info_v3_1 *smu_info = NULL; 915 916 if (!ss_info) 917 return BP_RESULT_BADINPUT; 918 919 if (!DATA_TABLES(dce_info)) 920 return BP_RESULT_BADBIOSTABLE; 921 922 if (!DATA_TABLES(smu_info)) 923 return BP_RESULT_BADBIOSTABLE; 924 925 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 926 DATA_TABLES(dce_info)); 927 if (!disp_cntl_tbl) 928 return BP_RESULT_BADBIOSTABLE; 929 930 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 931 if (!smu_info) 932 return BP_RESULT_BADBIOSTABLE; 933 934 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 935 ss_info->type.STEP_AND_DELAY_INFO = false; 936 ss_info->spread_percentage_divider = 1000; 937 /* BIOS no longer uses target clock. Always enable for now */ 938 ss_info->target_clock_range = 0xffffffff; 939 940 switch (id) { 941 case AS_SIGNAL_TYPE_DVI: 942 ss_info->spread_spectrum_percentage = 943 disp_cntl_tbl->dvi_ss_percentage; 944 ss_info->spread_spectrum_range = 945 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 946 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 947 ss_info->type.CENTER_MODE = true; 948 949 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 950 break; 951 case AS_SIGNAL_TYPE_HDMI: 952 ss_info->spread_spectrum_percentage = 953 disp_cntl_tbl->hdmi_ss_percentage; 954 ss_info->spread_spectrum_range = 955 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 956 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 957 ss_info->type.CENTER_MODE = true; 958 959 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 960 break; 961 /* TODO LVDS not support anymore? */ 962 case AS_SIGNAL_TYPE_DISPLAY_PORT: 963 ss_info->spread_spectrum_percentage = 964 smu_info->gpuclk_ss_percentage; 965 ss_info->spread_spectrum_range = 966 smu_info->gpuclk_ss_rate_10hz * 10; 967 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 968 ss_info->type.CENTER_MODE = true; 969 970 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 971 break; 972 case AS_SIGNAL_TYPE_GPU_PLL: 973 /* atom_firmware: DAL only get data from dce_info table. 974 * if data within smu_info is needed for DAL, VBIOS should 975 * copy it into dce_info 976 */ 977 result = BP_RESULT_UNSUPPORTED; 978 break; 979 default: 980 result = BP_RESULT_UNSUPPORTED; 981 } 982 983 return result; 984 } 985 986 static enum bp_result get_ss_info_v4_5( 987 struct bios_parser *bp, 988 uint32_t id, 989 uint32_t index, 990 struct spread_spectrum_info *ss_info) 991 { 992 enum bp_result result = BP_RESULT_OK; 993 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 994 995 if (!ss_info) 996 return BP_RESULT_BADINPUT; 997 998 if (!DATA_TABLES(dce_info)) 999 return BP_RESULT_BADBIOSTABLE; 1000 1001 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1002 DATA_TABLES(dce_info)); 1003 if (!disp_cntl_tbl) 1004 return BP_RESULT_BADBIOSTABLE; 1005 1006 ss_info->type.STEP_AND_DELAY_INFO = false; 1007 ss_info->spread_percentage_divider = 1000; 1008 /* BIOS no longer uses target clock. Always enable for now */ 1009 ss_info->target_clock_range = 0xffffffff; 1010 1011 switch (id) { 1012 case AS_SIGNAL_TYPE_DVI: 1013 ss_info->spread_spectrum_percentage = 1014 disp_cntl_tbl->dvi_ss_percentage; 1015 ss_info->spread_spectrum_range = 1016 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1017 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1018 ss_info->type.CENTER_MODE = true; 1019 1020 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1021 break; 1022 case AS_SIGNAL_TYPE_HDMI: 1023 ss_info->spread_spectrum_percentage = 1024 disp_cntl_tbl->hdmi_ss_percentage; 1025 ss_info->spread_spectrum_range = 1026 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1027 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1028 ss_info->type.CENTER_MODE = true; 1029 1030 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1031 break; 1032 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1033 ss_info->spread_spectrum_percentage = 1034 disp_cntl_tbl->dp_ss_percentage; 1035 ss_info->spread_spectrum_range = 1036 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1037 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1038 ss_info->type.CENTER_MODE = true; 1039 1040 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1041 break; 1042 case AS_SIGNAL_TYPE_GPU_PLL: 1043 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1044 * SMU Display PLL supposed to be without spread. 1045 * Better place for it would be in atom_display_controller_info_v4_5 table. 1046 */ 1047 result = BP_RESULT_UNSUPPORTED; 1048 break; 1049 default: 1050 result = BP_RESULT_UNSUPPORTED; 1051 break; 1052 } 1053 1054 return result; 1055 } 1056 1057 /** 1058 * bios_parser_get_spread_spectrum_info 1059 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1060 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1061 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1062 * ver 3.1, 1063 * there is only one entry for each signal /ss id. However, there is 1064 * no planning of supporting multiple spread Sprectum entry for EverGreen 1065 * @dcb: pointer to the DC BIOS 1066 * @signal: ASSignalType to be converted to info index 1067 * @index: number of entries that match the converted info index 1068 * @ss_info: sprectrum information structure, 1069 * return: Bios parser result code 1070 */ 1071 static enum bp_result bios_parser_get_spread_spectrum_info( 1072 struct dc_bios *dcb, 1073 enum as_signal_type signal, 1074 uint32_t index, 1075 struct spread_spectrum_info *ss_info) 1076 { 1077 struct bios_parser *bp = BP_FROM_DCB(dcb); 1078 enum bp_result result = BP_RESULT_UNSUPPORTED; 1079 struct atom_common_table_header *header; 1080 struct atom_data_revision tbl_revision; 1081 1082 if (!ss_info) /* check for bad input */ 1083 return BP_RESULT_BADINPUT; 1084 1085 if (!DATA_TABLES(dce_info)) 1086 return BP_RESULT_UNSUPPORTED; 1087 1088 header = GET_IMAGE(struct atom_common_table_header, 1089 DATA_TABLES(dce_info)); 1090 get_atom_data_table_revision(header, &tbl_revision); 1091 1092 switch (tbl_revision.major) { 1093 case 4: 1094 switch (tbl_revision.minor) { 1095 case 1: 1096 return get_ss_info_v4_1(bp, signal, index, ss_info); 1097 case 2: 1098 case 3: 1099 case 4: 1100 return get_ss_info_v4_2(bp, signal, index, ss_info); 1101 case 5: 1102 return get_ss_info_v4_5(bp, signal, index, ss_info); 1103 1104 default: 1105 ASSERT(0); 1106 break; 1107 } 1108 break; 1109 default: 1110 break; 1111 } 1112 /* there can not be more then one entry for SS Info table */ 1113 return result; 1114 } 1115 1116 static enum bp_result get_soc_bb_info_v4_4( 1117 struct bios_parser *bp, 1118 struct bp_soc_bb_info *soc_bb_info) 1119 { 1120 enum bp_result result = BP_RESULT_OK; 1121 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1122 1123 if (!soc_bb_info) 1124 return BP_RESULT_BADINPUT; 1125 1126 if (!DATA_TABLES(dce_info)) 1127 return BP_RESULT_BADBIOSTABLE; 1128 1129 if (!DATA_TABLES(smu_info)) 1130 return BP_RESULT_BADBIOSTABLE; 1131 1132 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1133 DATA_TABLES(dce_info)); 1134 if (!disp_cntl_tbl) 1135 return BP_RESULT_BADBIOSTABLE; 1136 1137 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1138 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1139 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1140 1141 return result; 1142 } 1143 1144 static enum bp_result get_soc_bb_info_v4_5( 1145 struct bios_parser *bp, 1146 struct bp_soc_bb_info *soc_bb_info) 1147 { 1148 enum bp_result result = BP_RESULT_OK; 1149 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1150 1151 if (!soc_bb_info) 1152 return BP_RESULT_BADINPUT; 1153 1154 if (!DATA_TABLES(dce_info)) 1155 return BP_RESULT_BADBIOSTABLE; 1156 1157 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1158 DATA_TABLES(dce_info)); 1159 if (!disp_cntl_tbl) 1160 return BP_RESULT_BADBIOSTABLE; 1161 1162 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1163 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1164 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1165 1166 return result; 1167 } 1168 1169 static enum bp_result bios_parser_get_soc_bb_info( 1170 struct dc_bios *dcb, 1171 struct bp_soc_bb_info *soc_bb_info) 1172 { 1173 struct bios_parser *bp = BP_FROM_DCB(dcb); 1174 enum bp_result result = BP_RESULT_UNSUPPORTED; 1175 struct atom_common_table_header *header; 1176 struct atom_data_revision tbl_revision; 1177 1178 if (!soc_bb_info) /* check for bad input */ 1179 return BP_RESULT_BADINPUT; 1180 1181 if (!DATA_TABLES(dce_info)) 1182 return BP_RESULT_UNSUPPORTED; 1183 1184 header = GET_IMAGE(struct atom_common_table_header, 1185 DATA_TABLES(dce_info)); 1186 get_atom_data_table_revision(header, &tbl_revision); 1187 1188 switch (tbl_revision.major) { 1189 case 4: 1190 switch (tbl_revision.minor) { 1191 case 1: 1192 case 2: 1193 case 3: 1194 break; 1195 case 4: 1196 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1197 break; 1198 case 5: 1199 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1200 break; 1201 default: 1202 break; 1203 } 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 return result; 1210 } 1211 1212 static enum bp_result get_disp_caps_v4_1( 1213 struct bios_parser *bp, 1214 uint8_t *dce_caps) 1215 { 1216 enum bp_result result = BP_RESULT_OK; 1217 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1218 1219 if (!dce_caps) 1220 return BP_RESULT_BADINPUT; 1221 1222 if (!DATA_TABLES(dce_info)) 1223 return BP_RESULT_BADBIOSTABLE; 1224 1225 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1226 DATA_TABLES(dce_info)); 1227 1228 if (!disp_cntl_tbl) 1229 return BP_RESULT_BADBIOSTABLE; 1230 1231 *dce_caps = disp_cntl_tbl->display_caps; 1232 1233 return result; 1234 } 1235 1236 static enum bp_result get_disp_caps_v4_2( 1237 struct bios_parser *bp, 1238 uint8_t *dce_caps) 1239 { 1240 enum bp_result result = BP_RESULT_OK; 1241 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1242 1243 if (!dce_caps) 1244 return BP_RESULT_BADINPUT; 1245 1246 if (!DATA_TABLES(dce_info)) 1247 return BP_RESULT_BADBIOSTABLE; 1248 1249 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1250 DATA_TABLES(dce_info)); 1251 1252 if (!disp_cntl_tbl) 1253 return BP_RESULT_BADBIOSTABLE; 1254 1255 *dce_caps = disp_cntl_tbl->display_caps; 1256 1257 return result; 1258 } 1259 1260 static enum bp_result get_disp_caps_v4_3( 1261 struct bios_parser *bp, 1262 uint8_t *dce_caps) 1263 { 1264 enum bp_result result = BP_RESULT_OK; 1265 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1266 1267 if (!dce_caps) 1268 return BP_RESULT_BADINPUT; 1269 1270 if (!DATA_TABLES(dce_info)) 1271 return BP_RESULT_BADBIOSTABLE; 1272 1273 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1274 DATA_TABLES(dce_info)); 1275 1276 if (!disp_cntl_tbl) 1277 return BP_RESULT_BADBIOSTABLE; 1278 1279 *dce_caps = disp_cntl_tbl->display_caps; 1280 1281 return result; 1282 } 1283 1284 static enum bp_result get_disp_caps_v4_4( 1285 struct bios_parser *bp, 1286 uint8_t *dce_caps) 1287 { 1288 enum bp_result result = BP_RESULT_OK; 1289 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1290 1291 if (!dce_caps) 1292 return BP_RESULT_BADINPUT; 1293 1294 if (!DATA_TABLES(dce_info)) 1295 return BP_RESULT_BADBIOSTABLE; 1296 1297 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1298 DATA_TABLES(dce_info)); 1299 1300 if (!disp_cntl_tbl) 1301 return BP_RESULT_BADBIOSTABLE; 1302 1303 *dce_caps = disp_cntl_tbl->display_caps; 1304 1305 return result; 1306 } 1307 1308 static enum bp_result get_disp_caps_v4_5( 1309 struct bios_parser *bp, 1310 uint8_t *dce_caps) 1311 { 1312 enum bp_result result = BP_RESULT_OK; 1313 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1314 1315 if (!dce_caps) 1316 return BP_RESULT_BADINPUT; 1317 1318 if (!DATA_TABLES(dce_info)) 1319 return BP_RESULT_BADBIOSTABLE; 1320 1321 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1322 DATA_TABLES(dce_info)); 1323 1324 if (!disp_cntl_tbl) 1325 return BP_RESULT_BADBIOSTABLE; 1326 1327 *dce_caps = disp_cntl_tbl->display_caps; 1328 1329 return result; 1330 } 1331 1332 static enum bp_result bios_parser_get_lttpr_interop( 1333 struct dc_bios *dcb, 1334 uint8_t *dce_caps) 1335 { 1336 struct bios_parser *bp = BP_FROM_DCB(dcb); 1337 enum bp_result result = BP_RESULT_UNSUPPORTED; 1338 struct atom_common_table_header *header; 1339 struct atom_data_revision tbl_revision; 1340 1341 if (!DATA_TABLES(dce_info)) 1342 return BP_RESULT_UNSUPPORTED; 1343 1344 header = GET_IMAGE(struct atom_common_table_header, 1345 DATA_TABLES(dce_info)); 1346 get_atom_data_table_revision(header, &tbl_revision); 1347 switch (tbl_revision.major) { 1348 case 4: 1349 switch (tbl_revision.minor) { 1350 case 1: 1351 result = get_disp_caps_v4_1(bp, dce_caps); 1352 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1353 break; 1354 case 2: 1355 result = get_disp_caps_v4_2(bp, dce_caps); 1356 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1357 break; 1358 case 3: 1359 result = get_disp_caps_v4_3(bp, dce_caps); 1360 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1361 break; 1362 case 4: 1363 result = get_disp_caps_v4_4(bp, dce_caps); 1364 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1365 break; 1366 case 5: 1367 result = get_disp_caps_v4_5(bp, dce_caps); 1368 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1369 break; 1370 1371 default: 1372 break; 1373 } 1374 break; 1375 default: 1376 break; 1377 } 1378 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1379 return result; 1380 } 1381 1382 static enum bp_result bios_parser_get_lttpr_caps( 1383 struct dc_bios *dcb, 1384 uint8_t *dce_caps) 1385 { 1386 struct bios_parser *bp = BP_FROM_DCB(dcb); 1387 enum bp_result result = BP_RESULT_UNSUPPORTED; 1388 struct atom_common_table_header *header; 1389 struct atom_data_revision tbl_revision; 1390 1391 if (!DATA_TABLES(dce_info)) 1392 return BP_RESULT_UNSUPPORTED; 1393 1394 *dce_caps = 0; 1395 header = GET_IMAGE(struct atom_common_table_header, 1396 DATA_TABLES(dce_info)); 1397 get_atom_data_table_revision(header, &tbl_revision); 1398 switch (tbl_revision.major) { 1399 case 4: 1400 switch (tbl_revision.minor) { 1401 case 1: 1402 result = get_disp_caps_v4_1(bp, dce_caps); 1403 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1404 break; 1405 case 2: 1406 result = get_disp_caps_v4_2(bp, dce_caps); 1407 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1408 break; 1409 case 3: 1410 result = get_disp_caps_v4_3(bp, dce_caps); 1411 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1412 break; 1413 case 4: 1414 result = get_disp_caps_v4_4(bp, dce_caps); 1415 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1416 break; 1417 case 5: 1418 result = get_disp_caps_v4_5(bp, dce_caps); 1419 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1420 break; 1421 default: 1422 break; 1423 } 1424 break; 1425 default: 1426 break; 1427 } 1428 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1429 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) { 1430 *dce_caps = 1; 1431 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled"); 1432 } 1433 return result; 1434 } 1435 1436 static enum bp_result get_embedded_panel_info_v2_1( 1437 struct bios_parser *bp, 1438 struct embedded_panel_info *info) 1439 { 1440 struct lcd_info_v2_1 *lvds; 1441 1442 if (!info) 1443 return BP_RESULT_BADINPUT; 1444 1445 if (!DATA_TABLES(lcd_info)) 1446 return BP_RESULT_UNSUPPORTED; 1447 1448 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1449 1450 if (!lvds) 1451 return BP_RESULT_BADBIOSTABLE; 1452 1453 /* TODO: previous vv1_3, should v2_1 */ 1454 if (!((lvds->table_header.format_revision == 2) 1455 && (lvds->table_header.content_revision >= 1))) 1456 return BP_RESULT_UNSUPPORTED; 1457 1458 memset(info, 0, sizeof(struct embedded_panel_info)); 1459 1460 /* We need to convert from 10KHz units into KHz units */ 1461 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1462 /* usHActive does not include borders, according to VBIOS team */ 1463 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1464 /* usHBlanking_Time includes borders, so we should really be 1465 * subtractingborders duing this translation, but LVDS generally 1466 * doesn't have borders, so we should be okay leaving this as is for 1467 * now. May need to revisit if we ever have LVDS with borders 1468 */ 1469 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1470 /* usVActive does not include borders, according to VBIOS team*/ 1471 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1472 /* usVBlanking_Time includes borders, so we should really be 1473 * subtracting borders duing this translation, but LVDS generally 1474 * doesn't have borders, so we should be okay leaving this as is for 1475 * now. May need to revisit if we ever have LVDS with borders 1476 */ 1477 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1478 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1479 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1480 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1481 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1482 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1483 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1484 1485 /* not provided by VBIOS */ 1486 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1487 1488 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1489 & ATOM_HSYNC_POLARITY); 1490 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1491 & ATOM_VSYNC_POLARITY); 1492 1493 /* not provided by VBIOS */ 1494 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1495 1496 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1497 & ATOM_H_REPLICATIONBY2); 1498 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1499 & ATOM_V_REPLICATIONBY2); 1500 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1501 & ATOM_COMPOSITESYNC); 1502 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1503 1504 /* not provided by VBIOS*/ 1505 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1506 /* not provided by VBIOS*/ 1507 info->ss_id = 0; 1508 1509 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1510 1511 return BP_RESULT_OK; 1512 } 1513 1514 static enum bp_result bios_parser_get_embedded_panel_info( 1515 struct dc_bios *dcb, 1516 struct embedded_panel_info *info) 1517 { 1518 struct bios_parser 1519 *bp = BP_FROM_DCB(dcb); 1520 struct atom_common_table_header *header; 1521 struct atom_data_revision tbl_revision; 1522 1523 if (!DATA_TABLES(lcd_info)) 1524 return BP_RESULT_FAILURE; 1525 1526 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1527 1528 if (!header) 1529 return BP_RESULT_BADBIOSTABLE; 1530 1531 get_atom_data_table_revision(header, &tbl_revision); 1532 1533 switch (tbl_revision.major) { 1534 case 2: 1535 switch (tbl_revision.minor) { 1536 case 1: 1537 return get_embedded_panel_info_v2_1(bp, info); 1538 default: 1539 break; 1540 } 1541 break; 1542 default: 1543 break; 1544 } 1545 1546 return BP_RESULT_FAILURE; 1547 } 1548 1549 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1550 { 1551 enum dal_device_type device_type = device_id.device_type; 1552 uint32_t enum_id = device_id.enum_id; 1553 1554 switch (device_type) { 1555 case DEVICE_TYPE_LCD: 1556 switch (enum_id) { 1557 case 1: 1558 return ATOM_DISPLAY_LCD1_SUPPORT; 1559 default: 1560 break; 1561 } 1562 break; 1563 case DEVICE_TYPE_DFP: 1564 switch (enum_id) { 1565 case 1: 1566 return ATOM_DISPLAY_DFP1_SUPPORT; 1567 case 2: 1568 return ATOM_DISPLAY_DFP2_SUPPORT; 1569 case 3: 1570 return ATOM_DISPLAY_DFP3_SUPPORT; 1571 case 4: 1572 return ATOM_DISPLAY_DFP4_SUPPORT; 1573 case 5: 1574 return ATOM_DISPLAY_DFP5_SUPPORT; 1575 case 6: 1576 return ATOM_DISPLAY_DFP6_SUPPORT; 1577 default: 1578 break; 1579 } 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 /* Unidentified device ID, return empty support mask. */ 1586 return 0; 1587 } 1588 1589 static bool bios_parser_is_device_id_supported( 1590 struct dc_bios *dcb, 1591 struct device_id id) 1592 { 1593 struct bios_parser *bp = BP_FROM_DCB(dcb); 1594 1595 uint32_t mask = get_support_mask_for_device_id(id); 1596 1597 switch (bp->object_info_tbl.revision.minor) { 1598 case 4: 1599 default: 1600 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1601 break; 1602 case 5: 1603 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1604 break; 1605 } 1606 1607 return false; 1608 } 1609 1610 static uint32_t bios_parser_get_ss_entry_number( 1611 struct dc_bios *dcb, 1612 enum as_signal_type signal) 1613 { 1614 /* TODO: DAL2 atomfirmware implementation does not need this. 1615 * why DAL3 need this? 1616 */ 1617 return 1; 1618 } 1619 1620 static enum bp_result bios_parser_transmitter_control( 1621 struct dc_bios *dcb, 1622 struct bp_transmitter_control *cntl) 1623 { 1624 struct bios_parser *bp = BP_FROM_DCB(dcb); 1625 1626 if (!bp->cmd_tbl.transmitter_control) 1627 return BP_RESULT_FAILURE; 1628 1629 return bp->cmd_tbl.transmitter_control(bp, cntl); 1630 } 1631 1632 static enum bp_result bios_parser_encoder_control( 1633 struct dc_bios *dcb, 1634 struct bp_encoder_control *cntl) 1635 { 1636 struct bios_parser *bp = BP_FROM_DCB(dcb); 1637 1638 if (!bp->cmd_tbl.dig_encoder_control) 1639 return BP_RESULT_FAILURE; 1640 1641 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1642 } 1643 1644 static enum bp_result bios_parser_set_pixel_clock( 1645 struct dc_bios *dcb, 1646 struct bp_pixel_clock_parameters *bp_params) 1647 { 1648 struct bios_parser *bp = BP_FROM_DCB(dcb); 1649 1650 if (!bp->cmd_tbl.set_pixel_clock) 1651 return BP_RESULT_FAILURE; 1652 1653 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1654 } 1655 1656 static enum bp_result bios_parser_set_dce_clock( 1657 struct dc_bios *dcb, 1658 struct bp_set_dce_clock_parameters *bp_params) 1659 { 1660 struct bios_parser *bp = BP_FROM_DCB(dcb); 1661 1662 if (!bp->cmd_tbl.set_dce_clock) 1663 return BP_RESULT_FAILURE; 1664 1665 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1666 } 1667 1668 static enum bp_result bios_parser_program_crtc_timing( 1669 struct dc_bios *dcb, 1670 struct bp_hw_crtc_timing_parameters *bp_params) 1671 { 1672 struct bios_parser *bp = BP_FROM_DCB(dcb); 1673 1674 if (!bp->cmd_tbl.set_crtc_timing) 1675 return BP_RESULT_FAILURE; 1676 1677 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1678 } 1679 1680 static enum bp_result bios_parser_enable_crtc( 1681 struct dc_bios *dcb, 1682 enum controller_id id, 1683 bool enable) 1684 { 1685 struct bios_parser *bp = BP_FROM_DCB(dcb); 1686 1687 if (!bp->cmd_tbl.enable_crtc) 1688 return BP_RESULT_FAILURE; 1689 1690 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1691 } 1692 1693 static enum bp_result bios_parser_enable_disp_power_gating( 1694 struct dc_bios *dcb, 1695 enum controller_id controller_id, 1696 enum bp_pipe_control_action action) 1697 { 1698 struct bios_parser *bp = BP_FROM_DCB(dcb); 1699 1700 if (!bp->cmd_tbl.enable_disp_power_gating) 1701 return BP_RESULT_FAILURE; 1702 1703 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1704 action); 1705 } 1706 1707 static enum bp_result bios_parser_enable_lvtma_control( 1708 struct dc_bios *dcb, 1709 uint8_t uc_pwr_on, 1710 uint8_t panel_instance) 1711 { 1712 struct bios_parser *bp = BP_FROM_DCB(dcb); 1713 1714 if (!bp->cmd_tbl.enable_lvtma_control) 1715 return BP_RESULT_FAILURE; 1716 1717 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1718 } 1719 1720 static bool bios_parser_is_accelerated_mode( 1721 struct dc_bios *dcb) 1722 { 1723 return bios_is_accelerated_mode(dcb); 1724 } 1725 1726 /** 1727 * bios_parser_set_scratch_critical_state - update critical state bit 1728 * in VBIOS scratch register 1729 * 1730 * @dcb: pointer to the DC BIO 1731 * @state: set or reset state 1732 */ 1733 static void bios_parser_set_scratch_critical_state( 1734 struct dc_bios *dcb, 1735 bool state) 1736 { 1737 bios_set_scratch_critical_state(dcb, state); 1738 } 1739 1740 struct atom_dig_transmitter_info_header_v5_3 { 1741 struct atom_common_table_header table_header; 1742 uint16_t dpphy_hdmi_settings_offset; 1743 uint16_t dpphy_dvi_settings_offset; 1744 uint16_t dpphy_dp_setting_table_offset; 1745 uint16_t uniphy_xbar_settings_v2_table_offset; 1746 uint16_t dpphy_internal_reg_overide_offset; 1747 }; 1748 1749 static enum bp_result bios_parser_get_firmware_info( 1750 struct dc_bios *dcb, 1751 struct dc_firmware_info *info) 1752 { 1753 struct bios_parser *bp = BP_FROM_DCB(dcb); 1754 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1755 struct atom_common_table_header *header; 1756 1757 struct atom_data_revision revision; 1758 1759 if (info && DATA_TABLES(firmwareinfo)) { 1760 header = GET_IMAGE(struct atom_common_table_header, 1761 DATA_TABLES(firmwareinfo)); 1762 get_atom_data_table_revision(header, &revision); 1763 switch (revision.major) { 1764 case 3: 1765 switch (revision.minor) { 1766 case 1: 1767 result = get_firmware_info_v3_1(bp, info); 1768 break; 1769 case 2: 1770 case 3: 1771 result = get_firmware_info_v3_2(bp, info); 1772 break; 1773 case 4: 1774 result = get_firmware_info_v3_4(bp, info); 1775 break; 1776 default: 1777 break; 1778 } 1779 break; 1780 default: 1781 break; 1782 } 1783 } 1784 1785 return result; 1786 } 1787 1788 static enum bp_result get_firmware_info_v3_1( 1789 struct bios_parser *bp, 1790 struct dc_firmware_info *info) 1791 { 1792 struct atom_firmware_info_v3_1 *firmware_info; 1793 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1794 1795 if (!info) 1796 return BP_RESULT_BADINPUT; 1797 1798 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1799 DATA_TABLES(firmwareinfo)); 1800 1801 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1802 DATA_TABLES(dce_info)); 1803 1804 if (!firmware_info || !dce_info) 1805 return BP_RESULT_BADBIOSTABLE; 1806 1807 memset(info, 0, sizeof(*info)); 1808 1809 /* Pixel clock pll information. */ 1810 /* We need to convert from 10KHz units into KHz units */ 1811 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1812 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1813 1814 /* 27MHz for Vega10: */ 1815 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1816 1817 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1818 if (info->pll_info.crystal_frequency == 0) 1819 info->pll_info.crystal_frequency = 27000; 1820 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1821 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1822 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1823 1824 /* Get GPU PLL VCO Clock */ 1825 1826 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1827 /* VBIOS gives in 10KHz */ 1828 info->smu_gpu_pll_output_freq = 1829 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1830 } 1831 1832 info->oem_i2c_present = false; 1833 1834 return BP_RESULT_OK; 1835 } 1836 1837 static enum bp_result get_firmware_info_v3_2( 1838 struct bios_parser *bp, 1839 struct dc_firmware_info *info) 1840 { 1841 struct atom_firmware_info_v3_2 *firmware_info; 1842 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1843 struct atom_common_table_header *header; 1844 struct atom_data_revision revision; 1845 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1846 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1847 1848 if (!info) 1849 return BP_RESULT_BADINPUT; 1850 1851 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1852 DATA_TABLES(firmwareinfo)); 1853 1854 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1855 DATA_TABLES(dce_info)); 1856 1857 if (!firmware_info || !dce_info) 1858 return BP_RESULT_BADBIOSTABLE; 1859 1860 memset(info, 0, sizeof(*info)); 1861 1862 header = GET_IMAGE(struct atom_common_table_header, 1863 DATA_TABLES(smu_info)); 1864 get_atom_data_table_revision(header, &revision); 1865 1866 if (revision.minor == 2) { 1867 /* Vega12 */ 1868 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1869 DATA_TABLES(smu_info)); 1870 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage); 1871 if (!smu_info_v3_2) 1872 return BP_RESULT_BADBIOSTABLE; 1873 1874 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1875 } else if (revision.minor == 3) { 1876 /* Vega20 */ 1877 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1878 DATA_TABLES(smu_info)); 1879 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage); 1880 if (!smu_info_v3_3) 1881 return BP_RESULT_BADBIOSTABLE; 1882 1883 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1884 } 1885 1886 // We need to convert from 10KHz units into KHz units. 1887 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1888 1889 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1890 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1891 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1892 if (info->pll_info.crystal_frequency == 0) { 1893 if (revision.minor == 2) 1894 info->pll_info.crystal_frequency = 27000; 1895 else if (revision.minor == 3) 1896 info->pll_info.crystal_frequency = 100000; 1897 } 1898 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1899 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1900 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1901 1902 /* Get GPU PLL VCO Clock */ 1903 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1904 if (revision.minor == 2) 1905 info->smu_gpu_pll_output_freq = 1906 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1907 else if (revision.minor == 3) 1908 info->smu_gpu_pll_output_freq = 1909 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1910 } 1911 1912 if (firmware_info->board_i2c_feature_id == 0x2) { 1913 info->oem_i2c_present = true; 1914 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1915 } else { 1916 info->oem_i2c_present = false; 1917 } 1918 1919 return BP_RESULT_OK; 1920 } 1921 1922 static enum bp_result get_firmware_info_v3_4( 1923 struct bios_parser *bp, 1924 struct dc_firmware_info *info) 1925 { 1926 struct atom_firmware_info_v3_4 *firmware_info; 1927 struct atom_common_table_header *header; 1928 struct atom_data_revision revision; 1929 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1930 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1931 1932 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1933 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1934 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1935 1936 if (!info) 1937 return BP_RESULT_BADINPUT; 1938 1939 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1940 DATA_TABLES(firmwareinfo)); 1941 1942 if (!firmware_info) 1943 return BP_RESULT_BADBIOSTABLE; 1944 1945 memset(info, 0, sizeof(*info)); 1946 1947 header = GET_IMAGE(struct atom_common_table_header, 1948 DATA_TABLES(dce_info)); 1949 1950 get_atom_data_table_revision(header, &revision); 1951 1952 switch (revision.major) { 1953 case 4: 1954 switch (revision.minor) { 1955 case 5: 1956 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1957 DATA_TABLES(dce_info)); 1958 1959 if (!dce_info_v4_5) 1960 return BP_RESULT_BADBIOSTABLE; 1961 1962 /* 100MHz expected */ 1963 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1964 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1965 /* 50MHz expected */ 1966 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1967 1968 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1969 break; 1970 1971 case 4: 1972 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1973 DATA_TABLES(dce_info)); 1974 1975 if (!dce_info_v4_4) 1976 return BP_RESULT_BADBIOSTABLE; 1977 1978 /* 100MHz expected */ 1979 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1980 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1981 /* 50MHz expected */ 1982 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1983 1984 /* Get SMU Display PLL VCO Frequency in KHz*/ 1985 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1986 break; 1987 1988 default: 1989 /* should not come here, keep as backup, as was before */ 1990 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1991 DATA_TABLES(dce_info)); 1992 1993 if (!dce_info_v4_1) 1994 return BP_RESULT_BADBIOSTABLE; 1995 1996 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 1997 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 1998 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 1999 break; 2000 } 2001 break; 2002 2003 default: 2004 ASSERT(0); 2005 break; 2006 } 2007 2008 header = GET_IMAGE(struct atom_common_table_header, 2009 DATA_TABLES(smu_info)); 2010 get_atom_data_table_revision(header, &revision); 2011 2012 switch (revision.major) { 2013 case 3: 2014 switch (revision.minor) { 2015 case 5: 2016 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2017 DATA_TABLES(smu_info)); 2018 2019 if (!smu_info_v3_5) 2020 return BP_RESULT_BADBIOSTABLE; 2021 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage); 2022 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2023 break; 2024 2025 default: 2026 break; 2027 } 2028 break; 2029 2030 case 4: 2031 switch (revision.minor) { 2032 case 0: 2033 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2034 DATA_TABLES(smu_info)); 2035 2036 if (!smu_info_v4_0) 2037 return BP_RESULT_BADBIOSTABLE; 2038 2039 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2040 break; 2041 2042 default: 2043 break; 2044 } 2045 break; 2046 2047 default: 2048 break; 2049 } 2050 2051 // We need to convert from 10KHz units into KHz units. 2052 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2053 2054 if (firmware_info->board_i2c_feature_id == 0x2) { 2055 info->oem_i2c_present = true; 2056 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2057 } else { 2058 info->oem_i2c_present = false; 2059 } 2060 2061 return BP_RESULT_OK; 2062 } 2063 2064 static enum bp_result bios_parser_get_encoder_cap_info( 2065 struct dc_bios *dcb, 2066 struct graphics_object_id object_id, 2067 struct bp_encoder_cap_info *info) 2068 { 2069 struct bios_parser *bp = BP_FROM_DCB(dcb); 2070 struct atom_display_object_path_v2 *object; 2071 struct atom_encoder_caps_record *record = NULL; 2072 2073 if (!info) 2074 return BP_RESULT_BADINPUT; 2075 2076 #if defined(CONFIG_DRM_AMD_DC_DCN) 2077 /* encoder cap record not available in v1_5 */ 2078 if (bp->object_info_tbl.revision.minor == 5) 2079 return BP_RESULT_NORECORD; 2080 #endif 2081 2082 object = get_bios_object(bp, object_id); 2083 2084 if (!object) 2085 return BP_RESULT_BADINPUT; 2086 2087 record = get_encoder_cap_record(bp, object); 2088 if (!record) 2089 return BP_RESULT_NORECORD; 2090 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id); 2091 2092 info->DP_HBR2_CAP = (record->encodercaps & 2093 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2094 info->DP_HBR2_EN = (record->encodercaps & 2095 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2096 info->DP_HBR3_EN = (record->encodercaps & 2097 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2098 info->HDMI_6GB_EN = (record->encodercaps & 2099 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2100 info->IS_DP2_CAPABLE = (record->encodercaps & 2101 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2102 info->DP_UHBR10_EN = (record->encodercaps & 2103 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2104 info->DP_UHBR13_5_EN = (record->encodercaps & 2105 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2106 info->DP_UHBR20_EN = (record->encodercaps & 2107 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2108 info->DP_IS_USB_C = (record->encodercaps & 2109 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2110 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C); 2111 2112 return BP_RESULT_OK; 2113 } 2114 2115 2116 static struct atom_encoder_caps_record *get_encoder_cap_record( 2117 struct bios_parser *bp, 2118 struct atom_display_object_path_v2 *object) 2119 { 2120 struct atom_common_record_header *header; 2121 uint32_t offset; 2122 2123 if (!object) { 2124 BREAK_TO_DEBUGGER(); /* Invalid object */ 2125 return NULL; 2126 } 2127 2128 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2129 2130 for (;;) { 2131 header = GET_IMAGE(struct atom_common_record_header, offset); 2132 2133 if (!header) 2134 return NULL; 2135 2136 offset += header->record_size; 2137 2138 if (header->record_type == LAST_RECORD_TYPE || 2139 !header->record_size) 2140 break; 2141 2142 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2143 continue; 2144 2145 if (sizeof(struct atom_encoder_caps_record) <= 2146 header->record_size) 2147 return (struct atom_encoder_caps_record *)header; 2148 } 2149 2150 return NULL; 2151 } 2152 2153 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2154 struct bios_parser *bp, 2155 struct atom_display_object_path_v2 *object) 2156 { 2157 struct atom_common_record_header *header; 2158 uint32_t offset; 2159 2160 if (!object) { 2161 BREAK_TO_DEBUGGER(); /* Invalid object */ 2162 return NULL; 2163 } 2164 2165 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2166 2167 for (;;) { 2168 header = GET_IMAGE(struct atom_common_record_header, offset); 2169 2170 if (!header) 2171 return NULL; 2172 2173 offset += header->record_size; 2174 2175 if (header->record_type == LAST_RECORD_TYPE || 2176 !header->record_size) 2177 break; 2178 2179 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2180 continue; 2181 2182 if (sizeof(struct atom_disp_connector_caps_record) <= 2183 header->record_size) 2184 return (struct atom_disp_connector_caps_record *)header; 2185 } 2186 2187 return NULL; 2188 } 2189 2190 static struct atom_connector_caps_record *get_connector_caps_record( 2191 struct bios_parser *bp, 2192 struct atom_display_object_path_v3 *object) 2193 { 2194 struct atom_common_record_header *header; 2195 uint32_t offset; 2196 2197 if (!object) { 2198 BREAK_TO_DEBUGGER(); /* Invalid object */ 2199 return NULL; 2200 } 2201 2202 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2203 2204 for (;;) { 2205 header = GET_IMAGE(struct atom_common_record_header, offset); 2206 2207 if (!header) 2208 return NULL; 2209 2210 offset += header->record_size; 2211 2212 if (header->record_type == ATOM_RECORD_END_TYPE || 2213 !header->record_size) 2214 break; 2215 2216 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2217 continue; 2218 2219 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2220 return (struct atom_connector_caps_record *)header; 2221 } 2222 2223 return NULL; 2224 } 2225 2226 static enum bp_result bios_parser_get_disp_connector_caps_info( 2227 struct dc_bios *dcb, 2228 struct graphics_object_id object_id, 2229 struct bp_disp_connector_caps_info *info) 2230 { 2231 struct bios_parser *bp = BP_FROM_DCB(dcb); 2232 struct atom_display_object_path_v2 *object; 2233 2234 struct atom_display_object_path_v3 *object_path_v3; 2235 struct atom_connector_caps_record *record_path_v3; 2236 2237 struct atom_disp_connector_caps_record *record = NULL; 2238 2239 if (!info) 2240 return BP_RESULT_BADINPUT; 2241 2242 switch (bp->object_info_tbl.revision.minor) { 2243 case 4: 2244 default: 2245 object = get_bios_object(bp, object_id); 2246 2247 if (!object) 2248 return BP_RESULT_BADINPUT; 2249 2250 record = get_disp_connector_caps_record(bp, object); 2251 if (!record) 2252 return BP_RESULT_NORECORD; 2253 2254 info->INTERNAL_DISPLAY = 2255 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2256 info->INTERNAL_DISPLAY_BL = 2257 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2258 break; 2259 case 5: 2260 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2261 2262 if (!object_path_v3) 2263 return BP_RESULT_BADINPUT; 2264 2265 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2266 if (!record_path_v3) 2267 return BP_RESULT_NORECORD; 2268 2269 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2270 ? 1 : 0; 2271 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2272 ? 1 : 0; 2273 break; 2274 } 2275 2276 return BP_RESULT_OK; 2277 } 2278 2279 static struct atom_connector_speed_record *get_connector_speed_cap_record( 2280 struct bios_parser *bp, 2281 struct atom_display_object_path_v3 *object) 2282 { 2283 struct atom_common_record_header *header; 2284 uint32_t offset; 2285 2286 if (!object) { 2287 BREAK_TO_DEBUGGER(); /* Invalid object */ 2288 return NULL; 2289 } 2290 2291 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2292 2293 for (;;) { 2294 header = GET_IMAGE(struct atom_common_record_header, offset); 2295 2296 if (!header) 2297 return NULL; 2298 2299 offset += header->record_size; 2300 2301 if (header->record_type == ATOM_RECORD_END_TYPE || 2302 !header->record_size) 2303 break; 2304 2305 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2306 continue; 2307 2308 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2309 return (struct atom_connector_speed_record *)header; 2310 } 2311 2312 return NULL; 2313 } 2314 2315 static enum bp_result bios_parser_get_connector_speed_cap_info( 2316 struct dc_bios *dcb, 2317 struct graphics_object_id object_id, 2318 struct bp_connector_speed_cap_info *info) 2319 { 2320 struct bios_parser *bp = BP_FROM_DCB(dcb); 2321 struct atom_display_object_path_v3 *object_path_v3; 2322 //struct atom_connector_speed_record *record = NULL; 2323 struct atom_connector_speed_record *record; 2324 2325 if (!info) 2326 return BP_RESULT_BADINPUT; 2327 2328 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2329 2330 if (!object_path_v3) 2331 return BP_RESULT_BADINPUT; 2332 2333 record = get_connector_speed_cap_record(bp, object_path_v3); 2334 if (!record) 2335 return BP_RESULT_NORECORD; 2336 2337 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2338 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2339 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2340 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2341 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2342 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2343 return BP_RESULT_OK; 2344 } 2345 2346 static enum bp_result get_vram_info_v23( 2347 struct bios_parser *bp, 2348 struct dc_vram_info *info) 2349 { 2350 struct atom_vram_info_header_v2_3 *info_v23; 2351 static enum bp_result result = BP_RESULT_OK; 2352 2353 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2354 DATA_TABLES(vram_info)); 2355 2356 if (info_v23 == NULL) 2357 return BP_RESULT_BADBIOSTABLE; 2358 2359 info->num_chans = info_v23->vram_module[0].channel_num; 2360 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2361 2362 return result; 2363 } 2364 2365 static enum bp_result get_vram_info_v24( 2366 struct bios_parser *bp, 2367 struct dc_vram_info *info) 2368 { 2369 struct atom_vram_info_header_v2_4 *info_v24; 2370 static enum bp_result result = BP_RESULT_OK; 2371 2372 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2373 DATA_TABLES(vram_info)); 2374 2375 if (info_v24 == NULL) 2376 return BP_RESULT_BADBIOSTABLE; 2377 2378 info->num_chans = info_v24->vram_module[0].channel_num; 2379 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2380 2381 return result; 2382 } 2383 2384 static enum bp_result get_vram_info_v25( 2385 struct bios_parser *bp, 2386 struct dc_vram_info *info) 2387 { 2388 struct atom_vram_info_header_v2_5 *info_v25; 2389 static enum bp_result result = BP_RESULT_OK; 2390 2391 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2392 DATA_TABLES(vram_info)); 2393 2394 if (info_v25 == NULL) 2395 return BP_RESULT_BADBIOSTABLE; 2396 2397 info->num_chans = info_v25->vram_module[0].channel_num; 2398 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2399 2400 return result; 2401 } 2402 2403 /* 2404 * get_integrated_info_v11 2405 * 2406 * @brief 2407 * Get V8 integrated BIOS information 2408 * 2409 * @param 2410 * bios_parser *bp - [in]BIOS parser handler to get master data table 2411 * integrated_info *info - [out] store and output integrated info 2412 * 2413 * @return 2414 * static enum bp_result - BP_RESULT_OK if information is available, 2415 * BP_RESULT_BADBIOSTABLE otherwise. 2416 */ 2417 static enum bp_result get_integrated_info_v11( 2418 struct bios_parser *bp, 2419 struct integrated_info *info) 2420 { 2421 struct atom_integrated_system_info_v1_11 *info_v11; 2422 uint32_t i; 2423 2424 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2425 DATA_TABLES(integratedsysteminfo)); 2426 2427 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage); 2428 if (info_v11 == NULL) 2429 return BP_RESULT_BADBIOSTABLE; 2430 2431 info->gpu_cap_info = 2432 le32_to_cpu(info_v11->gpucapinfo); 2433 /* 2434 * system_config: Bit[0] = 0 : PCIE power gating disabled 2435 * = 1 : PCIE power gating enabled 2436 * Bit[1] = 0 : DDR-PLL shut down disabled 2437 * = 1 : DDR-PLL shut down enabled 2438 * Bit[2] = 0 : DDR-PLL power down disabled 2439 * = 1 : DDR-PLL power down enabled 2440 */ 2441 info->system_config = le32_to_cpu(info_v11->system_config); 2442 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2443 info->memory_type = info_v11->memorytype; 2444 info->ma_channel_number = info_v11->umachannelnumber; 2445 info->lvds_ss_percentage = 2446 le16_to_cpu(info_v11->lvds_ss_percentage); 2447 info->dp_ss_control = 2448 le16_to_cpu(info_v11->reserved1); 2449 info->lvds_sspread_rate_in_10hz = 2450 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2451 info->hdmi_ss_percentage = 2452 le16_to_cpu(info_v11->hdmi_ss_percentage); 2453 info->hdmi_sspread_rate_in_10hz = 2454 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2455 info->dvi_ss_percentage = 2456 le16_to_cpu(info_v11->dvi_ss_percentage); 2457 info->dvi_sspread_rate_in_10_hz = 2458 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2459 info->lvds_misc = info_v11->lvds_misc; 2460 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2461 info->ext_disp_conn_info.gu_id[i] = 2462 info_v11->extdispconninfo.guid[i]; 2463 } 2464 2465 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2466 info->ext_disp_conn_info.path[i].device_connector_id = 2467 object_id_from_bios_object_id( 2468 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2469 2470 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2471 object_id_from_bios_object_id( 2472 le16_to_cpu( 2473 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2474 2475 info->ext_disp_conn_info.path[i].device_tag = 2476 le16_to_cpu( 2477 info_v11->extdispconninfo.path[i].device_tag); 2478 info->ext_disp_conn_info.path[i].device_acpi_enum = 2479 le16_to_cpu( 2480 info_v11->extdispconninfo.path[i].device_acpi_enum); 2481 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2482 info_v11->extdispconninfo.path[i].auxddclut_index; 2483 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2484 info_v11->extdispconninfo.path[i].hpdlut_index; 2485 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2486 info_v11->extdispconninfo.path[i].channelmapping; 2487 info->ext_disp_conn_info.path[i].caps = 2488 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2489 } 2490 info->ext_disp_conn_info.checksum = 2491 info_v11->extdispconninfo.checksum; 2492 2493 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2494 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2495 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2496 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2497 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2498 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2499 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2500 } 2501 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2502 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2503 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2504 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2505 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2506 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2507 } 2508 2509 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2510 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2511 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2512 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2513 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2514 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2515 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2516 } 2517 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2518 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2519 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2520 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2521 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2522 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2523 } 2524 2525 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2526 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2527 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2528 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2529 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2530 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2531 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2532 } 2533 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2534 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2535 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2536 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2537 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2538 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2539 } 2540 2541 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2542 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2543 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2544 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2545 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2546 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2547 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2548 } 2549 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2550 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2551 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2552 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2553 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2554 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2555 } 2556 2557 2558 /** TODO - review **/ 2559 #if 0 2560 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2561 * 10; 2562 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2563 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2564 2565 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2566 /* Convert [10KHz] into [KHz] */ 2567 info->disp_clk_voltage[i].max_supported_clk = 2568 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2569 ulMaximumSupportedCLK) * 10; 2570 info->disp_clk_voltage[i].voltage_index = 2571 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2572 } 2573 2574 info->boot_up_req_display_vector = 2575 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2576 info->boot_up_nb_voltage = 2577 le16_to_cpu(info_v11->usBootUpNBVoltage); 2578 info->ext_disp_conn_info_offset = 2579 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2580 info->gmc_restore_reset_time = 2581 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2582 info->minimum_n_clk = 2583 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2584 for (i = 1; i < 4; ++i) 2585 info->minimum_n_clk = 2586 info->minimum_n_clk < 2587 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2588 info->minimum_n_clk : le32_to_cpu( 2589 info_v11->ulNbpStateNClkFreq[i]); 2590 2591 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2592 info->ddr_dll_power_up_time = 2593 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2594 info->ddr_pll_power_up_time = 2595 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2596 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2597 info->max_lvds_pclk_freq_in_single_link = 2598 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2599 info->max_lvds_pclk_freq_in_single_link = 2600 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2601 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2602 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2603 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2604 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2605 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2606 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2607 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2608 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2609 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2610 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2611 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2612 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2613 info->lvds_off_to_on_delay_in_4ms = 2614 info_v11->ucLVDSOffToOnDelay_in4Ms; 2615 info->lvds_bit_depth_control_val = 2616 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2617 2618 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2619 /* Convert [10KHz] into [KHz] */ 2620 info->avail_s_clk[i].supported_s_clk = 2621 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2622 * 10; 2623 info->avail_s_clk[i].voltage_index = 2624 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2625 info->avail_s_clk[i].voltage_id = 2626 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2627 } 2628 #endif /* TODO*/ 2629 2630 return BP_RESULT_OK; 2631 } 2632 2633 static enum bp_result get_integrated_info_v2_1( 2634 struct bios_parser *bp, 2635 struct integrated_info *info) 2636 { 2637 struct atom_integrated_system_info_v2_1 *info_v2_1; 2638 uint32_t i; 2639 2640 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2641 DATA_TABLES(integratedsysteminfo)); 2642 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage); 2643 2644 if (info_v2_1 == NULL) 2645 return BP_RESULT_BADBIOSTABLE; 2646 2647 info->gpu_cap_info = 2648 le32_to_cpu(info_v2_1->gpucapinfo); 2649 /* 2650 * system_config: Bit[0] = 0 : PCIE power gating disabled 2651 * = 1 : PCIE power gating enabled 2652 * Bit[1] = 0 : DDR-PLL shut down disabled 2653 * = 1 : DDR-PLL shut down enabled 2654 * Bit[2] = 0 : DDR-PLL power down disabled 2655 * = 1 : DDR-PLL power down enabled 2656 */ 2657 info->system_config = le32_to_cpu(info_v2_1->system_config); 2658 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2659 info->memory_type = info_v2_1->memorytype; 2660 info->ma_channel_number = info_v2_1->umachannelnumber; 2661 info->dp_ss_control = 2662 le16_to_cpu(info_v2_1->reserved1); 2663 2664 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2665 info->ext_disp_conn_info.gu_id[i] = 2666 info_v2_1->extdispconninfo.guid[i]; 2667 } 2668 2669 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2670 info->ext_disp_conn_info.path[i].device_connector_id = 2671 object_id_from_bios_object_id( 2672 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2673 2674 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2675 object_id_from_bios_object_id( 2676 le16_to_cpu( 2677 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2678 2679 info->ext_disp_conn_info.path[i].device_tag = 2680 le16_to_cpu( 2681 info_v2_1->extdispconninfo.path[i].device_tag); 2682 info->ext_disp_conn_info.path[i].device_acpi_enum = 2683 le16_to_cpu( 2684 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2685 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2686 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2687 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2688 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2689 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2690 info_v2_1->extdispconninfo.path[i].channelmapping; 2691 info->ext_disp_conn_info.path[i].caps = 2692 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2693 } 2694 2695 info->ext_disp_conn_info.checksum = 2696 info_v2_1->extdispconninfo.checksum; 2697 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2698 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2699 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2700 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2701 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2702 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2703 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2704 } 2705 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2706 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2707 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2708 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2709 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2710 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2711 } 2712 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2713 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2714 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2715 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2716 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2717 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2718 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2719 } 2720 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2721 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2722 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2723 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2724 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2725 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2726 } 2727 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2728 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2729 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2730 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2731 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2732 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2733 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2734 } 2735 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2736 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2737 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2738 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2739 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2740 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2741 } 2742 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2743 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2744 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2745 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2746 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2747 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2748 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2749 } 2750 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2751 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2752 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2753 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2754 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2755 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2756 } 2757 2758 info->edp1_info.edp_backlight_pwm_hz = 2759 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2760 info->edp1_info.edp_ss_percentage = 2761 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2762 info->edp1_info.edp_ss_rate_10hz = 2763 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2764 info->edp1_info.edp_pwr_on_off_delay = 2765 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2766 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2767 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2768 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2769 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2770 info->edp1_info.edp_panel_bpc = 2771 info_v2_1->edp1_info.edp_panel_bpc; 2772 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2773 2774 info->edp2_info.edp_backlight_pwm_hz = 2775 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2776 info->edp2_info.edp_ss_percentage = 2777 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2778 info->edp2_info.edp_ss_rate_10hz = 2779 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2780 info->edp2_info.edp_pwr_on_off_delay = 2781 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2782 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2783 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2784 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2785 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2786 info->edp2_info.edp_panel_bpc = 2787 info_v2_1->edp2_info.edp_panel_bpc; 2788 info->edp2_info.edp_bootup_bl_level = 2789 info_v2_1->edp2_info.edp_bootup_bl_level; 2790 2791 return BP_RESULT_OK; 2792 } 2793 2794 static enum bp_result get_integrated_info_v2_2( 2795 struct bios_parser *bp, 2796 struct integrated_info *info) 2797 { 2798 struct atom_integrated_system_info_v2_2 *info_v2_2; 2799 uint32_t i; 2800 2801 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2802 DATA_TABLES(integratedsysteminfo)); 2803 2804 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage); 2805 2806 if (info_v2_2 == NULL) 2807 return BP_RESULT_BADBIOSTABLE; 2808 2809 info->gpu_cap_info = 2810 le32_to_cpu(info_v2_2->gpucapinfo); 2811 /* 2812 * system_config: Bit[0] = 0 : PCIE power gating disabled 2813 * = 1 : PCIE power gating enabled 2814 * Bit[1] = 0 : DDR-PLL shut down disabled 2815 * = 1 : DDR-PLL shut down enabled 2816 * Bit[2] = 0 : DDR-PLL power down disabled 2817 * = 1 : DDR-PLL power down enabled 2818 */ 2819 info->system_config = le32_to_cpu(info_v2_2->system_config); 2820 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2821 info->memory_type = info_v2_2->memorytype; 2822 info->ma_channel_number = info_v2_2->umachannelnumber; 2823 info->dp_ss_control = 2824 le16_to_cpu(info_v2_2->reserved1); 2825 2826 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2827 info->ext_disp_conn_info.gu_id[i] = 2828 info_v2_2->extdispconninfo.guid[i]; 2829 } 2830 2831 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2832 info->ext_disp_conn_info.path[i].device_connector_id = 2833 object_id_from_bios_object_id( 2834 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2835 2836 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2837 object_id_from_bios_object_id( 2838 le16_to_cpu( 2839 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2840 2841 info->ext_disp_conn_info.path[i].device_tag = 2842 le16_to_cpu( 2843 info_v2_2->extdispconninfo.path[i].device_tag); 2844 info->ext_disp_conn_info.path[i].device_acpi_enum = 2845 le16_to_cpu( 2846 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2847 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2848 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2849 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2850 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2851 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2852 info_v2_2->extdispconninfo.path[i].channelmapping; 2853 info->ext_disp_conn_info.path[i].caps = 2854 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2855 } 2856 2857 info->ext_disp_conn_info.checksum = 2858 info_v2_2->extdispconninfo.checksum; 2859 info->ext_disp_conn_info.fixdpvoltageswing = 2860 info_v2_2->extdispconninfo.fixdpvoltageswing; 2861 2862 info->edp1_info.edp_backlight_pwm_hz = 2863 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2864 info->edp1_info.edp_ss_percentage = 2865 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2866 info->edp1_info.edp_ss_rate_10hz = 2867 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2868 info->edp1_info.edp_pwr_on_off_delay = 2869 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2870 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2871 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2872 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2873 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2874 info->edp1_info.edp_panel_bpc = 2875 info_v2_2->edp1_info.edp_panel_bpc; 2876 info->edp1_info.edp_bootup_bl_level = 2877 2878 info->edp2_info.edp_backlight_pwm_hz = 2879 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2880 info->edp2_info.edp_ss_percentage = 2881 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2882 info->edp2_info.edp_ss_rate_10hz = 2883 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2884 info->edp2_info.edp_pwr_on_off_delay = 2885 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2886 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2887 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2888 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2889 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2890 info->edp2_info.edp_panel_bpc = 2891 info_v2_2->edp2_info.edp_panel_bpc; 2892 info->edp2_info.edp_bootup_bl_level = 2893 info_v2_2->edp2_info.edp_bootup_bl_level; 2894 2895 return BP_RESULT_OK; 2896 } 2897 2898 /* 2899 * construct_integrated_info 2900 * 2901 * @brief 2902 * Get integrated BIOS information based on table revision 2903 * 2904 * @param 2905 * bios_parser *bp - [in]BIOS parser handler to get master data table 2906 * integrated_info *info - [out] store and output integrated info 2907 * 2908 * @return 2909 * static enum bp_result - BP_RESULT_OK if information is available, 2910 * BP_RESULT_BADBIOSTABLE otherwise. 2911 */ 2912 static enum bp_result construct_integrated_info( 2913 struct bios_parser *bp, 2914 struct integrated_info *info) 2915 { 2916 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2917 2918 struct atom_common_table_header *header; 2919 struct atom_data_revision revision; 2920 2921 struct clock_voltage_caps temp = {0, 0}; 2922 uint32_t i; 2923 uint32_t j; 2924 2925 if (info && DATA_TABLES(integratedsysteminfo)) { 2926 header = GET_IMAGE(struct atom_common_table_header, 2927 DATA_TABLES(integratedsysteminfo)); 2928 2929 get_atom_data_table_revision(header, &revision); 2930 2931 switch (revision.major) { 2932 case 1: 2933 switch (revision.minor) { 2934 case 11: 2935 case 12: 2936 result = get_integrated_info_v11(bp, info); 2937 break; 2938 default: 2939 return result; 2940 } 2941 break; 2942 case 2: 2943 switch (revision.minor) { 2944 case 1: 2945 result = get_integrated_info_v2_1(bp, info); 2946 break; 2947 case 2: 2948 result = get_integrated_info_v2_2(bp, info); 2949 break; 2950 default: 2951 return result; 2952 } 2953 break; 2954 default: 2955 return result; 2956 } 2957 if (result == BP_RESULT_OK) { 2958 2959 DC_LOG_BIOS("edp1:\n" 2960 "\tedp_pwr_on_off_delay = %d\n" 2961 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2962 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2963 "\tedp_bootup_bl_level = %d\n", 2964 info->edp1_info.edp_pwr_on_off_delay, 2965 info->edp1_info.edp_pwr_on_vary_bl_to_blon, 2966 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff, 2967 info->edp1_info.edp_bootup_bl_level); 2968 DC_LOG_BIOS("edp2:\n" 2969 "\tedp_pwr_on_off_delayv = %d\n" 2970 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2971 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2972 "\tedp_bootup_bl_level = %d\n", 2973 info->edp2_info.edp_pwr_on_off_delay, 2974 info->edp2_info.edp_pwr_on_vary_bl_to_blon, 2975 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff, 2976 info->edp2_info.edp_bootup_bl_level); 2977 } 2978 } 2979 2980 if (result != BP_RESULT_OK) 2981 return result; 2982 else { 2983 // Log each external path 2984 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 2985 if (info->ext_disp_conn_info.path[i].device_tag != 0) 2986 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n" 2987 "DEVICE_TAG: 0x%x\n" 2988 "DEVICE_ACPI_ENUM: 0x%x\n" 2989 "DEVICE_CONNECTOR_ID: 0x%x\n" 2990 "EXT_AUX_DDC_LUT_INDEX: %d\n" 2991 "EXT_HPD_PIN_LUT_INDEX: %d\n" 2992 "EXT_ENCODER_OBJ_ID: 0x%x\n" 2993 "Encoder CAPS: 0x%x\n", 2994 i, 2995 info->ext_disp_conn_info.path[i].device_tag, 2996 info->ext_disp_conn_info.path[i].device_acpi_enum, 2997 info->ext_disp_conn_info.path[i].device_connector_id.id, 2998 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index, 2999 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index, 3000 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id, 3001 info->ext_disp_conn_info.path[i].caps 3002 ); 3003 if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) 3004 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3005 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) { 3006 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN; 3007 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3008 } 3009 } 3010 // Log the Checksum and Voltage Swing 3011 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n" 3012 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n", 3013 info->ext_disp_conn_info.checksum, 3014 info->ext_disp_conn_info.fixdpvoltageswing); 3015 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) { 3016 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF; 3017 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing); 3018 } 3019 } 3020 /* Sort voltage table from low to high*/ 3021 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 3022 for (j = i; j > 0; --j) { 3023 if (info->disp_clk_voltage[j].max_supported_clk < 3024 info->disp_clk_voltage[j-1].max_supported_clk 3025 ) { 3026 /* swap j and j - 1*/ 3027 temp = info->disp_clk_voltage[j-1]; 3028 info->disp_clk_voltage[j-1] = 3029 info->disp_clk_voltage[j]; 3030 info->disp_clk_voltage[j] = temp; 3031 } 3032 } 3033 } 3034 3035 return result; 3036 } 3037 3038 static enum bp_result bios_parser_get_vram_info( 3039 struct dc_bios *dcb, 3040 struct dc_vram_info *info) 3041 { 3042 struct bios_parser *bp = BP_FROM_DCB(dcb); 3043 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 3044 struct atom_common_table_header *header; 3045 struct atom_data_revision revision; 3046 3047 if (info && DATA_TABLES(vram_info)) { 3048 header = GET_IMAGE(struct atom_common_table_header, 3049 DATA_TABLES(vram_info)); 3050 3051 get_atom_data_table_revision(header, &revision); 3052 3053 switch (revision.major) { 3054 case 2: 3055 switch (revision.minor) { 3056 case 3: 3057 result = get_vram_info_v23(bp, info); 3058 break; 3059 case 4: 3060 result = get_vram_info_v24(bp, info); 3061 break; 3062 case 5: 3063 result = get_vram_info_v25(bp, info); 3064 break; 3065 default: 3066 break; 3067 } 3068 break; 3069 3070 default: 3071 return result; 3072 } 3073 3074 } 3075 return result; 3076 } 3077 3078 static struct integrated_info *bios_parser_create_integrated_info( 3079 struct dc_bios *dcb) 3080 { 3081 struct bios_parser *bp = BP_FROM_DCB(dcb); 3082 struct integrated_info *info = NULL; 3083 3084 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 3085 3086 if (info == NULL) { 3087 ASSERT_CRITICAL(0); 3088 return NULL; 3089 } 3090 3091 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3092 return info; 3093 3094 kfree(info); 3095 3096 return NULL; 3097 } 3098 3099 static enum bp_result update_slot_layout_info( 3100 struct dc_bios *dcb, 3101 unsigned int i, 3102 struct slot_layout_info *slot_layout_info) 3103 { 3104 unsigned int record_offset; 3105 unsigned int j; 3106 struct atom_display_object_path_v2 *object; 3107 struct atom_bracket_layout_record *record; 3108 struct atom_common_record_header *record_header; 3109 static enum bp_result result; 3110 struct bios_parser *bp; 3111 struct object_info_table *tbl; 3112 struct display_object_info_table_v1_4 *v1_4; 3113 3114 record = NULL; 3115 record_header = NULL; 3116 result = BP_RESULT_NORECORD; 3117 3118 bp = BP_FROM_DCB(dcb); 3119 tbl = &bp->object_info_tbl; 3120 v1_4 = tbl->v1_4; 3121 3122 object = &v1_4->display_path[i]; 3123 record_offset = (unsigned int) 3124 (object->disp_recordoffset) + 3125 (unsigned int)(bp->object_info_tbl_offset); 3126 3127 for (;;) { 3128 3129 record_header = (struct atom_common_record_header *) 3130 GET_IMAGE(struct atom_common_record_header, 3131 record_offset); 3132 if (record_header == NULL) { 3133 result = BP_RESULT_BADBIOSTABLE; 3134 break; 3135 } 3136 3137 /* the end of the list */ 3138 if (record_header->record_type == 0xff || 3139 record_header->record_size == 0) { 3140 break; 3141 } 3142 3143 if (record_header->record_type == 3144 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3145 sizeof(struct atom_bracket_layout_record) 3146 <= record_header->record_size) { 3147 record = (struct atom_bracket_layout_record *) 3148 (record_header); 3149 result = BP_RESULT_OK; 3150 break; 3151 } 3152 3153 record_offset += record_header->record_size; 3154 } 3155 3156 /* return if the record not found */ 3157 if (result != BP_RESULT_OK) 3158 return result; 3159 3160 /* get slot sizes */ 3161 slot_layout_info->length = record->bracketlen; 3162 slot_layout_info->width = record->bracketwidth; 3163 3164 /* get info for each connector in the slot */ 3165 slot_layout_info->num_of_connectors = record->conn_num; 3166 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3167 slot_layout_info->connectors[j].connector_type = 3168 (enum connector_layout_type) 3169 (record->conn_info[j].connector_type); 3170 switch (record->conn_info[j].connector_type) { 3171 case CONNECTOR_TYPE_DVI_D: 3172 slot_layout_info->connectors[j].connector_type = 3173 CONNECTOR_LAYOUT_TYPE_DVI_D; 3174 slot_layout_info->connectors[j].length = 3175 CONNECTOR_SIZE_DVI; 3176 break; 3177 3178 case CONNECTOR_TYPE_HDMI: 3179 slot_layout_info->connectors[j].connector_type = 3180 CONNECTOR_LAYOUT_TYPE_HDMI; 3181 slot_layout_info->connectors[j].length = 3182 CONNECTOR_SIZE_HDMI; 3183 break; 3184 3185 case CONNECTOR_TYPE_DISPLAY_PORT: 3186 slot_layout_info->connectors[j].connector_type = 3187 CONNECTOR_LAYOUT_TYPE_DP; 3188 slot_layout_info->connectors[j].length = 3189 CONNECTOR_SIZE_DP; 3190 break; 3191 3192 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3193 slot_layout_info->connectors[j].connector_type = 3194 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3195 slot_layout_info->connectors[j].length = 3196 CONNECTOR_SIZE_MINI_DP; 3197 break; 3198 3199 default: 3200 slot_layout_info->connectors[j].connector_type = 3201 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3202 slot_layout_info->connectors[j].length = 3203 CONNECTOR_SIZE_UNKNOWN; 3204 } 3205 3206 slot_layout_info->connectors[j].position = 3207 record->conn_info[j].position; 3208 slot_layout_info->connectors[j].connector_id = 3209 object_id_from_bios_object_id( 3210 record->conn_info[j].connectorobjid); 3211 } 3212 return result; 3213 } 3214 3215 static enum bp_result update_slot_layout_info_v2( 3216 struct dc_bios *dcb, 3217 unsigned int i, 3218 struct slot_layout_info *slot_layout_info) 3219 { 3220 unsigned int record_offset; 3221 struct atom_display_object_path_v3 *object; 3222 struct atom_bracket_layout_record_v2 *record; 3223 struct atom_common_record_header *record_header; 3224 static enum bp_result result; 3225 struct bios_parser *bp; 3226 struct object_info_table *tbl; 3227 struct display_object_info_table_v1_5 *v1_5; 3228 struct graphics_object_id connector_id; 3229 3230 record = NULL; 3231 record_header = NULL; 3232 result = BP_RESULT_NORECORD; 3233 3234 bp = BP_FROM_DCB(dcb); 3235 tbl = &bp->object_info_tbl; 3236 v1_5 = tbl->v1_5; 3237 3238 object = &v1_5->display_path[i]; 3239 record_offset = (unsigned int) 3240 (object->disp_recordoffset) + 3241 (unsigned int)(bp->object_info_tbl_offset); 3242 3243 for (;;) { 3244 3245 record_header = (struct atom_common_record_header *) 3246 GET_IMAGE(struct atom_common_record_header, 3247 record_offset); 3248 if (record_header == NULL) { 3249 result = BP_RESULT_BADBIOSTABLE; 3250 break; 3251 } 3252 3253 /* the end of the list */ 3254 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3255 record_header->record_size == 0) { 3256 break; 3257 } 3258 3259 if (record_header->record_type == 3260 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3261 sizeof(struct atom_bracket_layout_record_v2) 3262 <= record_header->record_size) { 3263 record = (struct atom_bracket_layout_record_v2 *) 3264 (record_header); 3265 result = BP_RESULT_OK; 3266 break; 3267 } 3268 3269 record_offset += record_header->record_size; 3270 } 3271 3272 /* return if the record not found */ 3273 if (result != BP_RESULT_OK) 3274 return result; 3275 3276 /* get slot sizes */ 3277 connector_id = object_id_from_bios_object_id(object->display_objid); 3278 3279 slot_layout_info->length = record->bracketlen; 3280 slot_layout_info->width = record->bracketwidth; 3281 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3282 slot_layout_info->connectors[i].position = record->conn_num; 3283 slot_layout_info->connectors[i].connector_id = connector_id; 3284 3285 switch (connector_id.id) { 3286 case CONNECTOR_ID_SINGLE_LINK_DVID: 3287 case CONNECTOR_ID_DUAL_LINK_DVID: 3288 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3289 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3290 break; 3291 3292 case CONNECTOR_ID_HDMI_TYPE_A: 3293 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3294 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3295 break; 3296 3297 case CONNECTOR_ID_DISPLAY_PORT: 3298 case CONNECTOR_ID_USBC: 3299 if (record->mini_type == MINI_TYPE_NORMAL) { 3300 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3301 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3302 } else { 3303 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3304 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3305 } 3306 break; 3307 3308 default: 3309 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3310 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3311 } 3312 return result; 3313 } 3314 3315 static enum bp_result get_bracket_layout_record( 3316 struct dc_bios *dcb, 3317 unsigned int bracket_layout_id, 3318 struct slot_layout_info *slot_layout_info) 3319 { 3320 unsigned int i; 3321 struct bios_parser *bp = BP_FROM_DCB(dcb); 3322 static enum bp_result result; 3323 struct object_info_table *tbl; 3324 struct display_object_info_table_v1_4 *v1_4; 3325 struct display_object_info_table_v1_5 *v1_5; 3326 3327 if (slot_layout_info == NULL) { 3328 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3329 return BP_RESULT_BADINPUT; 3330 } 3331 tbl = &bp->object_info_tbl; 3332 v1_4 = tbl->v1_4; 3333 v1_5 = tbl->v1_5; 3334 3335 result = BP_RESULT_NORECORD; 3336 switch (bp->object_info_tbl.revision.minor) { 3337 case 4: 3338 default: 3339 for (i = 0; i < v1_4->number_of_path; ++i) { 3340 if (bracket_layout_id == 3341 v1_4->display_path[i].display_objid) { 3342 result = update_slot_layout_info(dcb, i, slot_layout_info); 3343 break; 3344 } 3345 } 3346 break; 3347 case 5: 3348 for (i = 0; i < v1_5->number_of_path; ++i) 3349 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3350 break; 3351 } 3352 return result; 3353 } 3354 3355 static enum bp_result bios_get_board_layout_info( 3356 struct dc_bios *dcb, 3357 struct board_layout_info *board_layout_info) 3358 { 3359 unsigned int i; 3360 3361 struct bios_parser *bp; 3362 3363 static enum bp_result record_result; 3364 unsigned int max_slots; 3365 3366 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3367 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3368 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3369 0, 0 3370 }; 3371 3372 3373 bp = BP_FROM_DCB(dcb); 3374 3375 if (board_layout_info == NULL) { 3376 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3377 return BP_RESULT_BADINPUT; 3378 } 3379 3380 board_layout_info->num_of_slots = 0; 3381 max_slots = MAX_BOARD_SLOTS; 3382 3383 // Assume single slot on v1_5 3384 if (bp->object_info_tbl.revision.minor == 5) { 3385 max_slots = 1; 3386 } 3387 3388 for (i = 0; i < max_slots; ++i) { 3389 record_result = get_bracket_layout_record(dcb, 3390 slot_index_to_vbios_id[i], 3391 &board_layout_info->slots[i]); 3392 3393 if (record_result == BP_RESULT_NORECORD && i > 0) 3394 break; /* no more slots present in bios */ 3395 else if (record_result != BP_RESULT_OK) 3396 return record_result; /* fail */ 3397 3398 ++board_layout_info->num_of_slots; 3399 } 3400 3401 /* all data is valid */ 3402 board_layout_info->is_number_of_slots_valid = 1; 3403 board_layout_info->is_slots_size_valid = 1; 3404 board_layout_info->is_connector_offsets_valid = 1; 3405 board_layout_info->is_connector_lengths_valid = 1; 3406 3407 return BP_RESULT_OK; 3408 } 3409 3410 3411 static uint16_t bios_parser_pack_data_tables( 3412 struct dc_bios *dcb, 3413 void *dst) 3414 { 3415 // TODO: There is data bytes alignment issue, disable it for now. 3416 return 0; 3417 } 3418 3419 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3420 struct bios_parser *bp, 3421 uint32_t rev_major, 3422 uint32_t rev_minor, 3423 uint16_t *dc_golden_table_ver) 3424 { 3425 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3426 uint32_t dc_golden_offset = 0; 3427 *dc_golden_table_ver = 0; 3428 3429 if (!DATA_TABLES(dce_info)) 3430 return NULL; 3431 3432 /* ver.4.4 or higher */ 3433 switch (rev_major) { 3434 case 4: 3435 switch (rev_minor) { 3436 case 4: 3437 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3438 DATA_TABLES(dce_info)); 3439 if (!disp_cntl_tbl_4_4) 3440 return NULL; 3441 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3442 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3443 break; 3444 case 5: 3445 default: 3446 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3447 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3448 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3449 */ 3450 break; 3451 } 3452 break; 3453 } 3454 3455 if (!dc_golden_offset) 3456 return NULL; 3457 3458 if (*dc_golden_table_ver != 1) 3459 return NULL; 3460 3461 return GET_IMAGE(struct atom_dc_golden_table_v1, 3462 dc_golden_offset); 3463 } 3464 3465 static enum bp_result bios_get_atom_dc_golden_table( 3466 struct dc_bios *dcb) 3467 { 3468 struct bios_parser *bp = BP_FROM_DCB(dcb); 3469 enum bp_result result = BP_RESULT_OK; 3470 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3471 struct atom_common_table_header *header; 3472 struct atom_data_revision tbl_revision; 3473 uint16_t dc_golden_table_ver = 0; 3474 3475 header = GET_IMAGE(struct atom_common_table_header, 3476 DATA_TABLES(dce_info)); 3477 if (!header) 3478 return BP_RESULT_UNSUPPORTED; 3479 3480 get_atom_data_table_revision(header, &tbl_revision); 3481 3482 atom_dc_golden_table = bios_get_golden_table(bp, 3483 tbl_revision.major, 3484 tbl_revision.minor, 3485 &dc_golden_table_ver); 3486 3487 if (!atom_dc_golden_table) 3488 return BP_RESULT_UNSUPPORTED; 3489 3490 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3491 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3492 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3493 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3494 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3495 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3496 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3497 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3498 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3499 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3500 3501 return result; 3502 } 3503 3504 3505 static const struct dc_vbios_funcs vbios_funcs = { 3506 .get_connectors_number = bios_parser_get_connectors_number, 3507 3508 .get_connector_id = bios_parser_get_connector_id, 3509 3510 .get_src_obj = bios_parser_get_src_obj, 3511 3512 .get_i2c_info = bios_parser_get_i2c_info, 3513 3514 .get_hpd_info = bios_parser_get_hpd_info, 3515 3516 .get_device_tag = bios_parser_get_device_tag, 3517 3518 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3519 3520 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3521 3522 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3523 3524 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3525 3526 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3527 3528 .is_device_id_supported = bios_parser_is_device_id_supported, 3529 3530 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3531 3532 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3533 3534 3535 /* COMMANDS */ 3536 .encoder_control = bios_parser_encoder_control, 3537 3538 .transmitter_control = bios_parser_transmitter_control, 3539 3540 .enable_crtc = bios_parser_enable_crtc, 3541 3542 .set_pixel_clock = bios_parser_set_pixel_clock, 3543 3544 .set_dce_clock = bios_parser_set_dce_clock, 3545 3546 .program_crtc_timing = bios_parser_program_crtc_timing, 3547 3548 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3549 3550 .bios_parser_destroy = firmware_parser_destroy, 3551 3552 .get_board_layout_info = bios_get_board_layout_info, 3553 /* TODO: use this fn in hw init?*/ 3554 .pack_data_tables = bios_parser_pack_data_tables, 3555 3556 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3557 3558 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3559 3560 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3561 3562 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3563 3564 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3565 3566 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3567 3568 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3569 }; 3570 3571 static bool bios_parser2_construct( 3572 struct bios_parser *bp, 3573 struct bp_init_data *init, 3574 enum dce_version dce_version) 3575 { 3576 uint16_t *rom_header_offset = NULL; 3577 struct atom_rom_header_v2_2 *rom_header = NULL; 3578 struct display_object_info_table_v1_4 *object_info_tbl; 3579 struct atom_data_revision tbl_rev = {0}; 3580 3581 if (!init) 3582 return false; 3583 3584 if (!init->bios) 3585 return false; 3586 3587 bp->base.funcs = &vbios_funcs; 3588 bp->base.bios = init->bios; 3589 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3590 3591 bp->base.ctx = init->ctx; 3592 3593 bp->base.bios_local_image = NULL; 3594 3595 rom_header_offset = 3596 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3597 3598 if (!rom_header_offset) 3599 return false; 3600 3601 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3602 3603 if (!rom_header) 3604 return false; 3605 3606 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3607 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3608 return false; 3609 3610 bp->master_data_tbl = 3611 GET_IMAGE(struct atom_master_data_table_v2_1, 3612 rom_header->masterdatatable_offset); 3613 3614 if (!bp->master_data_tbl) 3615 return false; 3616 3617 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3618 3619 if (!bp->object_info_tbl_offset) 3620 return false; 3621 3622 object_info_tbl = 3623 GET_IMAGE(struct display_object_info_table_v1_4, 3624 bp->object_info_tbl_offset); 3625 3626 if (!object_info_tbl) 3627 return false; 3628 3629 get_atom_data_table_revision(&object_info_tbl->table_header, 3630 &bp->object_info_tbl.revision); 3631 3632 if (bp->object_info_tbl.revision.major == 1 3633 && bp->object_info_tbl.revision.minor == 4) { 3634 struct display_object_info_table_v1_4 *tbl_v1_4; 3635 3636 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3637 bp->object_info_tbl_offset); 3638 if (!tbl_v1_4) 3639 return false; 3640 3641 bp->object_info_tbl.v1_4 = tbl_v1_4; 3642 } else if (bp->object_info_tbl.revision.major == 1 3643 && bp->object_info_tbl.revision.minor == 5) { 3644 struct display_object_info_table_v1_5 *tbl_v1_5; 3645 3646 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3647 bp->object_info_tbl_offset); 3648 if (!tbl_v1_5) 3649 return false; 3650 3651 bp->object_info_tbl.v1_5 = tbl_v1_5; 3652 } else { 3653 ASSERT(0); 3654 return false; 3655 } 3656 3657 dal_firmware_parser_init_cmd_tbl(bp); 3658 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3659 3660 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3661 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3662 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3663 3664 return true; 3665 } 3666 3667 struct dc_bios *firmware_parser_create( 3668 struct bp_init_data *init, 3669 enum dce_version dce_version) 3670 { 3671 struct bios_parser *bp = NULL; 3672 3673 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 3674 if (!bp) 3675 return NULL; 3676 3677 if (bios_parser2_construct(bp, init, dce_version)) 3678 return &bp->base; 3679 3680 kfree(bp); 3681 return NULL; 3682 } 3683 3684 3685