1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @dcb: pointer to the DC BIOS 489 * @gpio_id: GPIO ID 490 * @info: GpioPin information structure 491 * return: Bios parser result code 492 * note: 493 * to get the GPIO PIN INFO, we need: 494 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 495 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 496 * to get the registerA offset/mask 497 */ 498 static enum bp_result bios_parser_get_gpio_pin_info( 499 struct dc_bios *dcb, 500 uint32_t gpio_id, 501 struct gpio_pin_info *info) 502 { 503 struct bios_parser *bp = BP_FROM_DCB(dcb); 504 struct atom_gpio_pin_lut_v2_1 *header; 505 uint32_t count = 0; 506 uint32_t i = 0; 507 508 if (!DATA_TABLES(gpio_pin_lut)) 509 return BP_RESULT_BADBIOSTABLE; 510 511 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 512 DATA_TABLES(gpio_pin_lut)); 513 if (!header) 514 return BP_RESULT_BADBIOSTABLE; 515 516 if (sizeof(struct atom_common_table_header) + 517 sizeof(struct atom_gpio_pin_assignment) 518 > le16_to_cpu(header->table_header.structuresize)) 519 return BP_RESULT_BADBIOSTABLE; 520 521 if (header->table_header.content_revision != 1) 522 return BP_RESULT_UNSUPPORTED; 523 524 /* Temporary hard code gpio pin info */ 525 #if defined(FOR_SIMNOW_BOOT) 526 { 527 struct atom_gpio_pin_assignment gpio_pin[8] = { 528 {0x5db5, 0, 0, 1, 0}, 529 {0x5db5, 8, 8, 2, 0}, 530 {0x5db5, 0x10, 0x10, 3, 0}, 531 {0x5db5, 0x18, 0x14, 4, 0}, 532 {0x5db5, 0x1A, 0x18, 5, 0}, 533 {0x5db5, 0x1C, 0x1C, 6, 0}, 534 }; 535 536 count = 6; 537 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 538 } 539 #else 540 count = (le16_to_cpu(header->table_header.structuresize) 541 - sizeof(struct atom_common_table_header)) 542 / sizeof(struct atom_gpio_pin_assignment); 543 #endif 544 for (i = 0; i < count; ++i) { 545 if (header->gpio_pin[i].gpio_id != gpio_id) 546 continue; 547 548 info->offset = 549 (uint32_t) le16_to_cpu( 550 header->gpio_pin[i].data_a_reg_index); 551 info->offset_y = info->offset + 2; 552 info->offset_en = info->offset + 1; 553 info->offset_mask = info->offset - 1; 554 555 info->mask = (uint32_t) (1 << 556 header->gpio_pin[i].gpio_bitshift); 557 info->mask_y = info->mask + 2; 558 info->mask_en = info->mask + 1; 559 info->mask_mask = info->mask - 1; 560 561 return BP_RESULT_OK; 562 } 563 564 return BP_RESULT_NORECORD; 565 } 566 567 static struct device_id device_type_from_device_id(uint16_t device_id) 568 { 569 570 struct device_id result_device_id; 571 572 result_device_id.raw_device_tag = device_id; 573 574 switch (device_id) { 575 case ATOM_DISPLAY_LCD1_SUPPORT: 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 result_device_id.enum_id = 1; 578 break; 579 580 case ATOM_DISPLAY_DFP1_SUPPORT: 581 result_device_id.device_type = DEVICE_TYPE_DFP; 582 result_device_id.enum_id = 1; 583 break; 584 585 case ATOM_DISPLAY_DFP2_SUPPORT: 586 result_device_id.device_type = DEVICE_TYPE_DFP; 587 result_device_id.enum_id = 2; 588 break; 589 590 case ATOM_DISPLAY_DFP3_SUPPORT: 591 result_device_id.device_type = DEVICE_TYPE_DFP; 592 result_device_id.enum_id = 3; 593 break; 594 595 case ATOM_DISPLAY_DFP4_SUPPORT: 596 result_device_id.device_type = DEVICE_TYPE_DFP; 597 result_device_id.enum_id = 4; 598 break; 599 600 case ATOM_DISPLAY_DFP5_SUPPORT: 601 result_device_id.device_type = DEVICE_TYPE_DFP; 602 result_device_id.enum_id = 5; 603 break; 604 605 case ATOM_DISPLAY_DFP6_SUPPORT: 606 result_device_id.device_type = DEVICE_TYPE_DFP; 607 result_device_id.enum_id = 6; 608 break; 609 610 default: 611 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 612 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 613 result_device_id.enum_id = 0; 614 } 615 return result_device_id; 616 } 617 618 static enum bp_result bios_parser_get_device_tag( 619 struct dc_bios *dcb, 620 struct graphics_object_id connector_object_id, 621 uint32_t device_tag_index, 622 struct connector_device_tag_info *info) 623 { 624 struct bios_parser *bp = BP_FROM_DCB(dcb); 625 struct atom_display_object_path_v2 *object; 626 627 if (!info) 628 return BP_RESULT_BADINPUT; 629 630 /* getBiosObject will return MXM object */ 631 object = get_bios_object(bp, connector_object_id); 632 633 if (!object) { 634 BREAK_TO_DEBUGGER(); /* Invalid object id */ 635 return BP_RESULT_BADINPUT; 636 } 637 638 info->acpi_device = 0; /* BIOS no longer provides this */ 639 info->dev_id = device_type_from_device_id(object->device_tag); 640 641 return BP_RESULT_OK; 642 } 643 644 static enum bp_result get_ss_info_v4_1( 645 struct bios_parser *bp, 646 uint32_t id, 647 uint32_t index, 648 struct spread_spectrum_info *ss_info) 649 { 650 enum bp_result result = BP_RESULT_OK; 651 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 652 struct atom_smu_info_v3_3 *smu_info = NULL; 653 654 if (!ss_info) 655 return BP_RESULT_BADINPUT; 656 657 if (!DATA_TABLES(dce_info)) 658 return BP_RESULT_BADBIOSTABLE; 659 660 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 661 DATA_TABLES(dce_info)); 662 if (!disp_cntl_tbl) 663 return BP_RESULT_BADBIOSTABLE; 664 665 666 ss_info->type.STEP_AND_DELAY_INFO = false; 667 ss_info->spread_percentage_divider = 1000; 668 /* BIOS no longer uses target clock. Always enable for now */ 669 ss_info->target_clock_range = 0xffffffff; 670 671 switch (id) { 672 case AS_SIGNAL_TYPE_DVI: 673 ss_info->spread_spectrum_percentage = 674 disp_cntl_tbl->dvi_ss_percentage; 675 ss_info->spread_spectrum_range = 676 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 677 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 678 ss_info->type.CENTER_MODE = true; 679 break; 680 case AS_SIGNAL_TYPE_HDMI: 681 ss_info->spread_spectrum_percentage = 682 disp_cntl_tbl->hdmi_ss_percentage; 683 ss_info->spread_spectrum_range = 684 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 685 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 686 ss_info->type.CENTER_MODE = true; 687 break; 688 /* TODO LVDS not support anymore? */ 689 case AS_SIGNAL_TYPE_DISPLAY_PORT: 690 ss_info->spread_spectrum_percentage = 691 disp_cntl_tbl->dp_ss_percentage; 692 ss_info->spread_spectrum_range = 693 disp_cntl_tbl->dp_ss_rate_10hz * 10; 694 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 695 ss_info->type.CENTER_MODE = true; 696 break; 697 case AS_SIGNAL_TYPE_GPU_PLL: 698 /* atom_firmware: DAL only get data from dce_info table. 699 * if data within smu_info is needed for DAL, VBIOS should 700 * copy it into dce_info 701 */ 702 result = BP_RESULT_UNSUPPORTED; 703 break; 704 case AS_SIGNAL_TYPE_XGMI: 705 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 706 DATA_TABLES(smu_info)); 707 if (!smu_info) 708 return BP_RESULT_BADBIOSTABLE; 709 710 ss_info->spread_spectrum_percentage = 711 smu_info->waflclk_ss_percentage; 712 ss_info->spread_spectrum_range = 713 smu_info->gpuclk_ss_rate_10hz * 10; 714 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 715 ss_info->type.CENTER_MODE = true; 716 break; 717 default: 718 result = BP_RESULT_UNSUPPORTED; 719 } 720 721 return result; 722 } 723 724 static enum bp_result get_ss_info_v4_2( 725 struct bios_parser *bp, 726 uint32_t id, 727 uint32_t index, 728 struct spread_spectrum_info *ss_info) 729 { 730 enum bp_result result = BP_RESULT_OK; 731 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 732 struct atom_smu_info_v3_1 *smu_info = NULL; 733 734 if (!ss_info) 735 return BP_RESULT_BADINPUT; 736 737 if (!DATA_TABLES(dce_info)) 738 return BP_RESULT_BADBIOSTABLE; 739 740 if (!DATA_TABLES(smu_info)) 741 return BP_RESULT_BADBIOSTABLE; 742 743 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 744 DATA_TABLES(dce_info)); 745 if (!disp_cntl_tbl) 746 return BP_RESULT_BADBIOSTABLE; 747 748 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 749 if (!smu_info) 750 return BP_RESULT_BADBIOSTABLE; 751 752 ss_info->type.STEP_AND_DELAY_INFO = false; 753 ss_info->spread_percentage_divider = 1000; 754 /* BIOS no longer uses target clock. Always enable for now */ 755 ss_info->target_clock_range = 0xffffffff; 756 757 switch (id) { 758 case AS_SIGNAL_TYPE_DVI: 759 ss_info->spread_spectrum_percentage = 760 disp_cntl_tbl->dvi_ss_percentage; 761 ss_info->spread_spectrum_range = 762 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 763 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 764 ss_info->type.CENTER_MODE = true; 765 break; 766 case AS_SIGNAL_TYPE_HDMI: 767 ss_info->spread_spectrum_percentage = 768 disp_cntl_tbl->hdmi_ss_percentage; 769 ss_info->spread_spectrum_range = 770 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 771 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 772 ss_info->type.CENTER_MODE = true; 773 break; 774 /* TODO LVDS not support anymore? */ 775 case AS_SIGNAL_TYPE_DISPLAY_PORT: 776 ss_info->spread_spectrum_percentage = 777 smu_info->gpuclk_ss_percentage; 778 ss_info->spread_spectrum_range = 779 smu_info->gpuclk_ss_rate_10hz * 10; 780 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 781 ss_info->type.CENTER_MODE = true; 782 break; 783 case AS_SIGNAL_TYPE_GPU_PLL: 784 /* atom_firmware: DAL only get data from dce_info table. 785 * if data within smu_info is needed for DAL, VBIOS should 786 * copy it into dce_info 787 */ 788 result = BP_RESULT_UNSUPPORTED; 789 break; 790 default: 791 result = BP_RESULT_UNSUPPORTED; 792 } 793 794 return result; 795 } 796 797 /** 798 * bios_parser_get_spread_spectrum_info 799 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 800 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 801 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 802 * ver 3.1, 803 * there is only one entry for each signal /ss id. However, there is 804 * no planning of supporting multiple spread Sprectum entry for EverGreen 805 * @dcb: pointer to the DC BIOS 806 * @signal: ASSignalType to be converted to info index 807 * @index: number of entries that match the converted info index 808 * @ss_info: sprectrum information structure, 809 * return: Bios parser result code 810 */ 811 static enum bp_result bios_parser_get_spread_spectrum_info( 812 struct dc_bios *dcb, 813 enum as_signal_type signal, 814 uint32_t index, 815 struct spread_spectrum_info *ss_info) 816 { 817 struct bios_parser *bp = BP_FROM_DCB(dcb); 818 enum bp_result result = BP_RESULT_UNSUPPORTED; 819 struct atom_common_table_header *header; 820 struct atom_data_revision tbl_revision; 821 822 if (!ss_info) /* check for bad input */ 823 return BP_RESULT_BADINPUT; 824 825 if (!DATA_TABLES(dce_info)) 826 return BP_RESULT_UNSUPPORTED; 827 828 header = GET_IMAGE(struct atom_common_table_header, 829 DATA_TABLES(dce_info)); 830 get_atom_data_table_revision(header, &tbl_revision); 831 832 switch (tbl_revision.major) { 833 case 4: 834 switch (tbl_revision.minor) { 835 case 1: 836 return get_ss_info_v4_1(bp, signal, index, ss_info); 837 case 2: 838 case 3: 839 return get_ss_info_v4_2(bp, signal, index, ss_info); 840 default: 841 break; 842 } 843 break; 844 default: 845 break; 846 } 847 /* there can not be more then one entry for SS Info table */ 848 return result; 849 } 850 851 static enum bp_result get_soc_bb_info_v4_4( 852 struct bios_parser *bp, 853 struct bp_soc_bb_info *soc_bb_info) 854 { 855 enum bp_result result = BP_RESULT_OK; 856 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 857 858 if (!soc_bb_info) 859 return BP_RESULT_BADINPUT; 860 861 if (!DATA_TABLES(dce_info)) 862 return BP_RESULT_BADBIOSTABLE; 863 864 if (!DATA_TABLES(smu_info)) 865 return BP_RESULT_BADBIOSTABLE; 866 867 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 868 DATA_TABLES(dce_info)); 869 if (!disp_cntl_tbl) 870 return BP_RESULT_BADBIOSTABLE; 871 872 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 873 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 874 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 875 876 return result; 877 } 878 879 static enum bp_result bios_parser_get_soc_bb_info( 880 struct dc_bios *dcb, 881 struct bp_soc_bb_info *soc_bb_info) 882 { 883 struct bios_parser *bp = BP_FROM_DCB(dcb); 884 enum bp_result result = BP_RESULT_UNSUPPORTED; 885 struct atom_common_table_header *header; 886 struct atom_data_revision tbl_revision; 887 888 if (!soc_bb_info) /* check for bad input */ 889 return BP_RESULT_BADINPUT; 890 891 if (!DATA_TABLES(dce_info)) 892 return BP_RESULT_UNSUPPORTED; 893 894 header = GET_IMAGE(struct atom_common_table_header, 895 DATA_TABLES(dce_info)); 896 get_atom_data_table_revision(header, &tbl_revision); 897 898 switch (tbl_revision.major) { 899 case 4: 900 switch (tbl_revision.minor) { 901 case 1: 902 case 2: 903 case 3: 904 break; 905 case 4: 906 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 907 break; 908 default: 909 break; 910 } 911 break; 912 default: 913 break; 914 } 915 916 return result; 917 } 918 919 static enum bp_result get_lttpr_caps_v4_1( 920 struct bios_parser *bp, 921 uint8_t *dce_caps) 922 { 923 enum bp_result result = BP_RESULT_OK; 924 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 925 926 if (!dce_caps) 927 return BP_RESULT_BADINPUT; 928 929 if (!DATA_TABLES(dce_info)) 930 return BP_RESULT_BADBIOSTABLE; 931 932 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 933 DATA_TABLES(dce_info)); 934 935 if (!disp_cntl_tbl) 936 return BP_RESULT_BADBIOSTABLE; 937 938 *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 939 940 return result; 941 } 942 943 static enum bp_result get_lttpr_caps_v4_2( 944 struct bios_parser *bp, 945 uint8_t *dce_caps) 946 { 947 enum bp_result result = BP_RESULT_OK; 948 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 949 950 if (!dce_caps) 951 return BP_RESULT_BADINPUT; 952 953 if (!DATA_TABLES(dce_info)) 954 return BP_RESULT_BADBIOSTABLE; 955 956 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 957 DATA_TABLES(dce_info)); 958 959 if (!disp_cntl_tbl) 960 return BP_RESULT_BADBIOSTABLE; 961 962 *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 963 964 return result; 965 } 966 967 static enum bp_result get_lttpr_caps_v4_3( 968 struct bios_parser *bp, 969 uint8_t *dce_caps) 970 { 971 enum bp_result result = BP_RESULT_OK; 972 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 973 974 if (!dce_caps) 975 return BP_RESULT_BADINPUT; 976 977 if (!DATA_TABLES(dce_info)) 978 return BP_RESULT_BADBIOSTABLE; 979 980 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 981 DATA_TABLES(dce_info)); 982 983 if (!disp_cntl_tbl) 984 return BP_RESULT_BADBIOSTABLE; 985 986 *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 987 988 return result; 989 } 990 991 static enum bp_result get_lttpr_caps_v4_4( 992 struct bios_parser *bp, 993 uint8_t *dce_caps) 994 { 995 enum bp_result result = BP_RESULT_OK; 996 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 997 998 if (!dce_caps) 999 return BP_RESULT_BADINPUT; 1000 1001 if (!DATA_TABLES(dce_info)) 1002 return BP_RESULT_BADBIOSTABLE; 1003 1004 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1005 DATA_TABLES(dce_info)); 1006 1007 if (!disp_cntl_tbl) 1008 return BP_RESULT_BADBIOSTABLE; 1009 1010 *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1011 1012 return result; 1013 } 1014 1015 static enum bp_result bios_parser_get_lttpr_caps( 1016 struct dc_bios *dcb, 1017 uint8_t *dce_caps) 1018 { 1019 struct bios_parser *bp = BP_FROM_DCB(dcb); 1020 enum bp_result result = BP_RESULT_UNSUPPORTED; 1021 struct atom_common_table_header *header; 1022 struct atom_data_revision tbl_revision; 1023 1024 if (!DATA_TABLES(dce_info)) 1025 return BP_RESULT_UNSUPPORTED; 1026 1027 header = GET_IMAGE(struct atom_common_table_header, 1028 DATA_TABLES(dce_info)); 1029 get_atom_data_table_revision(header, &tbl_revision); 1030 switch (tbl_revision.major) { 1031 case 4: 1032 switch (tbl_revision.minor) { 1033 case 1: 1034 result = get_lttpr_caps_v4_1(bp, dce_caps); 1035 break; 1036 case 2: 1037 result = get_lttpr_caps_v4_2(bp, dce_caps); 1038 break; 1039 case 3: 1040 result = get_lttpr_caps_v4_3(bp, dce_caps); 1041 break; 1042 case 4: 1043 result = get_lttpr_caps_v4_4(bp, dce_caps); 1044 break; 1045 default: 1046 break; 1047 } 1048 break; 1049 default: 1050 break; 1051 } 1052 1053 return result; 1054 } 1055 1056 static enum bp_result get_embedded_panel_info_v2_1( 1057 struct bios_parser *bp, 1058 struct embedded_panel_info *info) 1059 { 1060 struct lcd_info_v2_1 *lvds; 1061 1062 if (!info) 1063 return BP_RESULT_BADINPUT; 1064 1065 if (!DATA_TABLES(lcd_info)) 1066 return BP_RESULT_UNSUPPORTED; 1067 1068 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1069 1070 if (!lvds) 1071 return BP_RESULT_BADBIOSTABLE; 1072 1073 /* TODO: previous vv1_3, should v2_1 */ 1074 if (!((lvds->table_header.format_revision == 2) 1075 && (lvds->table_header.content_revision >= 1))) 1076 return BP_RESULT_UNSUPPORTED; 1077 1078 memset(info, 0, sizeof(struct embedded_panel_info)); 1079 1080 /* We need to convert from 10KHz units into KHz units */ 1081 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1082 /* usHActive does not include borders, according to VBIOS team */ 1083 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1084 /* usHBlanking_Time includes borders, so we should really be 1085 * subtractingborders duing this translation, but LVDS generally 1086 * doesn't have borders, so we should be okay leaving this as is for 1087 * now. May need to revisit if we ever have LVDS with borders 1088 */ 1089 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1090 /* usVActive does not include borders, according to VBIOS team*/ 1091 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1092 /* usVBlanking_Time includes borders, so we should really be 1093 * subtracting borders duing this translation, but LVDS generally 1094 * doesn't have borders, so we should be okay leaving this as is for 1095 * now. May need to revisit if we ever have LVDS with borders 1096 */ 1097 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1098 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1099 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1100 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1101 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1102 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1103 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1104 1105 /* not provided by VBIOS */ 1106 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1107 1108 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1109 & ATOM_HSYNC_POLARITY); 1110 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1111 & ATOM_VSYNC_POLARITY); 1112 1113 /* not provided by VBIOS */ 1114 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1115 1116 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1117 & ATOM_H_REPLICATIONBY2); 1118 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1119 & ATOM_V_REPLICATIONBY2); 1120 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1121 & ATOM_COMPOSITESYNC); 1122 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1123 1124 /* not provided by VBIOS*/ 1125 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1126 /* not provided by VBIOS*/ 1127 info->ss_id = 0; 1128 1129 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1130 1131 return BP_RESULT_OK; 1132 } 1133 1134 static enum bp_result bios_parser_get_embedded_panel_info( 1135 struct dc_bios *dcb, 1136 struct embedded_panel_info *info) 1137 { 1138 struct bios_parser 1139 *bp = BP_FROM_DCB(dcb); 1140 struct atom_common_table_header *header; 1141 struct atom_data_revision tbl_revision; 1142 1143 if (!DATA_TABLES(lcd_info)) 1144 return BP_RESULT_FAILURE; 1145 1146 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1147 1148 if (!header) 1149 return BP_RESULT_BADBIOSTABLE; 1150 1151 get_atom_data_table_revision(header, &tbl_revision); 1152 1153 switch (tbl_revision.major) { 1154 case 2: 1155 switch (tbl_revision.minor) { 1156 case 1: 1157 return get_embedded_panel_info_v2_1(bp, info); 1158 default: 1159 break; 1160 } 1161 break; 1162 default: 1163 break; 1164 } 1165 1166 return BP_RESULT_FAILURE; 1167 } 1168 1169 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1170 { 1171 enum dal_device_type device_type = device_id.device_type; 1172 uint32_t enum_id = device_id.enum_id; 1173 1174 switch (device_type) { 1175 case DEVICE_TYPE_LCD: 1176 switch (enum_id) { 1177 case 1: 1178 return ATOM_DISPLAY_LCD1_SUPPORT; 1179 default: 1180 break; 1181 } 1182 break; 1183 case DEVICE_TYPE_DFP: 1184 switch (enum_id) { 1185 case 1: 1186 return ATOM_DISPLAY_DFP1_SUPPORT; 1187 case 2: 1188 return ATOM_DISPLAY_DFP2_SUPPORT; 1189 case 3: 1190 return ATOM_DISPLAY_DFP3_SUPPORT; 1191 case 4: 1192 return ATOM_DISPLAY_DFP4_SUPPORT; 1193 case 5: 1194 return ATOM_DISPLAY_DFP5_SUPPORT; 1195 case 6: 1196 return ATOM_DISPLAY_DFP6_SUPPORT; 1197 default: 1198 break; 1199 } 1200 break; 1201 default: 1202 break; 1203 } 1204 1205 /* Unidentified device ID, return empty support mask. */ 1206 return 0; 1207 } 1208 1209 static bool bios_parser_is_device_id_supported( 1210 struct dc_bios *dcb, 1211 struct device_id id) 1212 { 1213 struct bios_parser *bp = BP_FROM_DCB(dcb); 1214 1215 uint32_t mask = get_support_mask_for_device_id(id); 1216 1217 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1218 mask) != 0; 1219 } 1220 1221 static uint32_t bios_parser_get_ss_entry_number( 1222 struct dc_bios *dcb, 1223 enum as_signal_type signal) 1224 { 1225 /* TODO: DAL2 atomfirmware implementation does not need this. 1226 * why DAL3 need this? 1227 */ 1228 return 1; 1229 } 1230 1231 static enum bp_result bios_parser_transmitter_control( 1232 struct dc_bios *dcb, 1233 struct bp_transmitter_control *cntl) 1234 { 1235 struct bios_parser *bp = BP_FROM_DCB(dcb); 1236 1237 if (!bp->cmd_tbl.transmitter_control) 1238 return BP_RESULT_FAILURE; 1239 1240 return bp->cmd_tbl.transmitter_control(bp, cntl); 1241 } 1242 1243 static enum bp_result bios_parser_encoder_control( 1244 struct dc_bios *dcb, 1245 struct bp_encoder_control *cntl) 1246 { 1247 struct bios_parser *bp = BP_FROM_DCB(dcb); 1248 1249 if (!bp->cmd_tbl.dig_encoder_control) 1250 return BP_RESULT_FAILURE; 1251 1252 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1253 } 1254 1255 static enum bp_result bios_parser_set_pixel_clock( 1256 struct dc_bios *dcb, 1257 struct bp_pixel_clock_parameters *bp_params) 1258 { 1259 struct bios_parser *bp = BP_FROM_DCB(dcb); 1260 1261 if (!bp->cmd_tbl.set_pixel_clock) 1262 return BP_RESULT_FAILURE; 1263 1264 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1265 } 1266 1267 static enum bp_result bios_parser_set_dce_clock( 1268 struct dc_bios *dcb, 1269 struct bp_set_dce_clock_parameters *bp_params) 1270 { 1271 struct bios_parser *bp = BP_FROM_DCB(dcb); 1272 1273 if (!bp->cmd_tbl.set_dce_clock) 1274 return BP_RESULT_FAILURE; 1275 1276 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1277 } 1278 1279 static enum bp_result bios_parser_program_crtc_timing( 1280 struct dc_bios *dcb, 1281 struct bp_hw_crtc_timing_parameters *bp_params) 1282 { 1283 struct bios_parser *bp = BP_FROM_DCB(dcb); 1284 1285 if (!bp->cmd_tbl.set_crtc_timing) 1286 return BP_RESULT_FAILURE; 1287 1288 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1289 } 1290 1291 static enum bp_result bios_parser_enable_crtc( 1292 struct dc_bios *dcb, 1293 enum controller_id id, 1294 bool enable) 1295 { 1296 struct bios_parser *bp = BP_FROM_DCB(dcb); 1297 1298 if (!bp->cmd_tbl.enable_crtc) 1299 return BP_RESULT_FAILURE; 1300 1301 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1302 } 1303 1304 static enum bp_result bios_parser_enable_disp_power_gating( 1305 struct dc_bios *dcb, 1306 enum controller_id controller_id, 1307 enum bp_pipe_control_action action) 1308 { 1309 struct bios_parser *bp = BP_FROM_DCB(dcb); 1310 1311 if (!bp->cmd_tbl.enable_disp_power_gating) 1312 return BP_RESULT_FAILURE; 1313 1314 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1315 action); 1316 } 1317 1318 static enum bp_result bios_parser_enable_lvtma_control( 1319 struct dc_bios *dcb, 1320 uint8_t uc_pwr_on, 1321 uint8_t panel_instance) 1322 { 1323 struct bios_parser *bp = BP_FROM_DCB(dcb); 1324 1325 if (!bp->cmd_tbl.enable_lvtma_control) 1326 return BP_RESULT_FAILURE; 1327 1328 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1329 } 1330 1331 static bool bios_parser_is_accelerated_mode( 1332 struct dc_bios *dcb) 1333 { 1334 return bios_is_accelerated_mode(dcb); 1335 } 1336 1337 /** 1338 * bios_parser_set_scratch_critical_state - update critical state bit 1339 * in VBIOS scratch register 1340 * 1341 * @dcb: pointer to the DC BIO 1342 * @state: set or reset state 1343 */ 1344 static void bios_parser_set_scratch_critical_state( 1345 struct dc_bios *dcb, 1346 bool state) 1347 { 1348 bios_set_scratch_critical_state(dcb, state); 1349 } 1350 1351 static enum bp_result bios_parser_get_firmware_info( 1352 struct dc_bios *dcb, 1353 struct dc_firmware_info *info) 1354 { 1355 struct bios_parser *bp = BP_FROM_DCB(dcb); 1356 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1357 struct atom_common_table_header *header; 1358 1359 struct atom_data_revision revision; 1360 1361 if (info && DATA_TABLES(firmwareinfo)) { 1362 header = GET_IMAGE(struct atom_common_table_header, 1363 DATA_TABLES(firmwareinfo)); 1364 get_atom_data_table_revision(header, &revision); 1365 switch (revision.major) { 1366 case 3: 1367 switch (revision.minor) { 1368 case 1: 1369 result = get_firmware_info_v3_1(bp, info); 1370 break; 1371 case 2: 1372 case 3: 1373 case 4: 1374 result = get_firmware_info_v3_2(bp, info); 1375 break; 1376 default: 1377 break; 1378 } 1379 break; 1380 default: 1381 break; 1382 } 1383 } 1384 1385 return result; 1386 } 1387 1388 static enum bp_result get_firmware_info_v3_1( 1389 struct bios_parser *bp, 1390 struct dc_firmware_info *info) 1391 { 1392 struct atom_firmware_info_v3_1 *firmware_info; 1393 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1394 1395 if (!info) 1396 return BP_RESULT_BADINPUT; 1397 1398 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1399 DATA_TABLES(firmwareinfo)); 1400 1401 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1402 DATA_TABLES(dce_info)); 1403 1404 if (!firmware_info || !dce_info) 1405 return BP_RESULT_BADBIOSTABLE; 1406 1407 memset(info, 0, sizeof(*info)); 1408 1409 /* Pixel clock pll information. */ 1410 /* We need to convert from 10KHz units into KHz units */ 1411 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1412 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1413 1414 /* 27MHz for Vega10: */ 1415 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1416 1417 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1418 if (info->pll_info.crystal_frequency == 0) 1419 info->pll_info.crystal_frequency = 27000; 1420 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1421 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1422 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1423 1424 /* Get GPU PLL VCO Clock */ 1425 1426 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1427 /* VBIOS gives in 10KHz */ 1428 info->smu_gpu_pll_output_freq = 1429 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1430 } 1431 1432 info->oem_i2c_present = false; 1433 1434 return BP_RESULT_OK; 1435 } 1436 1437 static enum bp_result get_firmware_info_v3_2( 1438 struct bios_parser *bp, 1439 struct dc_firmware_info *info) 1440 { 1441 struct atom_firmware_info_v3_2 *firmware_info; 1442 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1443 struct atom_common_table_header *header; 1444 struct atom_data_revision revision; 1445 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1446 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1447 1448 if (!info) 1449 return BP_RESULT_BADINPUT; 1450 1451 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1452 DATA_TABLES(firmwareinfo)); 1453 1454 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1455 DATA_TABLES(dce_info)); 1456 1457 if (!firmware_info || !dce_info) 1458 return BP_RESULT_BADBIOSTABLE; 1459 1460 memset(info, 0, sizeof(*info)); 1461 1462 header = GET_IMAGE(struct atom_common_table_header, 1463 DATA_TABLES(smu_info)); 1464 get_atom_data_table_revision(header, &revision); 1465 1466 if (revision.minor == 2) { 1467 /* Vega12 */ 1468 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1469 DATA_TABLES(smu_info)); 1470 1471 if (!smu_info_v3_2) 1472 return BP_RESULT_BADBIOSTABLE; 1473 1474 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1475 } else if (revision.minor == 3) { 1476 /* Vega20 */ 1477 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1478 DATA_TABLES(smu_info)); 1479 1480 if (!smu_info_v3_3) 1481 return BP_RESULT_BADBIOSTABLE; 1482 1483 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1484 } 1485 1486 // We need to convert from 10KHz units into KHz units. 1487 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1488 1489 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1490 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1491 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1492 if (info->pll_info.crystal_frequency == 0) { 1493 if (revision.minor == 2) 1494 info->pll_info.crystal_frequency = 27000; 1495 else if (revision.minor == 3) 1496 info->pll_info.crystal_frequency = 100000; 1497 } 1498 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1499 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1500 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1501 1502 /* Get GPU PLL VCO Clock */ 1503 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1504 if (revision.minor == 2) 1505 info->smu_gpu_pll_output_freq = 1506 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1507 else if (revision.minor == 3) 1508 info->smu_gpu_pll_output_freq = 1509 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1510 } 1511 1512 if (firmware_info->board_i2c_feature_id == 0x2) { 1513 info->oem_i2c_present = true; 1514 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1515 } else { 1516 info->oem_i2c_present = false; 1517 } 1518 1519 return BP_RESULT_OK; 1520 } 1521 1522 static enum bp_result bios_parser_get_encoder_cap_info( 1523 struct dc_bios *dcb, 1524 struct graphics_object_id object_id, 1525 struct bp_encoder_cap_info *info) 1526 { 1527 struct bios_parser *bp = BP_FROM_DCB(dcb); 1528 struct atom_display_object_path_v2 *object; 1529 struct atom_encoder_caps_record *record = NULL; 1530 1531 if (!info) 1532 return BP_RESULT_BADINPUT; 1533 1534 object = get_bios_object(bp, object_id); 1535 1536 if (!object) 1537 return BP_RESULT_BADINPUT; 1538 1539 record = get_encoder_cap_record(bp, object); 1540 if (!record) 1541 return BP_RESULT_NORECORD; 1542 1543 info->DP_HBR2_CAP = (record->encodercaps & 1544 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1545 info->DP_HBR2_EN = (record->encodercaps & 1546 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1547 info->DP_HBR3_EN = (record->encodercaps & 1548 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1549 info->HDMI_6GB_EN = (record->encodercaps & 1550 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1551 info->DP_IS_USB_C = (record->encodercaps & 1552 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1553 1554 return BP_RESULT_OK; 1555 } 1556 1557 1558 static struct atom_encoder_caps_record *get_encoder_cap_record( 1559 struct bios_parser *bp, 1560 struct atom_display_object_path_v2 *object) 1561 { 1562 struct atom_common_record_header *header; 1563 uint32_t offset; 1564 1565 if (!object) { 1566 BREAK_TO_DEBUGGER(); /* Invalid object */ 1567 return NULL; 1568 } 1569 1570 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1571 1572 for (;;) { 1573 header = GET_IMAGE(struct atom_common_record_header, offset); 1574 1575 if (!header) 1576 return NULL; 1577 1578 offset += header->record_size; 1579 1580 if (header->record_type == LAST_RECORD_TYPE || 1581 !header->record_size) 1582 break; 1583 1584 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1585 continue; 1586 1587 if (sizeof(struct atom_encoder_caps_record) <= 1588 header->record_size) 1589 return (struct atom_encoder_caps_record *)header; 1590 } 1591 1592 return NULL; 1593 } 1594 1595 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 1596 struct bios_parser *bp, 1597 struct atom_display_object_path_v2 *object) 1598 { 1599 struct atom_common_record_header *header; 1600 uint32_t offset; 1601 1602 if (!object) { 1603 BREAK_TO_DEBUGGER(); /* Invalid object */ 1604 return NULL; 1605 } 1606 1607 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 1608 1609 for (;;) { 1610 header = GET_IMAGE(struct atom_common_record_header, offset); 1611 1612 if (!header) 1613 return NULL; 1614 1615 offset += header->record_size; 1616 1617 if (header->record_type == LAST_RECORD_TYPE || 1618 !header->record_size) 1619 break; 1620 1621 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 1622 continue; 1623 1624 if (sizeof(struct atom_disp_connector_caps_record) <= 1625 header->record_size) 1626 return (struct atom_disp_connector_caps_record *)header; 1627 } 1628 1629 return NULL; 1630 } 1631 1632 static enum bp_result bios_parser_get_disp_connector_caps_info( 1633 struct dc_bios *dcb, 1634 struct graphics_object_id object_id, 1635 struct bp_disp_connector_caps_info *info) 1636 { 1637 struct bios_parser *bp = BP_FROM_DCB(dcb); 1638 struct atom_display_object_path_v2 *object; 1639 struct atom_disp_connector_caps_record *record = NULL; 1640 1641 if (!info) 1642 return BP_RESULT_BADINPUT; 1643 1644 object = get_bios_object(bp, object_id); 1645 1646 if (!object) 1647 return BP_RESULT_BADINPUT; 1648 1649 record = get_disp_connector_caps_record(bp, object); 1650 if (!record) 1651 return BP_RESULT_NORECORD; 1652 1653 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 1654 ? 1 : 0; 1655 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 1656 ? 1 : 0; 1657 1658 return BP_RESULT_OK; 1659 } 1660 1661 static enum bp_result get_vram_info_v23( 1662 struct bios_parser *bp, 1663 struct dc_vram_info *info) 1664 { 1665 struct atom_vram_info_header_v2_3 *info_v23; 1666 enum bp_result result = BP_RESULT_OK; 1667 1668 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1669 DATA_TABLES(vram_info)); 1670 1671 if (info_v23 == NULL) 1672 return BP_RESULT_BADBIOSTABLE; 1673 1674 info->num_chans = info_v23->vram_module[0].channel_num; 1675 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1676 1677 return result; 1678 } 1679 1680 static enum bp_result get_vram_info_v24( 1681 struct bios_parser *bp, 1682 struct dc_vram_info *info) 1683 { 1684 struct atom_vram_info_header_v2_4 *info_v24; 1685 enum bp_result result = BP_RESULT_OK; 1686 1687 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1688 DATA_TABLES(vram_info)); 1689 1690 if (info_v24 == NULL) 1691 return BP_RESULT_BADBIOSTABLE; 1692 1693 info->num_chans = info_v24->vram_module[0].channel_num; 1694 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1695 1696 return result; 1697 } 1698 1699 static enum bp_result get_vram_info_v25( 1700 struct bios_parser *bp, 1701 struct dc_vram_info *info) 1702 { 1703 struct atom_vram_info_header_v2_5 *info_v25; 1704 enum bp_result result = BP_RESULT_OK; 1705 1706 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1707 DATA_TABLES(vram_info)); 1708 1709 if (info_v25 == NULL) 1710 return BP_RESULT_BADBIOSTABLE; 1711 1712 info->num_chans = info_v25->vram_module[0].channel_num; 1713 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1714 1715 return result; 1716 } 1717 1718 /* 1719 * get_integrated_info_v11 1720 * 1721 * @brief 1722 * Get V8 integrated BIOS information 1723 * 1724 * @param 1725 * bios_parser *bp - [in]BIOS parser handler to get master data table 1726 * integrated_info *info - [out] store and output integrated info 1727 * 1728 * @return 1729 * enum bp_result - BP_RESULT_OK if information is available, 1730 * BP_RESULT_BADBIOSTABLE otherwise. 1731 */ 1732 static enum bp_result get_integrated_info_v11( 1733 struct bios_parser *bp, 1734 struct integrated_info *info) 1735 { 1736 struct atom_integrated_system_info_v1_11 *info_v11; 1737 uint32_t i; 1738 1739 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1740 DATA_TABLES(integratedsysteminfo)); 1741 1742 if (info_v11 == NULL) 1743 return BP_RESULT_BADBIOSTABLE; 1744 1745 info->gpu_cap_info = 1746 le32_to_cpu(info_v11->gpucapinfo); 1747 /* 1748 * system_config: Bit[0] = 0 : PCIE power gating disabled 1749 * = 1 : PCIE power gating enabled 1750 * Bit[1] = 0 : DDR-PLL shut down disabled 1751 * = 1 : DDR-PLL shut down enabled 1752 * Bit[2] = 0 : DDR-PLL power down disabled 1753 * = 1 : DDR-PLL power down enabled 1754 */ 1755 info->system_config = le32_to_cpu(info_v11->system_config); 1756 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1757 info->memory_type = info_v11->memorytype; 1758 info->ma_channel_number = info_v11->umachannelnumber; 1759 info->lvds_ss_percentage = 1760 le16_to_cpu(info_v11->lvds_ss_percentage); 1761 info->dp_ss_control = 1762 le16_to_cpu(info_v11->reserved1); 1763 info->lvds_sspread_rate_in_10hz = 1764 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1765 info->hdmi_ss_percentage = 1766 le16_to_cpu(info_v11->hdmi_ss_percentage); 1767 info->hdmi_sspread_rate_in_10hz = 1768 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1769 info->dvi_ss_percentage = 1770 le16_to_cpu(info_v11->dvi_ss_percentage); 1771 info->dvi_sspread_rate_in_10_hz = 1772 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1773 info->lvds_misc = info_v11->lvds_misc; 1774 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1775 info->ext_disp_conn_info.gu_id[i] = 1776 info_v11->extdispconninfo.guid[i]; 1777 } 1778 1779 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1780 info->ext_disp_conn_info.path[i].device_connector_id = 1781 object_id_from_bios_object_id( 1782 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1783 1784 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1785 object_id_from_bios_object_id( 1786 le16_to_cpu( 1787 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1788 1789 info->ext_disp_conn_info.path[i].device_tag = 1790 le16_to_cpu( 1791 info_v11->extdispconninfo.path[i].device_tag); 1792 info->ext_disp_conn_info.path[i].device_acpi_enum = 1793 le16_to_cpu( 1794 info_v11->extdispconninfo.path[i].device_acpi_enum); 1795 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1796 info_v11->extdispconninfo.path[i].auxddclut_index; 1797 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1798 info_v11->extdispconninfo.path[i].hpdlut_index; 1799 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1800 info_v11->extdispconninfo.path[i].channelmapping; 1801 info->ext_disp_conn_info.path[i].caps = 1802 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1803 } 1804 info->ext_disp_conn_info.checksum = 1805 info_v11->extdispconninfo.checksum; 1806 1807 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1808 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1809 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1810 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1811 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1812 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1813 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1814 } 1815 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1816 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1817 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1818 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1819 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1820 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1821 } 1822 1823 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1824 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1825 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1826 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1827 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1828 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1829 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1830 } 1831 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1832 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1833 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1834 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1835 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1836 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1837 } 1838 1839 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1840 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1841 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1842 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1843 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1844 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1845 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1846 } 1847 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1848 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1849 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1850 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1851 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1852 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1853 } 1854 1855 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1856 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1857 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1858 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1859 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1860 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1861 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1862 } 1863 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1864 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1865 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1866 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1867 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1868 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1869 } 1870 1871 1872 /** TODO - review **/ 1873 #if 0 1874 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1875 * 10; 1876 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1877 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1878 1879 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1880 /* Convert [10KHz] into [KHz] */ 1881 info->disp_clk_voltage[i].max_supported_clk = 1882 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1883 ulMaximumSupportedCLK) * 10; 1884 info->disp_clk_voltage[i].voltage_index = 1885 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1886 } 1887 1888 info->boot_up_req_display_vector = 1889 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1890 info->boot_up_nb_voltage = 1891 le16_to_cpu(info_v11->usBootUpNBVoltage); 1892 info->ext_disp_conn_info_offset = 1893 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1894 info->gmc_restore_reset_time = 1895 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1896 info->minimum_n_clk = 1897 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1898 for (i = 1; i < 4; ++i) 1899 info->minimum_n_clk = 1900 info->minimum_n_clk < 1901 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1902 info->minimum_n_clk : le32_to_cpu( 1903 info_v11->ulNbpStateNClkFreq[i]); 1904 1905 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1906 info->ddr_dll_power_up_time = 1907 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1908 info->ddr_pll_power_up_time = 1909 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1910 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1911 info->max_lvds_pclk_freq_in_single_link = 1912 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1913 info->max_lvds_pclk_freq_in_single_link = 1914 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1915 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1916 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1917 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1918 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1919 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1920 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1921 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1922 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1923 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1924 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1925 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1926 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1927 info->lvds_off_to_on_delay_in_4ms = 1928 info_v11->ucLVDSOffToOnDelay_in4Ms; 1929 info->lvds_bit_depth_control_val = 1930 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1931 1932 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1933 /* Convert [10KHz] into [KHz] */ 1934 info->avail_s_clk[i].supported_s_clk = 1935 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1936 * 10; 1937 info->avail_s_clk[i].voltage_index = 1938 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1939 info->avail_s_clk[i].voltage_id = 1940 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1941 } 1942 #endif /* TODO*/ 1943 1944 return BP_RESULT_OK; 1945 } 1946 1947 static enum bp_result get_integrated_info_v2_1( 1948 struct bios_parser *bp, 1949 struct integrated_info *info) 1950 { 1951 struct atom_integrated_system_info_v2_1 *info_v2_1; 1952 uint32_t i; 1953 1954 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 1955 DATA_TABLES(integratedsysteminfo)); 1956 1957 if (info_v2_1 == NULL) 1958 return BP_RESULT_BADBIOSTABLE; 1959 1960 info->gpu_cap_info = 1961 le32_to_cpu(info_v2_1->gpucapinfo); 1962 /* 1963 * system_config: Bit[0] = 0 : PCIE power gating disabled 1964 * = 1 : PCIE power gating enabled 1965 * Bit[1] = 0 : DDR-PLL shut down disabled 1966 * = 1 : DDR-PLL shut down enabled 1967 * Bit[2] = 0 : DDR-PLL power down disabled 1968 * = 1 : DDR-PLL power down enabled 1969 */ 1970 info->system_config = le32_to_cpu(info_v2_1->system_config); 1971 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 1972 info->memory_type = info_v2_1->memorytype; 1973 info->ma_channel_number = info_v2_1->umachannelnumber; 1974 info->dp_ss_control = 1975 le16_to_cpu(info_v2_1->reserved1); 1976 1977 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1978 info->ext_disp_conn_info.gu_id[i] = 1979 info_v2_1->extdispconninfo.guid[i]; 1980 } 1981 1982 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1983 info->ext_disp_conn_info.path[i].device_connector_id = 1984 object_id_from_bios_object_id( 1985 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 1986 1987 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1988 object_id_from_bios_object_id( 1989 le16_to_cpu( 1990 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 1991 1992 info->ext_disp_conn_info.path[i].device_tag = 1993 le16_to_cpu( 1994 info_v2_1->extdispconninfo.path[i].device_tag); 1995 info->ext_disp_conn_info.path[i].device_acpi_enum = 1996 le16_to_cpu( 1997 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 1998 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1999 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2000 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2001 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2002 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2003 info_v2_1->extdispconninfo.path[i].channelmapping; 2004 info->ext_disp_conn_info.path[i].caps = 2005 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2006 } 2007 2008 info->ext_disp_conn_info.checksum = 2009 info_v2_1->extdispconninfo.checksum; 2010 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2011 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2012 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2013 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2014 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2015 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2016 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2017 } 2018 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2019 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2020 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2021 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2022 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2023 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2024 } 2025 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2026 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2027 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2028 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2029 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2030 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2031 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2032 } 2033 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2034 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2035 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2036 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2037 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2038 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2039 } 2040 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2041 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2042 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2043 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2044 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2045 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2046 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2047 } 2048 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2049 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2050 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2051 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2052 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2053 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2054 } 2055 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2056 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2057 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2058 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2059 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2060 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2061 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2062 } 2063 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2064 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2065 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2066 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2067 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2068 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2069 } 2070 2071 info->edp1_info.edp_backlight_pwm_hz = 2072 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2073 info->edp1_info.edp_ss_percentage = 2074 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2075 info->edp1_info.edp_ss_rate_10hz = 2076 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2077 info->edp1_info.edp_pwr_on_off_delay = 2078 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2079 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2080 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2081 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2082 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2083 info->edp1_info.edp_panel_bpc = 2084 info_v2_1->edp1_info.edp_panel_bpc; 2085 info->edp1_info.edp_bootup_bl_level = 2086 2087 info->edp2_info.edp_backlight_pwm_hz = 2088 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2089 info->edp2_info.edp_ss_percentage = 2090 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2091 info->edp2_info.edp_ss_rate_10hz = 2092 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2093 info->edp2_info.edp_pwr_on_off_delay = 2094 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2095 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2096 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2097 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2098 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2099 info->edp2_info.edp_panel_bpc = 2100 info_v2_1->edp2_info.edp_panel_bpc; 2101 info->edp2_info.edp_bootup_bl_level = 2102 info_v2_1->edp2_info.edp_bootup_bl_level; 2103 2104 return BP_RESULT_OK; 2105 } 2106 2107 /* 2108 * construct_integrated_info 2109 * 2110 * @brief 2111 * Get integrated BIOS information based on table revision 2112 * 2113 * @param 2114 * bios_parser *bp - [in]BIOS parser handler to get master data table 2115 * integrated_info *info - [out] store and output integrated info 2116 * 2117 * @return 2118 * enum bp_result - BP_RESULT_OK if information is available, 2119 * BP_RESULT_BADBIOSTABLE otherwise. 2120 */ 2121 static enum bp_result construct_integrated_info( 2122 struct bios_parser *bp, 2123 struct integrated_info *info) 2124 { 2125 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2126 2127 struct atom_common_table_header *header; 2128 struct atom_data_revision revision; 2129 uint32_t i; 2130 uint32_t j; 2131 2132 if (info && DATA_TABLES(integratedsysteminfo)) { 2133 header = GET_IMAGE(struct atom_common_table_header, 2134 DATA_TABLES(integratedsysteminfo)); 2135 2136 get_atom_data_table_revision(header, &revision); 2137 2138 switch (revision.major) { 2139 case 1: 2140 switch (revision.minor) { 2141 case 11: 2142 case 12: 2143 result = get_integrated_info_v11(bp, info); 2144 break; 2145 default: 2146 return result; 2147 } 2148 break; 2149 case 2: 2150 switch (revision.minor) { 2151 case 1: 2152 result = get_integrated_info_v2_1(bp, info); 2153 break; 2154 default: 2155 return result; 2156 } 2157 break; 2158 default: 2159 return result; 2160 } 2161 } 2162 2163 if (result != BP_RESULT_OK) 2164 return result; 2165 2166 /* Sort voltage table from low to high*/ 2167 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2168 for (j = i; j > 0; --j) { 2169 if (info->disp_clk_voltage[j].max_supported_clk < 2170 info->disp_clk_voltage[j-1].max_supported_clk 2171 ) { 2172 /* swap j and j - 1*/ 2173 swap(info->disp_clk_voltage[j - 1], 2174 info->disp_clk_voltage[j]); 2175 } 2176 } 2177 } 2178 2179 return result; 2180 } 2181 2182 static enum bp_result bios_parser_get_vram_info( 2183 struct dc_bios *dcb, 2184 struct dc_vram_info *info) 2185 { 2186 struct bios_parser *bp = BP_FROM_DCB(dcb); 2187 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2188 struct atom_common_table_header *header; 2189 struct atom_data_revision revision; 2190 2191 if (info && DATA_TABLES(vram_info)) { 2192 header = GET_IMAGE(struct atom_common_table_header, 2193 DATA_TABLES(vram_info)); 2194 2195 get_atom_data_table_revision(header, &revision); 2196 2197 switch (revision.major) { 2198 case 2: 2199 switch (revision.minor) { 2200 case 3: 2201 result = get_vram_info_v23(bp, info); 2202 break; 2203 case 4: 2204 result = get_vram_info_v24(bp, info); 2205 break; 2206 case 5: 2207 result = get_vram_info_v25(bp, info); 2208 break; 2209 default: 2210 break; 2211 } 2212 break; 2213 2214 default: 2215 return result; 2216 } 2217 2218 } 2219 return result; 2220 } 2221 2222 static struct integrated_info *bios_parser_create_integrated_info( 2223 struct dc_bios *dcb) 2224 { 2225 struct bios_parser *bp = BP_FROM_DCB(dcb); 2226 struct integrated_info *info = NULL; 2227 2228 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2229 2230 if (info == NULL) { 2231 ASSERT_CRITICAL(0); 2232 return NULL; 2233 } 2234 2235 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2236 return info; 2237 2238 kfree(info); 2239 2240 return NULL; 2241 } 2242 2243 static enum bp_result update_slot_layout_info( 2244 struct dc_bios *dcb, 2245 unsigned int i, 2246 struct slot_layout_info *slot_layout_info) 2247 { 2248 unsigned int record_offset; 2249 unsigned int j; 2250 struct atom_display_object_path_v2 *object; 2251 struct atom_bracket_layout_record *record; 2252 struct atom_common_record_header *record_header; 2253 enum bp_result result; 2254 struct bios_parser *bp; 2255 struct object_info_table *tbl; 2256 struct display_object_info_table_v1_4 *v1_4; 2257 2258 record = NULL; 2259 record_header = NULL; 2260 result = BP_RESULT_NORECORD; 2261 2262 bp = BP_FROM_DCB(dcb); 2263 tbl = &bp->object_info_tbl; 2264 v1_4 = tbl->v1_4; 2265 2266 object = &v1_4->display_path[i]; 2267 record_offset = (unsigned int) 2268 (object->disp_recordoffset) + 2269 (unsigned int)(bp->object_info_tbl_offset); 2270 2271 for (;;) { 2272 2273 record_header = (struct atom_common_record_header *) 2274 GET_IMAGE(struct atom_common_record_header, 2275 record_offset); 2276 if (record_header == NULL) { 2277 result = BP_RESULT_BADBIOSTABLE; 2278 break; 2279 } 2280 2281 /* the end of the list */ 2282 if (record_header->record_type == 0xff || 2283 record_header->record_size == 0) { 2284 break; 2285 } 2286 2287 if (record_header->record_type == 2288 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2289 sizeof(struct atom_bracket_layout_record) 2290 <= record_header->record_size) { 2291 record = (struct atom_bracket_layout_record *) 2292 (record_header); 2293 result = BP_RESULT_OK; 2294 break; 2295 } 2296 2297 record_offset += record_header->record_size; 2298 } 2299 2300 /* return if the record not found */ 2301 if (result != BP_RESULT_OK) 2302 return result; 2303 2304 /* get slot sizes */ 2305 slot_layout_info->length = record->bracketlen; 2306 slot_layout_info->width = record->bracketwidth; 2307 2308 /* get info for each connector in the slot */ 2309 slot_layout_info->num_of_connectors = record->conn_num; 2310 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2311 slot_layout_info->connectors[j].connector_type = 2312 (enum connector_layout_type) 2313 (record->conn_info[j].connector_type); 2314 switch (record->conn_info[j].connector_type) { 2315 case CONNECTOR_TYPE_DVI_D: 2316 slot_layout_info->connectors[j].connector_type = 2317 CONNECTOR_LAYOUT_TYPE_DVI_D; 2318 slot_layout_info->connectors[j].length = 2319 CONNECTOR_SIZE_DVI; 2320 break; 2321 2322 case CONNECTOR_TYPE_HDMI: 2323 slot_layout_info->connectors[j].connector_type = 2324 CONNECTOR_LAYOUT_TYPE_HDMI; 2325 slot_layout_info->connectors[j].length = 2326 CONNECTOR_SIZE_HDMI; 2327 break; 2328 2329 case CONNECTOR_TYPE_DISPLAY_PORT: 2330 slot_layout_info->connectors[j].connector_type = 2331 CONNECTOR_LAYOUT_TYPE_DP; 2332 slot_layout_info->connectors[j].length = 2333 CONNECTOR_SIZE_DP; 2334 break; 2335 2336 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2337 slot_layout_info->connectors[j].connector_type = 2338 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2339 slot_layout_info->connectors[j].length = 2340 CONNECTOR_SIZE_MINI_DP; 2341 break; 2342 2343 default: 2344 slot_layout_info->connectors[j].connector_type = 2345 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2346 slot_layout_info->connectors[j].length = 2347 CONNECTOR_SIZE_UNKNOWN; 2348 } 2349 2350 slot_layout_info->connectors[j].position = 2351 record->conn_info[j].position; 2352 slot_layout_info->connectors[j].connector_id = 2353 object_id_from_bios_object_id( 2354 record->conn_info[j].connectorobjid); 2355 } 2356 return result; 2357 } 2358 2359 2360 static enum bp_result get_bracket_layout_record( 2361 struct dc_bios *dcb, 2362 unsigned int bracket_layout_id, 2363 struct slot_layout_info *slot_layout_info) 2364 { 2365 unsigned int i; 2366 struct bios_parser *bp = BP_FROM_DCB(dcb); 2367 enum bp_result result; 2368 struct object_info_table *tbl; 2369 struct display_object_info_table_v1_4 *v1_4; 2370 2371 if (slot_layout_info == NULL) { 2372 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2373 return BP_RESULT_BADINPUT; 2374 } 2375 tbl = &bp->object_info_tbl; 2376 v1_4 = tbl->v1_4; 2377 2378 result = BP_RESULT_NORECORD; 2379 for (i = 0; i < v1_4->number_of_path; ++i) { 2380 2381 if (bracket_layout_id == 2382 v1_4->display_path[i].display_objid) { 2383 result = update_slot_layout_info(dcb, i, 2384 slot_layout_info); 2385 break; 2386 } 2387 } 2388 return result; 2389 } 2390 2391 static enum bp_result bios_get_board_layout_info( 2392 struct dc_bios *dcb, 2393 struct board_layout_info *board_layout_info) 2394 { 2395 unsigned int i; 2396 enum bp_result record_result; 2397 2398 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2399 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2400 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2401 0, 0 2402 }; 2403 2404 if (board_layout_info == NULL) { 2405 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2406 return BP_RESULT_BADINPUT; 2407 } 2408 2409 board_layout_info->num_of_slots = 0; 2410 2411 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2412 record_result = get_bracket_layout_record(dcb, 2413 slot_index_to_vbios_id[i], 2414 &board_layout_info->slots[i]); 2415 2416 if (record_result == BP_RESULT_NORECORD && i > 0) 2417 break; /* no more slots present in bios */ 2418 else if (record_result != BP_RESULT_OK) 2419 return record_result; /* fail */ 2420 2421 ++board_layout_info->num_of_slots; 2422 } 2423 2424 /* all data is valid */ 2425 board_layout_info->is_number_of_slots_valid = 1; 2426 board_layout_info->is_slots_size_valid = 1; 2427 board_layout_info->is_connector_offsets_valid = 1; 2428 board_layout_info->is_connector_lengths_valid = 1; 2429 2430 return BP_RESULT_OK; 2431 } 2432 2433 2434 static uint16_t bios_parser_pack_data_tables( 2435 struct dc_bios *dcb, 2436 void *dst) 2437 { 2438 #ifdef PACK_BIOS_DATA 2439 struct bios_parser *bp = BP_FROM_DCB(dcb); 2440 struct atom_rom_header_v2_2 *rom_header = NULL; 2441 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2442 struct atom_common_table_header *data_tbl_header = NULL; 2443 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2444 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2445 struct atom_data_revision tbl_rev = {0}; 2446 uint16_t *rom_header_offset = NULL; 2447 const uint8_t *bios = bp->base.bios; 2448 uint8_t *bios_dst = (uint8_t *)dst; 2449 uint16_t packed_rom_header_offset; 2450 uint16_t packed_masterdatatable_offset; 2451 uint16_t packed_data_tbl_offset; 2452 uint16_t data_tbl_offset; 2453 unsigned int i; 2454 2455 rom_header_offset = 2456 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2457 2458 if (!rom_header_offset) 2459 return 0; 2460 2461 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2462 2463 if (!rom_header) 2464 return 0; 2465 2466 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2467 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2468 return 0; 2469 2470 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2471 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2472 return 0; 2473 2474 packed_rom_header_offset = 2475 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2476 2477 packed_masterdatatable_offset = 2478 packed_rom_header_offset + rom_header->table_header.structuresize; 2479 2480 packed_data_tbl_offset = 2481 packed_masterdatatable_offset + 2482 bp->master_data_tbl->table_header.structuresize; 2483 2484 packed_rom_header = 2485 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2486 2487 packed_master_data_tbl = 2488 (struct atom_master_data_table_v2_1 *)(bios_dst + 2489 packed_masterdatatable_offset); 2490 2491 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2492 2493 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2494 packed_rom_header_offset; 2495 2496 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2497 rom_header->table_header.structuresize); 2498 2499 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2500 2501 memcpy(&packed_master_data_tbl->table_header, 2502 &bp->master_data_tbl->table_header, 2503 sizeof(bp->master_data_tbl->table_header)); 2504 2505 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2506 2507 /* Each data table offset in data table list is 2 bytes, 2508 * we can use that to iterate through listOfdatatables 2509 * without knowing the name of each member. 2510 */ 2511 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2512 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2513 2514 if (data_tbl_offset) { 2515 data_tbl_header = 2516 (struct atom_common_table_header *)(bios + data_tbl_offset); 2517 2518 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2519 data_tbl_header->structuresize); 2520 2521 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2522 packed_data_tbl_offset; 2523 2524 packed_data_tbl_offset += data_tbl_header->structuresize; 2525 } else { 2526 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2527 } 2528 } 2529 return packed_data_tbl_offset; 2530 #endif 2531 // TODO: There is data bytes alignment issue, disable it for now. 2532 return 0; 2533 } 2534 2535 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2536 struct bios_parser *bp, 2537 uint32_t rev_major, 2538 uint32_t rev_minor, 2539 uint16_t *dc_golden_table_ver) 2540 { 2541 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2542 uint32_t dc_golden_offset = 0; 2543 *dc_golden_table_ver = 0; 2544 2545 if (!DATA_TABLES(dce_info)) 2546 return NULL; 2547 2548 /* ver.4.4 or higher */ 2549 switch (rev_major) { 2550 case 4: 2551 switch (rev_minor) { 2552 case 4: 2553 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2554 DATA_TABLES(dce_info)); 2555 if (!disp_cntl_tbl_4_4) 2556 return NULL; 2557 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2558 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2559 break; 2560 } 2561 break; 2562 } 2563 2564 if (!dc_golden_offset) 2565 return NULL; 2566 2567 if (*dc_golden_table_ver != 1) 2568 return NULL; 2569 2570 return GET_IMAGE(struct atom_dc_golden_table_v1, 2571 dc_golden_offset); 2572 } 2573 2574 static enum bp_result bios_get_atom_dc_golden_table( 2575 struct dc_bios *dcb) 2576 { 2577 struct bios_parser *bp = BP_FROM_DCB(dcb); 2578 enum bp_result result = BP_RESULT_OK; 2579 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2580 struct atom_common_table_header *header; 2581 struct atom_data_revision tbl_revision; 2582 uint16_t dc_golden_table_ver = 0; 2583 2584 header = GET_IMAGE(struct atom_common_table_header, 2585 DATA_TABLES(dce_info)); 2586 if (!header) 2587 return BP_RESULT_UNSUPPORTED; 2588 2589 get_atom_data_table_revision(header, &tbl_revision); 2590 2591 atom_dc_golden_table = bios_get_golden_table(bp, 2592 tbl_revision.major, 2593 tbl_revision.minor, 2594 &dc_golden_table_ver); 2595 2596 if (!atom_dc_golden_table) 2597 return BP_RESULT_UNSUPPORTED; 2598 2599 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2600 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2601 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2602 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2603 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2604 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2605 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2606 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2607 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2608 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2609 2610 return result; 2611 } 2612 2613 2614 static const struct dc_vbios_funcs vbios_funcs = { 2615 .get_connectors_number = bios_parser_get_connectors_number, 2616 2617 .get_connector_id = bios_parser_get_connector_id, 2618 2619 .get_src_obj = bios_parser_get_src_obj, 2620 2621 .get_i2c_info = bios_parser_get_i2c_info, 2622 2623 .get_hpd_info = bios_parser_get_hpd_info, 2624 2625 .get_device_tag = bios_parser_get_device_tag, 2626 2627 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2628 2629 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2630 2631 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2632 2633 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2634 2635 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2636 2637 .is_device_id_supported = bios_parser_is_device_id_supported, 2638 2639 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2640 2641 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2642 2643 2644 /* COMMANDS */ 2645 .encoder_control = bios_parser_encoder_control, 2646 2647 .transmitter_control = bios_parser_transmitter_control, 2648 2649 .enable_crtc = bios_parser_enable_crtc, 2650 2651 .set_pixel_clock = bios_parser_set_pixel_clock, 2652 2653 .set_dce_clock = bios_parser_set_dce_clock, 2654 2655 .program_crtc_timing = bios_parser_program_crtc_timing, 2656 2657 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2658 2659 .bios_parser_destroy = firmware_parser_destroy, 2660 2661 .get_board_layout_info = bios_get_board_layout_info, 2662 .pack_data_tables = bios_parser_pack_data_tables, 2663 2664 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2665 2666 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2667 2668 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2669 2670 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 2671 2672 .get_lttpr_caps = bios_parser_get_lttpr_caps, 2673 }; 2674 2675 static bool bios_parser2_construct( 2676 struct bios_parser *bp, 2677 struct bp_init_data *init, 2678 enum dce_version dce_version) 2679 { 2680 uint16_t *rom_header_offset = NULL; 2681 struct atom_rom_header_v2_2 *rom_header = NULL; 2682 struct display_object_info_table_v1_4 *object_info_tbl; 2683 struct atom_data_revision tbl_rev = {0}; 2684 2685 if (!init) 2686 return false; 2687 2688 if (!init->bios) 2689 return false; 2690 2691 bp->base.funcs = &vbios_funcs; 2692 bp->base.bios = init->bios; 2693 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2694 2695 bp->base.ctx = init->ctx; 2696 2697 bp->base.bios_local_image = NULL; 2698 2699 rom_header_offset = 2700 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2701 2702 if (!rom_header_offset) 2703 return false; 2704 2705 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2706 2707 if (!rom_header) 2708 return false; 2709 2710 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2711 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2712 return false; 2713 2714 bp->master_data_tbl = 2715 GET_IMAGE(struct atom_master_data_table_v2_1, 2716 rom_header->masterdatatable_offset); 2717 2718 if (!bp->master_data_tbl) 2719 return false; 2720 2721 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2722 2723 if (!bp->object_info_tbl_offset) 2724 return false; 2725 2726 object_info_tbl = 2727 GET_IMAGE(struct display_object_info_table_v1_4, 2728 bp->object_info_tbl_offset); 2729 2730 if (!object_info_tbl) 2731 return false; 2732 2733 get_atom_data_table_revision(&object_info_tbl->table_header, 2734 &bp->object_info_tbl.revision); 2735 2736 if (bp->object_info_tbl.revision.major == 1 2737 && bp->object_info_tbl.revision.minor >= 4) { 2738 struct display_object_info_table_v1_4 *tbl_v1_4; 2739 2740 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2741 bp->object_info_tbl_offset); 2742 if (!tbl_v1_4) 2743 return false; 2744 2745 bp->object_info_tbl.v1_4 = tbl_v1_4; 2746 } else 2747 return false; 2748 2749 dal_firmware_parser_init_cmd_tbl(bp); 2750 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2751 2752 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2753 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2754 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2755 2756 return true; 2757 } 2758 2759 struct dc_bios *firmware_parser_create( 2760 struct bp_init_data *init, 2761 enum dce_version dce_version) 2762 { 2763 struct bios_parser *bp = NULL; 2764 2765 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2766 if (!bp) 2767 return NULL; 2768 2769 if (bios_parser2_construct(bp, init, dce_version)) 2770 return &bp->base; 2771 2772 kfree(bp); 2773 return NULL; 2774 } 2775 2776 2777