1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @param gpio_id, GPIO ID 489 * @param info, GpioPin information structure 490 * @return Bios parser result code 491 * @note 492 * to get the GPIO PIN INFO, we need: 493 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 495 * to get the registerA offset/mask 496 */ 497 static enum bp_result bios_parser_get_gpio_pin_info( 498 struct dc_bios *dcb, 499 uint32_t gpio_id, 500 struct gpio_pin_info *info) 501 { 502 struct bios_parser *bp = BP_FROM_DCB(dcb); 503 struct atom_gpio_pin_lut_v2_1 *header; 504 uint32_t count = 0; 505 uint32_t i = 0; 506 507 if (!DATA_TABLES(gpio_pin_lut)) 508 return BP_RESULT_BADBIOSTABLE; 509 510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 511 DATA_TABLES(gpio_pin_lut)); 512 if (!header) 513 return BP_RESULT_BADBIOSTABLE; 514 515 if (sizeof(struct atom_common_table_header) + 516 sizeof(struct atom_gpio_pin_assignment) 517 > le16_to_cpu(header->table_header.structuresize)) 518 return BP_RESULT_BADBIOSTABLE; 519 520 if (header->table_header.content_revision != 1) 521 return BP_RESULT_UNSUPPORTED; 522 523 /* Temporary hard code gpio pin info */ 524 #if defined(FOR_SIMNOW_BOOT) 525 { 526 struct atom_gpio_pin_assignment gpio_pin[8] = { 527 {0x5db5, 0, 0, 1, 0}, 528 {0x5db5, 8, 8, 2, 0}, 529 {0x5db5, 0x10, 0x10, 3, 0}, 530 {0x5db5, 0x18, 0x14, 4, 0}, 531 {0x5db5, 0x1A, 0x18, 5, 0}, 532 {0x5db5, 0x1C, 0x1C, 6, 0}, 533 }; 534 535 count = 6; 536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 537 } 538 #else 539 count = (le16_to_cpu(header->table_header.structuresize) 540 - sizeof(struct atom_common_table_header)) 541 / sizeof(struct atom_gpio_pin_assignment); 542 #endif 543 for (i = 0; i < count; ++i) { 544 if (header->gpio_pin[i].gpio_id != gpio_id) 545 continue; 546 547 info->offset = 548 (uint32_t) le16_to_cpu( 549 header->gpio_pin[i].data_a_reg_index); 550 info->offset_y = info->offset + 2; 551 info->offset_en = info->offset + 1; 552 info->offset_mask = info->offset - 1; 553 554 info->mask = (uint32_t) (1 << 555 header->gpio_pin[i].gpio_bitshift); 556 info->mask_y = info->mask + 2; 557 info->mask_en = info->mask + 1; 558 info->mask_mask = info->mask - 1; 559 560 return BP_RESULT_OK; 561 } 562 563 return BP_RESULT_NORECORD; 564 } 565 566 static struct device_id device_type_from_device_id(uint16_t device_id) 567 { 568 569 struct device_id result_device_id; 570 571 result_device_id.raw_device_tag = device_id; 572 573 switch (device_id) { 574 case ATOM_DISPLAY_LCD1_SUPPORT: 575 result_device_id.device_type = DEVICE_TYPE_LCD; 576 result_device_id.enum_id = 1; 577 break; 578 579 case ATOM_DISPLAY_DFP1_SUPPORT: 580 result_device_id.device_type = DEVICE_TYPE_DFP; 581 result_device_id.enum_id = 1; 582 break; 583 584 case ATOM_DISPLAY_DFP2_SUPPORT: 585 result_device_id.device_type = DEVICE_TYPE_DFP; 586 result_device_id.enum_id = 2; 587 break; 588 589 case ATOM_DISPLAY_DFP3_SUPPORT: 590 result_device_id.device_type = DEVICE_TYPE_DFP; 591 result_device_id.enum_id = 3; 592 break; 593 594 case ATOM_DISPLAY_DFP4_SUPPORT: 595 result_device_id.device_type = DEVICE_TYPE_DFP; 596 result_device_id.enum_id = 4; 597 break; 598 599 case ATOM_DISPLAY_DFP5_SUPPORT: 600 result_device_id.device_type = DEVICE_TYPE_DFP; 601 result_device_id.enum_id = 5; 602 break; 603 604 case ATOM_DISPLAY_DFP6_SUPPORT: 605 result_device_id.device_type = DEVICE_TYPE_DFP; 606 result_device_id.enum_id = 6; 607 break; 608 609 default: 610 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 612 result_device_id.enum_id = 0; 613 } 614 return result_device_id; 615 } 616 617 static enum bp_result bios_parser_get_device_tag( 618 struct dc_bios *dcb, 619 struct graphics_object_id connector_object_id, 620 uint32_t device_tag_index, 621 struct connector_device_tag_info *info) 622 { 623 struct bios_parser *bp = BP_FROM_DCB(dcb); 624 struct atom_display_object_path_v2 *object; 625 626 if (!info) 627 return BP_RESULT_BADINPUT; 628 629 /* getBiosObject will return MXM object */ 630 object = get_bios_object(bp, connector_object_id); 631 632 if (!object) { 633 BREAK_TO_DEBUGGER(); /* Invalid object id */ 634 return BP_RESULT_BADINPUT; 635 } 636 637 info->acpi_device = 0; /* BIOS no longer provides this */ 638 info->dev_id = device_type_from_device_id(object->device_tag); 639 640 return BP_RESULT_OK; 641 } 642 643 static enum bp_result get_ss_info_v4_1( 644 struct bios_parser *bp, 645 uint32_t id, 646 uint32_t index, 647 struct spread_spectrum_info *ss_info) 648 { 649 enum bp_result result = BP_RESULT_OK; 650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 651 struct atom_smu_info_v3_3 *smu_info = NULL; 652 653 if (!ss_info) 654 return BP_RESULT_BADINPUT; 655 656 if (!DATA_TABLES(dce_info)) 657 return BP_RESULT_BADBIOSTABLE; 658 659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 660 DATA_TABLES(dce_info)); 661 if (!disp_cntl_tbl) 662 return BP_RESULT_BADBIOSTABLE; 663 664 665 ss_info->type.STEP_AND_DELAY_INFO = false; 666 ss_info->spread_percentage_divider = 1000; 667 /* BIOS no longer uses target clock. Always enable for now */ 668 ss_info->target_clock_range = 0xffffffff; 669 670 switch (id) { 671 case AS_SIGNAL_TYPE_DVI: 672 ss_info->spread_spectrum_percentage = 673 disp_cntl_tbl->dvi_ss_percentage; 674 ss_info->spread_spectrum_range = 675 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 677 ss_info->type.CENTER_MODE = true; 678 break; 679 case AS_SIGNAL_TYPE_HDMI: 680 ss_info->spread_spectrum_percentage = 681 disp_cntl_tbl->hdmi_ss_percentage; 682 ss_info->spread_spectrum_range = 683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 685 ss_info->type.CENTER_MODE = true; 686 break; 687 /* TODO LVDS not support anymore? */ 688 case AS_SIGNAL_TYPE_DISPLAY_PORT: 689 ss_info->spread_spectrum_percentage = 690 disp_cntl_tbl->dp_ss_percentage; 691 ss_info->spread_spectrum_range = 692 disp_cntl_tbl->dp_ss_rate_10hz * 10; 693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 694 ss_info->type.CENTER_MODE = true; 695 break; 696 case AS_SIGNAL_TYPE_GPU_PLL: 697 /* atom_firmware: DAL only get data from dce_info table. 698 * if data within smu_info is needed for DAL, VBIOS should 699 * copy it into dce_info 700 */ 701 result = BP_RESULT_UNSUPPORTED; 702 break; 703 case AS_SIGNAL_TYPE_XGMI: 704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 705 DATA_TABLES(smu_info)); 706 if (!smu_info) 707 return BP_RESULT_BADBIOSTABLE; 708 709 ss_info->spread_spectrum_percentage = 710 smu_info->waflclk_ss_percentage; 711 ss_info->spread_spectrum_range = 712 smu_info->gpuclk_ss_rate_10hz * 10; 713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 714 ss_info->type.CENTER_MODE = true; 715 break; 716 default: 717 result = BP_RESULT_UNSUPPORTED; 718 } 719 720 return result; 721 } 722 723 static enum bp_result get_ss_info_v4_2( 724 struct bios_parser *bp, 725 uint32_t id, 726 uint32_t index, 727 struct spread_spectrum_info *ss_info) 728 { 729 enum bp_result result = BP_RESULT_OK; 730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 731 struct atom_smu_info_v3_1 *smu_info = NULL; 732 733 if (!ss_info) 734 return BP_RESULT_BADINPUT; 735 736 if (!DATA_TABLES(dce_info)) 737 return BP_RESULT_BADBIOSTABLE; 738 739 if (!DATA_TABLES(smu_info)) 740 return BP_RESULT_BADBIOSTABLE; 741 742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 743 DATA_TABLES(dce_info)); 744 if (!disp_cntl_tbl) 745 return BP_RESULT_BADBIOSTABLE; 746 747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 748 if (!smu_info) 749 return BP_RESULT_BADBIOSTABLE; 750 751 ss_info->type.STEP_AND_DELAY_INFO = false; 752 ss_info->spread_percentage_divider = 1000; 753 /* BIOS no longer uses target clock. Always enable for now */ 754 ss_info->target_clock_range = 0xffffffff; 755 756 switch (id) { 757 case AS_SIGNAL_TYPE_DVI: 758 ss_info->spread_spectrum_percentage = 759 disp_cntl_tbl->dvi_ss_percentage; 760 ss_info->spread_spectrum_range = 761 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 763 ss_info->type.CENTER_MODE = true; 764 break; 765 case AS_SIGNAL_TYPE_HDMI: 766 ss_info->spread_spectrum_percentage = 767 disp_cntl_tbl->hdmi_ss_percentage; 768 ss_info->spread_spectrum_range = 769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 771 ss_info->type.CENTER_MODE = true; 772 break; 773 /* TODO LVDS not support anymore? */ 774 case AS_SIGNAL_TYPE_DISPLAY_PORT: 775 ss_info->spread_spectrum_percentage = 776 smu_info->gpuclk_ss_percentage; 777 ss_info->spread_spectrum_range = 778 smu_info->gpuclk_ss_rate_10hz * 10; 779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 780 ss_info->type.CENTER_MODE = true; 781 break; 782 case AS_SIGNAL_TYPE_GPU_PLL: 783 /* atom_firmware: DAL only get data from dce_info table. 784 * if data within smu_info is needed for DAL, VBIOS should 785 * copy it into dce_info 786 */ 787 result = BP_RESULT_UNSUPPORTED; 788 break; 789 default: 790 result = BP_RESULT_UNSUPPORTED; 791 } 792 793 return result; 794 } 795 796 /** 797 * bios_parser_get_spread_spectrum_info 798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 801 * ver 3.1, 802 * there is only one entry for each signal /ss id. However, there is 803 * no planning of supporting multiple spread Sprectum entry for EverGreen 804 * @param [in] this 805 * @param [in] signal, ASSignalType to be converted to info index 806 * @param [in] index, number of entries that match the converted info index 807 * @param [out] ss_info, sprectrum information structure, 808 * @return Bios parser result code 809 */ 810 static enum bp_result bios_parser_get_spread_spectrum_info( 811 struct dc_bios *dcb, 812 enum as_signal_type signal, 813 uint32_t index, 814 struct spread_spectrum_info *ss_info) 815 { 816 struct bios_parser *bp = BP_FROM_DCB(dcb); 817 enum bp_result result = BP_RESULT_UNSUPPORTED; 818 struct atom_common_table_header *header; 819 struct atom_data_revision tbl_revision; 820 821 if (!ss_info) /* check for bad input */ 822 return BP_RESULT_BADINPUT; 823 824 if (!DATA_TABLES(dce_info)) 825 return BP_RESULT_UNSUPPORTED; 826 827 header = GET_IMAGE(struct atom_common_table_header, 828 DATA_TABLES(dce_info)); 829 get_atom_data_table_revision(header, &tbl_revision); 830 831 switch (tbl_revision.major) { 832 case 4: 833 switch (tbl_revision.minor) { 834 case 1: 835 return get_ss_info_v4_1(bp, signal, index, ss_info); 836 case 2: 837 case 3: 838 return get_ss_info_v4_2(bp, signal, index, ss_info); 839 default: 840 break; 841 } 842 break; 843 default: 844 break; 845 } 846 /* there can not be more then one entry for SS Info table */ 847 return result; 848 } 849 850 static enum bp_result get_soc_bb_info_v4_4( 851 struct bios_parser *bp, 852 struct bp_soc_bb_info *soc_bb_info) 853 { 854 enum bp_result result = BP_RESULT_OK; 855 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 856 857 if (!soc_bb_info) 858 return BP_RESULT_BADINPUT; 859 860 if (!DATA_TABLES(dce_info)) 861 return BP_RESULT_BADBIOSTABLE; 862 863 if (!DATA_TABLES(smu_info)) 864 return BP_RESULT_BADBIOSTABLE; 865 866 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 867 DATA_TABLES(dce_info)); 868 if (!disp_cntl_tbl) 869 return BP_RESULT_BADBIOSTABLE; 870 871 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 872 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 873 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 874 875 return result; 876 } 877 878 static enum bp_result bios_parser_get_soc_bb_info( 879 struct dc_bios *dcb, 880 struct bp_soc_bb_info *soc_bb_info) 881 { 882 struct bios_parser *bp = BP_FROM_DCB(dcb); 883 enum bp_result result = BP_RESULT_UNSUPPORTED; 884 struct atom_common_table_header *header; 885 struct atom_data_revision tbl_revision; 886 887 if (!soc_bb_info) /* check for bad input */ 888 return BP_RESULT_BADINPUT; 889 890 if (!DATA_TABLES(dce_info)) 891 return BP_RESULT_UNSUPPORTED; 892 893 header = GET_IMAGE(struct atom_common_table_header, 894 DATA_TABLES(dce_info)); 895 get_atom_data_table_revision(header, &tbl_revision); 896 897 switch (tbl_revision.major) { 898 case 4: 899 switch (tbl_revision.minor) { 900 case 1: 901 case 2: 902 case 3: 903 break; 904 case 4: 905 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 906 default: 907 break; 908 } 909 break; 910 default: 911 break; 912 } 913 914 return result; 915 } 916 917 static enum bp_result get_embedded_panel_info_v2_1( 918 struct bios_parser *bp, 919 struct embedded_panel_info *info) 920 { 921 struct lcd_info_v2_1 *lvds; 922 923 if (!info) 924 return BP_RESULT_BADINPUT; 925 926 if (!DATA_TABLES(lcd_info)) 927 return BP_RESULT_UNSUPPORTED; 928 929 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 930 931 if (!lvds) 932 return BP_RESULT_BADBIOSTABLE; 933 934 /* TODO: previous vv1_3, should v2_1 */ 935 if (!((lvds->table_header.format_revision == 2) 936 && (lvds->table_header.content_revision >= 1))) 937 return BP_RESULT_UNSUPPORTED; 938 939 memset(info, 0, sizeof(struct embedded_panel_info)); 940 941 /* We need to convert from 10KHz units into KHz units */ 942 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 943 /* usHActive does not include borders, according to VBIOS team */ 944 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 945 /* usHBlanking_Time includes borders, so we should really be 946 * subtractingborders duing this translation, but LVDS generally 947 * doesn't have borders, so we should be okay leaving this as is for 948 * now. May need to revisit if we ever have LVDS with borders 949 */ 950 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 951 /* usVActive does not include borders, according to VBIOS team*/ 952 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 953 /* usVBlanking_Time includes borders, so we should really be 954 * subtracting borders duing this translation, but LVDS generally 955 * doesn't have borders, so we should be okay leaving this as is for 956 * now. May need to revisit if we ever have LVDS with borders 957 */ 958 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 959 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 960 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 961 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 962 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 963 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 964 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 965 966 /* not provided by VBIOS */ 967 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 968 969 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 970 & ATOM_HSYNC_POLARITY); 971 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 972 & ATOM_VSYNC_POLARITY); 973 974 /* not provided by VBIOS */ 975 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 976 977 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 978 & ATOM_H_REPLICATIONBY2); 979 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 980 & ATOM_V_REPLICATIONBY2); 981 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 982 & ATOM_COMPOSITESYNC); 983 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 984 985 /* not provided by VBIOS*/ 986 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 987 /* not provided by VBIOS*/ 988 info->ss_id = 0; 989 990 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 991 992 return BP_RESULT_OK; 993 } 994 995 static enum bp_result bios_parser_get_embedded_panel_info( 996 struct dc_bios *dcb, 997 struct embedded_panel_info *info) 998 { 999 struct bios_parser 1000 *bp = BP_FROM_DCB(dcb); 1001 struct atom_common_table_header *header; 1002 struct atom_data_revision tbl_revision; 1003 1004 if (!DATA_TABLES(lcd_info)) 1005 return BP_RESULT_FAILURE; 1006 1007 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1008 1009 if (!header) 1010 return BP_RESULT_BADBIOSTABLE; 1011 1012 get_atom_data_table_revision(header, &tbl_revision); 1013 1014 switch (tbl_revision.major) { 1015 case 2: 1016 switch (tbl_revision.minor) { 1017 case 1: 1018 return get_embedded_panel_info_v2_1(bp, info); 1019 default: 1020 break; 1021 } 1022 default: 1023 break; 1024 } 1025 1026 return BP_RESULT_FAILURE; 1027 } 1028 1029 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1030 { 1031 enum dal_device_type device_type = device_id.device_type; 1032 uint32_t enum_id = device_id.enum_id; 1033 1034 switch (device_type) { 1035 case DEVICE_TYPE_LCD: 1036 switch (enum_id) { 1037 case 1: 1038 return ATOM_DISPLAY_LCD1_SUPPORT; 1039 default: 1040 break; 1041 } 1042 break; 1043 case DEVICE_TYPE_DFP: 1044 switch (enum_id) { 1045 case 1: 1046 return ATOM_DISPLAY_DFP1_SUPPORT; 1047 case 2: 1048 return ATOM_DISPLAY_DFP2_SUPPORT; 1049 case 3: 1050 return ATOM_DISPLAY_DFP3_SUPPORT; 1051 case 4: 1052 return ATOM_DISPLAY_DFP4_SUPPORT; 1053 case 5: 1054 return ATOM_DISPLAY_DFP5_SUPPORT; 1055 case 6: 1056 return ATOM_DISPLAY_DFP6_SUPPORT; 1057 default: 1058 break; 1059 } 1060 break; 1061 default: 1062 break; 1063 } 1064 1065 /* Unidentified device ID, return empty support mask. */ 1066 return 0; 1067 } 1068 1069 static bool bios_parser_is_device_id_supported( 1070 struct dc_bios *dcb, 1071 struct device_id id) 1072 { 1073 struct bios_parser *bp = BP_FROM_DCB(dcb); 1074 1075 uint32_t mask = get_support_mask_for_device_id(id); 1076 1077 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1078 mask) != 0; 1079 } 1080 1081 static uint32_t bios_parser_get_ss_entry_number( 1082 struct dc_bios *dcb, 1083 enum as_signal_type signal) 1084 { 1085 /* TODO: DAL2 atomfirmware implementation does not need this. 1086 * why DAL3 need this? 1087 */ 1088 return 1; 1089 } 1090 1091 static enum bp_result bios_parser_transmitter_control( 1092 struct dc_bios *dcb, 1093 struct bp_transmitter_control *cntl) 1094 { 1095 struct bios_parser *bp = BP_FROM_DCB(dcb); 1096 1097 if (!bp->cmd_tbl.transmitter_control) 1098 return BP_RESULT_FAILURE; 1099 1100 return bp->cmd_tbl.transmitter_control(bp, cntl); 1101 } 1102 1103 static enum bp_result bios_parser_encoder_control( 1104 struct dc_bios *dcb, 1105 struct bp_encoder_control *cntl) 1106 { 1107 struct bios_parser *bp = BP_FROM_DCB(dcb); 1108 1109 if (!bp->cmd_tbl.dig_encoder_control) 1110 return BP_RESULT_FAILURE; 1111 1112 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1113 } 1114 1115 static enum bp_result bios_parser_set_pixel_clock( 1116 struct dc_bios *dcb, 1117 struct bp_pixel_clock_parameters *bp_params) 1118 { 1119 struct bios_parser *bp = BP_FROM_DCB(dcb); 1120 1121 if (!bp->cmd_tbl.set_pixel_clock) 1122 return BP_RESULT_FAILURE; 1123 1124 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1125 } 1126 1127 static enum bp_result bios_parser_set_dce_clock( 1128 struct dc_bios *dcb, 1129 struct bp_set_dce_clock_parameters *bp_params) 1130 { 1131 struct bios_parser *bp = BP_FROM_DCB(dcb); 1132 1133 if (!bp->cmd_tbl.set_dce_clock) 1134 return BP_RESULT_FAILURE; 1135 1136 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1137 } 1138 1139 static enum bp_result bios_parser_program_crtc_timing( 1140 struct dc_bios *dcb, 1141 struct bp_hw_crtc_timing_parameters *bp_params) 1142 { 1143 struct bios_parser *bp = BP_FROM_DCB(dcb); 1144 1145 if (!bp->cmd_tbl.set_crtc_timing) 1146 return BP_RESULT_FAILURE; 1147 1148 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1149 } 1150 1151 static enum bp_result bios_parser_enable_crtc( 1152 struct dc_bios *dcb, 1153 enum controller_id id, 1154 bool enable) 1155 { 1156 struct bios_parser *bp = BP_FROM_DCB(dcb); 1157 1158 if (!bp->cmd_tbl.enable_crtc) 1159 return BP_RESULT_FAILURE; 1160 1161 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1162 } 1163 1164 static enum bp_result bios_parser_enable_disp_power_gating( 1165 struct dc_bios *dcb, 1166 enum controller_id controller_id, 1167 enum bp_pipe_control_action action) 1168 { 1169 struct bios_parser *bp = BP_FROM_DCB(dcb); 1170 1171 if (!bp->cmd_tbl.enable_disp_power_gating) 1172 return BP_RESULT_FAILURE; 1173 1174 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1175 action); 1176 } 1177 1178 static enum bp_result bios_parser_enable_lvtma_control( 1179 struct dc_bios *dcb, 1180 uint8_t uc_pwr_on) 1181 { 1182 struct bios_parser *bp = BP_FROM_DCB(dcb); 1183 1184 if (!bp->cmd_tbl.enable_lvtma_control) 1185 return BP_RESULT_FAILURE; 1186 1187 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on); 1188 } 1189 1190 static bool bios_parser_is_accelerated_mode( 1191 struct dc_bios *dcb) 1192 { 1193 return bios_is_accelerated_mode(dcb); 1194 } 1195 1196 /** 1197 * bios_parser_set_scratch_critical_state 1198 * 1199 * @brief 1200 * update critical state bit in VBIOS scratch register 1201 * 1202 * @param 1203 * bool - to set or reset state 1204 */ 1205 static void bios_parser_set_scratch_critical_state( 1206 struct dc_bios *dcb, 1207 bool state) 1208 { 1209 bios_set_scratch_critical_state(dcb, state); 1210 } 1211 1212 static enum bp_result bios_parser_get_firmware_info( 1213 struct dc_bios *dcb, 1214 struct dc_firmware_info *info) 1215 { 1216 struct bios_parser *bp = BP_FROM_DCB(dcb); 1217 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1218 struct atom_common_table_header *header; 1219 1220 struct atom_data_revision revision; 1221 1222 if (info && DATA_TABLES(firmwareinfo)) { 1223 header = GET_IMAGE(struct atom_common_table_header, 1224 DATA_TABLES(firmwareinfo)); 1225 get_atom_data_table_revision(header, &revision); 1226 switch (revision.major) { 1227 case 3: 1228 switch (revision.minor) { 1229 case 1: 1230 result = get_firmware_info_v3_1(bp, info); 1231 break; 1232 case 2: 1233 case 3: 1234 case 4: 1235 result = get_firmware_info_v3_2(bp, info); 1236 break; 1237 default: 1238 break; 1239 } 1240 break; 1241 default: 1242 break; 1243 } 1244 } 1245 1246 return result; 1247 } 1248 1249 static enum bp_result get_firmware_info_v3_1( 1250 struct bios_parser *bp, 1251 struct dc_firmware_info *info) 1252 { 1253 struct atom_firmware_info_v3_1 *firmware_info; 1254 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1255 1256 if (!info) 1257 return BP_RESULT_BADINPUT; 1258 1259 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1260 DATA_TABLES(firmwareinfo)); 1261 1262 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1263 DATA_TABLES(dce_info)); 1264 1265 if (!firmware_info || !dce_info) 1266 return BP_RESULT_BADBIOSTABLE; 1267 1268 memset(info, 0, sizeof(*info)); 1269 1270 /* Pixel clock pll information. */ 1271 /* We need to convert from 10KHz units into KHz units */ 1272 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1273 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1274 1275 /* 27MHz for Vega10: */ 1276 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1277 1278 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1279 if (info->pll_info.crystal_frequency == 0) 1280 info->pll_info.crystal_frequency = 27000; 1281 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1282 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1283 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1284 1285 /* Get GPU PLL VCO Clock */ 1286 1287 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1288 /* VBIOS gives in 10KHz */ 1289 info->smu_gpu_pll_output_freq = 1290 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1291 } 1292 1293 info->oem_i2c_present = false; 1294 1295 return BP_RESULT_OK; 1296 } 1297 1298 static enum bp_result get_firmware_info_v3_2( 1299 struct bios_parser *bp, 1300 struct dc_firmware_info *info) 1301 { 1302 struct atom_firmware_info_v3_2 *firmware_info; 1303 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1304 struct atom_common_table_header *header; 1305 struct atom_data_revision revision; 1306 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1307 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1308 1309 if (!info) 1310 return BP_RESULT_BADINPUT; 1311 1312 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1313 DATA_TABLES(firmwareinfo)); 1314 1315 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1316 DATA_TABLES(dce_info)); 1317 1318 if (!firmware_info || !dce_info) 1319 return BP_RESULT_BADBIOSTABLE; 1320 1321 memset(info, 0, sizeof(*info)); 1322 1323 header = GET_IMAGE(struct atom_common_table_header, 1324 DATA_TABLES(smu_info)); 1325 get_atom_data_table_revision(header, &revision); 1326 1327 if (revision.minor == 2) { 1328 /* Vega12 */ 1329 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1330 DATA_TABLES(smu_info)); 1331 1332 if (!smu_info_v3_2) 1333 return BP_RESULT_BADBIOSTABLE; 1334 1335 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1336 } else if (revision.minor == 3) { 1337 /* Vega20 */ 1338 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1339 DATA_TABLES(smu_info)); 1340 1341 if (!smu_info_v3_3) 1342 return BP_RESULT_BADBIOSTABLE; 1343 1344 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1345 } 1346 1347 // We need to convert from 10KHz units into KHz units. 1348 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1349 1350 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1351 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1352 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1353 if (info->pll_info.crystal_frequency == 0) { 1354 if (revision.minor == 2) 1355 info->pll_info.crystal_frequency = 27000; 1356 else if (revision.minor == 3) 1357 info->pll_info.crystal_frequency = 100000; 1358 } 1359 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1360 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1361 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1362 1363 /* Get GPU PLL VCO Clock */ 1364 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1365 if (revision.minor == 2) 1366 info->smu_gpu_pll_output_freq = 1367 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1368 else if (revision.minor == 3) 1369 info->smu_gpu_pll_output_freq = 1370 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1371 } 1372 1373 if (firmware_info->board_i2c_feature_id == 0x2) { 1374 info->oem_i2c_present = true; 1375 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1376 } else { 1377 info->oem_i2c_present = false; 1378 } 1379 1380 return BP_RESULT_OK; 1381 } 1382 1383 static enum bp_result bios_parser_get_encoder_cap_info( 1384 struct dc_bios *dcb, 1385 struct graphics_object_id object_id, 1386 struct bp_encoder_cap_info *info) 1387 { 1388 struct bios_parser *bp = BP_FROM_DCB(dcb); 1389 struct atom_display_object_path_v2 *object; 1390 struct atom_encoder_caps_record *record = NULL; 1391 1392 if (!info) 1393 return BP_RESULT_BADINPUT; 1394 1395 object = get_bios_object(bp, object_id); 1396 1397 if (!object) 1398 return BP_RESULT_BADINPUT; 1399 1400 record = get_encoder_cap_record(bp, object); 1401 if (!record) 1402 return BP_RESULT_NORECORD; 1403 1404 info->DP_HBR2_CAP = (record->encodercaps & 1405 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1406 info->DP_HBR2_EN = (record->encodercaps & 1407 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1408 info->DP_HBR3_EN = (record->encodercaps & 1409 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1410 info->HDMI_6GB_EN = (record->encodercaps & 1411 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1412 info->DP_IS_USB_C = (record->encodercaps & 1413 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1414 1415 return BP_RESULT_OK; 1416 } 1417 1418 1419 static struct atom_encoder_caps_record *get_encoder_cap_record( 1420 struct bios_parser *bp, 1421 struct atom_display_object_path_v2 *object) 1422 { 1423 struct atom_common_record_header *header; 1424 uint32_t offset; 1425 1426 if (!object) { 1427 BREAK_TO_DEBUGGER(); /* Invalid object */ 1428 return NULL; 1429 } 1430 1431 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1432 1433 for (;;) { 1434 header = GET_IMAGE(struct atom_common_record_header, offset); 1435 1436 if (!header) 1437 return NULL; 1438 1439 offset += header->record_size; 1440 1441 if (header->record_type == LAST_RECORD_TYPE || 1442 !header->record_size) 1443 break; 1444 1445 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1446 continue; 1447 1448 if (sizeof(struct atom_encoder_caps_record) <= 1449 header->record_size) 1450 return (struct atom_encoder_caps_record *)header; 1451 } 1452 1453 return NULL; 1454 } 1455 1456 static enum bp_result get_vram_info_v23( 1457 struct bios_parser *bp, 1458 struct dc_vram_info *info) 1459 { 1460 struct atom_vram_info_header_v2_3 *info_v23; 1461 enum bp_result result = BP_RESULT_OK; 1462 1463 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1464 DATA_TABLES(vram_info)); 1465 1466 if (info_v23 == NULL) 1467 return BP_RESULT_BADBIOSTABLE; 1468 1469 info->num_chans = info_v23->vram_module[0].channel_num; 1470 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1471 1472 return result; 1473 } 1474 1475 static enum bp_result get_vram_info_v24( 1476 struct bios_parser *bp, 1477 struct dc_vram_info *info) 1478 { 1479 struct atom_vram_info_header_v2_4 *info_v24; 1480 enum bp_result result = BP_RESULT_OK; 1481 1482 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1483 DATA_TABLES(vram_info)); 1484 1485 if (info_v24 == NULL) 1486 return BP_RESULT_BADBIOSTABLE; 1487 1488 info->num_chans = info_v24->vram_module[0].channel_num; 1489 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1490 1491 return result; 1492 } 1493 1494 static enum bp_result get_vram_info_v25( 1495 struct bios_parser *bp, 1496 struct dc_vram_info *info) 1497 { 1498 struct atom_vram_info_header_v2_5 *info_v25; 1499 enum bp_result result = BP_RESULT_OK; 1500 1501 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1502 DATA_TABLES(vram_info)); 1503 1504 if (info_v25 == NULL) 1505 return BP_RESULT_BADBIOSTABLE; 1506 1507 info->num_chans = info_v25->vram_module[0].channel_num; 1508 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1509 1510 return result; 1511 } 1512 1513 /* 1514 * get_integrated_info_v11 1515 * 1516 * @brief 1517 * Get V8 integrated BIOS information 1518 * 1519 * @param 1520 * bios_parser *bp - [in]BIOS parser handler to get master data table 1521 * integrated_info *info - [out] store and output integrated info 1522 * 1523 * @return 1524 * enum bp_result - BP_RESULT_OK if information is available, 1525 * BP_RESULT_BADBIOSTABLE otherwise. 1526 */ 1527 static enum bp_result get_integrated_info_v11( 1528 struct bios_parser *bp, 1529 struct integrated_info *info) 1530 { 1531 struct atom_integrated_system_info_v1_11 *info_v11; 1532 uint32_t i; 1533 1534 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1535 DATA_TABLES(integratedsysteminfo)); 1536 1537 if (info_v11 == NULL) 1538 return BP_RESULT_BADBIOSTABLE; 1539 1540 info->gpu_cap_info = 1541 le32_to_cpu(info_v11->gpucapinfo); 1542 /* 1543 * system_config: Bit[0] = 0 : PCIE power gating disabled 1544 * = 1 : PCIE power gating enabled 1545 * Bit[1] = 0 : DDR-PLL shut down disabled 1546 * = 1 : DDR-PLL shut down enabled 1547 * Bit[2] = 0 : DDR-PLL power down disabled 1548 * = 1 : DDR-PLL power down enabled 1549 */ 1550 info->system_config = le32_to_cpu(info_v11->system_config); 1551 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1552 info->memory_type = info_v11->memorytype; 1553 info->ma_channel_number = info_v11->umachannelnumber; 1554 info->lvds_ss_percentage = 1555 le16_to_cpu(info_v11->lvds_ss_percentage); 1556 info->dp_ss_control = 1557 le16_to_cpu(info_v11->reserved1); 1558 info->lvds_sspread_rate_in_10hz = 1559 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1560 info->hdmi_ss_percentage = 1561 le16_to_cpu(info_v11->hdmi_ss_percentage); 1562 info->hdmi_sspread_rate_in_10hz = 1563 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1564 info->dvi_ss_percentage = 1565 le16_to_cpu(info_v11->dvi_ss_percentage); 1566 info->dvi_sspread_rate_in_10_hz = 1567 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1568 info->lvds_misc = info_v11->lvds_misc; 1569 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1570 info->ext_disp_conn_info.gu_id[i] = 1571 info_v11->extdispconninfo.guid[i]; 1572 } 1573 1574 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1575 info->ext_disp_conn_info.path[i].device_connector_id = 1576 object_id_from_bios_object_id( 1577 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1578 1579 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1580 object_id_from_bios_object_id( 1581 le16_to_cpu( 1582 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1583 1584 info->ext_disp_conn_info.path[i].device_tag = 1585 le16_to_cpu( 1586 info_v11->extdispconninfo.path[i].device_tag); 1587 info->ext_disp_conn_info.path[i].device_acpi_enum = 1588 le16_to_cpu( 1589 info_v11->extdispconninfo.path[i].device_acpi_enum); 1590 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1591 info_v11->extdispconninfo.path[i].auxddclut_index; 1592 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1593 info_v11->extdispconninfo.path[i].hpdlut_index; 1594 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1595 info_v11->extdispconninfo.path[i].channelmapping; 1596 info->ext_disp_conn_info.path[i].caps = 1597 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1598 } 1599 info->ext_disp_conn_info.checksum = 1600 info_v11->extdispconninfo.checksum; 1601 1602 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1603 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1604 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1605 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1606 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1607 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1608 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1609 } 1610 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1611 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1612 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1613 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1614 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1615 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1616 } 1617 1618 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1619 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1620 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1621 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1622 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1623 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1624 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1625 } 1626 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1627 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1628 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1629 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1630 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1631 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1632 } 1633 1634 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1635 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1636 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1637 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1638 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1639 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1640 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1641 } 1642 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1643 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1644 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1645 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1646 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1647 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1648 } 1649 1650 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1651 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1652 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1653 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1654 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1655 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1656 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1657 } 1658 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1659 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1660 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1661 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1662 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1663 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1664 } 1665 1666 1667 /** TODO - review **/ 1668 #if 0 1669 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1670 * 10; 1671 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1672 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1673 1674 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1675 /* Convert [10KHz] into [KHz] */ 1676 info->disp_clk_voltage[i].max_supported_clk = 1677 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1678 ulMaximumSupportedCLK) * 10; 1679 info->disp_clk_voltage[i].voltage_index = 1680 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1681 } 1682 1683 info->boot_up_req_display_vector = 1684 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1685 info->boot_up_nb_voltage = 1686 le16_to_cpu(info_v11->usBootUpNBVoltage); 1687 info->ext_disp_conn_info_offset = 1688 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1689 info->gmc_restore_reset_time = 1690 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1691 info->minimum_n_clk = 1692 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1693 for (i = 1; i < 4; ++i) 1694 info->minimum_n_clk = 1695 info->minimum_n_clk < 1696 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1697 info->minimum_n_clk : le32_to_cpu( 1698 info_v11->ulNbpStateNClkFreq[i]); 1699 1700 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1701 info->ddr_dll_power_up_time = 1702 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1703 info->ddr_pll_power_up_time = 1704 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1705 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1706 info->max_lvds_pclk_freq_in_single_link = 1707 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1708 info->max_lvds_pclk_freq_in_single_link = 1709 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1710 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1711 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1712 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1713 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1714 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1715 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1716 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1717 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1718 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1719 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1720 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1721 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1722 info->lvds_off_to_on_delay_in_4ms = 1723 info_v11->ucLVDSOffToOnDelay_in4Ms; 1724 info->lvds_bit_depth_control_val = 1725 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1726 1727 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1728 /* Convert [10KHz] into [KHz] */ 1729 info->avail_s_clk[i].supported_s_clk = 1730 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1731 * 10; 1732 info->avail_s_clk[i].voltage_index = 1733 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1734 info->avail_s_clk[i].voltage_id = 1735 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1736 } 1737 #endif /* TODO*/ 1738 1739 return BP_RESULT_OK; 1740 } 1741 1742 static enum bp_result get_integrated_info_v2_1( 1743 struct bios_parser *bp, 1744 struct integrated_info *info) 1745 { 1746 struct atom_integrated_system_info_v2_1 *info_v2_1; 1747 uint32_t i; 1748 1749 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 1750 DATA_TABLES(integratedsysteminfo)); 1751 1752 if (info_v2_1 == NULL) 1753 return BP_RESULT_BADBIOSTABLE; 1754 1755 info->gpu_cap_info = 1756 le32_to_cpu(info_v2_1->gpucapinfo); 1757 /* 1758 * system_config: Bit[0] = 0 : PCIE power gating disabled 1759 * = 1 : PCIE power gating enabled 1760 * Bit[1] = 0 : DDR-PLL shut down disabled 1761 * = 1 : DDR-PLL shut down enabled 1762 * Bit[2] = 0 : DDR-PLL power down disabled 1763 * = 1 : DDR-PLL power down enabled 1764 */ 1765 info->system_config = le32_to_cpu(info_v2_1->system_config); 1766 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 1767 info->memory_type = info_v2_1->memorytype; 1768 info->ma_channel_number = info_v2_1->umachannelnumber; 1769 info->dp_ss_control = 1770 le16_to_cpu(info_v2_1->reserved1); 1771 1772 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1773 info->ext_disp_conn_info.gu_id[i] = 1774 info_v2_1->extdispconninfo.guid[i]; 1775 } 1776 1777 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1778 info->ext_disp_conn_info.path[i].device_connector_id = 1779 object_id_from_bios_object_id( 1780 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 1781 1782 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1783 object_id_from_bios_object_id( 1784 le16_to_cpu( 1785 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 1786 1787 info->ext_disp_conn_info.path[i].device_tag = 1788 le16_to_cpu( 1789 info_v2_1->extdispconninfo.path[i].device_tag); 1790 info->ext_disp_conn_info.path[i].device_acpi_enum = 1791 le16_to_cpu( 1792 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 1793 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1794 info_v2_1->extdispconninfo.path[i].auxddclut_index; 1795 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1796 info_v2_1->extdispconninfo.path[i].hpdlut_index; 1797 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1798 info_v2_1->extdispconninfo.path[i].channelmapping; 1799 info->ext_disp_conn_info.path[i].caps = 1800 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 1801 } 1802 1803 info->ext_disp_conn_info.checksum = 1804 info_v2_1->extdispconninfo.checksum; 1805 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 1806 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 1807 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1808 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1809 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1810 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1811 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1812 } 1813 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 1814 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1815 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1816 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1817 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1818 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1819 } 1820 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 1821 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 1822 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1823 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1824 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1825 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1826 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1827 } 1828 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 1829 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1830 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1831 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1832 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1833 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1834 } 1835 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 1836 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 1837 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1838 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1839 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1840 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1841 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1842 } 1843 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 1844 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1845 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1846 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1847 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1848 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1849 } 1850 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 1851 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 1852 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1853 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1854 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1855 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1856 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1857 } 1858 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 1859 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1860 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1861 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1862 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1863 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1864 } 1865 1866 info->edp1_info.edp_backlight_pwm_hz = 1867 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 1868 info->edp1_info.edp_ss_percentage = 1869 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 1870 info->edp1_info.edp_ss_rate_10hz = 1871 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 1872 info->edp1_info.edp_pwr_on_off_delay = 1873 info_v2_1->edp1_info.edp_pwr_on_off_delay; 1874 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 1875 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 1876 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 1877 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 1878 info->edp1_info.edp_panel_bpc = 1879 info_v2_1->edp1_info.edp_panel_bpc; 1880 info->edp1_info.edp_bootup_bl_level = 1881 1882 info->edp2_info.edp_backlight_pwm_hz = 1883 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 1884 info->edp2_info.edp_ss_percentage = 1885 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 1886 info->edp2_info.edp_ss_rate_10hz = 1887 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 1888 info->edp2_info.edp_pwr_on_off_delay = 1889 info_v2_1->edp2_info.edp_pwr_on_off_delay; 1890 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 1891 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 1892 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 1893 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 1894 info->edp2_info.edp_panel_bpc = 1895 info_v2_1->edp2_info.edp_panel_bpc; 1896 info->edp2_info.edp_bootup_bl_level = 1897 info_v2_1->edp2_info.edp_bootup_bl_level; 1898 1899 return BP_RESULT_OK; 1900 } 1901 1902 /* 1903 * construct_integrated_info 1904 * 1905 * @brief 1906 * Get integrated BIOS information based on table revision 1907 * 1908 * @param 1909 * bios_parser *bp - [in]BIOS parser handler to get master data table 1910 * integrated_info *info - [out] store and output integrated info 1911 * 1912 * @return 1913 * enum bp_result - BP_RESULT_OK if information is available, 1914 * BP_RESULT_BADBIOSTABLE otherwise. 1915 */ 1916 static enum bp_result construct_integrated_info( 1917 struct bios_parser *bp, 1918 struct integrated_info *info) 1919 { 1920 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1921 1922 struct atom_common_table_header *header; 1923 struct atom_data_revision revision; 1924 uint32_t i; 1925 uint32_t j; 1926 1927 if (info && DATA_TABLES(integratedsysteminfo)) { 1928 header = GET_IMAGE(struct atom_common_table_header, 1929 DATA_TABLES(integratedsysteminfo)); 1930 1931 get_atom_data_table_revision(header, &revision); 1932 1933 switch (revision.major) { 1934 case 1: 1935 switch (revision.minor) { 1936 case 11: 1937 case 12: 1938 result = get_integrated_info_v11(bp, info); 1939 break; 1940 default: 1941 return result; 1942 } 1943 break; 1944 case 2: 1945 switch (revision.minor) { 1946 case 1: 1947 result = get_integrated_info_v2_1(bp, info); 1948 break; 1949 default: 1950 return result; 1951 } 1952 break; 1953 default: 1954 return result; 1955 } 1956 } 1957 1958 if (result != BP_RESULT_OK) 1959 return result; 1960 1961 /* Sort voltage table from low to high*/ 1962 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1963 for (j = i; j > 0; --j) { 1964 if (info->disp_clk_voltage[j].max_supported_clk < 1965 info->disp_clk_voltage[j-1].max_supported_clk 1966 ) { 1967 /* swap j and j - 1*/ 1968 swap(info->disp_clk_voltage[j - 1], 1969 info->disp_clk_voltage[j]); 1970 } 1971 } 1972 } 1973 1974 return result; 1975 } 1976 1977 static enum bp_result bios_parser_get_vram_info( 1978 struct dc_bios *dcb, 1979 struct dc_vram_info *info) 1980 { 1981 struct bios_parser *bp = BP_FROM_DCB(dcb); 1982 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1983 struct atom_common_table_header *header; 1984 struct atom_data_revision revision; 1985 1986 if (info && DATA_TABLES(vram_info)) { 1987 header = GET_IMAGE(struct atom_common_table_header, 1988 DATA_TABLES(vram_info)); 1989 1990 get_atom_data_table_revision(header, &revision); 1991 1992 switch (revision.major) { 1993 case 2: 1994 switch (revision.minor) { 1995 case 3: 1996 result = get_vram_info_v23(bp, info); 1997 break; 1998 case 4: 1999 result = get_vram_info_v24(bp, info); 2000 break; 2001 case 5: 2002 result = get_vram_info_v25(bp, info); 2003 break; 2004 default: 2005 break; 2006 } 2007 break; 2008 2009 default: 2010 return result; 2011 } 2012 2013 } 2014 return result; 2015 } 2016 2017 static struct integrated_info *bios_parser_create_integrated_info( 2018 struct dc_bios *dcb) 2019 { 2020 struct bios_parser *bp = BP_FROM_DCB(dcb); 2021 struct integrated_info *info = NULL; 2022 2023 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2024 2025 if (info == NULL) { 2026 ASSERT_CRITICAL(0); 2027 return NULL; 2028 } 2029 2030 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2031 return info; 2032 2033 kfree(info); 2034 2035 return NULL; 2036 } 2037 2038 static enum bp_result update_slot_layout_info( 2039 struct dc_bios *dcb, 2040 unsigned int i, 2041 struct slot_layout_info *slot_layout_info) 2042 { 2043 unsigned int record_offset; 2044 unsigned int j; 2045 struct atom_display_object_path_v2 *object; 2046 struct atom_bracket_layout_record *record; 2047 struct atom_common_record_header *record_header; 2048 enum bp_result result; 2049 struct bios_parser *bp; 2050 struct object_info_table *tbl; 2051 struct display_object_info_table_v1_4 *v1_4; 2052 2053 record = NULL; 2054 record_header = NULL; 2055 result = BP_RESULT_NORECORD; 2056 2057 bp = BP_FROM_DCB(dcb); 2058 tbl = &bp->object_info_tbl; 2059 v1_4 = tbl->v1_4; 2060 2061 object = &v1_4->display_path[i]; 2062 record_offset = (unsigned int) 2063 (object->disp_recordoffset) + 2064 (unsigned int)(bp->object_info_tbl_offset); 2065 2066 for (;;) { 2067 2068 record_header = (struct atom_common_record_header *) 2069 GET_IMAGE(struct atom_common_record_header, 2070 record_offset); 2071 if (record_header == NULL) { 2072 result = BP_RESULT_BADBIOSTABLE; 2073 break; 2074 } 2075 2076 /* the end of the list */ 2077 if (record_header->record_type == 0xff || 2078 record_header->record_size == 0) { 2079 break; 2080 } 2081 2082 if (record_header->record_type == 2083 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2084 sizeof(struct atom_bracket_layout_record) 2085 <= record_header->record_size) { 2086 record = (struct atom_bracket_layout_record *) 2087 (record_header); 2088 result = BP_RESULT_OK; 2089 break; 2090 } 2091 2092 record_offset += record_header->record_size; 2093 } 2094 2095 /* return if the record not found */ 2096 if (result != BP_RESULT_OK) 2097 return result; 2098 2099 /* get slot sizes */ 2100 slot_layout_info->length = record->bracketlen; 2101 slot_layout_info->width = record->bracketwidth; 2102 2103 /* get info for each connector in the slot */ 2104 slot_layout_info->num_of_connectors = record->conn_num; 2105 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2106 slot_layout_info->connectors[j].connector_type = 2107 (enum connector_layout_type) 2108 (record->conn_info[j].connector_type); 2109 switch (record->conn_info[j].connector_type) { 2110 case CONNECTOR_TYPE_DVI_D: 2111 slot_layout_info->connectors[j].connector_type = 2112 CONNECTOR_LAYOUT_TYPE_DVI_D; 2113 slot_layout_info->connectors[j].length = 2114 CONNECTOR_SIZE_DVI; 2115 break; 2116 2117 case CONNECTOR_TYPE_HDMI: 2118 slot_layout_info->connectors[j].connector_type = 2119 CONNECTOR_LAYOUT_TYPE_HDMI; 2120 slot_layout_info->connectors[j].length = 2121 CONNECTOR_SIZE_HDMI; 2122 break; 2123 2124 case CONNECTOR_TYPE_DISPLAY_PORT: 2125 slot_layout_info->connectors[j].connector_type = 2126 CONNECTOR_LAYOUT_TYPE_DP; 2127 slot_layout_info->connectors[j].length = 2128 CONNECTOR_SIZE_DP; 2129 break; 2130 2131 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2132 slot_layout_info->connectors[j].connector_type = 2133 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2134 slot_layout_info->connectors[j].length = 2135 CONNECTOR_SIZE_MINI_DP; 2136 break; 2137 2138 default: 2139 slot_layout_info->connectors[j].connector_type = 2140 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2141 slot_layout_info->connectors[j].length = 2142 CONNECTOR_SIZE_UNKNOWN; 2143 } 2144 2145 slot_layout_info->connectors[j].position = 2146 record->conn_info[j].position; 2147 slot_layout_info->connectors[j].connector_id = 2148 object_id_from_bios_object_id( 2149 record->conn_info[j].connectorobjid); 2150 } 2151 return result; 2152 } 2153 2154 2155 static enum bp_result get_bracket_layout_record( 2156 struct dc_bios *dcb, 2157 unsigned int bracket_layout_id, 2158 struct slot_layout_info *slot_layout_info) 2159 { 2160 unsigned int i; 2161 struct bios_parser *bp = BP_FROM_DCB(dcb); 2162 enum bp_result result; 2163 struct object_info_table *tbl; 2164 struct display_object_info_table_v1_4 *v1_4; 2165 2166 if (slot_layout_info == NULL) { 2167 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2168 return BP_RESULT_BADINPUT; 2169 } 2170 tbl = &bp->object_info_tbl; 2171 v1_4 = tbl->v1_4; 2172 2173 result = BP_RESULT_NORECORD; 2174 for (i = 0; i < v1_4->number_of_path; ++i) { 2175 2176 if (bracket_layout_id == 2177 v1_4->display_path[i].display_objid) { 2178 result = update_slot_layout_info(dcb, i, 2179 slot_layout_info); 2180 break; 2181 } 2182 } 2183 return result; 2184 } 2185 2186 static enum bp_result bios_get_board_layout_info( 2187 struct dc_bios *dcb, 2188 struct board_layout_info *board_layout_info) 2189 { 2190 unsigned int i; 2191 enum bp_result record_result; 2192 2193 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2194 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2195 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2196 0, 0 2197 }; 2198 2199 if (board_layout_info == NULL) { 2200 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2201 return BP_RESULT_BADINPUT; 2202 } 2203 2204 board_layout_info->num_of_slots = 0; 2205 2206 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2207 record_result = get_bracket_layout_record(dcb, 2208 slot_index_to_vbios_id[i], 2209 &board_layout_info->slots[i]); 2210 2211 if (record_result == BP_RESULT_NORECORD && i > 0) 2212 break; /* no more slots present in bios */ 2213 else if (record_result != BP_RESULT_OK) 2214 return record_result; /* fail */ 2215 2216 ++board_layout_info->num_of_slots; 2217 } 2218 2219 /* all data is valid */ 2220 board_layout_info->is_number_of_slots_valid = 1; 2221 board_layout_info->is_slots_size_valid = 1; 2222 board_layout_info->is_connector_offsets_valid = 1; 2223 board_layout_info->is_connector_lengths_valid = 1; 2224 2225 return BP_RESULT_OK; 2226 } 2227 2228 2229 static uint16_t bios_parser_pack_data_tables( 2230 struct dc_bios *dcb, 2231 void *dst) 2232 { 2233 #ifdef PACK_BIOS_DATA 2234 struct bios_parser *bp = BP_FROM_DCB(dcb); 2235 struct atom_rom_header_v2_2 *rom_header = NULL; 2236 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2237 struct atom_common_table_header *data_tbl_header = NULL; 2238 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2239 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2240 struct atom_data_revision tbl_rev = {0}; 2241 uint16_t *rom_header_offset = NULL; 2242 const uint8_t *bios = bp->base.bios; 2243 uint8_t *bios_dst = (uint8_t *)dst; 2244 uint16_t packed_rom_header_offset; 2245 uint16_t packed_masterdatatable_offset; 2246 uint16_t packed_data_tbl_offset; 2247 uint16_t data_tbl_offset; 2248 unsigned int i; 2249 2250 rom_header_offset = 2251 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2252 2253 if (!rom_header_offset) 2254 return 0; 2255 2256 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2257 2258 if (!rom_header) 2259 return 0; 2260 2261 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2262 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2263 return 0; 2264 2265 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2266 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2267 return 0; 2268 2269 packed_rom_header_offset = 2270 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2271 2272 packed_masterdatatable_offset = 2273 packed_rom_header_offset + rom_header->table_header.structuresize; 2274 2275 packed_data_tbl_offset = 2276 packed_masterdatatable_offset + 2277 bp->master_data_tbl->table_header.structuresize; 2278 2279 packed_rom_header = 2280 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2281 2282 packed_master_data_tbl = 2283 (struct atom_master_data_table_v2_1 *)(bios_dst + 2284 packed_masterdatatable_offset); 2285 2286 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2287 2288 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2289 packed_rom_header_offset; 2290 2291 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2292 rom_header->table_header.structuresize); 2293 2294 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2295 2296 memcpy(&packed_master_data_tbl->table_header, 2297 &bp->master_data_tbl->table_header, 2298 sizeof(bp->master_data_tbl->table_header)); 2299 2300 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2301 2302 /* Each data table offset in data table list is 2 bytes, 2303 * we can use that to iterate through listOfdatatables 2304 * without knowing the name of each member. 2305 */ 2306 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2307 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2308 2309 if (data_tbl_offset) { 2310 data_tbl_header = 2311 (struct atom_common_table_header *)(bios + data_tbl_offset); 2312 2313 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2314 data_tbl_header->structuresize); 2315 2316 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2317 packed_data_tbl_offset; 2318 2319 packed_data_tbl_offset += data_tbl_header->structuresize; 2320 } else { 2321 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2322 } 2323 } 2324 return packed_data_tbl_offset; 2325 #endif 2326 // TODO: There is data bytes alignment issue, disable it for now. 2327 return 0; 2328 } 2329 2330 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2331 struct bios_parser *bp, 2332 uint32_t rev_major, 2333 uint32_t rev_minor, 2334 uint16_t *dc_golden_table_ver) 2335 { 2336 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2337 uint32_t dc_golden_offset = 0; 2338 *dc_golden_table_ver = 0; 2339 2340 if (!DATA_TABLES(dce_info)) 2341 return NULL; 2342 2343 /* ver.4.4 or higher */ 2344 switch (rev_major) { 2345 case 4: 2346 switch (rev_minor) { 2347 case 4: 2348 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2349 DATA_TABLES(dce_info)); 2350 if (!disp_cntl_tbl_4_4) 2351 return NULL; 2352 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2353 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2354 break; 2355 } 2356 break; 2357 } 2358 2359 if (!dc_golden_offset) 2360 return NULL; 2361 2362 if (*dc_golden_table_ver != 1) 2363 return NULL; 2364 2365 return GET_IMAGE(struct atom_dc_golden_table_v1, 2366 dc_golden_offset); 2367 } 2368 2369 static enum bp_result bios_get_atom_dc_golden_table( 2370 struct dc_bios *dcb) 2371 { 2372 struct bios_parser *bp = BP_FROM_DCB(dcb); 2373 enum bp_result result = BP_RESULT_OK; 2374 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2375 struct atom_common_table_header *header; 2376 struct atom_data_revision tbl_revision; 2377 uint16_t dc_golden_table_ver = 0; 2378 2379 header = GET_IMAGE(struct atom_common_table_header, 2380 DATA_TABLES(dce_info)); 2381 if (!header) 2382 return BP_RESULT_UNSUPPORTED; 2383 2384 get_atom_data_table_revision(header, &tbl_revision); 2385 2386 atom_dc_golden_table = bios_get_golden_table(bp, 2387 tbl_revision.major, 2388 tbl_revision.minor, 2389 &dc_golden_table_ver); 2390 2391 if (!atom_dc_golden_table) 2392 return BP_RESULT_UNSUPPORTED; 2393 2394 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2395 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2396 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2397 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2398 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2399 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2400 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2401 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2402 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2403 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2404 2405 return result; 2406 } 2407 2408 2409 static const struct dc_vbios_funcs vbios_funcs = { 2410 .get_connectors_number = bios_parser_get_connectors_number, 2411 2412 .get_connector_id = bios_parser_get_connector_id, 2413 2414 .get_src_obj = bios_parser_get_src_obj, 2415 2416 .get_i2c_info = bios_parser_get_i2c_info, 2417 2418 .get_hpd_info = bios_parser_get_hpd_info, 2419 2420 .get_device_tag = bios_parser_get_device_tag, 2421 2422 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2423 2424 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2425 2426 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2427 2428 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2429 2430 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2431 2432 .is_device_id_supported = bios_parser_is_device_id_supported, 2433 2434 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2435 2436 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2437 2438 2439 /* COMMANDS */ 2440 .encoder_control = bios_parser_encoder_control, 2441 2442 .transmitter_control = bios_parser_transmitter_control, 2443 2444 .enable_crtc = bios_parser_enable_crtc, 2445 2446 .set_pixel_clock = bios_parser_set_pixel_clock, 2447 2448 .set_dce_clock = bios_parser_set_dce_clock, 2449 2450 .program_crtc_timing = bios_parser_program_crtc_timing, 2451 2452 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2453 2454 .bios_parser_destroy = firmware_parser_destroy, 2455 2456 .get_board_layout_info = bios_get_board_layout_info, 2457 .pack_data_tables = bios_parser_pack_data_tables, 2458 2459 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2460 2461 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2462 2463 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2464 }; 2465 2466 static bool bios_parser2_construct( 2467 struct bios_parser *bp, 2468 struct bp_init_data *init, 2469 enum dce_version dce_version) 2470 { 2471 uint16_t *rom_header_offset = NULL; 2472 struct atom_rom_header_v2_2 *rom_header = NULL; 2473 struct display_object_info_table_v1_4 *object_info_tbl; 2474 struct atom_data_revision tbl_rev = {0}; 2475 2476 if (!init) 2477 return false; 2478 2479 if (!init->bios) 2480 return false; 2481 2482 bp->base.funcs = &vbios_funcs; 2483 bp->base.bios = init->bios; 2484 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2485 2486 bp->base.ctx = init->ctx; 2487 2488 bp->base.bios_local_image = NULL; 2489 2490 rom_header_offset = 2491 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2492 2493 if (!rom_header_offset) 2494 return false; 2495 2496 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2497 2498 if (!rom_header) 2499 return false; 2500 2501 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2502 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2503 return false; 2504 2505 bp->master_data_tbl = 2506 GET_IMAGE(struct atom_master_data_table_v2_1, 2507 rom_header->masterdatatable_offset); 2508 2509 if (!bp->master_data_tbl) 2510 return false; 2511 2512 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2513 2514 if (!bp->object_info_tbl_offset) 2515 return false; 2516 2517 object_info_tbl = 2518 GET_IMAGE(struct display_object_info_table_v1_4, 2519 bp->object_info_tbl_offset); 2520 2521 if (!object_info_tbl) 2522 return false; 2523 2524 get_atom_data_table_revision(&object_info_tbl->table_header, 2525 &bp->object_info_tbl.revision); 2526 2527 if (bp->object_info_tbl.revision.major == 1 2528 && bp->object_info_tbl.revision.minor >= 4) { 2529 struct display_object_info_table_v1_4 *tbl_v1_4; 2530 2531 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2532 bp->object_info_tbl_offset); 2533 if (!tbl_v1_4) 2534 return false; 2535 2536 bp->object_info_tbl.v1_4 = tbl_v1_4; 2537 } else 2538 return false; 2539 2540 dal_firmware_parser_init_cmd_tbl(bp); 2541 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2542 2543 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2544 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2545 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2546 2547 return true; 2548 } 2549 2550 struct dc_bios *firmware_parser_create( 2551 struct bp_init_data *init, 2552 enum dce_version dce_version) 2553 { 2554 struct bios_parser *bp = NULL; 2555 2556 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2557 if (!bp) 2558 return NULL; 2559 2560 if (bios_parser2_construct(bp, init, dce_version)) 2561 return &bp->base; 2562 2563 kfree(bp); 2564 return NULL; 2565 } 2566 2567 2568