1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 29 #include "ObjectID.h" 30 #include "atomfirmware.h" 31 32 #include "dc_bios_types.h" 33 #include "include/grph_object_ctrl_defs.h" 34 #include "include/bios_parser_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 #define DC_LOGGER \ 48 bp->base.ctx->logger 49 50 #define LAST_RECORD_TYPE 0xff 51 #define SMU9_SYSPLL0_ID 0 52 53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 54 struct atom_i2c_record *record, 55 struct graphics_object_i2c_info *info); 56 57 static enum bp_result bios_parser_get_firmware_info( 58 struct dc_bios *dcb, 59 struct dc_firmware_info *info); 60 61 static enum bp_result bios_parser_get_encoder_cap_info( 62 struct dc_bios *dcb, 63 struct graphics_object_id object_id, 64 struct bp_encoder_cap_info *info); 65 66 static enum bp_result get_firmware_info_v3_1( 67 struct bios_parser *bp, 68 struct dc_firmware_info *info); 69 70 static enum bp_result get_firmware_info_v3_2( 71 struct bios_parser *bp, 72 struct dc_firmware_info *info); 73 74 static enum bp_result get_firmware_info_v3_4( 75 struct bios_parser *bp, 76 struct dc_firmware_info *info); 77 78 static enum bp_result get_firmware_info_v3_5( 79 struct bios_parser *bp, 80 struct dc_firmware_info *info); 81 82 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 83 struct atom_display_object_path_v2 *object); 84 85 static struct atom_encoder_caps_record *get_encoder_cap_record( 86 struct bios_parser *bp, 87 struct atom_display_object_path_v2 *object); 88 89 #define BIOS_IMAGE_SIZE_OFFSET 2 90 #define BIOS_IMAGE_SIZE_UNIT 512 91 92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 93 94 static void bios_parser2_destruct(struct bios_parser *bp) 95 { 96 kfree(bp->base.bios_local_image); 97 kfree(bp->base.integrated_info); 98 } 99 100 static void firmware_parser_destroy(struct dc_bios **dcb) 101 { 102 struct bios_parser *bp = BP_FROM_DCB(*dcb); 103 104 if (!bp) { 105 BREAK_TO_DEBUGGER(); 106 return; 107 } 108 109 bios_parser2_destruct(bp); 110 111 kfree(bp); 112 *dcb = NULL; 113 } 114 115 static void get_atom_data_table_revision( 116 struct atom_common_table_header *atom_data_tbl, 117 struct atom_data_revision *tbl_revision) 118 { 119 if (!tbl_revision) 120 return; 121 122 /* initialize the revision to 0 which is invalid revision */ 123 tbl_revision->major = 0; 124 tbl_revision->minor = 0; 125 126 if (!atom_data_tbl) 127 return; 128 129 tbl_revision->major = 130 (uint32_t) atom_data_tbl->format_revision & 0x3f; 131 tbl_revision->minor = 132 (uint32_t) atom_data_tbl->content_revision & 0x3f; 133 } 134 135 /* BIOS oject table displaypath is per connector. 136 * There is extra path not for connector. BIOS fill its encoderid as 0 137 */ 138 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 139 { 140 struct bios_parser *bp = BP_FROM_DCB(dcb); 141 unsigned int count = 0; 142 unsigned int i; 143 144 switch (bp->object_info_tbl.revision.minor) { 145 default: 146 case 4: 147 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 148 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 149 count++; 150 151 break; 152 153 case 5: 154 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 155 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 156 count++; 157 158 break; 159 } 160 return (uint8_t)count; 161 } 162 163 static struct graphics_object_id bios_parser_get_connector_id( 164 struct dc_bios *dcb, 165 uint8_t i) 166 { 167 struct bios_parser *bp = BP_FROM_DCB(dcb); 168 struct graphics_object_id object_id = dal_graphics_object_id_init( 169 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 170 struct object_info_table *tbl = &bp->object_info_tbl; 171 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 172 173 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 174 175 switch (bp->object_info_tbl.revision.minor) { 176 default: 177 case 4: 178 if (v1_4->number_of_path > i) { 179 /* If display_objid is generic object id, the encoderObj 180 * /extencoderobjId should be 0 181 */ 182 if (v1_4->display_path[i].encoderobjid != 0 && 183 v1_4->display_path[i].display_objid != 0) 184 object_id = object_id_from_bios_object_id( 185 v1_4->display_path[i].display_objid); 186 } 187 break; 188 189 case 5: 190 if (v1_5->number_of_path > i) { 191 /* If display_objid is generic object id, the encoderObjId 192 * should be 0 193 */ 194 if (v1_5->display_path[i].encoderobjid != 0 && 195 v1_5->display_path[i].display_objid != 0) 196 object_id = object_id_from_bios_object_id( 197 v1_5->display_path[i].display_objid); 198 } 199 break; 200 } 201 return object_id; 202 } 203 204 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 205 struct graphics_object_id object_id, uint32_t index, 206 struct graphics_object_id *src_object_id) 207 { 208 (void)index; 209 struct bios_parser *bp = BP_FROM_DCB(dcb); 210 unsigned int i; 211 enum bp_result bp_result = BP_RESULT_BADINPUT; 212 struct graphics_object_id obj_id = { 0 }; 213 struct object_info_table *tbl = &bp->object_info_tbl; 214 215 if (!src_object_id) 216 return bp_result; 217 218 switch (object_id.type) { 219 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 220 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 221 */ 222 case OBJECT_TYPE_ENCODER: 223 /* TODO: since num of src must be less than 2. 224 * If found in for loop, should break. 225 * DAL2 implementation may be changed too 226 */ 227 switch (bp->object_info_tbl.revision.minor) { 228 default: 229 case 4: 230 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 231 obj_id = object_id_from_bios_object_id( 232 tbl->v1_4->display_path[i].encoderobjid); 233 if (object_id.type == obj_id.type && 234 object_id.id == obj_id.id && 235 object_id.enum_id == obj_id.enum_id) { 236 *src_object_id = 237 object_id_from_bios_object_id( 238 0x1100); 239 /* break; */ 240 } 241 } 242 bp_result = BP_RESULT_OK; 243 break; 244 245 case 5: 246 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 247 obj_id = object_id_from_bios_object_id( 248 tbl->v1_5->display_path[i].encoderobjid); 249 if (object_id.type == obj_id.type && 250 object_id.id == obj_id.id && 251 object_id.enum_id == obj_id.enum_id) { 252 *src_object_id = 253 object_id_from_bios_object_id( 254 0x1100); 255 /* break; */ 256 } 257 } 258 bp_result = BP_RESULT_OK; 259 break; 260 } 261 break; 262 case OBJECT_TYPE_CONNECTOR: 263 switch (bp->object_info_tbl.revision.minor) { 264 default: 265 case 4: 266 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 267 obj_id = object_id_from_bios_object_id( 268 tbl->v1_4->display_path[i] 269 .display_objid); 270 271 if (object_id.type == obj_id.type && 272 object_id.id == obj_id.id && 273 object_id.enum_id == obj_id.enum_id) { 274 *src_object_id = 275 object_id_from_bios_object_id( 276 tbl->v1_4 277 ->display_path[i] 278 .encoderobjid); 279 /* break; */ 280 } 281 } 282 bp_result = BP_RESULT_OK; 283 break; 284 } 285 bp_result = BP_RESULT_OK; 286 break; 287 case 5: 288 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 289 obj_id = object_id_from_bios_object_id( 290 tbl->v1_5->display_path[i].display_objid); 291 292 if (object_id.type == obj_id.type && 293 object_id.id == obj_id.id && 294 object_id.enum_id == obj_id.enum_id) { 295 *src_object_id = object_id_from_bios_object_id( 296 tbl->v1_5->display_path[i].encoderobjid); 297 /* break; */ 298 } 299 } 300 bp_result = BP_RESULT_OK; 301 break; 302 303 default: 304 bp_result = BP_RESULT_OK; 305 break; 306 } 307 308 return bp_result; 309 } 310 311 /* from graphics_object_id, find display path which includes the object_id */ 312 static struct atom_display_object_path_v2 *get_bios_object( 313 struct bios_parser *bp, 314 struct graphics_object_id id) 315 { 316 unsigned int i; 317 struct graphics_object_id obj_id = {0}; 318 319 switch (id.type) { 320 case OBJECT_TYPE_ENCODER: 321 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 322 obj_id = object_id_from_bios_object_id( 323 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 324 if (id.type == obj_id.type && id.id == obj_id.id 325 && id.enum_id == obj_id.enum_id) 326 return &bp->object_info_tbl.v1_4->display_path[i]; 327 } 328 fallthrough; 329 case OBJECT_TYPE_CONNECTOR: 330 case OBJECT_TYPE_GENERIC: 331 /* Both Generic and Connector Object ID 332 * will be stored on display_objid 333 */ 334 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 335 obj_id = object_id_from_bios_object_id( 336 bp->object_info_tbl.v1_4->display_path[i].display_objid); 337 if (id.type == obj_id.type && id.id == obj_id.id 338 && id.enum_id == obj_id.enum_id) 339 return &bp->object_info_tbl.v1_4->display_path[i]; 340 } 341 fallthrough; 342 default: 343 return NULL; 344 } 345 } 346 347 /* from graphics_object_id, find display path which includes the object_id */ 348 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp, 349 struct graphics_object_id id) 350 { 351 unsigned int i; 352 struct graphics_object_id obj_id = {0}; 353 354 switch (id.type) { 355 case OBJECT_TYPE_ENCODER: 356 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 357 obj_id = object_id_from_bios_object_id( 358 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 359 if (id.type == obj_id.type && id.id == obj_id.id 360 && id.enum_id == obj_id.enum_id) 361 return &bp->object_info_tbl.v1_5->display_path[i]; 362 } 363 break; 364 365 case OBJECT_TYPE_CONNECTOR: 366 case OBJECT_TYPE_GENERIC: 367 /* Both Generic and Connector Object ID 368 * will be stored on display_objid 369 */ 370 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 371 obj_id = object_id_from_bios_object_id( 372 bp->object_info_tbl.v1_5->display_path[i].display_objid); 373 if (id.type == obj_id.type && id.id == obj_id.id 374 && id.enum_id == obj_id.enum_id) 375 return &bp->object_info_tbl.v1_5->display_path[i]; 376 } 377 break; 378 379 default: 380 return NULL; 381 } 382 383 return NULL; 384 } 385 386 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 387 struct graphics_object_id id, 388 struct graphics_object_i2c_info *info) 389 { 390 uint32_t offset; 391 struct atom_display_object_path_v2 *object; 392 393 struct atom_display_object_path_v3 *object_path_v3; 394 395 struct atom_common_record_header *header; 396 struct atom_i2c_record *record; 397 struct atom_i2c_record dummy_record = {0}; 398 struct bios_parser *bp = BP_FROM_DCB(dcb); 399 400 if (!info) 401 return BP_RESULT_BADINPUT; 402 403 if (id.type == OBJECT_TYPE_GENERIC) { 404 dummy_record.i2c_id = (uint8_t)id.id; 405 406 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 407 return BP_RESULT_OK; 408 else 409 return BP_RESULT_NORECORD; 410 } 411 412 switch (bp->object_info_tbl.revision.minor) { 413 case 4: 414 default: 415 object = get_bios_object(bp, id); 416 417 if (!object) 418 return BP_RESULT_BADINPUT; 419 420 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 421 break; 422 case 5: 423 object_path_v3 = get_bios_object_from_path_v3(bp, id); 424 425 if (!object_path_v3) 426 return BP_RESULT_BADINPUT; 427 428 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 429 break; 430 } 431 432 for (;;) { 433 header = GET_IMAGE(struct atom_common_record_header, offset); 434 435 if (!header) 436 return BP_RESULT_BADBIOSTABLE; 437 438 if (header->record_type == LAST_RECORD_TYPE || 439 !header->record_size) 440 break; 441 442 if (header->record_type == ATOM_I2C_RECORD_TYPE 443 && sizeof(struct atom_i2c_record) <= 444 header->record_size) { 445 /* get the I2C info */ 446 record = (struct atom_i2c_record *) header; 447 448 if (get_gpio_i2c_info(bp, record, info) == 449 BP_RESULT_OK) 450 return BP_RESULT_OK; 451 } 452 453 offset += header->record_size; 454 } 455 456 return BP_RESULT_NORECORD; 457 } 458 459 static enum bp_result get_gpio_i2c_info( 460 struct bios_parser *bp, 461 struct atom_i2c_record *record, 462 struct graphics_object_i2c_info *info) 463 { 464 struct atom_gpio_pin_lut_v2_1 *header; 465 uint32_t count = 0; 466 unsigned int table_index = 0; 467 bool find_valid = false; 468 struct atom_gpio_pin_assignment *pin; 469 470 if (!info) 471 return BP_RESULT_BADINPUT; 472 473 /* get the GPIO_I2C info */ 474 if (!DATA_TABLES(gpio_pin_lut)) 475 return BP_RESULT_BADBIOSTABLE; 476 477 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 478 DATA_TABLES(gpio_pin_lut)); 479 if (!header) 480 return BP_RESULT_BADBIOSTABLE; 481 482 if (sizeof(struct atom_common_table_header) + 483 sizeof(struct atom_gpio_pin_assignment) > 484 le16_to_cpu(header->table_header.structuresize)) 485 return BP_RESULT_BADBIOSTABLE; 486 487 /* TODO: is version change? */ 488 if (header->table_header.content_revision != 1) 489 return BP_RESULT_UNSUPPORTED; 490 491 /* get data count */ 492 count = (le16_to_cpu(header->table_header.structuresize) 493 - sizeof(struct atom_common_table_header)) 494 / sizeof(struct atom_gpio_pin_assignment); 495 496 if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut), 497 le16_to_cpu(header->table_header.structuresize))) 498 return BP_RESULT_BADBIOSTABLE; 499 500 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin; 501 502 for (table_index = 0; table_index < count; table_index++) { 503 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) && 504 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) && 505 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) { 506 /* still valid */ 507 find_valid = true; 508 break; 509 } 510 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment)); 511 } 512 513 /* If we don't find the entry that we are looking for then 514 * we will return BP_Result_BadBiosTable. 515 */ 516 if (find_valid == false) 517 return BP_RESULT_BADBIOSTABLE; 518 519 /* get the GPIO_I2C_INFO */ 520 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 521 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 522 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 523 info->i2c_slave_address = record->i2c_slave_addr; 524 525 /* TODO: check how to get register offset for en, Y, etc. */ 526 info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index); 527 info->gpio_info.clk_a_shift = pin->gpio_bitshift; 528 529 return BP_RESULT_OK; 530 } 531 532 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp, 533 struct atom_display_object_path_v3 *object) 534 { 535 struct atom_common_record_header *header; 536 uint32_t offset; 537 538 if (!object) { 539 BREAK_TO_DEBUGGER(); /* Invalid object */ 540 return NULL; 541 } 542 543 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 544 545 for (;;) { 546 header = GET_IMAGE(struct atom_common_record_header, offset); 547 548 if (!header) 549 return NULL; 550 551 if (header->record_type == ATOM_RECORD_END_TYPE || 552 !header->record_size) 553 break; 554 555 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 556 && sizeof(struct atom_hpd_int_record) <= 557 header->record_size) 558 return (struct atom_hpd_int_record *) header; 559 560 offset += header->record_size; 561 } 562 563 return NULL; 564 } 565 566 static enum bp_result bios_parser_get_hpd_info( 567 struct dc_bios *dcb, 568 struct graphics_object_id id, 569 struct graphics_object_hpd_info *info) 570 { 571 struct bios_parser *bp = BP_FROM_DCB(dcb); 572 struct atom_display_object_path_v2 *object; 573 struct atom_display_object_path_v3 *object_path_v3; 574 struct atom_hpd_int_record *record = NULL; 575 576 if (!info) 577 return BP_RESULT_BADINPUT; 578 579 switch (bp->object_info_tbl.revision.minor) { 580 case 4: 581 default: 582 object = get_bios_object(bp, id); 583 584 if (!object) 585 return BP_RESULT_BADINPUT; 586 587 record = get_hpd_record(bp, object); 588 break; 589 case 5: 590 object_path_v3 = get_bios_object_from_path_v3(bp, id); 591 592 if (!object_path_v3) 593 return BP_RESULT_BADINPUT; 594 595 record = get_hpd_record_for_path_v3(bp, object_path_v3); 596 break; 597 } 598 599 if (record != NULL) { 600 info->hpd_int_gpio_uid = record->pin_id; 601 info->hpd_active = record->plugin_pin_state; 602 return BP_RESULT_OK; 603 } 604 605 return BP_RESULT_NORECORD; 606 } 607 608 static struct atom_hpd_int_record *get_hpd_record( 609 struct bios_parser *bp, 610 struct atom_display_object_path_v2 *object) 611 { 612 struct atom_common_record_header *header; 613 uint32_t offset; 614 615 if (!object) { 616 BREAK_TO_DEBUGGER(); /* Invalid object */ 617 return NULL; 618 } 619 620 offset = le16_to_cpu(object->disp_recordoffset) 621 + bp->object_info_tbl_offset; 622 623 for (;;) { 624 header = GET_IMAGE(struct atom_common_record_header, offset); 625 626 if (!header) 627 return NULL; 628 629 if (header->record_type == LAST_RECORD_TYPE || 630 !header->record_size) 631 break; 632 633 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 634 && sizeof(struct atom_hpd_int_record) <= 635 header->record_size) 636 return (struct atom_hpd_int_record *) header; 637 638 offset += header->record_size; 639 } 640 641 return NULL; 642 } 643 644 /** 645 * bios_parser_get_gpio_pin_info 646 * Get GpioPin information of input gpio id 647 * 648 * @dcb: pointer to the DC BIOS 649 * @gpio_id: GPIO ID 650 * @info: GpioPin information structure 651 * return: Bios parser result code 652 * note: 653 * to get the GPIO PIN INFO, we need: 654 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 655 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 656 * to get the registerA offset/mask 657 */ 658 static enum bp_result bios_parser_get_gpio_pin_info( 659 struct dc_bios *dcb, 660 uint32_t gpio_id, 661 struct gpio_pin_info *info) 662 { 663 struct bios_parser *bp = BP_FROM_DCB(dcb); 664 struct atom_gpio_pin_lut_v2_1 *header; 665 uint32_t count = 0; 666 uint32_t i = 0; 667 668 if (!DATA_TABLES(gpio_pin_lut)) 669 return BP_RESULT_BADBIOSTABLE; 670 671 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 672 DATA_TABLES(gpio_pin_lut)); 673 if (!header) 674 return BP_RESULT_BADBIOSTABLE; 675 676 if (sizeof(struct atom_common_table_header) + 677 sizeof(struct atom_gpio_pin_assignment) 678 > le16_to_cpu(header->table_header.structuresize)) 679 return BP_RESULT_BADBIOSTABLE; 680 681 if (header->table_header.content_revision != 1) 682 return BP_RESULT_UNSUPPORTED; 683 684 /* Temporary hard code gpio pin info */ 685 count = (le16_to_cpu(header->table_header.structuresize) 686 - sizeof(struct atom_common_table_header)) 687 / sizeof(struct atom_gpio_pin_assignment); 688 689 if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut), 690 le16_to_cpu(header->table_header.structuresize))) 691 return BP_RESULT_BADBIOSTABLE; 692 693 for (i = 0; i < count; ++i) { 694 if (header->gpio_pin[i].gpio_id != gpio_id) 695 continue; 696 697 info->offset = 698 (uint32_t) le16_to_cpu( 699 header->gpio_pin[i].data_a_reg_index); 700 info->offset_y = info->offset + 2; 701 info->offset_en = info->offset + 1; 702 info->offset_mask = info->offset - 1; 703 704 if (header->gpio_pin[i].gpio_bitshift >= 32) 705 return BP_RESULT_BADBIOSTABLE; 706 707 info->mask = 1u << header->gpio_pin[i].gpio_bitshift; 708 info->mask_y = info->mask + 2; 709 info->mask_en = info->mask + 1; 710 info->mask_mask = info->mask - 1; 711 712 return BP_RESULT_OK; 713 } 714 715 return BP_RESULT_NORECORD; 716 } 717 718 static struct device_id device_type_from_device_id(uint16_t device_id) 719 { 720 721 struct device_id result_device_id; 722 723 result_device_id.raw_device_tag = device_id; 724 725 switch (device_id) { 726 case ATOM_DISPLAY_LCD1_SUPPORT: 727 result_device_id.device_type = DEVICE_TYPE_LCD; 728 result_device_id.enum_id = 1; 729 break; 730 731 case ATOM_DISPLAY_LCD2_SUPPORT: 732 result_device_id.device_type = DEVICE_TYPE_LCD; 733 result_device_id.enum_id = 2; 734 break; 735 736 case ATOM_DISPLAY_DFP1_SUPPORT: 737 result_device_id.device_type = DEVICE_TYPE_DFP; 738 result_device_id.enum_id = 1; 739 break; 740 741 case ATOM_DISPLAY_DFP2_SUPPORT: 742 result_device_id.device_type = DEVICE_TYPE_DFP; 743 result_device_id.enum_id = 2; 744 break; 745 746 case ATOM_DISPLAY_DFP3_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_DFP; 748 result_device_id.enum_id = 3; 749 break; 750 751 case ATOM_DISPLAY_DFP4_SUPPORT: 752 result_device_id.device_type = DEVICE_TYPE_DFP; 753 result_device_id.enum_id = 4; 754 break; 755 756 case ATOM_DISPLAY_DFP5_SUPPORT: 757 result_device_id.device_type = DEVICE_TYPE_DFP; 758 result_device_id.enum_id = 5; 759 break; 760 761 case ATOM_DISPLAY_DFP6_SUPPORT: 762 result_device_id.device_type = DEVICE_TYPE_DFP; 763 result_device_id.enum_id = 6; 764 break; 765 766 default: 767 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 768 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 769 result_device_id.enum_id = 0; 770 } 771 return result_device_id; 772 } 773 774 static enum bp_result bios_parser_get_device_tag( 775 struct dc_bios *dcb, 776 struct graphics_object_id connector_object_id, 777 uint32_t device_tag_index, 778 struct connector_device_tag_info *info) 779 { 780 (void)device_tag_index; 781 struct bios_parser *bp = BP_FROM_DCB(dcb); 782 struct atom_display_object_path_v2 *object; 783 784 struct atom_display_object_path_v3 *object_path_v3; 785 786 787 if (!info) 788 return BP_RESULT_BADINPUT; 789 790 switch (bp->object_info_tbl.revision.minor) { 791 case 4: 792 default: 793 /* getBiosObject will return MXM object */ 794 object = get_bios_object(bp, connector_object_id); 795 796 if (!object) { 797 BREAK_TO_DEBUGGER(); /* Invalid object id */ 798 return BP_RESULT_BADINPUT; 799 } 800 801 info->acpi_device = 0; /* BIOS no longer provides this */ 802 info->dev_id = device_type_from_device_id(object->device_tag); 803 break; 804 case 5: 805 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 806 807 if (!object_path_v3) { 808 BREAK_TO_DEBUGGER(); /* Invalid object id */ 809 return BP_RESULT_BADINPUT; 810 } 811 info->acpi_device = 0; /* BIOS no longer provides this */ 812 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 813 break; 814 } 815 816 return BP_RESULT_OK; 817 } 818 819 static enum bp_result get_ss_info_v4_1( 820 struct bios_parser *bp, 821 uint32_t id, 822 uint32_t index, 823 struct spread_spectrum_info *ss_info) 824 { 825 (void)index; 826 enum bp_result result = BP_RESULT_OK; 827 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 828 struct atom_smu_info_v3_3 *smu_info = NULL; 829 830 if (!ss_info) 831 return BP_RESULT_BADINPUT; 832 833 if (!DATA_TABLES(dce_info)) 834 return BP_RESULT_BADBIOSTABLE; 835 836 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 837 DATA_TABLES(dce_info)); 838 if (!disp_cntl_tbl) 839 return BP_RESULT_BADBIOSTABLE; 840 841 842 ss_info->type.STEP_AND_DELAY_INFO = false; 843 ss_info->spread_percentage_divider = 1000; 844 /* BIOS no longer uses target clock. Always enable for now */ 845 ss_info->target_clock_range = 0xffffffff; 846 847 switch (id) { 848 case AS_SIGNAL_TYPE_DVI: 849 ss_info->spread_spectrum_percentage = 850 disp_cntl_tbl->dvi_ss_percentage; 851 ss_info->spread_spectrum_range = 852 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 853 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 854 ss_info->type.CENTER_MODE = true; 855 856 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 857 break; 858 case AS_SIGNAL_TYPE_HDMI: 859 ss_info->spread_spectrum_percentage = 860 disp_cntl_tbl->hdmi_ss_percentage; 861 ss_info->spread_spectrum_range = 862 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 863 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 864 ss_info->type.CENTER_MODE = true; 865 866 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 867 break; 868 /* TODO LVDS not support anymore? */ 869 case AS_SIGNAL_TYPE_DISPLAY_PORT: 870 ss_info->spread_spectrum_percentage = 871 disp_cntl_tbl->dp_ss_percentage; 872 ss_info->spread_spectrum_range = 873 disp_cntl_tbl->dp_ss_rate_10hz * 10; 874 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 875 ss_info->type.CENTER_MODE = true; 876 877 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 878 break; 879 case AS_SIGNAL_TYPE_GPU_PLL: 880 /* atom_firmware: DAL only get data from dce_info table. 881 * if data within smu_info is needed for DAL, VBIOS should 882 * copy it into dce_info 883 */ 884 result = BP_RESULT_UNSUPPORTED; 885 break; 886 case AS_SIGNAL_TYPE_XGMI: 887 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 888 DATA_TABLES(smu_info)); 889 if (!smu_info) 890 return BP_RESULT_BADBIOSTABLE; 891 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 892 ss_info->spread_spectrum_percentage = 893 smu_info->waflclk_ss_percentage; 894 ss_info->spread_spectrum_range = 895 smu_info->gpuclk_ss_rate_10hz * 10; 896 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 897 ss_info->type.CENTER_MODE = true; 898 899 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 900 break; 901 default: 902 result = BP_RESULT_UNSUPPORTED; 903 } 904 905 return result; 906 } 907 908 static enum bp_result get_ss_info_v4_2( 909 struct bios_parser *bp, 910 uint32_t id, 911 uint32_t index, 912 struct spread_spectrum_info *ss_info) 913 { 914 (void)index; 915 enum bp_result result = BP_RESULT_OK; 916 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 917 struct atom_smu_info_v3_1 *smu_info = NULL; 918 919 if (!ss_info) 920 return BP_RESULT_BADINPUT; 921 922 if (!DATA_TABLES(dce_info)) 923 return BP_RESULT_BADBIOSTABLE; 924 925 if (!DATA_TABLES(smu_info)) 926 return BP_RESULT_BADBIOSTABLE; 927 928 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 929 DATA_TABLES(dce_info)); 930 if (!disp_cntl_tbl) 931 return BP_RESULT_BADBIOSTABLE; 932 933 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 934 if (!smu_info) 935 return BP_RESULT_BADBIOSTABLE; 936 937 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 938 ss_info->type.STEP_AND_DELAY_INFO = false; 939 ss_info->spread_percentage_divider = 1000; 940 /* BIOS no longer uses target clock. Always enable for now */ 941 ss_info->target_clock_range = 0xffffffff; 942 943 switch (id) { 944 case AS_SIGNAL_TYPE_DVI: 945 ss_info->spread_spectrum_percentage = 946 disp_cntl_tbl->dvi_ss_percentage; 947 ss_info->spread_spectrum_range = 948 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 949 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 950 ss_info->type.CENTER_MODE = true; 951 952 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 953 break; 954 case AS_SIGNAL_TYPE_HDMI: 955 ss_info->spread_spectrum_percentage = 956 disp_cntl_tbl->hdmi_ss_percentage; 957 ss_info->spread_spectrum_range = 958 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 959 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 960 ss_info->type.CENTER_MODE = true; 961 962 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 963 break; 964 /* TODO LVDS not support anymore? */ 965 case AS_SIGNAL_TYPE_DISPLAY_PORT: 966 ss_info->spread_spectrum_percentage = 967 smu_info->gpuclk_ss_percentage; 968 ss_info->spread_spectrum_range = 969 smu_info->gpuclk_ss_rate_10hz * 10; 970 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 971 ss_info->type.CENTER_MODE = true; 972 973 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 974 break; 975 case AS_SIGNAL_TYPE_GPU_PLL: 976 /* atom_firmware: DAL only get data from dce_info table. 977 * if data within smu_info is needed for DAL, VBIOS should 978 * copy it into dce_info 979 */ 980 result = BP_RESULT_UNSUPPORTED; 981 break; 982 default: 983 result = BP_RESULT_UNSUPPORTED; 984 } 985 986 return result; 987 } 988 989 static enum bp_result get_ss_info_v4_5( 990 struct bios_parser *bp, 991 uint32_t id, 992 uint32_t index, 993 struct spread_spectrum_info *ss_info) 994 { 995 (void)index; 996 enum bp_result result = BP_RESULT_OK; 997 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 998 999 if (!ss_info) 1000 return BP_RESULT_BADINPUT; 1001 1002 if (!DATA_TABLES(dce_info)) 1003 return BP_RESULT_BADBIOSTABLE; 1004 1005 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1006 DATA_TABLES(dce_info)); 1007 if (!disp_cntl_tbl) 1008 return BP_RESULT_BADBIOSTABLE; 1009 1010 ss_info->type.STEP_AND_DELAY_INFO = false; 1011 ss_info->spread_percentage_divider = 1000; 1012 /* BIOS no longer uses target clock. Always enable for now */ 1013 ss_info->target_clock_range = 0xffffffff; 1014 1015 switch (id) { 1016 case AS_SIGNAL_TYPE_DVI: 1017 ss_info->spread_spectrum_percentage = 1018 disp_cntl_tbl->dvi_ss_percentage; 1019 ss_info->spread_spectrum_range = 1020 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1021 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1022 ss_info->type.CENTER_MODE = true; 1023 1024 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1025 break; 1026 case AS_SIGNAL_TYPE_HDMI: 1027 ss_info->spread_spectrum_percentage = 1028 disp_cntl_tbl->hdmi_ss_percentage; 1029 ss_info->spread_spectrum_range = 1030 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1031 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1032 ss_info->type.CENTER_MODE = true; 1033 1034 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1035 break; 1036 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1037 if (bp->base.integrated_info) { 1038 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage); 1039 ss_info->spread_spectrum_percentage = 1040 bp->base.integrated_info->gpuclk_ss_percentage; 1041 ss_info->type.CENTER_MODE = 1042 bp->base.integrated_info->gpuclk_ss_type; 1043 } else { 1044 ss_info->spread_spectrum_percentage = 1045 disp_cntl_tbl->dp_ss_percentage; 1046 ss_info->spread_spectrum_range = 1047 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1048 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1049 ss_info->type.CENTER_MODE = true; 1050 } 1051 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1052 break; 1053 case AS_SIGNAL_TYPE_GPU_PLL: 1054 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1055 * SMU Display PLL supposed to be without spread. 1056 * Better place for it would be in atom_display_controller_info_v4_5 table. 1057 */ 1058 result = BP_RESULT_UNSUPPORTED; 1059 break; 1060 default: 1061 result = BP_RESULT_UNSUPPORTED; 1062 break; 1063 } 1064 1065 return result; 1066 } 1067 1068 /** 1069 * bios_parser_get_spread_spectrum_info 1070 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1071 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1072 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1073 * ver 3.1, 1074 * there is only one entry for each signal /ss id. However, there is 1075 * no planning of supporting multiple spread Sprectum entry for EverGreen 1076 * @dcb: pointer to the DC BIOS 1077 * @signal: ASSignalType to be converted to info index 1078 * @index: number of entries that match the converted info index 1079 * @ss_info: sprectrum information structure, 1080 * return: Bios parser result code 1081 */ 1082 static enum bp_result bios_parser_get_spread_spectrum_info( 1083 struct dc_bios *dcb, 1084 enum as_signal_type signal, 1085 uint32_t index, 1086 struct spread_spectrum_info *ss_info) 1087 { 1088 struct bios_parser *bp = BP_FROM_DCB(dcb); 1089 enum bp_result result = BP_RESULT_UNSUPPORTED; 1090 struct atom_common_table_header *header; 1091 struct atom_data_revision tbl_revision; 1092 1093 if (!ss_info) /* check for bad input */ 1094 return BP_RESULT_BADINPUT; 1095 1096 if (!DATA_TABLES(dce_info)) 1097 return BP_RESULT_UNSUPPORTED; 1098 1099 header = GET_IMAGE(struct atom_common_table_header, 1100 DATA_TABLES(dce_info)); 1101 get_atom_data_table_revision(header, &tbl_revision); 1102 1103 switch (tbl_revision.major) { 1104 case 4: 1105 switch (tbl_revision.minor) { 1106 case 1: 1107 return get_ss_info_v4_1(bp, signal, index, ss_info); 1108 case 2: 1109 case 3: 1110 case 4: 1111 return get_ss_info_v4_2(bp, signal, index, ss_info); 1112 case 5: 1113 return get_ss_info_v4_5(bp, signal, index, ss_info); 1114 1115 default: 1116 ASSERT(0); 1117 break; 1118 } 1119 break; 1120 default: 1121 break; 1122 } 1123 /* there can not be more then one entry for SS Info table */ 1124 return result; 1125 } 1126 1127 static enum bp_result get_soc_bb_info_v4_4( 1128 struct bios_parser *bp, 1129 struct bp_soc_bb_info *soc_bb_info) 1130 { 1131 enum bp_result result = BP_RESULT_OK; 1132 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1133 1134 if (!soc_bb_info) 1135 return BP_RESULT_BADINPUT; 1136 1137 if (!DATA_TABLES(dce_info)) 1138 return BP_RESULT_BADBIOSTABLE; 1139 1140 if (!DATA_TABLES(smu_info)) 1141 return BP_RESULT_BADBIOSTABLE; 1142 1143 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1144 DATA_TABLES(dce_info)); 1145 if (!disp_cntl_tbl) 1146 return BP_RESULT_BADBIOSTABLE; 1147 1148 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1149 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1150 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1151 1152 return result; 1153 } 1154 1155 static enum bp_result get_soc_bb_info_v4_5( 1156 struct bios_parser *bp, 1157 struct bp_soc_bb_info *soc_bb_info) 1158 { 1159 enum bp_result result = BP_RESULT_OK; 1160 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1161 1162 if (!soc_bb_info) 1163 return BP_RESULT_BADINPUT; 1164 1165 if (!DATA_TABLES(dce_info)) 1166 return BP_RESULT_BADBIOSTABLE; 1167 1168 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1169 DATA_TABLES(dce_info)); 1170 if (!disp_cntl_tbl) 1171 return BP_RESULT_BADBIOSTABLE; 1172 1173 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1174 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1175 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1176 1177 return result; 1178 } 1179 1180 static enum bp_result bios_parser_get_soc_bb_info( 1181 struct dc_bios *dcb, 1182 struct bp_soc_bb_info *soc_bb_info) 1183 { 1184 struct bios_parser *bp = BP_FROM_DCB(dcb); 1185 enum bp_result result = BP_RESULT_UNSUPPORTED; 1186 struct atom_common_table_header *header; 1187 struct atom_data_revision tbl_revision; 1188 1189 if (!soc_bb_info) /* check for bad input */ 1190 return BP_RESULT_BADINPUT; 1191 1192 if (!DATA_TABLES(dce_info)) 1193 return BP_RESULT_UNSUPPORTED; 1194 1195 header = GET_IMAGE(struct atom_common_table_header, 1196 DATA_TABLES(dce_info)); 1197 get_atom_data_table_revision(header, &tbl_revision); 1198 1199 switch (tbl_revision.major) { 1200 case 4: 1201 switch (tbl_revision.minor) { 1202 case 1: 1203 case 2: 1204 case 3: 1205 break; 1206 case 4: 1207 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1208 break; 1209 case 5: 1210 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1211 break; 1212 default: 1213 break; 1214 } 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 return result; 1221 } 1222 1223 static enum bp_result get_disp_caps_v4_1( 1224 struct bios_parser *bp, 1225 uint8_t *dce_caps) 1226 { 1227 enum bp_result result = BP_RESULT_OK; 1228 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1229 1230 if (!dce_caps) 1231 return BP_RESULT_BADINPUT; 1232 1233 if (!DATA_TABLES(dce_info)) 1234 return BP_RESULT_BADBIOSTABLE; 1235 1236 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1237 DATA_TABLES(dce_info)); 1238 1239 if (!disp_cntl_tbl) 1240 return BP_RESULT_BADBIOSTABLE; 1241 1242 *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; 1243 1244 return result; 1245 } 1246 1247 static enum bp_result get_disp_caps_v4_2( 1248 struct bios_parser *bp, 1249 uint8_t *dce_caps) 1250 { 1251 enum bp_result result = BP_RESULT_OK; 1252 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1253 1254 if (!dce_caps) 1255 return BP_RESULT_BADINPUT; 1256 1257 if (!DATA_TABLES(dce_info)) 1258 return BP_RESULT_BADBIOSTABLE; 1259 1260 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1261 DATA_TABLES(dce_info)); 1262 1263 if (!disp_cntl_tbl) 1264 return BP_RESULT_BADBIOSTABLE; 1265 1266 *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; 1267 1268 return result; 1269 } 1270 1271 static enum bp_result get_disp_caps_v4_3( 1272 struct bios_parser *bp, 1273 uint8_t *dce_caps) 1274 { 1275 enum bp_result result = BP_RESULT_OK; 1276 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1277 1278 if (!dce_caps) 1279 return BP_RESULT_BADINPUT; 1280 1281 if (!DATA_TABLES(dce_info)) 1282 return BP_RESULT_BADBIOSTABLE; 1283 1284 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1285 DATA_TABLES(dce_info)); 1286 1287 if (!disp_cntl_tbl) 1288 return BP_RESULT_BADBIOSTABLE; 1289 1290 *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; 1291 1292 return result; 1293 } 1294 1295 static enum bp_result get_disp_caps_v4_4( 1296 struct bios_parser *bp, 1297 uint8_t *dce_caps) 1298 { 1299 enum bp_result result = BP_RESULT_OK; 1300 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1301 1302 if (!dce_caps) 1303 return BP_RESULT_BADINPUT; 1304 1305 if (!DATA_TABLES(dce_info)) 1306 return BP_RESULT_BADBIOSTABLE; 1307 1308 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1309 DATA_TABLES(dce_info)); 1310 1311 if (!disp_cntl_tbl) 1312 return BP_RESULT_BADBIOSTABLE; 1313 1314 *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; 1315 1316 return result; 1317 } 1318 1319 static enum bp_result get_disp_caps_v4_5( 1320 struct bios_parser *bp, 1321 uint8_t *dce_caps) 1322 { 1323 enum bp_result result = BP_RESULT_OK; 1324 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1325 1326 if (!dce_caps) 1327 return BP_RESULT_BADINPUT; 1328 1329 if (!DATA_TABLES(dce_info)) 1330 return BP_RESULT_BADBIOSTABLE; 1331 1332 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1333 DATA_TABLES(dce_info)); 1334 1335 if (!disp_cntl_tbl) 1336 return BP_RESULT_BADBIOSTABLE; 1337 1338 *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; 1339 1340 return result; 1341 } 1342 1343 static enum bp_result bios_parser_get_lttpr_interop( 1344 struct dc_bios *dcb, 1345 uint8_t *dce_caps) 1346 { 1347 struct bios_parser *bp = BP_FROM_DCB(dcb); 1348 enum bp_result result = BP_RESULT_UNSUPPORTED; 1349 struct atom_common_table_header *header; 1350 struct atom_data_revision tbl_revision; 1351 1352 if (!DATA_TABLES(dce_info)) 1353 return BP_RESULT_UNSUPPORTED; 1354 1355 header = GET_IMAGE(struct atom_common_table_header, 1356 DATA_TABLES(dce_info)); 1357 get_atom_data_table_revision(header, &tbl_revision); 1358 switch (tbl_revision.major) { 1359 case 4: 1360 switch (tbl_revision.minor) { 1361 case 1: 1362 result = get_disp_caps_v4_1(bp, dce_caps); 1363 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1364 break; 1365 case 2: 1366 result = get_disp_caps_v4_2(bp, dce_caps); 1367 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1368 break; 1369 case 3: 1370 result = get_disp_caps_v4_3(bp, dce_caps); 1371 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1372 break; 1373 case 4: 1374 result = get_disp_caps_v4_4(bp, dce_caps); 1375 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1376 break; 1377 case 5: 1378 result = get_disp_caps_v4_5(bp, dce_caps); 1379 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1380 break; 1381 1382 default: 1383 break; 1384 } 1385 break; 1386 default: 1387 break; 1388 } 1389 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1390 return result; 1391 } 1392 1393 static enum bp_result bios_parser_get_lttpr_caps( 1394 struct dc_bios *dcb, 1395 uint8_t *dce_caps) 1396 { 1397 struct bios_parser *bp = BP_FROM_DCB(dcb); 1398 enum bp_result result = BP_RESULT_UNSUPPORTED; 1399 struct atom_common_table_header *header; 1400 struct atom_data_revision tbl_revision; 1401 1402 if (!DATA_TABLES(dce_info)) 1403 return BP_RESULT_UNSUPPORTED; 1404 1405 *dce_caps = 0; 1406 header = GET_IMAGE(struct atom_common_table_header, 1407 DATA_TABLES(dce_info)); 1408 get_atom_data_table_revision(header, &tbl_revision); 1409 switch (tbl_revision.major) { 1410 case 4: 1411 switch (tbl_revision.minor) { 1412 case 1: 1413 result = get_disp_caps_v4_1(bp, dce_caps); 1414 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1415 break; 1416 case 2: 1417 result = get_disp_caps_v4_2(bp, dce_caps); 1418 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1419 break; 1420 case 3: 1421 result = get_disp_caps_v4_3(bp, dce_caps); 1422 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1423 break; 1424 case 4: 1425 result = get_disp_caps_v4_4(bp, dce_caps); 1426 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1427 break; 1428 case 5: 1429 result = get_disp_caps_v4_5(bp, dce_caps); 1430 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1431 break; 1432 default: 1433 break; 1434 } 1435 break; 1436 default: 1437 break; 1438 } 1439 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1440 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) { 1441 *dce_caps = 1; 1442 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled"); 1443 } 1444 return result; 1445 } 1446 1447 static enum bp_result get_embedded_panel_info_v2_1( 1448 struct bios_parser *bp, 1449 struct embedded_panel_info *info) 1450 { 1451 struct lcd_info_v2_1 *lvds; 1452 1453 if (!info) 1454 return BP_RESULT_BADINPUT; 1455 1456 if (!DATA_TABLES(lcd_info)) 1457 return BP_RESULT_UNSUPPORTED; 1458 1459 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1460 1461 if (!lvds) 1462 return BP_RESULT_BADBIOSTABLE; 1463 1464 /* TODO: previous vv1_3, should v2_1 */ 1465 if (!((lvds->table_header.format_revision == 2) 1466 && (lvds->table_header.content_revision >= 1))) 1467 return BP_RESULT_UNSUPPORTED; 1468 1469 memset(info, 0, sizeof(struct embedded_panel_info)); 1470 1471 /* We need to convert from 10KHz units into KHz units */ 1472 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1473 /* usHActive does not include borders, according to VBIOS team */ 1474 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1475 /* usHBlanking_Time includes borders, so we should really be 1476 * subtractingborders duing this translation, but LVDS generally 1477 * doesn't have borders, so we should be okay leaving this as is for 1478 * now. May need to revisit if we ever have LVDS with borders 1479 */ 1480 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1481 /* usVActive does not include borders, according to VBIOS team*/ 1482 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1483 /* usVBlanking_Time includes borders, so we should really be 1484 * subtracting borders duing this translation, but LVDS generally 1485 * doesn't have borders, so we should be okay leaving this as is for 1486 * now. May need to revisit if we ever have LVDS with borders 1487 */ 1488 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1489 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1490 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1491 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1492 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1493 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1494 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1495 1496 /* not provided by VBIOS */ 1497 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1498 1499 info->lcd_timing.misc_info.H_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo & 1500 ATOM_HSYNC_POLARITY); 1501 info->lcd_timing.misc_info.V_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo & 1502 ATOM_VSYNC_POLARITY); 1503 1504 /* not provided by VBIOS */ 1505 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1506 1507 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1508 & ATOM_H_REPLICATIONBY2); 1509 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1510 & ATOM_V_REPLICATIONBY2); 1511 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1512 & ATOM_COMPOSITESYNC); 1513 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1514 1515 /* not provided by VBIOS*/ 1516 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1517 /* not provided by VBIOS*/ 1518 info->ss_id = 0; 1519 1520 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1521 1522 return BP_RESULT_OK; 1523 } 1524 1525 static enum bp_result bios_parser_get_embedded_panel_info( 1526 struct dc_bios *dcb, 1527 struct embedded_panel_info *info) 1528 { 1529 struct bios_parser 1530 *bp = BP_FROM_DCB(dcb); 1531 struct atom_common_table_header *header; 1532 struct atom_data_revision tbl_revision; 1533 1534 if (!DATA_TABLES(lcd_info)) 1535 return BP_RESULT_FAILURE; 1536 1537 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1538 1539 if (!header) 1540 return BP_RESULT_BADBIOSTABLE; 1541 1542 get_atom_data_table_revision(header, &tbl_revision); 1543 1544 switch (tbl_revision.major) { 1545 case 2: 1546 switch (tbl_revision.minor) { 1547 case 1: 1548 return get_embedded_panel_info_v2_1(bp, info); 1549 default: 1550 break; 1551 } 1552 break; 1553 default: 1554 break; 1555 } 1556 1557 return BP_RESULT_FAILURE; 1558 } 1559 1560 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1561 { 1562 enum dal_device_type device_type = device_id.device_type; 1563 uint32_t enum_id = device_id.enum_id; 1564 1565 switch (device_type) { 1566 case DEVICE_TYPE_LCD: 1567 switch (enum_id) { 1568 case 1: 1569 return ATOM_DISPLAY_LCD1_SUPPORT; 1570 default: 1571 break; 1572 } 1573 break; 1574 case DEVICE_TYPE_DFP: 1575 switch (enum_id) { 1576 case 1: 1577 return ATOM_DISPLAY_DFP1_SUPPORT; 1578 case 2: 1579 return ATOM_DISPLAY_DFP2_SUPPORT; 1580 case 3: 1581 return ATOM_DISPLAY_DFP3_SUPPORT; 1582 case 4: 1583 return ATOM_DISPLAY_DFP4_SUPPORT; 1584 case 5: 1585 return ATOM_DISPLAY_DFP5_SUPPORT; 1586 case 6: 1587 return ATOM_DISPLAY_DFP6_SUPPORT; 1588 default: 1589 break; 1590 } 1591 break; 1592 default: 1593 break; 1594 } 1595 1596 /* Unidentified device ID, return empty support mask. */ 1597 return 0; 1598 } 1599 1600 static bool bios_parser_is_device_id_supported( 1601 struct dc_bios *dcb, 1602 struct device_id id) 1603 { 1604 struct bios_parser *bp = BP_FROM_DCB(dcb); 1605 1606 uint32_t mask = get_support_mask_for_device_id(id); 1607 1608 switch (bp->object_info_tbl.revision.minor) { 1609 case 4: 1610 default: 1611 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1612 break; 1613 case 5: 1614 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1615 break; 1616 } 1617 } 1618 1619 static uint32_t bios_parser_get_ss_entry_number( 1620 struct dc_bios *dcb, 1621 enum as_signal_type signal) 1622 { 1623 (void)dcb; 1624 (void)signal; 1625 /* TODO: DAL2 atomfirmware implementation does not need this. 1626 * why DAL3 need this? 1627 */ 1628 return 1; 1629 } 1630 1631 static enum bp_result bios_parser_transmitter_control( 1632 struct dc_bios *dcb, 1633 struct bp_transmitter_control *cntl) 1634 { 1635 struct bios_parser *bp = BP_FROM_DCB(dcb); 1636 1637 if (!bp->cmd_tbl.transmitter_control) 1638 return BP_RESULT_FAILURE; 1639 1640 return bp->cmd_tbl.transmitter_control(bp, cntl); 1641 } 1642 1643 static enum bp_result bios_parser_encoder_control( 1644 struct dc_bios *dcb, 1645 struct bp_encoder_control *cntl) 1646 { 1647 struct bios_parser *bp = BP_FROM_DCB(dcb); 1648 1649 if (!bp->cmd_tbl.dig_encoder_control) 1650 return BP_RESULT_FAILURE; 1651 1652 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1653 } 1654 1655 static enum bp_result bios_parser_set_pixel_clock( 1656 struct dc_bios *dcb, 1657 struct bp_pixel_clock_parameters *bp_params) 1658 { 1659 struct bios_parser *bp = BP_FROM_DCB(dcb); 1660 1661 if (!bp->cmd_tbl.set_pixel_clock) 1662 return BP_RESULT_FAILURE; 1663 1664 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1665 } 1666 1667 static enum bp_result bios_parser_set_dce_clock( 1668 struct dc_bios *dcb, 1669 struct bp_set_dce_clock_parameters *bp_params) 1670 { 1671 struct bios_parser *bp = BP_FROM_DCB(dcb); 1672 1673 if (!bp->cmd_tbl.set_dce_clock) 1674 return BP_RESULT_FAILURE; 1675 1676 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1677 } 1678 1679 static enum bp_result bios_parser_program_crtc_timing( 1680 struct dc_bios *dcb, 1681 struct bp_hw_crtc_timing_parameters *bp_params) 1682 { 1683 struct bios_parser *bp = BP_FROM_DCB(dcb); 1684 1685 if (!bp->cmd_tbl.set_crtc_timing) 1686 return BP_RESULT_FAILURE; 1687 1688 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1689 } 1690 1691 static enum bp_result bios_parser_enable_crtc( 1692 struct dc_bios *dcb, 1693 enum controller_id id, 1694 bool enable) 1695 { 1696 struct bios_parser *bp = BP_FROM_DCB(dcb); 1697 1698 if (!bp->cmd_tbl.enable_crtc) 1699 return BP_RESULT_FAILURE; 1700 1701 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1702 } 1703 1704 static enum bp_result bios_parser_enable_disp_power_gating( 1705 struct dc_bios *dcb, 1706 enum controller_id controller_id, 1707 enum bp_pipe_control_action action) 1708 { 1709 struct bios_parser *bp = BP_FROM_DCB(dcb); 1710 1711 if (!bp->cmd_tbl.enable_disp_power_gating) 1712 return BP_RESULT_FAILURE; 1713 1714 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1715 action); 1716 } 1717 1718 static enum bp_result bios_parser_enable_lvtma_control( 1719 struct dc_bios *dcb, 1720 uint8_t uc_pwr_on, 1721 uint8_t pwrseq_instance, 1722 uint8_t bypass_panel_control_wait) 1723 { 1724 struct bios_parser *bp = BP_FROM_DCB(dcb); 1725 1726 if (!bp->cmd_tbl.enable_lvtma_control) 1727 return BP_RESULT_FAILURE; 1728 1729 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait); 1730 } 1731 1732 static bool bios_parser_is_accelerated_mode( 1733 struct dc_bios *dcb) 1734 { 1735 return bios_is_accelerated_mode(dcb); 1736 } 1737 1738 /** 1739 * bios_parser_set_scratch_critical_state - update critical state bit 1740 * in VBIOS scratch register 1741 * 1742 * @dcb: pointer to the DC BIO 1743 * @state: set or reset state 1744 */ 1745 static void bios_parser_set_scratch_critical_state( 1746 struct dc_bios *dcb, 1747 bool state) 1748 { 1749 bios_set_scratch_critical_state(dcb, state); 1750 } 1751 1752 static enum bp_result bios_parser_get_firmware_info( 1753 struct dc_bios *dcb, 1754 struct dc_firmware_info *info) 1755 { 1756 struct bios_parser *bp = BP_FROM_DCB(dcb); 1757 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1758 struct atom_common_table_header *header; 1759 1760 struct atom_data_revision revision; 1761 1762 if (info && DATA_TABLES(firmwareinfo)) { 1763 header = GET_IMAGE(struct atom_common_table_header, 1764 DATA_TABLES(firmwareinfo)); 1765 get_atom_data_table_revision(header, &revision); 1766 switch (revision.major) { 1767 case 3: 1768 switch (revision.minor) { 1769 case 1: 1770 result = get_firmware_info_v3_1(bp, info); 1771 break; 1772 case 2: 1773 case 3: 1774 result = get_firmware_info_v3_2(bp, info); 1775 break; 1776 case 4: 1777 result = get_firmware_info_v3_4(bp, info); 1778 break; 1779 case 5: 1780 result = get_firmware_info_v3_5(bp, info); 1781 break; 1782 default: 1783 break; 1784 } 1785 break; 1786 default: 1787 break; 1788 } 1789 } 1790 1791 return result; 1792 } 1793 1794 static enum bp_result get_firmware_info_v3_1( 1795 struct bios_parser *bp, 1796 struct dc_firmware_info *info) 1797 { 1798 struct atom_firmware_info_v3_1 *firmware_info; 1799 struct atom_firmware_info_v3_2 *firmware_info32; 1800 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1801 1802 if (!info) 1803 return BP_RESULT_BADINPUT; 1804 1805 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1806 DATA_TABLES(firmwareinfo)); 1807 firmware_info32 = GET_IMAGE(struct atom_firmware_info_v3_2, 1808 DATA_TABLES(firmwareinfo)); 1809 1810 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1811 DATA_TABLES(dce_info)); 1812 1813 if (!firmware_info || !firmware_info32 || !dce_info) 1814 return BP_RESULT_BADBIOSTABLE; 1815 1816 memset(info, 0, sizeof(*info)); 1817 1818 /* Pixel clock pll information. */ 1819 /* We need to convert from 10KHz units into KHz units */ 1820 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1821 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1822 1823 /* 27MHz for Vega10: */ 1824 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1825 1826 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1827 if (info->pll_info.crystal_frequency == 0) 1828 info->pll_info.crystal_frequency = 27000; 1829 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1830 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1831 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1832 1833 /* Get GPU PLL VCO Clock */ 1834 1835 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1836 /* VBIOS gives in 10KHz */ 1837 info->smu_gpu_pll_output_freq = 1838 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1839 } 1840 1841 /* These fields are marked as reserved in v3_1, but they appear to be populated 1842 * properly. 1843 */ 1844 if (firmware_info32 && firmware_info32->board_i2c_feature_id == 0x2) { 1845 info->oem_i2c_present = true; 1846 info->oem_i2c_obj_id = firmware_info32->board_i2c_feature_gpio_id; 1847 } else { 1848 info->oem_i2c_present = false; 1849 } 1850 1851 return BP_RESULT_OK; 1852 } 1853 1854 static enum bp_result get_firmware_info_v3_2( 1855 struct bios_parser *bp, 1856 struct dc_firmware_info *info) 1857 { 1858 struct atom_firmware_info_v3_2 *firmware_info; 1859 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1860 struct atom_common_table_header *header; 1861 struct atom_data_revision revision; 1862 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1863 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1864 1865 if (!info) 1866 return BP_RESULT_BADINPUT; 1867 1868 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1869 DATA_TABLES(firmwareinfo)); 1870 1871 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1872 DATA_TABLES(dce_info)); 1873 1874 if (!firmware_info || !dce_info) 1875 return BP_RESULT_BADBIOSTABLE; 1876 1877 memset(info, 0, sizeof(*info)); 1878 1879 header = GET_IMAGE(struct atom_common_table_header, 1880 DATA_TABLES(smu_info)); 1881 get_atom_data_table_revision(header, &revision); 1882 1883 if (revision.minor == 2) { 1884 /* Vega12 */ 1885 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1886 DATA_TABLES(smu_info)); 1887 if (!smu_info_v3_2) 1888 return BP_RESULT_BADBIOSTABLE; 1889 1890 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage); 1891 1892 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1893 } else if (revision.minor == 3) { 1894 /* Vega20 */ 1895 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1896 DATA_TABLES(smu_info)); 1897 if (!smu_info_v3_3) 1898 return BP_RESULT_BADBIOSTABLE; 1899 1900 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage); 1901 1902 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1903 } 1904 1905 // We need to convert from 10KHz units into KHz units. 1906 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1907 1908 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1909 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1910 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1911 if (info->pll_info.crystal_frequency == 0) { 1912 if (revision.minor == 2) 1913 info->pll_info.crystal_frequency = 27000; 1914 else if (revision.minor == 3) 1915 info->pll_info.crystal_frequency = 100000; 1916 } 1917 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1918 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1919 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1920 1921 /* Get GPU PLL VCO Clock */ 1922 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1923 if (revision.minor == 2) 1924 info->smu_gpu_pll_output_freq = 1925 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1926 else if (revision.minor == 3) 1927 info->smu_gpu_pll_output_freq = 1928 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1929 } 1930 1931 if (firmware_info->board_i2c_feature_id == 0x2) { 1932 info->oem_i2c_present = true; 1933 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1934 } else { 1935 info->oem_i2c_present = false; 1936 } 1937 1938 return BP_RESULT_OK; 1939 } 1940 1941 static enum bp_result get_firmware_info_v3_4( 1942 struct bios_parser *bp, 1943 struct dc_firmware_info *info) 1944 { 1945 struct atom_firmware_info_v3_4 *firmware_info; 1946 struct atom_common_table_header *header; 1947 struct atom_data_revision revision; 1948 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1949 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1950 1951 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1952 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1953 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1954 1955 if (!info) 1956 return BP_RESULT_BADINPUT; 1957 1958 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1959 DATA_TABLES(firmwareinfo)); 1960 1961 if (!firmware_info) 1962 return BP_RESULT_BADBIOSTABLE; 1963 1964 memset(info, 0, sizeof(*info)); 1965 1966 header = GET_IMAGE(struct atom_common_table_header, 1967 DATA_TABLES(dce_info)); 1968 1969 get_atom_data_table_revision(header, &revision); 1970 1971 switch (revision.major) { 1972 case 4: 1973 switch (revision.minor) { 1974 case 5: 1975 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1976 DATA_TABLES(dce_info)); 1977 1978 if (!dce_info_v4_5) 1979 return BP_RESULT_BADBIOSTABLE; 1980 1981 /* 100MHz expected */ 1982 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1983 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1984 /* 50MHz expected */ 1985 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1986 1987 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1988 break; 1989 1990 case 4: 1991 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1992 DATA_TABLES(dce_info)); 1993 1994 if (!dce_info_v4_4) 1995 return BP_RESULT_BADBIOSTABLE; 1996 1997 /* 100MHz expected */ 1998 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1999 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 2000 /* 50MHz expected */ 2001 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 2002 2003 /* Get SMU Display PLL VCO Frequency in KHz*/ 2004 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 2005 break; 2006 2007 default: 2008 /* should not come here, keep as backup, as was before */ 2009 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 2010 DATA_TABLES(dce_info)); 2011 2012 if (!dce_info_v4_1) 2013 return BP_RESULT_BADBIOSTABLE; 2014 2015 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 2016 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 2017 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 2018 break; 2019 } 2020 break; 2021 2022 default: 2023 ASSERT(0); 2024 break; 2025 } 2026 2027 header = GET_IMAGE(struct atom_common_table_header, 2028 DATA_TABLES(smu_info)); 2029 get_atom_data_table_revision(header, &revision); 2030 2031 switch (revision.major) { 2032 case 3: 2033 switch (revision.minor) { 2034 case 5: 2035 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2036 DATA_TABLES(smu_info)); 2037 2038 if (!smu_info_v3_5) 2039 return BP_RESULT_BADBIOSTABLE; 2040 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage); 2041 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2042 break; 2043 2044 default: 2045 break; 2046 } 2047 break; 2048 2049 case 4: 2050 switch (revision.minor) { 2051 case 0: 2052 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2053 DATA_TABLES(smu_info)); 2054 2055 if (!smu_info_v4_0) 2056 return BP_RESULT_BADBIOSTABLE; 2057 2058 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2059 break; 2060 2061 default: 2062 break; 2063 } 2064 break; 2065 2066 default: 2067 break; 2068 } 2069 2070 // We need to convert from 10KHz units into KHz units. 2071 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2072 2073 if (firmware_info->board_i2c_feature_id == 0x2) { 2074 info->oem_i2c_present = true; 2075 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2076 } else { 2077 info->oem_i2c_present = false; 2078 } 2079 2080 return BP_RESULT_OK; 2081 } 2082 2083 static enum bp_result get_firmware_info_v3_5( 2084 struct bios_parser *bp, 2085 struct dc_firmware_info *info) 2086 { 2087 struct atom_firmware_info_v3_5 *firmware_info; 2088 struct atom_common_table_header *header; 2089 struct atom_data_revision revision; 2090 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 2091 2092 if (!info) 2093 return BP_RESULT_BADINPUT; 2094 2095 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_5, 2096 DATA_TABLES(firmwareinfo)); 2097 2098 if (!firmware_info) 2099 return BP_RESULT_BADBIOSTABLE; 2100 2101 memset(info, 0, sizeof(*info)); 2102 2103 if (firmware_info->board_i2c_feature_id == 0x2) { 2104 info->oem_i2c_present = true; 2105 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2106 } else { 2107 info->oem_i2c_present = false; 2108 } 2109 2110 header = GET_IMAGE(struct atom_common_table_header, 2111 DATA_TABLES(dce_info)); 2112 2113 get_atom_data_table_revision(header, &revision); 2114 2115 switch (revision.major) { 2116 case 4: 2117 switch (revision.minor) { 2118 case 5: 2119 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 2120 DATA_TABLES(dce_info)); 2121 2122 if (!dce_info_v4_5) 2123 return BP_RESULT_BADBIOSTABLE; 2124 2125 /* 100MHz expected */ 2126 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 2127 break; 2128 default: 2129 break; 2130 } 2131 break; 2132 default: 2133 break; 2134 } 2135 2136 2137 return BP_RESULT_OK; 2138 } 2139 2140 static enum bp_result bios_parser_get_encoder_cap_info( 2141 struct dc_bios *dcb, 2142 struct graphics_object_id object_id, 2143 struct bp_encoder_cap_info *info) 2144 { 2145 struct bios_parser *bp = BP_FROM_DCB(dcb); 2146 struct atom_display_object_path_v2 *object; 2147 struct atom_encoder_caps_record *record = NULL; 2148 2149 if (!info) 2150 return BP_RESULT_BADINPUT; 2151 2152 #if defined(CONFIG_DRM_AMD_DC_FP) 2153 /* encoder cap record not available in v1_5 */ 2154 if (bp->object_info_tbl.revision.minor == 5) 2155 return BP_RESULT_NORECORD; 2156 #endif 2157 2158 object = get_bios_object(bp, object_id); 2159 2160 if (!object) 2161 return BP_RESULT_BADINPUT; 2162 2163 record = get_encoder_cap_record(bp, object); 2164 if (!record) 2165 return BP_RESULT_NORECORD; 2166 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id); 2167 2168 info->DP_HBR2_CAP = (record->encodercaps & 2169 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2170 info->DP_HBR2_EN = (record->encodercaps & 2171 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2172 info->DP_HBR3_EN = (record->encodercaps & 2173 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2174 info->HDMI_6GB_EN = (record->encodercaps & 2175 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2176 info->IS_DP2_CAPABLE = (record->encodercaps & 2177 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2178 info->DP_UHBR10_EN = (record->encodercaps & 2179 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2180 info->DP_UHBR13_5_EN = (record->encodercaps & 2181 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2182 info->DP_UHBR20_EN = (record->encodercaps & 2183 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2184 info->DP_IS_USB_C = (record->encodercaps & 2185 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2186 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C); 2187 2188 return BP_RESULT_OK; 2189 } 2190 2191 2192 static struct atom_encoder_caps_record *get_encoder_cap_record( 2193 struct bios_parser *bp, 2194 struct atom_display_object_path_v2 *object) 2195 { 2196 struct atom_common_record_header *header; 2197 uint32_t offset; 2198 2199 if (!object) { 2200 BREAK_TO_DEBUGGER(); /* Invalid object */ 2201 return NULL; 2202 } 2203 2204 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2205 2206 for (;;) { 2207 header = GET_IMAGE(struct atom_common_record_header, offset); 2208 2209 if (!header) 2210 return NULL; 2211 2212 offset += header->record_size; 2213 2214 if (header->record_type == LAST_RECORD_TYPE || 2215 !header->record_size) 2216 break; 2217 2218 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2219 continue; 2220 2221 if (sizeof(struct atom_encoder_caps_record) <= 2222 header->record_size) 2223 return (struct atom_encoder_caps_record *)header; 2224 } 2225 2226 return NULL; 2227 } 2228 2229 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2230 struct bios_parser *bp, 2231 struct atom_display_object_path_v2 *object) 2232 { 2233 struct atom_common_record_header *header; 2234 uint32_t offset; 2235 2236 if (!object) { 2237 BREAK_TO_DEBUGGER(); /* Invalid object */ 2238 return NULL; 2239 } 2240 2241 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2242 2243 for (;;) { 2244 header = GET_IMAGE(struct atom_common_record_header, offset); 2245 2246 if (!header) 2247 return NULL; 2248 2249 offset += header->record_size; 2250 2251 if (header->record_type == LAST_RECORD_TYPE || 2252 !header->record_size) 2253 break; 2254 2255 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2256 continue; 2257 2258 if (sizeof(struct atom_disp_connector_caps_record) <= 2259 header->record_size) 2260 return (struct atom_disp_connector_caps_record *)header; 2261 } 2262 2263 return NULL; 2264 } 2265 2266 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp, 2267 struct atom_display_object_path_v3 *object) 2268 { 2269 struct atom_common_record_header *header; 2270 uint32_t offset; 2271 2272 if (!object) { 2273 BREAK_TO_DEBUGGER(); /* Invalid object */ 2274 return NULL; 2275 } 2276 2277 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2278 2279 for (;;) { 2280 header = GET_IMAGE(struct atom_common_record_header, offset); 2281 2282 if (!header) 2283 return NULL; 2284 2285 offset += header->record_size; 2286 2287 if (header->record_type == ATOM_RECORD_END_TYPE || 2288 !header->record_size) 2289 break; 2290 2291 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2292 continue; 2293 2294 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2295 return (struct atom_connector_caps_record *)header; 2296 } 2297 2298 return NULL; 2299 } 2300 2301 static enum bp_result bios_parser_get_disp_connector_caps_info( 2302 struct dc_bios *dcb, 2303 struct graphics_object_id object_id, 2304 struct bp_disp_connector_caps_info *info) 2305 { 2306 struct bios_parser *bp = BP_FROM_DCB(dcb); 2307 struct atom_display_object_path_v2 *object; 2308 struct atom_display_object_path_v3 *object_path_v3; 2309 struct atom_connector_caps_record *record_path_v3; 2310 struct atom_disp_connector_caps_record *record = NULL; 2311 2312 if (!info) 2313 return BP_RESULT_BADINPUT; 2314 2315 switch (bp->object_info_tbl.revision.minor) { 2316 case 4: 2317 default: 2318 object = get_bios_object(bp, object_id); 2319 2320 if (!object) 2321 return BP_RESULT_BADINPUT; 2322 2323 record = get_disp_connector_caps_record(bp, object); 2324 if (!record) 2325 return BP_RESULT_NORECORD; 2326 2327 info->INTERNAL_DISPLAY = 2328 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2329 info->INTERNAL_DISPLAY_BL = 2330 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2331 break; 2332 case 5: 2333 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2334 2335 if (!object_path_v3) 2336 return BP_RESULT_BADINPUT; 2337 2338 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2339 if (!record_path_v3) 2340 return BP_RESULT_NORECORD; 2341 2342 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2343 ? 1 : 0; 2344 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2345 ? 1 : 0; 2346 break; 2347 } 2348 2349 return BP_RESULT_OK; 2350 } 2351 2352 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp, 2353 struct atom_display_object_path_v3 *object) 2354 { 2355 struct atom_common_record_header *header; 2356 uint32_t offset; 2357 2358 if (!object) { 2359 BREAK_TO_DEBUGGER(); /* Invalid object */ 2360 return NULL; 2361 } 2362 2363 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2364 2365 for (;;) { 2366 header = GET_IMAGE(struct atom_common_record_header, offset); 2367 2368 if (!header) 2369 return NULL; 2370 2371 offset += header->record_size; 2372 2373 if (header->record_type == ATOM_RECORD_END_TYPE || 2374 !header->record_size) 2375 break; 2376 2377 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2378 continue; 2379 2380 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2381 return (struct atom_connector_speed_record *)header; 2382 } 2383 2384 return NULL; 2385 } 2386 2387 static enum bp_result bios_parser_get_connector_speed_cap_info( 2388 struct dc_bios *dcb, 2389 struct graphics_object_id object_id, 2390 struct bp_connector_speed_cap_info *info) 2391 { 2392 struct bios_parser *bp = BP_FROM_DCB(dcb); 2393 struct atom_display_object_path_v3 *object_path_v3; 2394 //struct atom_connector_speed_record *record = NULL; 2395 struct atom_connector_speed_record *record; 2396 2397 if (!info) 2398 return BP_RESULT_BADINPUT; 2399 2400 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2401 2402 if (!object_path_v3) 2403 return BP_RESULT_BADINPUT; 2404 2405 record = get_connector_speed_cap_record(bp, object_path_v3); 2406 if (!record) 2407 return BP_RESULT_NORECORD; 2408 2409 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2410 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2411 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2412 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2413 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2414 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2415 return BP_RESULT_OK; 2416 } 2417 2418 static enum bp_result get_vram_info_v23( 2419 struct bios_parser *bp, 2420 struct dc_vram_info *info) 2421 { 2422 struct atom_vram_info_header_v2_3 *info_v23; 2423 static enum bp_result result = BP_RESULT_OK; 2424 2425 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2426 DATA_TABLES(vram_info)); 2427 2428 if (info_v23 == NULL) 2429 return BP_RESULT_BADBIOSTABLE; 2430 2431 info->num_chans = info_v23->vram_module[0].channel_num; 2432 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2433 2434 return result; 2435 } 2436 2437 static enum bp_result get_vram_info_v24( 2438 struct bios_parser *bp, 2439 struct dc_vram_info *info) 2440 { 2441 struct atom_vram_info_header_v2_4 *info_v24; 2442 static enum bp_result result = BP_RESULT_OK; 2443 2444 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2445 DATA_TABLES(vram_info)); 2446 2447 if (info_v24 == NULL) 2448 return BP_RESULT_BADBIOSTABLE; 2449 2450 info->num_chans = info_v24->vram_module[0].channel_num; 2451 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2452 2453 return result; 2454 } 2455 2456 static enum bp_result get_vram_info_v25( 2457 struct bios_parser *bp, 2458 struct dc_vram_info *info) 2459 { 2460 struct atom_vram_info_header_v2_5 *info_v25; 2461 static enum bp_result result = BP_RESULT_OK; 2462 2463 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2464 DATA_TABLES(vram_info)); 2465 2466 if (info_v25 == NULL) 2467 return BP_RESULT_BADBIOSTABLE; 2468 2469 info->num_chans = info_v25->vram_module[0].channel_num; 2470 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2471 2472 return result; 2473 } 2474 2475 static enum bp_result get_vram_info_v30( 2476 struct bios_parser *bp, 2477 struct dc_vram_info *info) 2478 { 2479 struct atom_vram_info_header_v3_0 *info_v30; 2480 enum bp_result result = BP_RESULT_OK; 2481 2482 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0, 2483 DATA_TABLES(vram_info)); 2484 2485 if (info_v30 == NULL) 2486 return BP_RESULT_BADBIOSTABLE; 2487 2488 info->num_chans = info_v30->channel_num; 2489 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; 2490 2491 return result; 2492 } 2493 2494 static enum bp_result get_vram_info_from_umc_info_v40( 2495 struct bios_parser *bp, 2496 struct dc_vram_info *info) 2497 { 2498 struct atom_umc_info_v4_0 *info_v40; 2499 enum bp_result result = BP_RESULT_OK; 2500 2501 info_v40 = GET_IMAGE(struct atom_umc_info_v4_0, 2502 DATA_TABLES(umc_info)); 2503 2504 if (info_v40 == NULL) 2505 return BP_RESULT_BADBIOSTABLE; 2506 2507 info->num_chans = info_v40->channel_num; 2508 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8; 2509 2510 return result; 2511 } 2512 2513 /* 2514 * get_integrated_info_v11 2515 * 2516 * @brief 2517 * Get V8 integrated BIOS information 2518 * 2519 * @param 2520 * bios_parser *bp - [in]BIOS parser handler to get master data table 2521 * integrated_info *info - [out] store and output integrated info 2522 * 2523 * @return 2524 * static enum bp_result - BP_RESULT_OK if information is available, 2525 * BP_RESULT_BADBIOSTABLE otherwise. 2526 */ 2527 static enum bp_result get_integrated_info_v11( 2528 struct bios_parser *bp, 2529 struct integrated_info *info) 2530 { 2531 struct atom_integrated_system_info_v1_11 *info_v11; 2532 uint32_t i; 2533 2534 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2535 DATA_TABLES(integratedsysteminfo)); 2536 2537 if (info_v11 == NULL) 2538 return BP_RESULT_BADBIOSTABLE; 2539 2540 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage); 2541 2542 info->gpu_cap_info = 2543 le32_to_cpu(info_v11->gpucapinfo); 2544 /* 2545 * system_config: Bit[0] = 0 : PCIE power gating disabled 2546 * = 1 : PCIE power gating enabled 2547 * Bit[1] = 0 : DDR-PLL shut down disabled 2548 * = 1 : DDR-PLL shut down enabled 2549 * Bit[2] = 0 : DDR-PLL power down disabled 2550 * = 1 : DDR-PLL power down enabled 2551 */ 2552 info->system_config = le32_to_cpu(info_v11->system_config); 2553 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2554 info->memory_type = info_v11->memorytype; 2555 info->ma_channel_number = info_v11->umachannelnumber; 2556 info->lvds_ss_percentage = 2557 le16_to_cpu(info_v11->lvds_ss_percentage); 2558 info->dp_ss_control = 2559 le16_to_cpu(info_v11->reserved1); 2560 info->lvds_sspread_rate_in_10hz = 2561 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2562 info->hdmi_ss_percentage = 2563 le16_to_cpu(info_v11->hdmi_ss_percentage); 2564 info->hdmi_sspread_rate_in_10hz = 2565 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2566 info->dvi_ss_percentage = 2567 le16_to_cpu(info_v11->dvi_ss_percentage); 2568 info->dvi_sspread_rate_in_10_hz = 2569 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2570 info->lvds_misc = info_v11->lvds_misc; 2571 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2572 info->ext_disp_conn_info.gu_id[i] = 2573 info_v11->extdispconninfo.guid[i]; 2574 } 2575 2576 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2577 info->ext_disp_conn_info.path[i].device_connector_id = 2578 object_id_from_bios_object_id( 2579 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2580 2581 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2582 object_id_from_bios_object_id( 2583 le16_to_cpu( 2584 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2585 2586 info->ext_disp_conn_info.path[i].device_tag = 2587 le16_to_cpu( 2588 info_v11->extdispconninfo.path[i].device_tag); 2589 info->ext_disp_conn_info.path[i].device_acpi_enum = 2590 le16_to_cpu( 2591 info_v11->extdispconninfo.path[i].device_acpi_enum); 2592 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2593 info_v11->extdispconninfo.path[i].auxddclut_index; 2594 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2595 info_v11->extdispconninfo.path[i].hpdlut_index; 2596 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2597 info_v11->extdispconninfo.path[i].channelmapping; 2598 info->ext_disp_conn_info.path[i].caps = 2599 (unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2600 } 2601 info->ext_disp_conn_info.checksum = 2602 info_v11->extdispconninfo.checksum; 2603 2604 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2605 info->dp0_ext_hdmi_reg_num = min_t(u8, info_v11->dp0_retimer_set.HdmiRegNum, 2606 ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings)); 2607 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2608 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2609 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2610 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2611 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2612 } 2613 info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp0_retimer_set.Hdmi6GRegNum, 2614 ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings)); 2615 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2616 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2617 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2618 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2619 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2620 } 2621 2622 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2623 info->dp1_ext_hdmi_reg_num = min_t(u8, info_v11->dp1_retimer_set.HdmiRegNum, 2624 ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings)); 2625 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2626 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2627 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2628 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2629 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2630 } 2631 info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp1_retimer_set.Hdmi6GRegNum, 2632 ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings)); 2633 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2634 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2635 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2636 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2637 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2638 } 2639 2640 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2641 info->dp2_ext_hdmi_reg_num = min_t(u8, info_v11->dp2_retimer_set.HdmiRegNum, 2642 ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings)); 2643 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2644 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2645 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2646 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2647 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2648 } 2649 info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp2_retimer_set.Hdmi6GRegNum, 2650 ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings)); 2651 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2652 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2653 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2654 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2655 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2656 } 2657 2658 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2659 info->dp3_ext_hdmi_reg_num = min_t(u8, info_v11->dp3_retimer_set.HdmiRegNum, 2660 ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings)); 2661 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2662 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2663 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2664 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2665 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2666 } 2667 info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp3_retimer_set.Hdmi6GRegNum, 2668 ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings)); 2669 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2670 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2671 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2672 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2673 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2674 } 2675 2676 2677 /** TODO - review **/ 2678 #if 0 2679 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2680 * 10; 2681 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2682 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2683 2684 info->boot_up_req_display_vector = 2685 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2686 info->boot_up_nb_voltage = 2687 le16_to_cpu(info_v11->usBootUpNBVoltage); 2688 info->ext_disp_conn_info_offset = 2689 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2690 info->gmc_restore_reset_time = 2691 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2692 info->minimum_n_clk = 2693 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2694 for (i = 1; i < 4; ++i) 2695 info->minimum_n_clk = 2696 info->minimum_n_clk < 2697 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2698 info->minimum_n_clk : le32_to_cpu( 2699 info_v11->ulNbpStateNClkFreq[i]); 2700 2701 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2702 info->ddr_dll_power_up_time = 2703 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2704 info->ddr_pll_power_up_time = 2705 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2706 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2707 info->max_lvds_pclk_freq_in_single_link = 2708 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2709 info->max_lvds_pclk_freq_in_single_link = 2710 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2711 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2712 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2713 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2714 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2715 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2716 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2717 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2718 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2719 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2720 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2721 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2722 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2723 info->lvds_off_to_on_delay_in_4ms = 2724 info_v11->ucLVDSOffToOnDelay_in4Ms; 2725 info->lvds_bit_depth_control_val = 2726 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2727 2728 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2729 /* Convert [10KHz] into [KHz] */ 2730 info->avail_s_clk[i].supported_s_clk = 2731 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2732 * 10; 2733 info->avail_s_clk[i].voltage_index = 2734 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2735 info->avail_s_clk[i].voltage_id = 2736 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2737 } 2738 #endif /* TODO*/ 2739 2740 return BP_RESULT_OK; 2741 } 2742 2743 static enum bp_result get_integrated_info_v2_1( 2744 struct bios_parser *bp, 2745 struct integrated_info *info) 2746 { 2747 struct atom_integrated_system_info_v2_1 *info_v2_1; 2748 uint32_t i; 2749 2750 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2751 DATA_TABLES(integratedsysteminfo)); 2752 2753 if (info_v2_1 == NULL) 2754 return BP_RESULT_BADBIOSTABLE; 2755 2756 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage); 2757 2758 info->gpu_cap_info = 2759 le32_to_cpu(info_v2_1->gpucapinfo); 2760 /* 2761 * system_config: Bit[0] = 0 : PCIE power gating disabled 2762 * = 1 : PCIE power gating enabled 2763 * Bit[1] = 0 : DDR-PLL shut down disabled 2764 * = 1 : DDR-PLL shut down enabled 2765 * Bit[2] = 0 : DDR-PLL power down disabled 2766 * = 1 : DDR-PLL power down enabled 2767 */ 2768 info->system_config = le32_to_cpu(info_v2_1->system_config); 2769 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2770 info->memory_type = info_v2_1->memorytype; 2771 info->ma_channel_number = info_v2_1->umachannelnumber; 2772 info->dp_ss_control = 2773 le16_to_cpu(info_v2_1->reserved1); 2774 2775 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2776 info->ext_disp_conn_info.gu_id[i] = 2777 info_v2_1->extdispconninfo.guid[i]; 2778 } 2779 2780 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2781 info->ext_disp_conn_info.path[i].device_connector_id = 2782 object_id_from_bios_object_id( 2783 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2784 2785 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2786 object_id_from_bios_object_id( 2787 le16_to_cpu( 2788 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2789 2790 info->ext_disp_conn_info.path[i].device_tag = 2791 le16_to_cpu( 2792 info_v2_1->extdispconninfo.path[i].device_tag); 2793 info->ext_disp_conn_info.path[i].device_acpi_enum = 2794 le16_to_cpu( 2795 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2796 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2797 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2798 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2799 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2800 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2801 info_v2_1->extdispconninfo.path[i].channelmapping; 2802 info->ext_disp_conn_info.path[i].caps = 2803 (unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2804 } 2805 2806 info->ext_disp_conn_info.checksum = 2807 info_v2_1->extdispconninfo.checksum; 2808 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2809 info->dp0_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.HdmiRegNum, 2810 ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings)); 2811 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2812 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2813 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2814 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2815 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2816 } 2817 info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.Hdmi6GRegNum, 2818 ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings)); 2819 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2820 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2821 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2822 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2823 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2824 } 2825 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2826 info->dp1_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.HdmiRegNum, 2827 ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings)); 2828 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2829 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2830 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2831 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2832 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2833 } 2834 info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.Hdmi6GRegNum, 2835 ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings)); 2836 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2837 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2838 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2839 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2840 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2841 } 2842 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2843 info->dp2_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.HdmiRegNum, 2844 ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings)); 2845 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2846 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2847 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2848 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2849 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2850 } 2851 info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.Hdmi6GRegNum, 2852 ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings)); 2853 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2854 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2855 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2856 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2857 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2858 } 2859 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2860 info->dp3_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.HdmiRegNum, 2861 ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings)); 2862 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2863 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2864 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2865 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2866 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2867 } 2868 info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.Hdmi6GRegNum, 2869 ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings)); 2870 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2871 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2872 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2873 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2874 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2875 } 2876 2877 info->edp1_info.edp_backlight_pwm_hz = 2878 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2879 info->edp1_info.edp_ss_percentage = 2880 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2881 info->edp1_info.edp_ss_rate_10hz = 2882 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2883 info->edp1_info.edp_pwr_on_off_delay = 2884 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2885 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2886 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2887 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2888 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2889 info->edp1_info.edp_panel_bpc = 2890 info_v2_1->edp1_info.edp_panel_bpc; 2891 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2892 2893 info->edp2_info.edp_backlight_pwm_hz = 2894 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2895 info->edp2_info.edp_ss_percentage = 2896 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2897 info->edp2_info.edp_ss_rate_10hz = 2898 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2899 info->edp2_info.edp_pwr_on_off_delay = 2900 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2901 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2902 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2903 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2904 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2905 info->edp2_info.edp_panel_bpc = 2906 info_v2_1->edp2_info.edp_panel_bpc; 2907 info->edp2_info.edp_bootup_bl_level = 2908 info_v2_1->edp2_info.edp_bootup_bl_level; 2909 2910 return BP_RESULT_OK; 2911 } 2912 2913 static enum bp_result get_integrated_info_v2_2( 2914 struct bios_parser *bp, 2915 struct integrated_info *info) 2916 { 2917 struct atom_integrated_system_info_v2_2 *info_v2_2; 2918 uint32_t i; 2919 2920 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2921 DATA_TABLES(integratedsysteminfo)); 2922 2923 if (info_v2_2 == NULL) 2924 return BP_RESULT_BADBIOSTABLE; 2925 2926 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage); 2927 2928 info->gpu_cap_info = 2929 le32_to_cpu(info_v2_2->gpucapinfo); 2930 /* 2931 * system_config: Bit[0] = 0 : PCIE power gating disabled 2932 * = 1 : PCIE power gating enabled 2933 * Bit[1] = 0 : DDR-PLL shut down disabled 2934 * = 1 : DDR-PLL shut down enabled 2935 * Bit[2] = 0 : DDR-PLL power down disabled 2936 * = 1 : DDR-PLL power down enabled 2937 */ 2938 info->system_config = le32_to_cpu(info_v2_2->system_config); 2939 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2940 info->memory_type = info_v2_2->memorytype; 2941 info->ma_channel_number = info_v2_2->umachannelnumber; 2942 info->dp_ss_control = 2943 le16_to_cpu(info_v2_2->reserved1); 2944 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage; 2945 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type; 2946 2947 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2948 info->ext_disp_conn_info.gu_id[i] = 2949 info_v2_2->extdispconninfo.guid[i]; 2950 } 2951 2952 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2953 info->ext_disp_conn_info.path[i].device_connector_id = 2954 object_id_from_bios_object_id( 2955 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2956 2957 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2958 object_id_from_bios_object_id( 2959 le16_to_cpu( 2960 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2961 2962 info->ext_disp_conn_info.path[i].device_tag = 2963 le16_to_cpu( 2964 info_v2_2->extdispconninfo.path[i].device_tag); 2965 info->ext_disp_conn_info.path[i].device_acpi_enum = 2966 le16_to_cpu( 2967 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2968 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2969 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2970 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2971 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2972 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2973 info_v2_2->extdispconninfo.path[i].channelmapping; 2974 info->ext_disp_conn_info.path[i].caps = 2975 (unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2976 } 2977 2978 info->ext_disp_conn_info.checksum = 2979 info_v2_2->extdispconninfo.checksum; 2980 info->ext_disp_conn_info.fixdpvoltageswing = 2981 info_v2_2->extdispconninfo.fixdpvoltageswing; 2982 2983 info->edp1_info.edp_backlight_pwm_hz = 2984 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2985 info->edp1_info.edp_ss_percentage = 2986 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2987 info->edp1_info.edp_ss_rate_10hz = 2988 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2989 info->edp1_info.edp_pwr_on_off_delay = 2990 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2991 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2992 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2993 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2994 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2995 info->edp1_info.edp_panel_bpc = 2996 info_v2_2->edp1_info.edp_panel_bpc; 2997 info->edp1_info.edp_bootup_bl_level = 2998 info_v2_2->edp1_info.edp_bootup_bl_level; 2999 3000 info->edp2_info.edp_backlight_pwm_hz = 3001 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 3002 info->edp2_info.edp_ss_percentage = 3003 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 3004 info->edp2_info.edp_ss_rate_10hz = 3005 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 3006 info->edp2_info.edp_pwr_on_off_delay = 3007 info_v2_2->edp2_info.edp_pwr_on_off_delay; 3008 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 3009 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 3010 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 3011 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 3012 info->edp2_info.edp_panel_bpc = 3013 info_v2_2->edp2_info.edp_panel_bpc; 3014 info->edp2_info.edp_bootup_bl_level = 3015 info_v2_2->edp2_info.edp_bootup_bl_level; 3016 3017 return BP_RESULT_OK; 3018 } 3019 3020 /* 3021 * construct_integrated_info 3022 * 3023 * @brief 3024 * Get integrated BIOS information based on table revision 3025 * 3026 * @param 3027 * bios_parser *bp - [in]BIOS parser handler to get master data table 3028 * integrated_info *info - [out] store and output integrated info 3029 * 3030 * @return 3031 * static enum bp_result - BP_RESULT_OK if information is available, 3032 * BP_RESULT_BADBIOSTABLE otherwise. 3033 */ 3034 static enum bp_result construct_integrated_info( 3035 struct bios_parser *bp, 3036 struct integrated_info *info) 3037 { 3038 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 3039 3040 struct atom_common_table_header *header; 3041 struct atom_data_revision revision; 3042 3043 int32_t i; 3044 3045 if (!info) 3046 return result; 3047 3048 if (info && DATA_TABLES(integratedsysteminfo)) { 3049 header = GET_IMAGE(struct atom_common_table_header, 3050 DATA_TABLES(integratedsysteminfo)); 3051 3052 get_atom_data_table_revision(header, &revision); 3053 3054 switch (revision.major) { 3055 case 1: 3056 switch (revision.minor) { 3057 case 11: 3058 case 12: 3059 result = get_integrated_info_v11(bp, info); 3060 break; 3061 default: 3062 return result; 3063 } 3064 break; 3065 case 2: 3066 switch (revision.minor) { 3067 case 1: 3068 result = get_integrated_info_v2_1(bp, info); 3069 break; 3070 case 2: 3071 case 3: 3072 result = get_integrated_info_v2_2(bp, info); 3073 break; 3074 default: 3075 return result; 3076 } 3077 break; 3078 default: 3079 return result; 3080 } 3081 if (result == BP_RESULT_OK) { 3082 3083 DC_LOG_BIOS("edp1:\n" 3084 "\tedp_pwr_on_off_delay = %d\n" 3085 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 3086 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 3087 "\tedp_bootup_bl_level = %d\n", 3088 info->edp1_info.edp_pwr_on_off_delay, 3089 info->edp1_info.edp_pwr_on_vary_bl_to_blon, 3090 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff, 3091 info->edp1_info.edp_bootup_bl_level); 3092 DC_LOG_BIOS("edp2:\n" 3093 "\tedp_pwr_on_off_delayv = %d\n" 3094 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 3095 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 3096 "\tedp_bootup_bl_level = %d\n", 3097 info->edp2_info.edp_pwr_on_off_delay, 3098 info->edp2_info.edp_pwr_on_vary_bl_to_blon, 3099 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff, 3100 info->edp2_info.edp_bootup_bl_level); 3101 } 3102 } 3103 3104 if (result != BP_RESULT_OK) 3105 return result; 3106 else { 3107 // Log each external path 3108 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 3109 if (info->ext_disp_conn_info.path[i].device_tag != 0) 3110 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n" 3111 "DEVICE_TAG: 0x%x\n" 3112 "DEVICE_ACPI_ENUM: 0x%x\n" 3113 "DEVICE_CONNECTOR_ID: 0x%x\n" 3114 "EXT_AUX_DDC_LUT_INDEX: %d\n" 3115 "EXT_HPD_PIN_LUT_INDEX: %d\n" 3116 "EXT_ENCODER_OBJ_ID: 0x%x\n" 3117 "Encoder CAPS: 0x%x\n", 3118 i, 3119 info->ext_disp_conn_info.path[i].device_tag, 3120 info->ext_disp_conn_info.path[i].device_acpi_enum, 3121 info->ext_disp_conn_info.path[i].device_connector_id.id, 3122 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index, 3123 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index, 3124 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id, 3125 info->ext_disp_conn_info.path[i].caps 3126 ); 3127 if ((info->ext_disp_conn_info.path[i].caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) 3128 DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3129 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) { 3130 info->ext_disp_conn_info.path[i].caps &= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 3131 info->ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN; 3132 DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3133 } 3134 } 3135 // Log the Checksum and Voltage Swing 3136 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n" 3137 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n", 3138 info->ext_disp_conn_info.checksum, 3139 info->ext_disp_conn_info.fixdpvoltageswing); 3140 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) { 3141 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF; 3142 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing); 3143 } 3144 } 3145 3146 return result; 3147 } 3148 3149 static enum bp_result bios_parser_get_vram_info( 3150 struct dc_bios *dcb, 3151 struct dc_vram_info *info) 3152 { 3153 struct bios_parser *bp = BP_FROM_DCB(dcb); 3154 enum bp_result result = BP_RESULT_BADBIOSTABLE; 3155 struct atom_common_table_header *header; 3156 struct atom_data_revision revision; 3157 3158 // vram info moved to umc_info for DCN4x 3159 if (info && DATA_TABLES(umc_info)) { 3160 header = GET_IMAGE(struct atom_common_table_header, 3161 DATA_TABLES(umc_info)); 3162 3163 get_atom_data_table_revision(header, &revision); 3164 3165 switch (revision.major) { 3166 case 4: 3167 switch (revision.minor) { 3168 case 0: 3169 result = get_vram_info_from_umc_info_v40(bp, info); 3170 break; 3171 default: 3172 break; 3173 } 3174 break; 3175 default: 3176 break; 3177 } 3178 } 3179 3180 if (result != BP_RESULT_OK && info && DATA_TABLES(vram_info)) { 3181 header = GET_IMAGE(struct atom_common_table_header, 3182 DATA_TABLES(vram_info)); 3183 3184 get_atom_data_table_revision(header, &revision); 3185 3186 switch (revision.major) { 3187 case 2: 3188 switch (revision.minor) { 3189 case 3: 3190 result = get_vram_info_v23(bp, info); 3191 break; 3192 case 4: 3193 result = get_vram_info_v24(bp, info); 3194 break; 3195 case 5: 3196 result = get_vram_info_v25(bp, info); 3197 break; 3198 default: 3199 break; 3200 } 3201 break; 3202 3203 case 3: 3204 switch (revision.minor) { 3205 case 0: 3206 result = get_vram_info_v30(bp, info); 3207 break; 3208 default: 3209 break; 3210 } 3211 break; 3212 3213 default: 3214 return result; 3215 } 3216 3217 } 3218 return result; 3219 } 3220 3221 static struct integrated_info *bios_parser_create_integrated_info( 3222 struct dc_bios *dcb) 3223 { 3224 struct bios_parser *bp = BP_FROM_DCB(dcb); 3225 struct integrated_info *info; 3226 3227 info = kzalloc_obj(struct integrated_info); 3228 3229 if (info == NULL) { 3230 ASSERT_CRITICAL(0); 3231 return NULL; 3232 } 3233 3234 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3235 return info; 3236 3237 kfree(info); 3238 3239 return NULL; 3240 } 3241 3242 static enum bp_result update_slot_layout_info( 3243 struct dc_bios *dcb, 3244 unsigned int i, 3245 struct slot_layout_info *slot_layout_info) 3246 { 3247 unsigned int record_offset; 3248 unsigned int j; 3249 struct atom_display_object_path_v2 *object; 3250 struct atom_bracket_layout_record *record; 3251 struct atom_common_record_header *record_header; 3252 static enum bp_result result; 3253 struct bios_parser *bp; 3254 struct object_info_table *tbl; 3255 struct display_object_info_table_v1_4 *v1_4; 3256 3257 record = NULL; 3258 record_header = NULL; 3259 result = BP_RESULT_NORECORD; 3260 3261 bp = BP_FROM_DCB(dcb); 3262 tbl = &bp->object_info_tbl; 3263 v1_4 = tbl->v1_4; 3264 3265 object = &v1_4->display_path[i]; 3266 record_offset = (unsigned int) 3267 (object->disp_recordoffset) + 3268 (unsigned int)(bp->object_info_tbl_offset); 3269 3270 for (;;) { 3271 3272 record_header = (struct atom_common_record_header *) 3273 GET_IMAGE(struct atom_common_record_header, 3274 record_offset); 3275 if (record_header == NULL) { 3276 result = BP_RESULT_BADBIOSTABLE; 3277 break; 3278 } 3279 3280 /* the end of the list */ 3281 if (record_header->record_type == 0xff || 3282 record_header->record_size == 0) { 3283 break; 3284 } 3285 3286 if (record_header->record_type == 3287 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3288 sizeof(struct atom_bracket_layout_record) 3289 <= record_header->record_size) { 3290 record = (struct atom_bracket_layout_record *) 3291 (record_header); 3292 result = BP_RESULT_OK; 3293 break; 3294 } 3295 3296 record_offset += record_header->record_size; 3297 } 3298 3299 /* return if the record not found */ 3300 if (result != BP_RESULT_OK) 3301 return result; 3302 3303 /* get slot sizes */ 3304 slot_layout_info->length = record->bracketlen; 3305 slot_layout_info->width = record->bracketwidth; 3306 3307 /* get info for each connector in the slot */ 3308 slot_layout_info->num_of_connectors = record->conn_num; 3309 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3310 slot_layout_info->connectors[j].connector_type = 3311 (enum connector_layout_type) 3312 (record->conn_info[j].connector_type); 3313 switch (record->conn_info[j].connector_type) { 3314 case CONNECTOR_TYPE_DVI_D: 3315 slot_layout_info->connectors[j].connector_type = 3316 CONNECTOR_LAYOUT_TYPE_DVI_D; 3317 slot_layout_info->connectors[j].length = 3318 CONNECTOR_SIZE_DVI; 3319 break; 3320 3321 case CONNECTOR_TYPE_HDMI: 3322 slot_layout_info->connectors[j].connector_type = 3323 CONNECTOR_LAYOUT_TYPE_HDMI; 3324 slot_layout_info->connectors[j].length = 3325 CONNECTOR_SIZE_HDMI; 3326 break; 3327 3328 case CONNECTOR_TYPE_DISPLAY_PORT: 3329 slot_layout_info->connectors[j].connector_type = 3330 CONNECTOR_LAYOUT_TYPE_DP; 3331 slot_layout_info->connectors[j].length = 3332 CONNECTOR_SIZE_DP; 3333 break; 3334 3335 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3336 slot_layout_info->connectors[j].connector_type = 3337 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3338 slot_layout_info->connectors[j].length = 3339 CONNECTOR_SIZE_MINI_DP; 3340 break; 3341 3342 default: 3343 slot_layout_info->connectors[j].connector_type = 3344 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3345 slot_layout_info->connectors[j].length = 3346 CONNECTOR_SIZE_UNKNOWN; 3347 } 3348 3349 slot_layout_info->connectors[j].position = 3350 record->conn_info[j].position; 3351 slot_layout_info->connectors[j].connector_id = 3352 object_id_from_bios_object_id( 3353 record->conn_info[j].connectorobjid); 3354 } 3355 return result; 3356 } 3357 3358 static enum bp_result update_slot_layout_info_v2( 3359 struct dc_bios *dcb, 3360 unsigned int i, 3361 struct slot_layout_info *slot_layout_info) 3362 { 3363 unsigned int record_offset; 3364 struct atom_display_object_path_v3 *object; 3365 struct atom_bracket_layout_record_v2 *record; 3366 struct atom_common_record_header *record_header; 3367 static enum bp_result result; 3368 struct bios_parser *bp; 3369 struct object_info_table *tbl; 3370 struct display_object_info_table_v1_5 *v1_5; 3371 struct graphics_object_id connector_id; 3372 3373 record = NULL; 3374 record_header = NULL; 3375 result = BP_RESULT_NORECORD; 3376 3377 bp = BP_FROM_DCB(dcb); 3378 tbl = &bp->object_info_tbl; 3379 v1_5 = tbl->v1_5; 3380 3381 object = &v1_5->display_path[i]; 3382 record_offset = (unsigned int) 3383 (object->disp_recordoffset) + 3384 (unsigned int)(bp->object_info_tbl_offset); 3385 3386 for (;;) { 3387 3388 record_header = (struct atom_common_record_header *) 3389 GET_IMAGE(struct atom_common_record_header, 3390 record_offset); 3391 if (record_header == NULL) { 3392 result = BP_RESULT_BADBIOSTABLE; 3393 break; 3394 } 3395 3396 /* the end of the list */ 3397 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3398 record_header->record_size == 0) { 3399 break; 3400 } 3401 3402 if (record_header->record_type == 3403 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3404 sizeof(struct atom_bracket_layout_record_v2) 3405 <= record_header->record_size) { 3406 record = (struct atom_bracket_layout_record_v2 *) 3407 (record_header); 3408 result = BP_RESULT_OK; 3409 break; 3410 } 3411 3412 record_offset += record_header->record_size; 3413 } 3414 3415 /* return if the record not found */ 3416 if (result != BP_RESULT_OK) 3417 return result; 3418 3419 /* get slot sizes */ 3420 connector_id = object_id_from_bios_object_id(object->display_objid); 3421 3422 slot_layout_info->length = record->bracketlen; 3423 slot_layout_info->width = record->bracketwidth; 3424 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3425 slot_layout_info->connectors[i].position = record->conn_num; 3426 slot_layout_info->connectors[i].connector_id = connector_id; 3427 3428 switch (connector_id.id) { 3429 case CONNECTOR_ID_SINGLE_LINK_DVID: 3430 case CONNECTOR_ID_DUAL_LINK_DVID: 3431 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3432 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3433 break; 3434 3435 case CONNECTOR_ID_HDMI_TYPE_A: 3436 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3437 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3438 break; 3439 3440 case CONNECTOR_ID_DISPLAY_PORT: 3441 case CONNECTOR_ID_USBC: 3442 if (record->mini_type == MINI_TYPE_NORMAL) { 3443 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3444 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3445 } else { 3446 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3447 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3448 } 3449 break; 3450 3451 default: 3452 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3453 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3454 } 3455 return result; 3456 } 3457 3458 static enum bp_result get_bracket_layout_record( 3459 struct dc_bios *dcb, 3460 unsigned int bracket_layout_id, 3461 struct slot_layout_info *slot_layout_info) 3462 { 3463 unsigned int i; 3464 struct bios_parser *bp = BP_FROM_DCB(dcb); 3465 static enum bp_result result; 3466 struct object_info_table *tbl; 3467 struct display_object_info_table_v1_4 *v1_4; 3468 struct display_object_info_table_v1_5 *v1_5; 3469 3470 if (slot_layout_info == NULL) { 3471 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3472 return BP_RESULT_BADINPUT; 3473 } 3474 3475 tbl = &bp->object_info_tbl; 3476 v1_4 = tbl->v1_4; 3477 v1_5 = tbl->v1_5; 3478 3479 result = BP_RESULT_NORECORD; 3480 switch (bp->object_info_tbl.revision.minor) { 3481 case 4: 3482 default: 3483 for (i = 0; i < v1_4->number_of_path; ++i) { 3484 if (bracket_layout_id == v1_4->display_path[i].display_objid) { 3485 result = update_slot_layout_info(dcb, i, slot_layout_info); 3486 break; 3487 } 3488 } 3489 break; 3490 case 5: 3491 for (i = 0; i < v1_5->number_of_path; ++i) 3492 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3493 break; 3494 } 3495 3496 return result; 3497 } 3498 3499 static enum bp_result bios_get_board_layout_info( 3500 struct dc_bios *dcb, 3501 struct board_layout_info *board_layout_info) 3502 { 3503 unsigned int i; 3504 struct bios_parser *bp; 3505 static enum bp_result record_result; 3506 unsigned int max_slots; 3507 3508 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3509 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3510 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3511 0, 0 3512 }; 3513 3514 bp = BP_FROM_DCB(dcb); 3515 3516 if (board_layout_info == NULL) { 3517 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3518 return BP_RESULT_BADINPUT; 3519 } 3520 3521 board_layout_info->num_of_slots = 0; 3522 max_slots = MAX_BOARD_SLOTS; 3523 3524 // Assume single slot on v1_5 3525 if (bp->object_info_tbl.revision.minor == 5) { 3526 max_slots = 1; 3527 } 3528 3529 for (i = 0; i < max_slots; ++i) { 3530 record_result = get_bracket_layout_record(dcb, 3531 slot_index_to_vbios_id[i], 3532 &board_layout_info->slots[i]); 3533 3534 if (record_result == BP_RESULT_NORECORD && i > 0) 3535 break; /* no more slots present in bios */ 3536 else if (record_result != BP_RESULT_OK) 3537 return record_result; /* fail */ 3538 3539 ++board_layout_info->num_of_slots; 3540 } 3541 3542 /* all data is valid */ 3543 board_layout_info->is_number_of_slots_valid = 1; 3544 board_layout_info->is_slots_size_valid = 1; 3545 board_layout_info->is_connector_offsets_valid = 1; 3546 board_layout_info->is_connector_lengths_valid = 1; 3547 3548 return BP_RESULT_OK; 3549 } 3550 3551 3552 static uint16_t bios_parser_pack_data_tables( 3553 struct dc_bios *dcb, 3554 void *dst) 3555 { 3556 (void)dcb; 3557 (void)dst; 3558 // TODO: There is data bytes alignment issue, disable it for now. 3559 return 0; 3560 } 3561 3562 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3563 struct bios_parser *bp, 3564 uint32_t rev_major, 3565 uint32_t rev_minor, 3566 uint16_t *dc_golden_table_ver) 3567 { 3568 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3569 uint32_t dc_golden_offset = 0; 3570 *dc_golden_table_ver = 0; 3571 3572 if (!DATA_TABLES(dce_info)) 3573 return NULL; 3574 3575 /* ver.4.4 or higher */ 3576 switch (rev_major) { 3577 case 4: 3578 switch (rev_minor) { 3579 case 4: 3580 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3581 DATA_TABLES(dce_info)); 3582 if (!disp_cntl_tbl_4_4) 3583 return NULL; 3584 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3585 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3586 break; 3587 case 5: 3588 default: 3589 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3590 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3591 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3592 */ 3593 break; 3594 } 3595 break; 3596 } 3597 3598 if (!dc_golden_offset) 3599 return NULL; 3600 3601 if (*dc_golden_table_ver != 1) 3602 return NULL; 3603 3604 return GET_IMAGE(struct atom_dc_golden_table_v1, 3605 dc_golden_offset); 3606 } 3607 3608 static enum bp_result bios_get_atom_dc_golden_table( 3609 struct dc_bios *dcb) 3610 { 3611 struct bios_parser *bp = BP_FROM_DCB(dcb); 3612 enum bp_result result = BP_RESULT_OK; 3613 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3614 struct atom_common_table_header *header; 3615 struct atom_data_revision tbl_revision; 3616 uint16_t dc_golden_table_ver = 0; 3617 3618 header = GET_IMAGE(struct atom_common_table_header, 3619 DATA_TABLES(dce_info)); 3620 if (!header) 3621 return BP_RESULT_UNSUPPORTED; 3622 3623 get_atom_data_table_revision(header, &tbl_revision); 3624 3625 atom_dc_golden_table = bios_get_golden_table(bp, 3626 tbl_revision.major, 3627 tbl_revision.minor, 3628 &dc_golden_table_ver); 3629 3630 if (!atom_dc_golden_table) 3631 return BP_RESULT_UNSUPPORTED; 3632 3633 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3634 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3635 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3636 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3637 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3638 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3639 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3640 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3641 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3642 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3643 3644 return result; 3645 } 3646 3647 3648 static const struct dc_vbios_funcs vbios_funcs = { 3649 .get_connectors_number = bios_parser_get_connectors_number, 3650 3651 .get_connector_id = bios_parser_get_connector_id, 3652 3653 .get_src_obj = bios_parser_get_src_obj, 3654 3655 .get_i2c_info = bios_parser_get_i2c_info, 3656 3657 .get_hpd_info = bios_parser_get_hpd_info, 3658 3659 .get_device_tag = bios_parser_get_device_tag, 3660 3661 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3662 3663 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3664 3665 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3666 3667 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3668 3669 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3670 3671 .is_device_id_supported = bios_parser_is_device_id_supported, 3672 3673 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3674 3675 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3676 3677 3678 /* COMMANDS */ 3679 .encoder_control = bios_parser_encoder_control, 3680 3681 .transmitter_control = bios_parser_transmitter_control, 3682 3683 .enable_crtc = bios_parser_enable_crtc, 3684 3685 .set_pixel_clock = bios_parser_set_pixel_clock, 3686 3687 .set_dce_clock = bios_parser_set_dce_clock, 3688 3689 .program_crtc_timing = bios_parser_program_crtc_timing, 3690 3691 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3692 3693 .bios_parser_destroy = firmware_parser_destroy, 3694 3695 .get_board_layout_info = bios_get_board_layout_info, 3696 .pack_data_tables = bios_parser_pack_data_tables, 3697 3698 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3699 3700 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3701 3702 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3703 3704 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3705 3706 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3707 3708 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3709 3710 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3711 }; 3712 3713 static bool bios_parser2_construct( 3714 struct bios_parser *bp, 3715 struct bp_init_data *init, 3716 enum dce_version dce_version) 3717 { 3718 uint16_t *rom_header_offset = NULL; 3719 struct atom_rom_header_v2_2 *rom_header = NULL; 3720 struct display_object_info_table_v1_4 *object_info_tbl; 3721 struct atom_data_revision tbl_rev = {0}; 3722 3723 if (!init) 3724 return false; 3725 3726 if (!init->bios) 3727 return false; 3728 3729 bp->base.funcs = &vbios_funcs; 3730 bp->base.bios = init->bios; 3731 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3732 3733 bp->base.ctx = init->ctx; 3734 3735 bp->base.bios_local_image = NULL; 3736 3737 rom_header_offset = 3738 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3739 3740 if (!rom_header_offset) 3741 return false; 3742 3743 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3744 3745 if (!rom_header) 3746 return false; 3747 3748 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3749 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3750 return false; 3751 3752 bp->master_data_tbl = 3753 GET_IMAGE(struct atom_master_data_table_v2_1, 3754 rom_header->masterdatatable_offset); 3755 3756 if (!bp->master_data_tbl) 3757 return false; 3758 3759 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3760 3761 if (!bp->object_info_tbl_offset) 3762 return false; 3763 3764 object_info_tbl = 3765 GET_IMAGE(struct display_object_info_table_v1_4, 3766 bp->object_info_tbl_offset); 3767 3768 if (!object_info_tbl) 3769 return false; 3770 3771 get_atom_data_table_revision(&object_info_tbl->table_header, 3772 &bp->object_info_tbl.revision); 3773 3774 if (bp->object_info_tbl.revision.major == 1 3775 && bp->object_info_tbl.revision.minor == 4) { 3776 struct display_object_info_table_v1_4 *tbl_v1_4; 3777 3778 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3779 bp->object_info_tbl_offset); 3780 if (!tbl_v1_4) 3781 return false; 3782 3783 bp->object_info_tbl.v1_4 = tbl_v1_4; 3784 } else if (bp->object_info_tbl.revision.major == 1 3785 && bp->object_info_tbl.revision.minor == 5) { 3786 struct display_object_info_table_v1_5 *tbl_v1_5; 3787 3788 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3789 bp->object_info_tbl_offset); 3790 if (!tbl_v1_5) 3791 return false; 3792 3793 bp->object_info_tbl.v1_5 = tbl_v1_5; 3794 } else { 3795 ASSERT(0); 3796 return false; 3797 } 3798 3799 dal_firmware_parser_init_cmd_tbl(bp); 3800 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3801 3802 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3803 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3804 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3805 bios_parser_get_soc_bb_info(&bp->base, &bp->base.bb_info); 3806 return true; 3807 } 3808 3809 struct dc_bios *firmware_parser_create( 3810 struct bp_init_data *init, 3811 enum dce_version dce_version) 3812 { 3813 struct bios_parser *bp; 3814 3815 bp = kzalloc_obj(struct bios_parser); 3816 if (!bp) 3817 return NULL; 3818 3819 if (bios_parser2_construct(bp, init, dce_version)) 3820 return &bp->base; 3821 3822 kfree(bp); 3823 return NULL; 3824 } 3825 3826 3827